TLV2461AMUB [TI]
FAMILY OF LOW-POWER RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH SHUTDOWN; 系列低功耗轨至轨输入/输出运算放大器,带有关断的型号: | TLV2461AMUB |
厂家: | TEXAS INSTRUMENTS |
描述: | FAMILY OF LOW-POWER RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH SHUTDOWN |
文件: | 总58页 (文件大小:1455K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢈ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢉ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢄ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢊ ꢇ ꢀꢁꢂ ꢃꢄ ꢅꢋ ꢌ
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SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TLV2460
DBV PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
D
Rail-to-Rail Output Swing
Gain Bandwidth Product . . . 6.4 MHz
80 mA Output Drive Capability
Supply Current . . . 500 µA/channel
Input Offset Voltage . . . 100 µV
Input Noise Voltage . . . 11 nV/√Hz
Slew Rate . . . 1.6 V/µs
1
2
3
6
5
4
V
DD+
OUT
GND
SHDN
IN−
IN+
Micropower Shutdown Mode
(TLV2460/3/5) . . . 0.3 µA/Channel
D
Universal Operational Amplifier EVM
D
Available in Q-Temp Automotive
HighRel Automotive Applications
Configuration Control/Print Support
Qualification to Automotive Standards
description
The TLV246x is a family of low-power rail-to-rail input/output operational amplifiers specifically designed for
portable applications. The input common-mode voltage range extends beyond the supply rails for maximum
dynamic range in low-voltage systems. The amplifier output has rail-to-rail performance with high-output-drive
capability, solving one of the limitations of older rail-to-rail input/output operational amplifiers. This rail-to-rail
dynamic range and high output drive make the TLV246x ideal for buffering analog-to-digital converters.
The operational amplifier has 6.4 MHz of bandwidth and 1.6 V/µs of slew rate with only 500 µA of supply current,
providing good ac performance with low power consumption. Three members of the family offer a shutdown
terminal, which places the amplifier in an ultralow supply current mode (I
the operational-amplifier output is placed in a high-impedance state. DC applications are also well served with
= 0.3 µA/ch). While in shutdown,
DD
an input noise voltage of 11 nV/√Hz and input offset voltage of 100 µV.
This family is available in the low-profile SOT23, MSOP, and TSSOP packages. The TLV2460 is the first
rail-to-rail input/output operational amplifier with shutdown available in the 6-pin SOT23, making it perfect for
high-density circuits. The family is specified over an expanded temperature range (T = −40°C to 125°C) for
A
use in industrial control and automotive systems, and over the military temperature range
(T = −55°C to 125°C) for use in military systems.
A
SELECTION GUIDE
GBW SLEW RATE
[MHz] [V/µs]
V
[V]
V
I
/ch
I
V
I
O
DD
IO
DD
IB
n, 1 kHz
DEVICE
SHUTDOWN
RAIL-RAIL
[µV]
150
360
250
20
[µA]
550
1000
600
23
[pA]
1300
2
[nV/√Hz]
[mA]
25
6
TLV246x(A)
TLV277x(A)
TLV247x(A)
TLV245x(A)
TLV225x(A)
TLV226x(A)
2.7−6
2.5−5.5
2.7−6
2.7−6
2.7−8
2.7−8
6.4
5.1
1.6
10.5
1.5
11
17
15
52
19
12
Y
Y
I/O
O
2.5
500
1
2.8
20
10
3
Y
I/O
I/O
—
0.22
0.2
0.11
0.12
0.55
Y
200
300
35
—
—
200
1
0.71
3
—
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 1998−2004, Texas Instruments Incorporated
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SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TLV2460C/I/AI and TLV2461C/I/AI AVAILABLE OPTIONS
PACKAGED DEVICES
V
max
IO
†
T
A
SMALL OUTLINE
(D)
SOT-23
(DBV)
PLASTIC DIP
(P)
AT 25°C
2000 µV
2000 µV
1500 µV
SYMBOL
TLV2460CD
TLV2461CD
TLV2460CDBV
TLV2461CDBV
VAOC
VAPC
TLV2460CP
TLV2461CP
0°C to 70°C
TLV2460ID
TLV2461ID
TLV2460IDBV
TLV2461IDBV
VAOI
VAPI
TLV2460IP
TLV2461IP
−40°C to 125°C
TLV2460AID
TLV2461AID
—
—
—
—
TLV2460AIP
TLV2461AIP
†
‡
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2460CDR).
Chip forms are tested at T = 25°C only.
A
TLV2460M/AM/Q/AQ and TLV2461M/AM/Q/AQ AVAILABLE OPTIONS
PACKAGED DEVICES
V
max
SMALL
OUTLINE
(D)
SMALL
OUTLINE
(PW)
CERAMIC
FLATPACK
(U)
IO
T
A
CERAMIC DIP
(JG)
CHIP CARRIER
(FK)
†
†
AT 25°C
TLV2460QD
TLV2461QD
TLV2460QPW
TLV2461QPW
—
—
—
—
—
—
2000 µV
1500 µV
2000 µV
1500 µV
−40°C to 125°C
TLV2460AQD
TLV2461AQD
TLV2460AQPW
TLV2461AQPW
—
—
—
—
—
—
—
—
—
—
TLV2460MJG
TLV2461MJG
TLV2460MU
TLV2461MU
TLV2460MFK
TLV2461MFK
−55°C to 125°C
—
—
—
—
TLV2460AMJG
TLV2461AMJG
TLV2460AMU
TLV2461AMU
TLV2460AMFK
TLV2461AMFK
†
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2460QDR).
TLV2462C/I/AI and TLV2463C/I/AI AVAILABLE OPTIONS
PACKAGED DEVICES
V
max
SMALL
OUTLINE
(D)
IO
†
T
MSOP
(DGK)
MSOP
PLASTIC DIP
(N)
PLASTIC DIP
(P)
A
†
AT 25°C
SYMBOL
xxTIAAI
xxTIAAJ
SYMBOL
(DGS)
TLV2462CD
TLV2463CD
TLV2462CDGK
—
—
—
—
TLV2462CP
—
0°C to 70°C
2000 µV
2000 µV
1500 µV
TLV2463CDGS xxTIAAK
TLV2463CN
TLV2462ID
TLV2463ID
TLV2462IDGK
—
—
—
xxTIAAL
—
TLV2462IP
—
TLV2463IDGS
TLV2463IN
−40°C to
125°C
TLV2462AID
TLV2463AID
—
—
—
—
—
—
—
—
—
TLV2462AIP
—
TLV2463AIN
†
‡
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2462CDR).
Chip forms are tested at T = 25°C only.
A
2
WWW.TI.COM
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SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TLV2462M/AM/Q/AQ and TLV2463M/AM/Q/AQ AVAILABLE OPTIONS
PACKAGED DEVICES
V
max
SMALL
OUTLINE
(D)
SMALL
OUTLINE
(PW)
CERAMIC
DIP
CERAMIC
FLATPACK
(U)
CHIP CAR-
RIER
IO
T
A
CERAMIC DIP
(JG)
†
†
AT 25°C
(J)
(FK)
TLV2462QD
TLV2463QD
TLV2462QPW
TLV2463QPW
—
—
—
—
—
—
—
—
2000 µV
1500 µV
2000 µV
1500 µV
−40°C to 125°C
TLV2462AQD
TLV2463AQD
TLV2462AQPW
TLV2463AQPW
—
—
—
—
—
—
—
—
—
—
—
—
TLV2462MJG
—
—
TLV2462MU
TLV2462MFK
TLV2463MFK
TLV2463MJ
−55°C to 125°C
—
—
—
—
TLV2462AMJG
—
—
TLV2462AMU
TLV2462AMFK
TLV2463AMFK
TLV2463AMJ
†
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2462QDR).
TLV2464C/I/AI and TLV2465C/I/AI AVAILABLE OPTIONS
PACKAGED DEVICES
V
max
IO
T
SMALL OUTLINE
(D)
PLASTIC DIP
(N)
TSSOP
(PW)
A
AT 25°C
2000 µV
2000 µV
1500 µV
TLV2464CD
TLV2465CD
TLV2464CN
TLV2465CN
TLV2464CPW
TLV2465CPW
0°C to 70°C
TLV2464ID
TLV2465ID
TLV2464IN
TLV2465IN
TLV2464IPW
TLV2465IPW
−40°C to 125°C
TLV2464AID
TLV2465AID
TLV2464AIN
TLV2465AIN
TLV2464AIPW
TLV2465AIPW
†
‡
This package is available taped and reeled. To order this packaging option, add an R suffix to the part
number(e.g., TLV2464CDR).
Chip forms are tested at T = 25°C only.
A
TLV2464M/AM/Q/AQ and TLV2465M/AM/Q/AQ AVAILABLE OPTIONS
PACKAGED DEVICES
SMALL
V
IO
max
SMALL
OUTLINE
(D)
T
A
CERAMIC DIP
CHIP CARRIER
(FK)
†
†
AT 25°C
OUTLINE
(PW)
(J)
TLV2464QD
TLV2465QD
TLV2464QPW
TLV2465QPW
—
—
—
—
2000 µV
1500 µV
2000 µV
1500 µV
-40°C to 125°C
TLV2464AQD
TLV2465AQD
TLV2464AQPW
TLV2465AQPW
—
—
—
—
—
—
—
—
TLV2464MJ
TLV2465MJ
TLV2464MFK
TLV2465MFK
−55°C to 125°C
—
—
—
—
TLV2464AMJ
TLV2465AMJ
TLV2464AMFK
TLV2465AMFK
†
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number
(e.g., TLV2464QDR).
3
WWW.TI.COM
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SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
(1)
TLV246x PACKAGE PINOUTS
TLV2460
DBV PACKAGE
(TOP VIEW)
TLV2460
D, P, JG, OR PW PACKAGE
(TOP VIEW)
TLV2461
DBV PACKAGE
(TOP VIEW)
1
2
3
1
2
3
6
5
4
V
5
V
DD+
OUT
GND
OUT
GND
NC
SHDN
1
2
3
4
8
7
6
5
DD+
IN−
IN+
V
+
DD
SHDN
IN−
OUT
NC
GND
4
IN−
IN+
IN+
TLV2463
TLV2461
TLV2462
DGS PACKAGE
(TOP VIEW)
D, P, JG, OR PW PACKAGE
(TOP VIEW)
D, DGK, P, JG, OR PW PACKAGE
(TOP VIEW)
1
1OUT
1IN−
1IN+
GND
V
2OUT
2IN−
2IN+
2SHDN
+
DD
10
NC
IN−
NC
V
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
GND
V
+
DD
1
2
3
4
8
7
6
5
2
3
4
5
9
8
7
6
+
2OUT
2IN−
2IN+
DD
IN+
OUT
NC
GND
1SHDN
TLV2463
D, N, J, OR PW PACKAGE
TLV2465
D, N, PWP, J, OR PW PACKAGE
TLV2464
D, N, PWP, J, OR PW PACKAGE
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
1OUT
1IN−
1IN+
GND
NC
V
+
1OUT
1IN−
1IN+
4OUT
4IN−
1
2
3
4
5
6
7
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DD
1
2
3
4
5
6
7
14
13
12
11
10
9
1OUT
1IN−
1IN+
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
2OUT
2IN−
2IN+
NC
4IN+
V
+
GND
DD
V
+
DD
2IN+
2IN−
3IN+
2IN+
2IN−
1SHDN
NC
2SHDN
NC
3IN−
8
2OUT
3OUT
3/4SHDN
8
2OUT
1/2SHDN
NC − No internal connection
(1) SOT−23 may or may not be indicated
TYPICAL PIN 1 INDICATORS
Pin 1
Printed or
Molded Dot
Pin 1
Pin 1
Pin 1
Stripe
Bevel Edges
Molded ”U” Shape
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ꢍꢌꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑ ꢒꢓꢔꢑ ꢒ ꢕꢖ ꢖꢌꢏ ꢁ ꢓꢀꢑ ꢓꢖꢌꢏ ꢁ ꢏꢗ ꢔꢘꢀꢙ ꢑ ꢘ ꢀꢔ ꢘꢀ
ꢑ ꢔꢕꢖ ꢌꢀ ꢏꢑ ꢗꢌꢁ ꢌꢎ ꢔꢁ ꢏꢍ ꢏꢕ ꢖꢚ ꢒ ꢏꢀ ꢛ ꢚꢛꢘ ꢀꢜ ꢑ ꢒꢗ
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
(1)
TLV246x PACKAGE PINOUTS (continued)
TLV2461
U PACKAGE
(TOP VIEW)
TLV2462
U PACKAGE
(TOP VIEW)
TLV2460
U PACKAGE
(TOP VIEW)
1
2
3
4
5
10
9
1
10
9
1
10
9
NC
NC
IN−
IN+
GND
NC
NC
V
OUTPUT
NC
NC
1OUT
1IN−
1IN+
GND
NC
V
2OUT
2IN−
2IN+
NC
NC
IN−
IN+
GND
NC
SHDN
2
3
4
5
2
3
4
5
DD+
8
8
8
V
DD
DD
7
7
7
OUTPUT
NC
6
6
6
TLV2460
FK PACKAGE
(TOP VIEW)
TLV2461
FK PACKAGE
(TOP VIEW)
TLV2462
FK PACKAGE
(TOP VIEW)
3
2
1
20 19
3
2
1
20 19
3
2
1
20 19
NC
IN−
NC
IN+
NC
NC
V
4
5
6
7
8
18
17
16
15
14
NC
NC
1IN+
NC
2IN−
18
4
18
17
16
15
14
4
5
6
7
8
DD
IN−
NC
IN+
NC
V
NC
5
6
7
8
17
16
15
14
DD
NC
NC
GND
NC
2IN+
NC
OUT
NC
OUT
NC
NC
NC
9
10 11 12 13
9
10 11 12 13
9
10 11 12 13
TLV2463
FK PACKAGE
(TOP VIEW)
TLV2465
FK PACKAGE
(TOP VIEW)
TLV2464
FK PACKAGE
(TOP VIEW)
3
2
1
20 19
3
2
1
20 19
3
2
1
20 19
1IN+
4IN+
18
4
5
6
7
8
1IN+
NC
4IN+
NC
1IN+
NC
2IN−
NC
4
5
6
7
8
18
17
16
15
14
4
18
17
16
15
14
V
GND
NC
17
16
15
14
DD+
NC
5
6
7
8
V
GND
NC
GND
NC
2IN+
NC
DD+
NC
2IN+
2IN−
3IN+
3IN−
2IN+
3IN+
NC
NC
9
10 11 12 13
9
10 11 12 13
9
10 11 12 13
NC − No internal connection
(1) SOT−23 may or may not be indicated
5
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SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Differential input voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.2 V to V
+ 0.2 V
200 mA
175 mA
ID
DD
Input current, I (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Total input current, I (into V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 mA
I
DD+
Total output current, I (out of GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
O
Operating free-air temperature range, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
I and Q suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to GND.
DISSIPATION RATING TABLE FOR C and I SUFFIX
≤ 25°C T < 125°C
A
θ
JC
θ
JA
T
A
PACKAGE
POWER RATING
POWER RATING
(°C/W)
(°C/W)
D (8)
38.3
176
710 mW
142 mW
D (14)
D (16)
DBV (5)
DBV (6)
DGK
26.9
25.7
55
122.6
114.7
324.1
294.3
259.9
1022 mW
1090 mW
385 mW
425 mW
481 mW
204.4 mW
218 mW
77.1 mW
84.9 mW
96.2 mW
55
54.2
DGS
N (14, 16)
P (8)
54.1
32
257.7
78
485 mW
1600 mW
1200 mW
720 mW
774 mW
97 mW
320.5 mW
240.4 mW
144 mW
41
104
PW (14)
PW (16)
29.3
28.7
173.6
161.4
154.9 mW
NOTE: Thermal resistances are not production tested and are for informational
purposes only.
DISSIPATION RATING TABLE FOR Q and M SUFFIX
T
≤ 25°C
DERATING FACTOR
‡
T
= 70°C
T
= 85°C
T = 125°C
A
POWER RATING
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
POWER RATING
A
FK
JG
U
1375 mW
11.0 mW/°C
8.4 mW/°C
5.4 mW/°C
880 mW
715 mW
275 mW
1050 mW
672 mW
546 mW
210 mW
675 mW
432 mW
350 mW
135 mW
‡
This is the inverse of the traditional junction-to-ambient thermal resistance (RΘ ). Thermal resistances are not production tested and are for
informational purposes only.
JA
6
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ꢑ ꢔꢕꢖ ꢌꢀ ꢏꢑ ꢗꢌꢁ ꢌꢎ ꢔꢁ ꢏꢍ ꢏꢕ ꢖꢚ ꢒ ꢏꢀ ꢛ ꢚꢛꢘ ꢀꢜ ꢑ ꢒꢗ
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
recommended operating conditions
MIN
2.7
1.35
0
MAX
UNIT
Single supply
Split supply
6
3
Supply voltage, V
DD
V
V
Common-mode input voltage range, V
ICR
V
DD
70
C-suffix
0
Operating free-air temperature, T
I-suffix and Q-suffix
M-suffix
−40
−55
2
125
125
°C
A
V
V
IH
‡
Shutdown on/off voltage level
V
0.7
IL
‡
Relative to voltage on the GND terminal of the device.
electrical characteristics at specified free-air temperature, V
= 3 V (unless otherwise noted)
DD
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2000
2200
1500
1700
T
A
UNIT
25°C
Full range
25°C
500
V
V
V
= 3 V,
DD
IC
V
IO
Input offset voltage
µV
= 1.5 V,
= 1.5 V,
= 50 Ω
500
O
TLV246xA
TLV246xC
Full range
R
S
α
VIO
Temperature coefficient of input offset voltage
Input offset current
2
µV/°C
25°C
2.8
7
20
75
14
25
75
Full range
I
IO
nA
V
V
V
= 3 V,
DD
TLV246xI/Q/M Full range
= 1.5 V,
= 1.5 V,
= 50 Ω
IC
25°C
4.4
O
R
S
TLV246xC
Full range
I
Input bias current
nA
V
IB
TLV246xI/Q/M Full range
25°C
Full range
25°C
2.9
2.7
0.1
0.3
50
I
I
= −2.5 mA
= −10 mA
= 1.5 V,
OH
2.8
2.5
V
V
High-level output voltage
OH
OH
Full range
25°C
V
V
I
I
= 2.5 mA
= 10 mA
IC
OL
Full range
25°C
0.2
0.5
Low-level output voltage
V
OL
= 1.5 V,
IC
OL
Full range
25°C
Sourcing
Sinking
Full range
25°C
20
20
I
I
Short-circuit output current
Output current
mA
mA
OS
40
Full range
25°C
Measured 1 V from rail
= 10 kΩ,
40
O
25°C
90
89
105
Large-signal differential voltage
amplification
A
VD
R
dB
V
= 1 V
L
O(PP)
Full range
9
10
Ω
r
Differential input resistance
25°C
i(d)
†
Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix.
7
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SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, V
(continued)
= 3 V (unless otherwise noted)
DD
†
PARAMETER
TEST CONDITIONS
f = 10 kHz
f = 100 kHz,
= 0 to 3 V,
MIN
TYP
MAX
T
A
UNIT
pF
Common-mode input
capacitance
c
z
25°C
7
i(c)
o
Ω
Closed-loop output impedance
A
= 10
25°C
25°C
33
80
V
66
64
60
80
75
85
80
V
ICR
TLV246xC
Full range
CMRR
Common-mode rejection ratio
dB
dB
R
= 50 Ω
S
TLV246xI/Q/M Full range
25°C
Full range
25°C
85
95
V
= 2.7 V to 6 V,
V
IC
= V
/2,
DD
DD
No load
Supply voltage rejection ratio
k
SVR
(∆V
DD
/∆V )
IO
V
= 3 V to 5 V,
V
= V
/2,
DD
No load
IC
DD
Full range
25°C
0.5 0.575
I
I
Supply current (per channels)
V
O
= 1.5 V,
No load
mA
DD
Full range
25°C
0.9
0.3
2.5
Supply current in shutdown
(TLV2460, TLV2463, TLV2465)
SHDN < 0.7 V,
Per channel in shutdown
µA
DD(SHDN)
Full range
†
Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix.
operating characteristics at specified free-air temperature, V
= 3 V (unless otherwise noted)
DD
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
T
A
25°C
0.9
1.6
V
R
= 0.8 V,
C
= 160 pF,
L
O(PP)
= 10 kΩ
SR
Slew rate at unity gain
V/µs
Full
range
0.8
L
f = 100 Hz
f = 1 kHz
f = 1 kHz
25°C
25°C
25°C
16
11
nV/√Hz
pA/√Hz
V
I
Equivalent input noise voltage
Equivalent input noise current
n
0.13
n
A
= 1
0.006%
0.02%
0.08%
7.6
V
Total harmonic distortion plus
noise
V
R
= 2 V,
= 10 kΩ, f = 1 kHz
O(PP)
L
A
V
= 10
= 100
THD + N
25°C
25°C
A
V
Both channels
t
Amplifier turnon time
A
V
= 1, R = 10 kΩ
µs
Channel 1 only,
Channel 2 on
(on)
L
7.65
333
328
Both channels
Channel 1 only,
Channel 2 on
t
(off)
Amplifier turnoff time
A
V
= 1, R = 10 kΩ
25°C
25°C
ns
L
Channel 2 only,
Channel 1 on
329
5.2
R
= 10 kΩ,
L
Gain-bandwidth product
MHz
f = 10 kHz, C = 160 pF
L
V
= 2 V,
0.1%
1.47
1.78
1.77
1.98
(STEP)PP
A
= −1,
C
L
= 10 pF,
V
0.01%
0.1%
R
= 10 kΩ
L
t
s
Settling time
25°C
µs
V
= 2 V,
(STEP)PP
= −1, C = 56 pF,
L
A
V
0.01%
R
= 10 kΩ
L
φ
m
Phase margin at unity gain
Gain margin
25°C
25°C
44°
R
= 10 kΩ,
C
= 160 pF
L
L
7
dB
†
Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix.
8
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SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2000
2200
1500
1700
T
A
UNIT
25°C
Full range
25°C
500
V
V
V
= 5 V,
DD
V
IO
Input offset voltage
µV
500
= 2.5,
= 2.5 V,
= 50 Ω
IC
TLV246xA
O
Full range
R
S
Temperature coefficient of input off-
set voltage
α
VIO
25°C
2
µV/°C
25°C
0.3
7
15
60
14
30
60
TLV246xC
Full range
I
Input offset current
Input bias current
nA
IO
V
V
V
= 5 V,
DD
TLV246xI/Q/M Full range
= 2.5 V,
= 2.5 V,
= 50 Ω
IC
25°C
1.3
O
R
S
TLV246xC
Full range
I
nA
V
IB
TLV246xI/Q/M Full range
25°C
Full range
25°C
4.9
4.8
0.1
0.2
145
100
I
I
= −2.5 mA
= −10 mA
= 2.5 V,
OH
4.8
4.7
V
High-level output voltage
Low-level output voltage
OH
OL
OH
Full range
25°C
V
V
I
I
= 2.5 mA
= 10 mA
IC
OL
Full range
25°C
0.2
0.3
V
V
= 2.5 V,
IC
OL
Full range
25°C
Sourcing
Full range
25°C
60
60
I
I
Short-circuit output current
Output current
mA
OS
Sinking
Full range
25°C
Measured at 1 V from rail
80
mA
dB
O
25°C
92
90
109
Large-signal differential voltage
amplification
V
V
= 2.5 V,
= 1 V to 4 V
R
= 10 kΩ,
IC
O
L
A
VD
Full range
25°C
9
10
r
Differential input resistance
Ω
pF
Ω
i(d)
c
z
Common-mode input capacitance
Closed-loop output impedance
f = 10 kHz
25°C
7
29
85
i(c)
o
f = 100 kHz,
A
= 10
25°C
V
25°C
71
69
60
80
75
85
80
V
R
= 0 V to 5 V,
= 50 Ω
ICR
TLV246xC
Full range
CMRR
Common-mode rejection ratio
dB
S
TLV246xI/Q/M Full range
25°C
Full range
25°C
85
95
V
= 2.7 V to 6 V,
V
= V
/2,
DD
IC
DD
dB
dB
mA
µA
No load
Supply voltage rejection ratio
k
SVR
(∆V
DD
/∆V )
IO
V
= 3 V to 5 V,
V
= V
/2,
DD
No load
IC
DD
Full range
25°C
0.55
1
0.65
1
I
Supply current (per channel)
V
O
= 2.5 V,
No load,
DD
Full range
25°C
Supply current in shutdown
(TLV2460, TLV2463, TLV2465)
SHDN < 0.7 V, Per channels in
shutdown
I
DD(SHDN)
Full range
3
†
Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix.
9
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SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
operating characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
T
A
25°C
0.9
1.6
V
R
= 2 V,
C
= 160 pF,
L
O(PP)
= 10 kΩ
SR
Slew rate at unity gain
V/µs
Full
range
0.8
L
f = 100 Hz
f = 1 kHz
25°C
25°C
25°C
14
11
nV/√Hz
pA/√Hz
V
I
Equivalent input noise voltage
Equivalent input noise current
n
f = 100 Hz
0.13
n
A
= 1
0.004%
0.01%
0.04%
7.6
V
V
R
= 4 V,
O(PP)
= 10 kΩ,
A
V
= 10
= 100
THD + N Total harmonic distortion plus noise
25°C
L
f = 10 kHz
A
V
Both channels
Channel 1 only,
Channel 2 on
7.65
t
Amplifier turnon time
A
= 1, R = 10 kΩ
25°C
µs
(on)
(off)
V
L
Channel 2 only,
Channel 1 on
7.25
333
328
Both channels
Channel 1 only,
Channel 2 on
t
Amplifier turnoff time
A
V
= 1, R = 10 kΩ
25°C
25°C
ns
L
Channel 2 only,
Channel 1 on
329
f = 10 kHz,
= 160 pF
R = 10 kΩ,
L
Gain-bandwidth product
6.4
1.53
1.83
3.13
3.33
MHz
C
L
V
= 2 V,
= 2 V,
(STEP)PP
0.1%
A
= −1,
= 10 pF,
= 10 kΩ
V
C
R
L
L
0.01%
0.1%
t
s
Settling time
25°C
µs
V
(STEP)PP
A
= −1,
= 56 pF,
= 10 kΩ
V
C
R
L
L
0.01%
φ
m
Phase margin at unity gain
Gain margin
25°C
25°C
45°
R
= 10 kΩ,
C = 160 pF
L
L
7
dB
†
Full range is 0°C to 70°C for the C suffix, −40°C to 125°C for the I and Q suffixes, and −55°C to 125°C for the M suffix.
10
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SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
V
Input offset voltage
Input bias current
Input offset current
vs Common-mode input voltage
vs Free-air temperature
1, 2
3, 4
3, 4
5, 6
7, 8
9, 10
11, 12
11, 12
13
IO
I
I
IB
vs Free-air temperature
vs High-level output current
vs Low-level output current
vs Frequency
IO
V
V
V
High-level output voltage
Low-level output voltage
OH
OL
Peak-to-peak output voltage
Open-loop gain
O(PP)
vs Frequency
Phase
vs Frequency
A
VD
Differential voltage amplification
Capacitive load
vs Load resistance
vs Load resistance
vs Frequency
14
Z
o
Output impedance
15, 16
17
CMRR
Common-mode rejection ratio
Supply-voltage rejection ratio
vs Frequency
k
vs Frequency
18, 19
20
SVR
vs Supply voltage
vs Free-air temperature
I
Supply current
DD
21
Amplifier turnon characteristics
Amplifier turnoff characteristics
Supply current turnon
Supply current turnoff
Shutdown supply current
Slew rate
22
23
24
25
vs Free-air temperature
vs Supply voltage
26
SR
27
vs Frequency
28, 29
30, 31
V
n
Equivalent input noise voltage
vs Common-mode input voltage
THD
Total harmonic distortion
vs Frequency
32, 33
34, 35
11, 12
THD+N
Total harmonic distortion plus noise
vs Peak-to-peak signal amplitude
vs Frequency
φ
m
Phase margin
vs Load capacitance
vs Free-air temperature
vs Supply voltage
36
37
38
Gain bandwidth product
vs Free-air temperature
39
Large signal follower
Small signal follower
Inverting large signal
Inverting small signal
40, 41
42, 43
44, 45
46, 47
11
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SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
1
0.8
0.6
0.4
1
0.8
0.6
0.4
V
T
= 3 V
= 25°C
DD
A
V
T
A
= 5 V
= 25°C
DD
0.2
0
0.2
0
−0.2
−0.4
−0.6
−0.2
−0.4
−0.6
−0.8
−1
−0.8
−1
0
0.5
1
1.5
2
2.5
3
0
1
2
3
4
5
V
ICR
− Common-Mode Input Voltage − V
V
ICR
− Common-Mode Input Voltage − V
Figure 1
Figure 2
INPUT BIAS AND INPUT OFFSET CURRENT
INPUT BIAS AND INPUT OFFSET CURRENT
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
5
4.5
4
6
5
4
3
V
= 3 V
DD
V = 1.5 V
V
= 5 V
DD
V = 2.5 V
I
I
IB
I
I
IB
3.5
3
2.5
2
2
1
1.5
1
0.5
0
I
IO
I
IO
0
−0.5
−1
−55 −35 −15
5
25
45
65
85 105 125
−55 −35 −15
5
25
45
65
85 105 125
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 3
Figure 4
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ꢑ ꢔꢕꢖ ꢌꢀ ꢏꢑ ꢗꢌꢁ ꢌꢎ ꢔꢁ ꢏꢍ ꢏꢕ ꢖꢚ ꢒ ꢏꢀ ꢛ ꢚꢛꢘ ꢀꢜ ꢑ ꢒꢗ
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3
5
V
= 3 V
DC
DD
V
= 5 V
DC
DD
4.5
4
2.5
T
A
= −55°C
T = −55°C
A
3.5
3
2
1.5
1
T
T
= 125°C
A
T = 125°C
A
2.5
= 85°C
A
T
A
= 85°C
2
T
= 25°C
A
T
A
= 25°C
1.5
1
T
= −40°C
A
T = −40°C
A
0.5
0
0.5
0
0
10
20
30
40
50
60
70
80
0
20 40 60 80 100 120 140 160 180 200
I
− High-Level Output Current − mA
OH
I
− High-Level Output Current − mA
OH
Figure 5
Figure 6
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
3
4.5
4
V
DD
= 3 V
DC
V
DD
= 5 V
DC
2.5
T
= −40°C
T
= −40°C
A
A
3.5
3
2
1.5
1
T
= 25°C
= 85°C
A
T
= 25°C
= 85°C
A
2.5
2
T
T
A
T
T
A
A
A
= 125°C
= 125°C
1.5
1
0.5
0
T
= −55°C
A
0.5
0
T
A
= −55°C
0
10
20
30
40
50
60
70
0
20
40
60
80
100 120 140 160
I
− Low-Level Output Current − mA
OL
I
− Low-Level Output Current − mA
OL
Figure 7
Figure 8
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SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
PEAK-TO-PEAK OUTPUT VOLTAGE
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
vs
FREQUENCY
FREQUENCY
3
2.5
2
5.5
5
V
= 3 V
DD
= −10
V
= 5 V
DD
A = −10
V
A
V
THD = 1%
= 10 kΩ
THD = 1%
R = 10 kΩ
L
4.5
4
R
L
3.5
3
1.5
2.5
2
1.5
1
1
0.5
0
0.5
0
10k
100k
1M
10M
10k
100k
1M
10M
f − Frequency − Hz
f − Frequency − Hz
Figure 9
Figure 10
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
100
90
80
70
60
50
40
40°
V
R
C
= 1.5 V
= 10 kΩ
= 0
DD
L
L
20°
0°
T
A
= 25°C
−20°
−40°
−60°
−80°
−100°
A
VD
30
20
Phase
−120°
−140°
−160°
−180°
−200°
10
0
−10
−20
10
100
1k
10k
100k
1M
10M
f − Frequency − Hz
Figure 11
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ꢍꢌꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑ ꢒꢓꢔꢑ ꢒ ꢕꢖ ꢖꢌꢏ ꢁ ꢓꢀꢑ ꢓꢖꢌꢏ ꢁ ꢏꢗ ꢔꢘꢀꢙ ꢑ ꢘ ꢀꢔ ꢘꢀ
ꢑ ꢔꢕꢖ ꢌꢀ ꢏꢑ ꢗꢌꢁ ꢌꢎ ꢔꢁ ꢏꢍ ꢏꢕ ꢖꢚ ꢒ ꢏꢀ ꢛ ꢚꢛꢘ ꢀꢜ ꢑ ꢒꢗ
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
100
90
80
70
60
50
40
40°
V
R
C
=
2.5 V
DD
L
L
20°
0°
= 10 kΩ
= 0
= 25°C
T
A
−20°
−40°
−60°
−80°
−100°
A
VD
30
20
Phase
−120°
−140°
−160°
−180°
−200°
10
0
−10
−20
10
100
1k
10k
100k
1M
10M
f − Frequency − Hz
Figure 12
DIFFERENTIAL VOLTAGE AMPLIFICATION
CAPACITIVE LOAD
vs
LOAD RESISTANCE
vs
LOAD RESISTANCE
180
160
140
120
100
80
10000
1000
100
T
= 25°C
A
Phase Margin < 30°
V
= 2.5 V
DD
V
DD
= 1.5 V
60
Phase Margin > 30°
40
V
= 5 V
DD
Phase Margin = 30°
= 25°C
20
T
A
0
100
1k
10k
100k
1M
10
100
1k
10k
R
− Load Resistance − Ω
L
R − Load Resistance − Ω
L
Figure 13
Figure 14
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ꢁ
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ꢃ
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ꢅ
ꢖ
ꢚ
ꢉ
ꢌ
ꢛ
ꢇ
ꢏ
ꢘ
ꢀ
ꢁ
ꢀ
ꢁ
ꢂ
ꢔ
ꢑ
ꢃ
ꢄ
ꢘ
ꢒ
ꢅ
ꢀ
ꢗ
ꢄ
ꢙ
ꢇ
ꢑ
ꢀ
ꢘ
ꢁ
ꢀ
ꢂ
ꢔ
ꢃ
ꢘ
ꢄ
ꢅ
ꢀ
ꢊ
ꢇ
ꢀ
ꢁꢂ
ꢃ
ꢄ
ꢅ
ꢋ
ꢌ
ꢍ
ꢌ
ꢁ
ꢐ
ꢏ
ꢁ
ꢓ
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ꢏ
ꢗ
ꢑ
ꢔ
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SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
OUTPUT IMPEDANCE
vs
OUTPUT IMPEDANCE
vs
FREQUENCY
FREQUENCY
1000
100
10
1000
100
10
V
T
A
= 1.5 V
= 25°C
DD
V
T
A
= 2.5 V
= 25°C
DD
A
V
= 100
A
V
= 100
= 10
1
1
A
V
= 10
= 1
A
V
0.1
A
V
0.1
A
V
= 1
0.01
0.01
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
f − Frequency − Hz
f − Frequency − Hz
Figure 15
Figure 16
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
90
85
80
75
V
V
= 5 V
DD
= 2.5 V
IC
V
V
= 3 V
DD
= 1.5 V
IC
70
65
60
10
100
1k
10k
100k
1M
10M
f − Frequency − Hz
Figure 17
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ꢍꢌꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑ ꢒꢓꢔꢑ ꢒ ꢕꢖ ꢖꢌꢏ ꢁ ꢓꢀꢑ ꢓꢖꢌꢏ ꢁ ꢏꢗ ꢔꢘꢀꢙ ꢑ ꢘ ꢀꢔ ꢘꢀ
ꢑ ꢔꢕꢖ ꢌꢀ ꢏꢑ ꢗꢌꢁ ꢌꢎ ꢔꢁ ꢏꢍ ꢏꢕ ꢖꢚ ꢒ ꢏꢀ ꢛ ꢚꢛꢘ ꢀꢜ ꢑ ꢒꢗ
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
SUPPLY-VOLTAGE REJECTION RATIO
SUPPLY-VOLTAGE REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
110
100
90
80
70
+k
SVR
+k
SVR
V
T
A
=
1.5 V
DD
V
T
=
2.5 V
DD
A
= 25°C
= 25°C
−k
SVR
90
80
70
60
−k
SVR
60
50
40
+k
SVR
+k
SVR
50
40
−k
SVR
−k
SVR
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
f − Frequency − Hz
f − Frequency − Hz
Figure 18
Figure 19
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
0.8
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
I
= 125°C
DD
I
= 85°C
DD
0.7
0.6
V
= 5 V
DD
V = 2.5 V
I
0.5
0.40
0.30
V
= 3 V
DD
V = 1.5 V
I
I
I
= 25°C
DD
I
= −55°C
DD
= −40°C
DD
0.20
0.10
0.35
0.30
2.5
3
3.5
4
4.5
5
5.5
6
−55 −35 −15
5
25
45
65
85 105 125
V
DD
− Supply Voltage − V
T
A
− Free-Air Temperature − °C
Figure 20
Figure 21
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SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
AMPLIFIER WITH A SHUTDOWN PULSE
AMPLIFIER WITH A SHUTDOWN PULSE
TURNOFF CHARACTERISTICS
TURNON CHARACTERISTICS
5
4
3
2
1
0
3
2
5
4
3
2
1
0
3
2
V
R
= 5 V
= 10 kΩ
= 1
DD
L
Shutdown Pin
Shutdown Pin
A
V
A
T
= 25°C
Amplifier Output
Amplifier Output
V
R
= 5 V
= 10 kΩ
= 1
DD
L
A
V
A
1
0
T
= 25°C
1
0
−5
−3
−1
1
3
5
7
9
11
−5
−3
−1
1
3
5
7
t − Time − µs
t − Time − µs
Figure 22
Figure 23
SUPPLY CURRENT WITH A SHUTDOWN PULSE
TURNON CHARACTERISTICS
1
5.5
Shutdown Pin
0.8
4.5
3.5
2.5
1.5
0.6
0.4
Supply Current
0.2
0
V
= 5 V
DD
V = 2.5 V
0.5
I
A
= 1
= 25°C
V
T
A
−0.2
−0.5
−0.4
−0.2
0
0.2
0.4
0.6
t − Time − µs
Figure 24
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ꢍꢌꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑ ꢒꢓꢔꢑ ꢒ ꢕꢖ ꢖꢌꢏ ꢁ ꢓꢀꢑ ꢓꢖꢌꢏ ꢁ ꢏꢗ ꢔꢘꢀꢙ ꢑ ꢘ ꢀꢔ ꢘꢀ
ꢑ ꢔꢕꢖ ꢌꢀ ꢏꢑ ꢗꢌꢁ ꢌꢎ ꢔꢁ ꢏꢍ ꢏꢕ ꢖꢚ ꢒ ꢏꢀ ꢛ ꢚꢛꢘ ꢀꢜ ꢑ ꢒꢗ
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
TURNOFF SUPPLY CURRENT
WITH A SHUTDOWN PULSE
1
5.5
4.5
V
= 5 V
DD
V = 2.5 V
I
Shutdown Pin
Supply Current
A
= 1
= 25°C
V
A
0.8
T
0.6
0.4
3.5
2.5
0.2
0
1.5
0.5
−0.2
−0.5
0.6
−0.4
−0.2
0
0.2
0.4
t − Time − µs
Figure 25
SHUTDOWN SUPPLY CURRENT
vs
SLEW RATE
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
3
2.5
2
1.8
1.75
1.7
1.65
1.6
V
= 5 V
DD
V = 2.5 V
SR+
I
1.5
1
1.55
SR−
V
= 3 V
DD
1.5
1.45
1.4
0.5
V = 1.5 V
I
V
C
= 2 V
= 160 pF
= 1
= 10 kΩ
= 25°C
O(PP)
L
0
−0.5
−1
A
V
R
L
1.35
1.3
T
A
−55 −35 −15
5
25
45
65
85 105 125
2.5
3
3.5
4
4.5
5
5.5
6
T
A
− Free-Air Temperature − °C
V
DD
− Supply Voltage − V
Figure 26
Figure 27
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SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
EQUIVALENT INPUT NOISE VOLTAGE
EQUIVALENT INPUT NOISE VOLTAGE
vs
vs
FREQUENCY
FREQUENCY
18
17
18
17
V
= 3 V
DD
= 10
V
= 5 V
DD
A = 10
V
A
V
V = 1.5 V
I
A
V = 2.5 V
I
T
= 25°C
T = 25°C
A
16
15
14
16
15
14
13
12
13
12
11
10
11
10
100
1k
10k
100k
100
1k
10k
100k
f − Frequency − Hz
f − Frequency − Hz
Figure 28
Figure 29
EQUIVALENT INPUT NOISE VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
EQUIVALENT INPUT NOISE VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
20
20
15
14
13
12
V
= 3 V
DD
= 10
V
= 5 V
DD
A = 10
V
A
V
f = 1 kHz
f = 1 kHz
15
14
13
12
T
A
= 25°C
T
A
= 25°C
11
10
11
10
0
0.5
1
1.5
2
2.5
3
0
1
2
3
4
5
V
ICR
− Common-Mode Input Voltage − V
V
ICR
− Common-Mode Input Voltage − V
Figure 30
Figure 31
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ꢍꢌꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑ ꢒꢓꢔꢑ ꢒ ꢕꢖ ꢖꢌꢏ ꢁ ꢓꢀꢑ ꢓꢖꢌꢏ ꢁ ꢏꢗ ꢔꢘꢀꢙ ꢑ ꢘ ꢀꢔ ꢘꢀ
ꢑ ꢔꢕꢖ ꢌꢀ ꢏꢑ ꢗꢌꢁ ꢌꢎ ꢔꢁ ꢏꢍ ꢏꢕ ꢖꢚ ꢒ ꢏꢀ ꢛ ꢚꢛꢘ ꢀꢜ ꢑ ꢒꢗ
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION
vs
vs
FREQUENCY
FREQUENCY
0.5
0.1
1
V
V
R
=
1.5 V
= 2 V
DD
O(PP)
L
V
V
=
2.5 V
= 4 V
DD
O(PP)
L
= 10 kΩ
R = 10 kΩ
A
= 100
= 10
= 1
V
0.1
A
V
= 100
= 10
= 1
A
V
A
V
0.010
0.001
A
V
0.010
0.001
A
V
10
100
1k
10k
100k
10
100
1k
10k
100k
f − Frequency − Hz
f − Frequency − Hz
Figure 32
Figure 33
TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
vs
PEAK-TO-PEAK SIGNAL AMPLITUDE
PEAK-TO-PEAK SIGNAL AMPLITUDE
1
1
R
= 250 Ω
V
= 3 V
L
DD
= 1
R
= 250 Ω
A
L
V
TA = 25°C
R
= 2 kΩ
L
R
= 2 kΩ
L
0.1
0.1
R
= 10 kΩ
L
R
= 10 kΩ
L
0.010
0.001
0.010
0.001
R
= 100 kΩ
R
= 100 kΩ
L
L
V
= 5 V
DD
= 1
A
V
A
T
= 25°C
1
1.2 1.4 1.6 1.8
2
2.2 2.4 2.6 2.8
3
3.2
4
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9
Peak-to-Peak Signal Amplitude − V
5
Peak-to-Peak Signal Amplitude − V
Figure 34
Figure 35
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SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
LOAD CAPACITANCE
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
90
80
70
60
50
40
30
20
10
0
60
55
50
V
T
R
=
2.5 V
DD
A
L
R
C
= 10 kΩ
= 160 pF
L
L
= 25°C
= 10 kΩ
R
= 50 Ω
null
V
V
=
=
2.5 V
1.5 V
DD
45
40
R
= 20 Ω
null
DD
R
= 0 Ω
null
35
30
10
100
1k
10k
100k
−55 −35 −15
5
25
45
65
85 105 125
C
L
− Load Capacitance − pF
T
A
− Free-Air Temperature − °C
Figure 36
Figure 37
GAIN BANDWIDTH PRODUCT
GAIN BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
vs
SUPPLY VOLTAGE
5
5
C
R
= 160 pF
= 10 kΩ
L
L
R
C
= 10 kΩ
= 160 pF
L
L
4.75
f = 10 kHz
4.75
4.5
4.25
4
T
A
= 25°C
V
=
2.5 V
DD
4.5
4.25
4
3.75
3.5
V
DD
= 1.5 V
3.75
3.5
3.25
3
2.5
3
3.5
4
4.5
5
5.5
6
−55 −35 −15
5
25
45
65
85 105 125
V
DD
− Supply Voltage − V
T
A
− Free-Air Temperature − °C
Figure 38
Figure 39
22
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ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢀꢁꢂꢃ ꢄ ꢅ ꢈ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢉ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢄ ꢇ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢊ ꢇ ꢀꢁꢂ ꢃꢄ ꢅꢋ ꢌ
ꢍꢌꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑ ꢒꢓꢔꢑ ꢒ ꢕꢖ ꢖꢌꢏ ꢁ ꢓꢀꢑ ꢓꢖꢌꢏ ꢁ ꢏꢗ ꢔꢘꢀꢙ ꢑ ꢘ ꢀꢔ ꢘꢀ
ꢑ ꢔꢕꢖ ꢌꢀ ꢏꢑ ꢗꢌꢁ ꢌꢎ ꢔꢁ ꢏꢍ ꢏꢕ ꢖꢚ ꢒ ꢏꢀ ꢛ ꢚꢛꢘ ꢀꢜ ꢑ ꢒꢗ
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
LARGE SIGNAL FOLLOWER
LARGE SIGNAL FOLLOWER
2.2
2
3.7
3.3
Input
Input
1.8
1.6
1.4
1.2
2.9
2.5
2.1
Output
Output
V
V
= 5 V
DD
I(PP)
V
V
= 3 V
DD
I(PP)
Input
Input
= 2 V
V = 2.5 V
= 1 V
V = 1.5 V
I
R
C
I
R
C
= 10 kΩ
= 160 pF
= 1
L
L
Output
Output
= 10 kΩ
= 160 pF
= 1
L
L
1.7
1.3
A
V
A
1
A
V
A
T
= 25°C
T
= 25°C
0.8
−2
0
2
4
6
8
10 12 14 16 18
−2
0
2
4
6
8
10 12 14 16 18
t − Time − µs
t − Time − µs
Figure 40
Figure 41
SMALL SIGNAL FOLLOWER
SMALL SIGNAL FOLLOWER
1.6
2.6
2.55
2.5
1.55
1.5
Input
Input
Output
Output
1.45
1.4
2.45
2.4
V
V
= 3 V
= 100 mV
V
V
= 5 V
= 100 mV
DD
I(PP)
DD
I(PP)
C
A
T
A
= 160 pF
= 1
= 25°C
C
A
T
A
= 160 pF
= 1
= 25°C
L
V
L
V
V = 1.5 V
V = 2.5 V
I
I
R
= 10 kΩ
R = 10 kΩ
L
L
−0.2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
−0.2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
t − Time − µs
t − Time − µs
Figure 42
Figure 43
23
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ꢍ
ꢌ
ꢁ
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SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
INVERTING LARGE SIGNAL
INVERTING LARGE SIGNAL
Input
4
2.3
Input
2.1
1.9
1.7
1.5
1.3
1.1
0.9
3.5
3
V
V
= 3 V
= 1 V
V
V
= 5 V
= 2 V
DD
I(PP)
DD
I(PP)
V = 1.5 V
V = 2.5 V
I
I
R
C
= 10 kΩ
= 160 pF
= −1
R
C
= 10 kΩ
= 160 pF
= −1
L
L
L
L
2.5
2
A
A
V
A
V
A
T
= 25°C
T
= 25°C
Output
Output
1.5
1
0.7
0.5
−0.2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
−0.2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
t − Time − µs
t − Time − µs
Figure 44
Figure 45
INVERTING SMALL SIGNAL
INVERTING SMALL SIGNAL
1.6
1.55
1.5
2.6
Input
Input
2.55
2.5
V
V
= 3 V
DD
I(PP)
V
V
= 5 V
DD
I(PP)
= 100 mV
V = 1.5 V
= 100 mV
V = 2.5 V
I
R
C
I
R
C
= 10 kΩ
= 160 pF
= −1
L
L
= 10 kΩ
= 160 pF
= −1
L
L
A
V
A
A
V
A
T
= 25°C
T
= 25°C
1.45
1.4
2.45
2.4
Output
Output
−0.2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
−0.2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
t − Time − µs
t − Time − µs
Figure 46
Figure 47
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ꢍꢌꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑ ꢒꢓꢔꢑ ꢒ ꢕꢖ ꢖꢌꢏ ꢁ ꢓꢀꢑ ꢓꢖꢌꢏ ꢁ ꢏꢗ ꢔꢘꢀꢙ ꢑ ꢘ ꢀꢔ ꢘꢀ
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SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
PARAMETER MEASUREMENT INFORMATION
R
_
+
null
R
L
C
L
Figure 48
APPLICATION INFORMATION
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series (R
) with the output of the amplifier, as
NULL
shown in Figure 49. A minimum value of 20 Ω should work well for most applications.
R
F
R
G
_
R
NULL
Input
Output
LOAD
+
C
Figure 49. Driving a Capacitive Load
offset voltage
The output offset voltage, (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times
OO
IO
IB
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
R
F
I
IB−
R
G
+
−
+
V
I
V
O
R
S
I
IB+
R
R
F
F
V
+ V
1 ) ǒ Ǔ " I
R
1 ) ǒ Ǔ " I
R
ǒ Ǔ ǒ Ǔ
OO
IO
IB)
S
IB–
F
R
R
G
G
Figure 50. Output Offset Voltage Model
25
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SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 51).
R
R
F
G
−
V
1
O
+
V
I
R1
V
C1
f
+
–3dB
2pR1C1
R
O
F
1
ǒ
Ǔ
+
ǒ
1 )
Ǔ
V
R
1 ) sR1C1
I
G
Figure 51. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
+
_
V
I
1
R1
R2
f
+
–3dB
2pRC
C2
R
F
1
R
=
G
R
F
2 −
)
R
(
Q
G
Figure 52. 2-Pole Low-Pass Sallen-Key Filter
26
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ꢍꢌꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑ ꢒꢓꢔꢑ ꢒ ꢕꢖ ꢖꢌꢏ ꢁ ꢓꢀꢑ ꢓꢖꢌꢏ ꢁ ꢏꢗ ꢔꢘꢀꢙ ꢑ ꢘ ꢀꢔ ꢘꢀ
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SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
shutdown function
Three members of the TLV246x family (TLV2460/3/5) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied low, the supply current is reduced to 0.3 µA/channel,
the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the
shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care
should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place
the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to V /2.
DD
Therefore, when operating the device with split supply voltages (e.g. 2.5 V), the shutdown terminal needs to
be pulled to V − (not GND) to disable the operational amplifier.
DD
The amplifier’s output with a shutdown pulse is shown in Figures 22, 23, 24, and 25. The amplifier is powered
with a single 5-V supply and configured as a noninverting configuration with a gain of 5. The amplifier turnon
and turnoff times are measured from the 50% point of the shutdown pulse to the 50% point of the output
waveform. The times for the single, dual, and quad are listed in the data tables.
circuit layout considerations
To achieve the levels of high performance of the TLV246x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
D
Ground planes − It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D
Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D
D
Sockets − Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
Short trace runs/compact part placements − Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at
the input of the amplifier.
D
Surface-mount passive components − Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
27
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SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
general power dissipation considerations
For a given θ , the maximum power dissipation is shown in Figure 53 and is calculated by the following formula:
JA
T
–T
MAX
A
P
+
ǒ Ǔ
D
q
JA
Where:
P
= Maximum power dissipation of THS246x IC (watts)
= Absolute maximum junction temperature (150°C)
= Free-ambient air temperature (°C)
D
T
MAX
T
A
θ
= θ + θ
JA
JC CA
θ
θ
= Thermal coefficient from junction to case
JC
= Thermal coefficient from case to ambient air (°C/W)
CA
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
2
T
= 150°C
PDIP Package
J
Low-K Test PCB
1.75
θ
= 104°C/W
JA
1.5
1.25
1
MSOP Package
Low-K Test PCB
SOIC Package
Low-K Test PCB
θ
= 260°C/W
JA
θ
= 176°C/W
JA
0.75
0.5
SOT-23 Package
Low-K Test PCB
0.25
0
θ
= 324°C/W
JA
−55−40 −25 −10
5
20 35 50 65 80 95 110 125
T
A
− Free-Air Temperature − °C
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 53. Maximum Power Dissipation vs Free-Air Temperature
28
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ꢍꢌꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑ ꢒꢓꢔꢑ ꢒ ꢕꢖ ꢖꢌꢏ ꢁ ꢓꢀꢑ ꢓꢖꢌꢏ ꢁ ꢏꢗ ꢔꢘꢀꢙ ꢑ ꢘ ꢀꢔ ꢘꢀ
ꢑ ꢔꢕꢖ ꢌꢀ ꢏꢑ ꢗꢌꢁ ꢌꢎ ꢔꢁ ꢏꢍ ꢏꢕ ꢖꢚ ꢒ ꢏꢀ ꢛ ꢚꢛꢘ ꢀꢜ ꢑ ꢒꢗ
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts Release 8, the model generation
software used with Microsim PSpice. The Boyle macromodel (see Note 2) and subcircuit in Figure 54 are
generated using the TLV246x typical electrical and operating characteristics at T = 25°C. Using this
A
information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most
cases):
D
D
D
D
D
D
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
D
D
D
D
D
D
Unity-gain frequency
Common-mode rejection ratio
Phase margin
Quiescent power dissipation
Input bias current
DC output resistance
AC output resistance
Short-circuit output current limit
Open-loop voltage amplification
NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Intergrated Circuit Operational Amplifiers”, IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
99
EGND
+
−
FB
RO2
C2
R2
VB
6
3
7
V
DD+
+
+
−
9
VLIM
RSS
VD
ISS
CSS
+
−
−
8
GA
GCM
RP
53
10
2
1
IN −
IN+
DC
RO1
J1
J2
OUT
5
DLN
DE
11
12
92
54
C1
91
90
DP
+
−
+
+
+
RD1
RD2
DLP
VLP
VLN
VE
HLIM
−
−
−
4
GND
.SUBCKT TLV246X 1 2 3 4 5
RD1
RD2
R01
R02
RP
3
11
12
5
2.8964E3
2.8964E3
5.6000
C1
11
6
12
7
2.46034E−12
3
C2
10.0000E−12
8
CSS
DC
10
5
99
53
5
91
90
3
0
99
443.21E−15
7
99
4
6.2000
DY
DY
DX
DX
DX
3
8.9127
10.610E6
DC 0
DC .7836
DC .7436
DC 0
DC 117
DC 117
DE
54
90
92
4
RSS
VB
10
9
99
0
DLP
DLN
DP
VC
VE
VLIM
VLP
VLN
3
53
4
54
7
EGND
FB
99
7
POLY (2) (3,0) (4,0) 0 .5 .5
POLY (5) VB VC VE VLP
8
91
0
0
+ VLN 0 21.600E6 −1E3 1E3 22E6 −22E6
92
GA
6
0
6
4
0
2
1
9
11
10
12 345.26E−6
99 15.4226E−9
.MODEL DX D (IS=800.00E−18)
GCM
ISS
HLIM
J1
0
.MODEL DY D (IS=800.00E−18 Rs = 1m Cjo=10p)
10
90
11
12
6
DC 18.850E−6
VLIM 1K
10 JX1
10 JX2
100.00E3
.MODEL JX1 NJF (IS=1.0000E−12 BETA=6.3239E−3
+ VTO=−1)
.MODEL JX2 NJF (IS=1.0000E−12 BETA=6.3239E−3
J2
R2
+ VTO=−1)
.ENDS
Figure 54. Boyle Macromodels and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
29
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ꢌ
ꢚ
ꢇ
ꢀ
ꢁ
ꢂ
ꢑ
ꢃ
ꢄ
ꢓ
ꢅ
ꢖ
ꢚ
ꢉ
ꢌ
ꢛ
ꢇ
ꢏ
ꢘ
ꢀ
ꢁ
ꢀ
ꢁ
ꢂ
ꢔ
ꢑ
ꢃ
ꢄ
ꢘ
ꢒ
ꢅ
ꢀ
ꢗ
ꢄ
ꢙ
ꢇ
ꢑ
ꢀ
ꢘ
ꢁ
ꢀ
ꢂ
ꢔ
ꢃ
ꢘ
ꢄ
ꢅ
ꢀ
ꢊ
ꢇ
ꢀ
ꢁꢂ
ꢃ
ꢄ
ꢅ
ꢋ
ꢌ
ꢍ
ꢌ
ꢁ
ꢐ
ꢏ
ꢁ
ꢓ
ꢀ
ꢏ
ꢗ
ꢑ
ꢔ
ꢌ
ꢀ
ꢏ
ꢑ
ꢗ
ꢌ
ꢔꢁ
ꢏ
ꢏ
ꢕ
ꢒ
ꢏ
ꢀ
ꢛ
ꢜ
SLOS220J − JULY 1998 − REVISED FEBRUARY 2004
macromodel information (continued)
.subckt TLV_246Y 1 2 3 4 5 6
rp
3
71
99
4
8.9127
10.610E6
1G
c1
11
72
10
70
54
90
92
4
12
7
2.4603E−12
rss
rs1
rs2
rs3
rs4
s1
10
6
c2
10.000E−12
css
dc
99
53
70
91
90
3
443.21E−15
6
4
1G
dy
dy
dx
dx
dx
6
4
1G
1G
6 4 s1x
6 4 s1x
6 4 s1x
6 4 s2x
dc 0
dc .7836
dc .7436
dc 0
dc 117
dc 117
de
6
4
dlp
dln
dp
71
70
10
74
9
4
s2
5
s3
74
4
egnd
fb
99
7
0
poly(2) (3,0) (4,0) 0 .5 .5
poly(5) vb vc ve vlp vln 0
s4
99
vb
0
21.600E6 −1E3 1E3 22E6 −22E6
vc
3
53
4
ga
72
0
0
11 12 345.26E−6
10 99 15.422E−9
dc 18.850E−6
vlim 1K
10 jx1
10 jx2
ve
54
7
gcm
iss
hlim
j1
72
4
vlim
vlp
vln
8
74
90
11
12
72
3
91
0
0
0
92
2
.model dx D(Is=800.00E−18)
j2
r2
rd1
rd2
ro1
ro2
1
.model dy D(Is=800.00E−18 Rs=1m Cjo=10p)
.model jx1 NJF(Is=1.0000E−12 Beta=6.3239E−3 Vto=−1)
.model jx2 NJF(Is=1.0000E−12 Beta=6.3239E−3 Vto=−1)
.model s1x VSWITCH(Roff=1E8 Ron=1.0 Voff=2.5 Von=0.0)
.model s2x VSWITCH(Roff=1E8 Ron=1.0 Voff=0 Von=2.5)
.ends
9
100.00E3
2.8964E3
2.8964E3
5.6000
11
12
70
99
3
8
7
6.2000
Figure 54. Boyle Macromodels and Subcircuit (Continued)
30
WWW.TI.COM
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CFP
Drawing
FK
U
5962-0051201Q2A
5962-0051201QHA
5962-0051201QPA
5962-0051202Q2A
5962-0051202QHA
5962-0051202QPA
5962-0051203Q2A
5962-0051203QHA
5962-0051203QPA
5962-0051204Q2A
5962-0051204QHA
5962-0051204QPA
5962-0051205Q2A
5962-0051205QHA
5962-0051205QPA
5962-0051206Q2A
5962-0051206QHA
5962-0051206QPA
5962-0051207Q2A
5962-0051207QCA
5962-0051208Q2A
5962-0051208QCA
TLV2460AIDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
20
10
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
CDIP
LCCC
CFP
JG
FK
U
20
10
8
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
CDIP
LCCC
CFP
JG
FK
U
20
10
8
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
CDIP
LCCC
CFP
JG
FK
U
20
10
8
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
CDIP
LCCC
CFP
JG
FK
U
20
10
8
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
CDIP
LCCC
CFP
JG
FK
U
20
10
8
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
CDIP
LCCC
CDIP
LCCC
CDIP
SOIC
JG
FK
J
20
14
20
14
8
POST-PLATE N / A for Pkg Type
A42 SNPB N / A for Pkg Type
POST-PLATE N / A for Pkg Type
A42 SNPB N / A for Pkg Type
FK
J
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2460AIDRG4
TLV2460AIP
ACTIVE
ACTIVE
ACTIVE
SOIC
PDIP
PDIP
D
P
P
8
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
POST-PLATE N / A for Pkg Type
TLV2460AIPE4
50
Pb-Free
(RoHS)
TLV2460AMFKB
TLV2460AMJG
TLV2460AMJGB
TLV2460AMUB
TLV2460AQDR
TLV2460AQPW
TLV2460AQPWR
TLV2460CD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
FK
JG
JG
U
20
8
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
A42 SNPB
A42 SNPB
A42 SNPB
Call TI
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
Call TI
CDIP
8
1
CFP
10
8
1
SOIC
TSSOP
TSSOP
SOIC
D
2500
150
2000
PW
PW
D
8
Call TI
Call TI
8
Call TI
Call TI
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2460CDBVR
TLV2460CDBVRG4
TLV2460CDBVT
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
6
6
6
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
no Sb/Br)
TLV2460CDBVTG4
TLV2460CDG4
TLV2460CDR
TLV2460CDRG4
TLV2460CP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOIC
DBV
D
6
8
8
8
8
8
8
6
6
6
6
8
8
8
8
8
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLV2460CPE4
TLV2460ID
PDIP
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SOIC
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2460IDBVR
TLV2460IDBVRG4
TLV2460IDBVT
TLV2460IDBVTG4
TLV2460IDG4
TLV2460IDR
SOT-23
SOT-23
SOT-23
SOT-23
SOIC
DBV
DBV
DBV
DBV
D
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2460IDRG4
TLV2460IP
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
POST-PLATE N / A for Pkg Type
TLV2460IPE4
PDIP
P
50
Pb-Free
(RoHS)
TLV2460MFKB
TLV2460MJG
TLV2460MJGB
TLV2460MUB
TLV2460QD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
FK
JG
JG
U
20
8
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
A42 SNPB
A42 SNPB
A42 SNPB
Call TI
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
Call TI
CDIP
8
1
CFP
10
8
1
SOIC
SOIC
TSSOP
TSSOP
SOIC
D
75
TLV2460QDR
TLV2460QPW
TLV2460QPWR
TLV2461AID
D
8
2500
150
2000
Call TI
Call TI
PW
PW
D
8
Call TI
Call TI
8
Call TI
Call TI
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2461AIDG4
TLV2461AIDR
TLV2461AIDRG4
TLV2461AIP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
D
D
D
P
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
CU NIPDAU N / A for Pkg Type
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
(RoHS)
TLV2461AIPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
POST-PLATE N / A for Pkg Type
TLV2461AMFKB
TLV2461AMJGB
TLV2461AMUB
TLV2461AQD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
JG
U
20
8
1
1
TBD
TBD
TBD
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
10
8
1
SOIC
D
75
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2461AQDR
TLV2461AQPW
TLV2461AQPWR
TLV2461CD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
TSSOP
TSSOP
SOIC
D
PW
PW
D
8
8
8
8
2500
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
2000
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2461CDBVR
TLV2461CDBVRG4
TLV2461CDBVT
TLV2461CDBVTG4
TLV2461CDG4
TLV2461CDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOIC
DBV
DBV
DBV
DBV
D
5
5
5
5
8
8
8
8
8
8
5
5
5
5
8
8
8
8
8
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2461CDRG4
TLV2461CP
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLV2461CPE4
TLV2461ID
PDIP
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SOIC
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2461IDBVR
TLV2461IDBVRG4
TLV2461IDBVT
TLV2461IDBVTG4
TLV2461IDG4
TLV2461IDR
SOT-23
SOT-23
SOT-23
SOT-23
SOIC
DBV
DBV
DBV
DBV
D
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2461IDRG4
TLV2461IP
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLV2461IPE4
PDIP
P
50
Pb-Free
CU NIPDAU N / A for Pkg Type
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
(RoHS)
TLV2461MFKB
TLV2461MJGB
TLV2461MUB
TLV2461QD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
FK
JG
U
20
8
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
Call TI
N / A for Pkg Type
N / A for Pkg Type
Call TI
CFP
10
8
1
SOIC
D
75
2500
TLV2461QDR
TLV2461QPW
TLV2461QPWR
TLV2462AID
SOIC
D
8
Call TI
Call TI
TSSOP
TSSOP
SOIC
PW
PW
D
8
Call TI
Call TI
8
2000
Call TI
Call TI
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2462AIDG4
TLV2462AIDR
TLV2462AIDRG4
TLV2462AIP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
PDIP
D
D
D
P
P
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
POST-PLATE N / A for Pkg Type
TLV2462AIPE4
50
Pb-Free
(RoHS)
TLV2462AMFKB
TLV2462AMJG
TLV2462AMJGB
TLV2462AMUB
TLV2462AQD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CDIP
CFP
FK
JG
JG
U
20
8
1
1
TBD
TBD
TBD
TBD
A42 SNPB
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
8
1
10
8
1
SOIC
D
75
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2462AQDR
ACTIVE
SOIC
D
8
2500
2000
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2462AQPWR
TLV2462CD
ACTIVE
ACTIVE
TSSOP
SOIC
PW
D
8
8
TBD
CU NIPDAU Level-1-220C-UNLIM
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2462CDG4
TLV2462CDGK
TLV2462CDGKG4
TLV2462CDGKR
TLV2462CDGKRG4
TLV2462CDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
MSOP
MSOP
MSOP
MSOP
SOIC
SOIC
PDIP
D
DGK
DGK
DGK
DGK
D
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2462CDRG4
TLV2462CP
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLV2462CPE4
PDIP
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
Orderable Device
TLV2462ID
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2462IDG4
TLV2462IDGK
TLV2462IDGKG4
TLV2462IDGKR
TLV2462IDGKRG4
TLV2462IDR
SOIC
MSOP
MSOP
MSOP
MSOP
SOIC
SOIC
PDIP
D
DGK
DGK
DGK
DGK
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2462IDRG4
TLV2462IP
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
POST-PLATE N / A for Pkg Type
TLV2462IPE4
PDIP
P
50
Pb-Free
(RoHS)
TLV2462MFKB
TLV2462MJG
TLV2462MJGB
TLV2462MUB
TLV2462QD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CDIP
CFP
FK
JG
JG
U
20
8
1
1
TBD
TBD
TBD
TBD
A42 SNPB
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
8
1
10
8
1
SOIC
D
75
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2462QDR
ACTIVE
SOIC
D
8
2500
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2462QPW
TLV2462QPWR
TLV2463AID
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
SOIC
PW
PW
D
8
8
150
TBD
TBD
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
2000
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2463AIDG4
TLV2463AIDR
TLV2463AIDRG4
TLV2463AIN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
PDIP
D
D
D
N
N
14
14
14
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
POST-PLATE N / A for Pkg Type
TLV2463AINE4
25
Pb-Free
(RoHS)
TLV2463AMFKB
TLV2463AMJ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
FK
J
20
14
14
14
14
14
14
1
1
TBD
TBD
TBD
TBD
TBD
TBD
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
TLV2463AMJB
TLV2463AQD
TLV2463AQDR
TLV2463AQPWR
TLV2463CD
CDIP
J
1
SOIC
SOIC
TSSOP
SOIC
D
50
75
2000
CU NIPDAU Level-1-220C-UNLIM
Call TI Call TI
CU NIPDAU Level-1-250C-UNLIM
D
PW
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 5
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
no Sb/Br)
TLV2463CDG4
TLV2463CDGS
TLV2463CDGSG4
TLV2463CDGSR
TLV2463CDGSRG4
TLV2463CDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
MSOP
MSOP
MSOP
MSOP
SOIC
SOIC
PDIP
D
DGS
DGS
DGS
DGS
D
14
10
10
10
10
14
14
14
14
14
14
10
10
10
10
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2463CDRG4
TLV2463CN
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLV2463CNE4
TLV2463ID
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SOIC
SOIC
MSOP
MSOP
MSOP
MSOP
PDIP
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2463IDG4
TLV2463IDGS
TLV2463IDGSG4
TLV2463IDGSR
TLV2463IDGSRG4
TLV2463IN
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGS
DGS
DGS
DGS
N
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
POST-PLATE N / A for Pkg Type
TLV2463INE4
PDIP
N
25
Pb-Free
(RoHS)
TLV2463MFKB
TLV2463MJ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
FK
J
20
14
14
14
14
14
14
1
1
TBD
TBD
TBD
TBD
TBD
TBD
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
TLV2463MJB
TLV2463QD
CDIP
J
1
SOIC
SOIC
TSSOP
SOIC
D
75
CU NIPDAU Level-1-220C-UNLIM
Call TI Call TI
CU NIPDAU Level-1-250C-UNLIM
TLV2463QDR
TLV2463QPWR
TLV2464AID
D
2500
2000
PW
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2464AIDG4
TLV2464AIDR
TLV2464AIDRG4
TLV2464AIN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
D
D
D
N
14
14
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
CU NIPDAU N / A for Pkg Type
Addendum-Page 6
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
(RoHS)
TLV2464AINE4
TLV2464AIPW
TLV2464AIPWG4
TLV2464AIPWR
TLV2464AIPWRG4
TLV2464CD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
N
PW
PW
PW
PW
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2464CDG4
TLV2464CDR
TLV2464CDRG4
TLV2464CN
SOIC
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLV2464CNE4
TLV2464CPW
TLV2464CPWG4
TLV2464CPWR
TLV2464CPWRG4
TLV2464ID
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
PW
D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2464IDG4
TLV2464IDR
SOIC
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2464IDRG4
TLV2464IN
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLV2464INE4
TLV2464IPW
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2464IPWG4
TLV2464IPWR
TLV2464IPWRG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 7
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
Orderable Device
TLV2465AID
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2465AIDG4
TLV2465AIPWR
TLV2465AIPWRG4
TLV2465CD
SOIC
TSSOP
TSSOP
SOIC
D
PW
PW
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2465CDG4
TLV2465CDR
TLV2465CDRG4
TLV2465CN
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLV2465CNE4
TLV2465CPW
TLV2465CPWG4
TLV2465CPWR
TLV2465CPWRG4
TLV2465ID
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
PW
D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2465IDG4
TLV2465IDR
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2465IDRG4
TLV2465IN
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLV2465INE4
TLV2465IPW
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2465IPWG4
TLV2465IPWR
TLV2465IPWRG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 8
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 9
PACKAGE MATERIALS INFORMATION
www.ti.com
7-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-May-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
180
180
330
180
180
330
330
180
180
330
180
180
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330
(mm)
12
9
TLV2460AIDR
TLV2460CDBVR
TLV2460CDBVT
TLV2460CDR
D
DBV
DBV
D
8
6
TAI
LEN
LEN
TAI
6.4
3.15
3.15
6.4
5.2
3.2
3.2
5.2
3.2
3.2
5.2
5.2
3.2
3.2
5.2
3.2
3.2
5.2
5.2
3.4
5.2
5.2
3.4
5.2
3.4
3.4
5.6
5.6
5.6
5.6
5.6
5.6
2.1
1.4
1.4
2.1
1.4
1.4
2.1
2.1
1.4
1.4
2.1
1.4
1.4
2.1
2.1
1.4
2.1
2.1
1.4
2.1
1.4
1.4
1.6
1.6
1.6
1.6
1.6
1.6
8
4
4
8
4
4
8
8
4
4
8
4
4
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
12
8
Q1
NONE
NONE
Q1
6
9
8
8
12
9
12
8
TLV2460IDBVR
TLV2460IDBVT
TLV2460IDR
DBV
DBV
D
6
LEN
LEN
TAI
3.15
3.15
6.4
NONE
NONE
Q1
6
9
8
8
12
12
9
12
12
8
TLV2461AIDR
TLV2461CDBVR
TLV2461CDBVT
TLV2461CDR
D
8
TAI
6.4
Q1
DBV
DBV
D
5
LEN
LEN
TAI
3.15
3.15
6.4
NONE
NONE
Q1
5
9
8
8
12
9
12
8
TLV2461IDBVR
TLV2461IDBVT
TLV2461IDR
DBV
DBV
D
5
LEN
LEN
TAI
3.15
3.15
6.4
NONE
NONE
Q1
5
9
8
8
12
12
8
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
TLV2462AIDR
TLV2462CDGKR
TLV2462CDR
D
8
TAI
6.4
Q1
DGK
D
8
HNT
TAI
5.3
NONE
Q1
8
12
0
6.4
TLV2462CDR
D
8
FMX
HNT
TAI
6.4
Q1
TLV2462IDGKR
TLV2462IDR
DGK
D
8
8
5.3
NONE
Q1
8
12
8
6.4
TLV2463CDGSR
TLV2463IDGSR
TLV2464AIPWR
TLV2464CPWR
TLV2464IPWR
TLV2465AIPWR
TLV2465CPWR
TLV2465IPWR
DGS
DGS
PW
PW
PW
PW
PW
PW
10
10
14
14
14
16
16
16
HNT
HNT
MLA
MLA
MLA
MLA
MLA
MLA
5.3
NONE
NONE
Q1
8
5.3
12
12
12
12
12
12
7.0
7.0
Q1
7.0
Q1
7.0
Q1
7.0
Q1
7.0
Q1
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-May-2007
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
TLV2460AIDR
TLV2460CDBVR
TLV2460CDBVT
TLV2460CDR
D
DBV
DBV
D
8
6
TAI
LEN
LEN
TAI
346.0
182.4
182.4
346.0
182.4
182.4
346.0
346.0
182.4
182.4
346.0
182.4
182.4
346.0
346.0
358.0
346.0
342.9
358.0
346.0
358.0
358.0
342.9
342.9
342.9
346.0
182.4
182.4
346.0
182.4
182.4
346.0
346.0
182.4
182.4
346.0
182.4
182.4
346.0
346.0
335.0
346.0
336.6
335.0
346.0
335.0
335.0
336.6
336.6
336.6
61.0
17.3
17.3
61.0
17.3
17.3
61.0
61.0
17.3
17.3
61.0
17.3
17.3
61.0
61.0
35.0
61.0
20.6
35.0
61.0
35.0
35.0
20.6
20.6
20.6
6
8
TLV2460IDBVR
TLV2460IDBVT
TLV2460IDR
DBV
DBV
D
6
LEN
LEN
TAI
6
8
TLV2461AIDR
TLV2461CDBVR
TLV2461CDBVT
TLV2461CDR
D
8
TAI
DBV
DBV
D
5
LEN
LEN
TAI
5
8
TLV2461IDBVR
TLV2461IDBVT
TLV2461IDR
DBV
DBV
D
5
LEN
LEN
TAI
5
8
TLV2462AIDR
TLV2462CDGKR
TLV2462CDR
D
8
TAI
DGK
D
8
HNT
TAI
8
TLV2462CDR
D
8
FMX
HNT
TAI
TLV2462IDGKR
TLV2462IDR
DGK
D
8
8
TLV2463CDGSR
TLV2463IDGSR
TLV2464AIPWR
TLV2464CPWR
TLV2464IPWR
DGS
DGS
PW
PW
PW
10
10
14
14
14
HNT
HNT
MLA
MLA
MLA
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
7-May-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
TLV2465AIPWR
TLV2465CPWR
TLV2465IPWR
PW
PW
PW
16
16
16
MLA
MLA
MLA
342.9
342.9
342.9
336.6
336.6
336.6
20.6
20.6
20.6
Pack Materials-Page 4
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.063 (1,60)
0.015 (0,38)
0.020 (0,51) MIN
0.200 (5,08) MAX
0.130 (3,30) MIN
Seating Plane
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Wireless
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www.ti.com/wireless
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