TLV2463AQPWRQ1 [TI]
FAMILY OF LOW POWER RAIL TO RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH SHUTDOWN; 系列低功耗轨至轨输入/输出运算放大器，带有关断
| 型号： | TLV2463AQPWRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | FAMILY OF LOW POWER RAIL TO RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH SHUTDOWN |
| 文件： | 总33页 (文件大小：689K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈꢉ ꢊ ꢋ ꢀꢁꢂꢃ ꢄ ꢅ ꢊ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢌ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄꢅ ꢄꢇ ꢈꢉ ꢊ
ꢍꢇꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑꢒꢈꢓꢑ ꢒ ꢔꢕ ꢕꢇꢏ ꢁ ꢈꢀꢑ ꢈꢕꢇꢏ ꢁ ꢏꢖ ꢓꢗꢀ ꢘ ꢑ ꢗꢀ ꢓꢗ ꢀ
ꢑ ꢓꢔꢕ ꢇꢀ ꢏꢑ ꢖꢇꢁ ꢇꢎ ꢓꢁ ꢏꢍ ꢏꢔ ꢕꢙ ꢒ ꢏꢀ ꢚ ꢙꢚꢗ ꢀꢛ ꢑ ꢒꢖ
SGLS008B − MARCH 2003 − REVISED MAY 2004
D
Qualification in Accordance With
AEC-Q100
D
D
D
D
Input Noise Voltage . . . 11 nV/√Hz
Slew Rate . . . 1.6 V/µs
Micropower Shutdown Mode
(TLV2460/3/5) . . . 0.3 µA/Channel
†
D
Qualified for Automotive Applications
D
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
Universal Operational Amplifier EVM
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
TLV2460
D OR PW PACKAGE
(TOP VIEW)
D
D
D
D
D
Rail-to-Rail Output Swing
NC
IN−
SHDN
1
2
3
4
8
7
6
5
Gain Bandwidth Product . . . 6.4 MHz
80 mA Output Drive Capability
Supply Current . . . 500 µA/channel
Input Offset Voltage . . . 100 µV
V
+
DD
IN+
OUT
NC
GND
†
Contact factory for details. Q100 qualification data available on
request.
description
The TLV246x is a family of low-power rail-to-rail input/output operational amplifiers specifically designed for
portable applications. The input common-mode voltage range extends beyond the supply rails for maximum
dynamic range in low-voltage systems. The amplifier output has rail-to-rail performance with high-output-drive
capability, solving one of the limitations of older rail-to-rail input/output operational amplifiers. This rail-to-rail
dynamic range and high output drive make the TLV246x ideal for buffering analog-to-digital converters.
The operational amplifier has 6.4 MHz of bandwidth and 1.6 V/µs of slew rate with only 500 µA of supply current,
providing good ac performance with low power consumption. Devices are available with an optional shutdown
terminal, which places the amplifier in an ultralow supply current mode (I
the operational-amplifier output is placed in a high-impedance state. DC applications are also well served with
= 0.3 µA/ch). While in shutdown,
DD
an input noise voltage of 11 nV/√Hz and input offset voltage of 100 µV.
‡
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
T
A
PACKAGE
§
−40°C to 125°C
−40°C to 125°C
SOP − D
TSSOP − PW
Tape and reel
Tape and reel
TLV2464AQDRQ1
V2464AQ1
V2464AQ
TLV2464AQPWRQ1
‡
§
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
All other device/package combinations are Product Preview.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003 − 2004 Texas Instruments Incorporated
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1
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SGLS008B − MARCH 2003 − REVISED MAY 2004
TLV246x PACKAGE PINOUTS
TLV2461
D OR PW PACKAGE
(TOP VIEW)
TLV2462
D OR PW PACKAGE
(TOP VIEW)
NC
IN−
NC
V
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
GND
V
+
1
2
3
4
8
7
6
5
DD
+
2OUT
2IN−
2IN+
DD
IN+
OUT
NC
GND
TLV2464
TLV2463
D OR PW PACKAGE
D OR PW PACKAGE
(TOP VIEW)
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
1OUT
1IN−
1IN+
GND
NC
V
+
1OUT
1IN−
1IN+
1
2
3
4
5
6
7
14
13
12
11
10
9
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
DD
2OUT
2IN−
2IN+
NC
V
+
DD
2IN+
2IN−
1SHDN
NC
2SHDN
NC
8
8
2OUT
NC − No internal connection
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢊ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢌ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄꢅ ꢄꢇ ꢈꢉ ꢊ
ꢍꢇꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑꢒꢈꢓꢑ ꢒ ꢔꢕ ꢕꢇꢏ ꢁ ꢈꢀꢑ ꢈꢕꢇꢏ ꢁ ꢏꢖ ꢓꢗꢀ ꢘ ꢑ ꢗꢀ ꢓꢗ ꢀ
ꢑ ꢓꢔꢕ ꢇꢀ ꢏꢑ ꢖꢇꢁ ꢇꢎ ꢓꢁ ꢏꢍ ꢏꢔ ꢕꢙ ꢒ ꢏꢀ ꢚ ꢙꢚꢗ ꢀꢛ ꢑ ꢒꢖ
SGLS008B − MARCH 2003 − REVISED MAY 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Differential input voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.2 V to V
+ 0.2 V
200 mA
175 mA
ID
DD
Input current, I (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Total input current, I (into V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 mA
I
DD+
Total output current, I (out of GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
O
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
A
Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
Thermal resistance, Junction-to-Ambient, Θ : D (8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176°C/W
JA
D (14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W
D (16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W
PW (14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to GND.
recommended operating conditions
MIN
2.7
MAX
UNIT
Single supply
6
3
Supply voltage, V
DD
V
Split supply
1.35
−0.2
−40
2
Common-mode input voltage range, V
ICR
V
+0.2
125
V
DD
Operating free-air temperature, T
°C
A
V
V
IH
‡
Shutdown on/off voltage level
V
0.7
IL
‡
Relative to voltage on the GND terminal of the device.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SGLS008B − MARCH 2003 − REVISED MAY 2004
electrical characteristics at specified free-air temperature, V
= 3 V (unless otherwise noted)
DD
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1500
1700
T
A
UNIT
25°C
150
V
IO
Input offset voltage
µV
V
V
= 3 V,
V
IC
= 1.5 V,
Full range
DD
= 1.5 V,
R
= 50 Ω
O
S
Temperature coefficient of input offset
voltage
α
VIO
2
µV/°C
nA
25°C
Full range
25°C
2.8
7
75
14
75
I
IO
Input offset current
Input bias current
V
V
= 3 V,
V
= 1.5 V,
DD
IC
= 1.5 V,
R
= 50 Ω
4.4
2.9
2.7
0.1
0.3
50
O
S
I
IB
nA
Full range
25°C
I
I
= −2.5 mA
= −10 mA
= 1.5 V,
OH
Full range
25°C
2.8
2.5
V
High-level output voltage
Low-level output voltage
V
V
OH
OL
OH
Full range
25°C
V
V
I
I
= 2.5 mA
IC
OL
Full range
25°C
0.2
0.5
V
= 1.5 V,
= 10 mA
IC
OL
Full range
25°C
Sourcing
Sinking
Full range
25°C
20
20
I
I
Short-circuit output current
Output current
mA
OS
40
Full range
25°C
Measured 1 V from rail
= 10 kΩ
40
mA
dB
O
25°C
90
89
105
Large-signal differential voltage
amplification
A
VD
R
L
Full range
25°C
9
10
Ω
pF
Ω
r
Differential input resistance
i(d)
c
z
Common-mode input capacitance
Closed-loop output impedance
f = 10 kHz
25°C
7
33
80
i(c)
o
f = 100 kHz,
A
V
= 10
25°C
25°C
66
60
80
75
85
80
CMRR
Common-mode rejection ratio
V
V
= 0 V to 3 V,
R
= 50 Ω
dB
ICR
S
Full range
25°C
85
95
= 2.7 V to 6 V,
V
IC
= V
/2,
/2,
DD
DD
DD
No load
Full range
25°C
Supply voltage rejection ratio
k
dB
SVR
(∆V
DD
/∆V )
IO
V
= 3 V to 5 V,
V
IC
= V
DD
No load
Full range
25°C
0.5 0.575
I
Supply current (per channels)
V
O
= 1.5 V,
No load
mA
DD
Full range
25°C
0.9
0.3
2.5
Supply current in shutdown (TLV2460,
TLV2463)
SHDN < 0.7 V,
Per channel in shutdown
I
µA
DD(SHDN)
Full range
†
Full range is −40°C to 125°C for the Q suffix.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢊ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢌ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄꢅ ꢄꢇ ꢈꢉ ꢊ
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SGLS008B − MARCH 2003 − REVISED MAY 2004
operating characteristics at specified free-air temperature, V
= 3 V (unless otherwise noted)
DD
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
T
A
25°C
1
1.6
V
R
= 2 V,
C
= 160 pF,
L
O(PP)
= 10 kΩ
SR
Slew rate at unity gain
V/µs
Full
range
0.8
L
f = 100 Hz
f = 1 kHz
f = 1 kHz
25°C
25°C
25°C
16
11
nV/√Hz
pA/√Hz
V
I
Equivalent input noise voltage
Equivalent input noise current
n
0.13
n
A
= 1
0.006%
0.02%
0.08%
7.6
V
Total harmonic distortion plus
noise
V
R
= 2 V,
= 10 kΩ, f = 1 kHz
O(PP)
L
A
V
= 10
= 100
THD + N
25°C
25°C
A
V
Both channels
t
Amplifier turnon time
A
V
= 1, R = 10 kΩ
µs
Channel 1 only,
Channel 2 on
(on)
L
7.65
333
328
Both channels
Channel 1 only,
Channel 2 on
t
Amplifier turnoff time
A
V
= 1, R = 10 kΩ
25°C
25°C
ns
(off)
L
Channel 2 only,
Channel 1 on
329
Gain-bandwidth product
5.2
MHz
f = 10 kHz, C = 160 pF
R = 10 kΩ,
L
L
V
= 2 V,
0.1%
1.47
(STEP)PP
A
= −1,
C
L
= 10 pF,
V
0.01%
0.1%
1.78
1.77
1.98
R
= 10 kΩ
L
t
s
Settling time
25°C
µs
V
= 2 V,
(STEP)PP
= −1, C = 56 pF,
L
A
V
0.01%
R
= 10 kΩ
L
φ
m
Phase margin at unity gain
Gain margin
25°C
25°C
44°
R
= 10 kΩ,
C
= 160 pF
L
L
7
dB
†
Full range is −40°C to 125°C for the Q suffix.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SGLS008B − MARCH 2003 − REVISED MAY 2004
electrical characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1500
1700
T
A
UNIT
25°C
150
V
IO
Input offset voltage
µV
Full range
V
V
= 5 V,
V
IC
= 2.5,
DD
= 2.5 V,
R
= 50 Ω
O
S
Temperature coefficient of input offset
voltage
α
VIO
25°C
2
µV/°C
nA
25°C
Full range
25°C
0.3
7
60
14
60
I
IO
Input offset current
Input bias current
V
V
= 5 V,
V
= 2.5 V,
DD
IC
= 2.5 V,
R
= 50 Ω
1.3
4.9
4.8
0.1
0.2
145
100
O
S
I
IB
nA
Full range
25°C
I
I
= −2.5 mA
= −10 mA
= 2.5 V,
OH
Full range
25°C
4.8
4.7
V
High-level output voltage
Low-level output voltage
V
V
OH
OL
OH
Full range
25°C
V
I
I
= 2.5 mA
= 10 mA
IC
IC
OL
Full range
25°C
0.2
0.3
V
V
= 2.5 V,
OL
Full range
25°C
Sourcing
Sinking
Full range
25°C
60
60
I
I
Short-circuit output current
Output current
mA
OS
Full range
25°C
Measured at 1 V from rail
80
mA
dB
O
25°C
92
90
109
Large-signal differential voltage
amplification
V
IC
V
O
= 2.5 V,
= 1 V to 4 V
R
= 10 kΩ,
L
A
VD
Full range
25°C
9
10
r
Differential input resistance
Ω
pF
Ω
i(d)
c
z
Common-mode input capacitance
Closed-loop output impedance
f = 10 kHz
25°C
7
29
85
i(c)
o
f = 100 kHz,
A
V
= 10
25°C
25°C
71
60
80
75
85
80
V
R
= 0 V to 5 V,
= 50 Ω
ICR
CMRR
Common-mode rejection ratio
dB
dB
dB
mA
µA
Full range
25°C
S
85
95
V
DD
= 2.7 V to 6 V,
No load,
V
= V
= V
/2
Full range
25°C
IC
DD
Supply voltage rejection ratio
k
SVR
(∆V
DD
/∆V )
IO
V
= 3 V to 5 V,
DD
No load,
V
IC
/2
Full range
25°C
DD
0.55
1
0.65
1
I
I
Supply current (per channel)
V
O
= 2.5 V,
No load,
DD
Full range
25°C
Supply current in shutdown
(TLV2460, TLV2463)
SHDN < 0.7 V, Per channels in
shutdown
DD(SHDN)
Full range
3
†
Full range is −40°C to 125°C for the Q suffix.
6
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ꢍꢇꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑꢒꢈꢓꢑ ꢒ ꢔꢕ ꢕꢇꢏ ꢁ ꢈꢀꢑ ꢈꢕꢇꢏ ꢁ ꢏꢖ ꢓꢗꢀ ꢘ ꢑ ꢗꢀ ꢓꢗ ꢀ
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ꢏ
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ꢖ
ꢇ
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ꢇ
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ꢁ
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ꢔ
ꢕ
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ꢙ
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ꢑ
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SGLS008B − MARCH 2003 − REVISED MAY 2004
operating characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
T
A
25°C
1
1.6
V
R
= 2 V,
C
= 160 pF,
L
O(PP)
= 10 kΩ
SR
Slew rate at unity gain
V/µs
Full
range
0.8
L
f = 100 Hz
f = 1 kHz
25°C
25°C
25°C
14
11
nV/√Hz
pA/√Hz
V
I
Equivalent input noise voltage
Equivalent input noise current
n
f = 100 Hz
0.13
n
A
= 1
0.004%
0.01%
0.04%
7.6
V
V
R
= 4 V,
O(PP)
= 10 kΩ,
A
V
= 10
= 100
THD + N Total harmonic distortion plus noise
25°C
L
f = 10 kHz
A
V
Both channels
Channel 1 only,
Channel 2 on
7.65
t
Amplifier turnon time
A
= 1, R = 10 kΩ
25°C
µs
(on)
(off)
V
L
Channel 2 only,
Channel 1 on
7.25
333
328
Both channels
Channel 1 only,
Channel 2 on
t
Amplifier turnoff time
A
V
= 1, R = 10 kΩ
25°C
25°C
ns
L
Channel 2 only,
Channel 1 on
329
f = 10 kHz,
= 160 pF
R = 10 kΩ,
L
Gain-bandwidth product
6.4
1.53
1.83
3.13
3.33
MHz
C
L
V
= 2 V,
= 2 V,
(STEP)PP
0.1%
A
= −1,
= 10 pF,
= 10 kΩ
V
C
R
L
L
0.01%
0.1%
t
s
Settling time
25°C
µs
V
(STEP)PP
A
= −1,
= 56 pF,
= 10 kΩ
V
C
R
L
L
0.01%
φ
m
Phase margin at unity gain
Gain margin
25°C
25°C
45°
R
= 10 kΩ,
C = 160 pF
L
L
7
dB
†
Full range is −40°C to 125°C for the Q suffix.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢊ
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ꢏ
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ꢇ
ꢁ
ꢇ
ꢎ
ꢓ
ꢁ
ꢏ
ꢍ
ꢏ
ꢔ
ꢕ
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ꢒ
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SGLS008B − MARCH 2003 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
1, 2
3, 4
3, 4
5, 6
7, 8
9, 10
11, 12
11, 12
13
V
Input offset voltage
Input bias current
Input offset current
vs Common-mode input voltage
vs Free-air temperature
vs Free-air temperature
vs High-level output current
vs Low-level output current
vs Frequency
IO
I
I
IB
IO
V
V
V
High-level output voltage
Low-level output voltage
OH
OL
Peak-to-peak output voltage
Open-loop gain
O(PP)
vs Frequency
Phase
vs Frequency
A
VD
Differential voltage amplification
Capacitive load
vs Load resistance
vs Load resistance
vs Frequency
14
Z
o
Output impedance
15, 16
17
CMRR
Common-mode rejection ratio
Supply-voltage rejection ratio
vs Frequency
k
vs Frequency
18, 19
20
SVR
vs Supply voltage
I
Supply current
DD
vs Free-air temperature
21
Amplifier turnon characteristics
Amplifier turnoff characteristics
Supply current turnon
Supply current turnoff
Shutdown supply current
Slew rate
22
23
24
25
vs Free-air temperature
vs Supply voltage
26
SR
27
vs Frequency
28, 29
30, 31
V
n
Equivalent input noise voltage
vs Common-mode input voltage
THD
Total harmonic distortion
vs Frequency
32, 33
34, 35
11, 12
THD+N
Total harmonic distortion plus noise
vs Peak-to-peak signal amplitude
vs Frequency
φ
m
Phase margin
vs Load capacitance
vs Free-air temperature
vs Supply voltage
36
37
38
Gain bandwidth product
vs Free-air temperature
39
Large signal follower
Small signal follower
Inverting large signal
Inverting small signal
40, 41
42, 43
44, 45
46, 47
8
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ꢍꢇꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑꢒꢈꢓꢑ ꢒ ꢔꢕ ꢕꢇꢏ ꢁ ꢈꢀꢑ ꢈꢕꢇꢏ ꢁ ꢏꢖ ꢓꢗꢀ ꢘ ꢑ ꢗꢀ ꢓꢗ ꢀ
ꢑ ꢓꢔꢕ ꢇꢀ ꢏꢑ ꢖꢇꢁ ꢇꢎ ꢓꢁ ꢏꢍ ꢏꢔ ꢕꢙ ꢒ ꢏꢀ ꢚ ꢙꢚꢗ ꢀꢛ ꢑ ꢒꢖ
SGLS008B − MARCH 2003 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
1
0.8
0.6
0.4
1
0.8
0.6
0.4
V
T
= 3 V
= 25°C
DD
A
V
T
A
= 5 V
= 25°C
DD
0.2
0
0.2
0
−0.2
−0.4
−0.6
−0.2
−0.4
−0.6
−0.8
−1
−0.8
−1
0
0.5
1
1.5
2
2.5
3
0
1
2
3
4
5
V
ICR
− Common-Mode Input Voltage − V
V
ICR
− Common-Mode Input Voltage − V
Figure 1
Figure 2
INPUT BIAS AND INPUT OFFSET CURRENT
INPUT BIAS AND INPUT OFFSET CURRENT
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
5
4.5
4
6
5
4
3
V
= 3 V
DD
V = 1.5 V
V
= 5 V
DD
V = 2.5 V
I
I
IB
I
I
IB
3.5
3
2.5
2
2
1
1.5
1
0.5
0
I
IO
I
IO
0
−0.5
−1
−55 −35 −15
5
25
45
65
85 105 125
−55 −35 −15
5
25
45
65
85 105 125
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 3
Figure 4
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢇ
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ꢍꢇꢎ ꢏ ꢁꢐ ꢑꢍ ꢁ ꢑꢒꢈꢓ ꢑꢒ ꢔ ꢕ ꢕꢇ ꢏ ꢁꢈꢀꢑ ꢈꢕꢇꢏ ꢁ ꢏꢖ ꢓꢗꢀ ꢘꢑ ꢗꢀ ꢓꢗ ꢀ
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ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢀ
ꢁꢂ
ꢃ
ꢄ
ꢅ
ꢄ
ꢇ
ꢈ
ꢉ
ꢊ
ꢑ
ꢓ
ꢔ
ꢕ
ꢇ
ꢀ
ꢏ
ꢑ
ꢖ
ꢇ
ꢁ
ꢇ
ꢎ
ꢓ
ꢁ
ꢏ
ꢍ
ꢏ
ꢔ
ꢕ
ꢙ
ꢒ
ꢏ
ꢀꢚ
ꢙ
ꢚ
ꢗ
ꢀ
ꢛ
ꢑ
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ꢖ
SGLS008B − MARCH 2003 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3
5
V
= 3 V
DC
DD
V
= 5 V
DC
DD
4.5
4
2.5
T
A
= −55°C
T = −55°C
A
3.5
3
2
1.5
1
T
T
= 125°C
A
T = 125°C
A
2.5
= 85°C
A
T
A
= 85°C
2
T
= 25°C
A
T
A
= 25°C
1.5
1
T
= −40°C
A
T = −40°C
A
0.5
0
0.5
0
0
10
20
30
40
50
60
70
80
0
20 40 60 80 100 120 140 160 180 200
I
− High-Level Output Current − mA
OH
I
− High-Level Output Current − mA
OH
Figure 5
Figure 6
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
3
4.5
4
V
DD
= 3 V
DC
V
DD
= 5 V
DC
2.5
T
= −40°C
T
= −40°C
A
A
3.5
3
2
1.5
1
T
= 25°C
= 85°C
A
T
= 25°C
= 85°C
A
2.5
2
T
T
A
T
T
A
A
A
= 125°C
= 125°C
1.5
1
0.5
0
T
= −55°C
A
0.5
0
T
A
= −55°C
0
10
20
30
40
50
60
70
0
20
40
60
80
100 120 140 160
I
− Low-Level Output Current − mA
OL
I
− Low-Level Output Current − mA
OL
Figure 7
Figure 8
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢊ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢌ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄꢅ ꢄꢇ ꢈꢉ ꢊ
ꢍꢇꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑꢒꢈꢓꢑ ꢒ ꢔꢕ ꢕꢇꢏ ꢁ ꢈꢀꢑ ꢈꢕꢇꢏ ꢁ ꢏꢖ ꢓꢗꢀ ꢘ ꢑ ꢗꢀ ꢓꢗ ꢀ
ꢑ ꢓꢔꢕ ꢇꢀ ꢏꢑ ꢖꢇꢁ ꢇꢎ ꢓꢁ ꢏꢍ ꢏꢔ ꢕꢙ ꢒ ꢏꢀ ꢚ ꢙꢚꢗ ꢀꢛ ꢑ ꢒꢖ
SGLS008B − MARCH 2003 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
PEAK-TO-PEAK OUTPUT VOLTAGE
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
vs
FREQUENCY
FREQUENCY
3
2.5
2
5.5
5
V
= 3 V
DD
= −10
V
= 5 V
DD
A = −10
V
A
V
THD = 1%
= 10 kΩ
THD = 1%
R = 10 kΩ
L
4.5
4
R
L
3.5
3
1.5
2.5
2
1.5
1
1
0.5
0
0.5
0
10k
100k
1M
10M
10k
100k
1M
10M
f − Frequency − Hz
f − Frequency − Hz
Figure 9
Figure 10
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
100
90
80
70
60
50
40
40°
V
R
C
= 1.5 V
= 10 kΩ
= 0
DD
L
L
20°
0°
T
A
= 25°C
−20°
−40°
−60°
−80°
−100°
A
VD
30
20
Phase
−120°
−140°
−160°
−180°
−200°
10
0
−10
−20
10
100
1k
10k
100k
1M
10M
f − Frequency − Hz
Figure 11
11
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ꢇ
ꢈ
ꢉ
ꢊ
ꢑ
ꢓ
ꢔ
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ꢇ
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ꢏ
ꢑ
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ꢇ
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ꢇ
ꢎ
ꢓ
ꢁ
ꢏ
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SGLS008B − MARCH 2003 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
100
90
80
70
60
50
40
40°
20°
0°
V
R
C
= 2.5 V
= 10 kΩ
= 0
DD
L
L
T
A
= 25°C
−20°
−40°
−60°
−80°
A
VD
−100°
30
20
Phase
−120°
−140°
−160°
−180°
−200°
10
0
−10
−20
10
100
1k
10k
100k
1M
10M
f − Frequency − Hz
Figure 12
DIFFERENTIAL VOLTAGE AMPLIFICATION
CAPACITIVE LOAD
vs
LOAD RESISTANCE
vs
LOAD RESISTANCE
180
160
140
120
100
80
10000
1000
100
T
= 25°C
A
Phase Margin < 30°
V
= 2.5 V
DD
V
DD
= 1.5 V
60
Phase Margin > 30°
40
V
= 5 V
DD
Phase Margin = 30°
= 25°C
20
T
A
0
100
1k
10k
100k
1M
10
100
1k
10k
R
− Load Resistance − Ω
L
R − Load Resistance − Ω
L
Figure 13
Figure 14
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢊ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢌ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄꢅ ꢄꢇ ꢈꢉ ꢊ
ꢍꢇꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑꢒꢈꢓꢑ ꢒ ꢔꢕ ꢕꢇꢏ ꢁ ꢈꢀꢑ ꢈꢕꢇꢏ ꢁ ꢏꢖ ꢓꢗꢀ ꢘ ꢑ ꢗꢀ ꢓꢗ ꢀ
ꢑ ꢓꢔꢕ ꢇꢀ ꢏꢑ ꢖꢇꢁ ꢇꢎ ꢓꢁ ꢏꢍ ꢏꢔ ꢕꢙ ꢒ ꢏꢀ ꢚ ꢙꢚꢗ ꢀꢛ ꢑ ꢒꢖ
SGLS008B − MARCH 2003 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
OUTPUT IMPEDANCE
vs
OUTPUT IMPEDANCE
vs
FREQUENCY
FREQUENCY
1000
100
10
1000
100
10
V
T
A
= 1.5 V
= 25°C
DD
V
T
A
= 2.5 V
= 25°C
DD
A
V
= 100
A
V
= 100
= 10
1
1
A
V
= 10
= 1
A
V
0.1
A
V
0.1
A
V
= 1
0.01
0.01
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
f − Frequency − Hz
f − Frequency − Hz
Figure 15
Figure 16
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
90
85
80
75
V
V
= 5 V
DD
= 2.5 V
IC
V
V
= 3 V
DD
= 1.5 V
IC
70
65
60
10
100
1k
10k
100k
1M
10M
f − Frequency − Hz
Figure 17
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
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ꢃ
ꢄ
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ꢆ
ꢇ
ꢈ
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ꢊ
ꢋ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢊ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢃ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢀ
ꢁ
ꢂ
ꢃ
ꢍꢇꢎ ꢏ ꢁꢐ ꢑꢍ ꢁ ꢑꢒꢈꢓ ꢑꢒ ꢔ ꢕ ꢕꢇ ꢏ ꢁꢈꢀꢑ ꢈꢕꢇꢏ ꢁ ꢏꢖ ꢓꢗꢀ ꢘꢑ ꢗꢀ ꢓꢗ ꢀ
ꢄ
ꢅ
ꢌ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢀ
ꢁꢂ
ꢃ
ꢄ
ꢅ
ꢄ
ꢇ
ꢈ
ꢉ
ꢊ
ꢑ
ꢓ
ꢔ
ꢕ
ꢇ
ꢀ
ꢏ
ꢑ
ꢖ
ꢇ
ꢁ
ꢇ
ꢎ
ꢓ
ꢁ
ꢏ
ꢍ
ꢏ
ꢔ
ꢕ
ꢙ
ꢒ
ꢏ
ꢀꢚ
ꢙ
ꢚ
ꢗ
ꢀ
ꢛ
ꢑ
ꢒ
ꢖ
SGLS008B − MARCH 2003 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
SUPPLY-VOLTAGE REJECTION RATIO
SUPPLY-VOLTAGE REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
110
100
90
80
70
+k
SVR
+k
SVR
V
T
A
=
1.5 V
DD
V
T
=
2.5 V
DD
A
= 25°C
= 25°C
−k
SVR
90
80
70
60
−k
SVR
60
50
40
+k
SVR
+k
SVR
50
40
−k
SVR
−k
SVR
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
f − Frequency − Hz
f − Frequency − Hz
Figure 18
Figure 19
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
0.8
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
I
= 125°C
DD
I
= 85°C
DD
0.7
0.6
V
= 5 V
DD
V = 2.5 V
I
0.5
0.40
0.30
V
= 3 V
DD
V = 1.5 V
I
I
I
= 25°C
DD
I
= −55°C
DD
= −40°C
DD
0.20
0.10
0.35
0.30
2.5
3
3.5
4
4.5
5
5.5
6
−55 −35 −15
5
25
45
65
85 105 125
V
DD
− Supply Voltage − V
T
A
− Free-Air Temperature − °C
Figure 20
Figure 21
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢊ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢌ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄꢅ ꢄꢇ ꢈꢉ ꢊ
ꢍꢇꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑꢒꢈꢓꢑ ꢒ ꢔꢕ ꢕꢇꢏ ꢁ ꢈꢀꢑ ꢈꢕꢇꢏ ꢁ ꢏꢖ ꢓꢗꢀ ꢘ ꢑ ꢗꢀ ꢓꢗ ꢀ
ꢑ ꢓꢔꢕ ꢇꢀ ꢏꢑ ꢖꢇꢁ ꢇꢎ ꢓꢁ ꢏꢍ ꢏꢔ ꢕꢙ ꢒ ꢏꢀ ꢚ ꢙꢚꢗ ꢀꢛ ꢑ ꢒꢖ
SGLS008B − MARCH 2003 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
AMPLIFIER WITH A SHUTDOWN PULSE
TURNON CHARACTERISTICS
AMPLIFIER WITH A SHUTDOWN PULSE
TURNOFF CHARACTERISTICS
5
4
3
2
1
0
3
2
5
4
3
2
1
0
3
2
V
R
= 5 V
= 10 kΩ
= 1
DD
L
Shutdown Pin
Shutdown Pin
A
V
A
T
= 25°C
Amplifier Output
Amplifier Output
V
R
= 5 V
= 10 kΩ
= 1
DD
L
A
V
A
1
0
T
= 25°C
1
0
−5
−3
−1
1
3
5
7
9
11
−5
−3
−1
1
3
5
7
t − Time − µs
t − Time − µs
Figure 22
Figure 23
SUPPLY CURRENT WITH A SHUTDOWN PULSE
TURNON CHARACTERISTICS
1
5.5
Shutdown Pin
0.8
4.5
3.5
2.5
1.5
0.6
0.4
Supply Current
0.2
0
V
= 5 V
DD
V = 2.5 V
0.5
I
A
= 1
= 25°C
V
T
A
−0.2
−0.5
−0.4
−0.2
0
0.2
0.4
0.6
t − Time − µs
Figure 24
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
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ꢃ
ꢄ
ꢅ
ꢊ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢃ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢀ
ꢁ
ꢂ
ꢃ
ꢍꢇꢎ ꢏ ꢁꢐ ꢑꢍ ꢁ ꢑꢒꢈꢓ ꢑꢒ ꢔ ꢕ ꢕꢇ ꢏ ꢁꢈꢀꢑ ꢈꢕꢇꢏ ꢁ ꢏꢖ ꢓꢗꢀ ꢘꢑ ꢗꢀ ꢓꢗ ꢀ
ꢄ
ꢅ
ꢌ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢀ
ꢁꢂ
ꢃ
ꢄ
ꢅ
ꢄ
ꢇ
ꢈ
ꢉ
ꢊ
ꢑ
ꢓ
ꢔ
ꢕ
ꢇ
ꢀ
ꢏ
ꢑ
ꢖ
ꢇ
ꢁ
ꢇ
ꢎ
ꢓ
ꢁ
ꢏ
ꢍ
ꢏ
ꢔ
ꢕ
ꢙ
ꢒ
ꢏ
ꢀꢚ
ꢙ
ꢚ
ꢗ
ꢀ
ꢛ
ꢑ
ꢒ
ꢖ
SGLS008B − MARCH 2003 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
TURNOFF SUPPLY CURRENT
WITH A SHUTDOWN PULSE
1
5.5
4.5
V
= 5 V
DD
V = 2.5 V
I
Shutdown Pin
Supply Current
A
= 1
= 25°C
V
A
0.8
T
0.6
0.4
3.5
2.5
0.2
0
1.5
0.5
−0.2
−0.5
0.6
−0.4
−0.2
0
0.2
0.4
t − Time − µs
Figure 25
SHUTDOWN SUPPLY CURRENT
vs
SLEW RATE
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
3
2.5
2
1.8
1.75
1.7
1.65
1.6
V
= 5 V
DD
V = 2.5 V
SR+
I
1.5
1
1.55
SR−
V
= 3 V
DD
1.5
1.45
1.4
0.5
V = 1.5 V
I
V
C
= 2 V
= 160 pF
= 1
= 10 kΩ
= 25°C
O(PP)
L
0
−0.5
−1
A
V
R
L
1.35
1.3
T
A
−55 −35 −15
5
25
45
65
85 105 125
2.5
3
3.5
4
4.5
5
5.5
6
T
A
− Free-Air Temperature − °C
V
DD
− Supply Voltage − V
Figure 26
Figure 27
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢊ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢌ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄꢅ ꢄꢇ ꢈꢉ ꢊ
ꢍꢇꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑꢒꢈꢓꢑ ꢒ ꢔꢕ ꢕꢇꢏ ꢁ ꢈꢀꢑ ꢈꢕꢇꢏ ꢁ ꢏꢖ ꢓꢗꢀ ꢘ ꢑ ꢗꢀ ꢓꢗ ꢀ
ꢑ ꢓꢔꢕ ꢇꢀ ꢏꢑ ꢖꢇꢁ ꢇꢎ ꢓꢁ ꢏꢍ ꢏꢔ ꢕꢙ ꢒ ꢏꢀ ꢚ ꢙꢚꢗ ꢀꢛ ꢑ ꢒꢖ
SGLS008B − MARCH 2003 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
EQUIVALENT INPUT NOISE VOLTAGE
EQUIVALENT INPUT NOISE VOLTAGE
vs
vs
FREQUENCY
FREQUENCY
18
17
18
17
V
= 3 V
DD
= 10
V
= 5 V
DD
A = 10
V
A
V
V = 1.5 V
I
A
V = 2.5 V
I
T
= 25°C
T = 25°C
A
16
15
14
16
15
14
13
12
13
12
11
10
11
10
100
1k
10k
100k
100
1k
10k
100k
f − Frequency − Hz
f − Frequency − Hz
Figure 28
Figure 29
EQUIVALENT INPUT NOISE VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
EQUIVALENT INPUT NOISE VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
20
20
15
14
13
12
V
= 3 V
DD
= 10
V
= 5 V
DD
A = 10
V
A
V
f = 1 kHz
f = 1 kHz
15
14
13
12
T
A
= 25°C
T
A
= 25°C
11
10
11
10
0
0.5
1
1.5
2
2.5
3
0
1
2
3
4
5
V
ICR
− Common-Mode Input Voltage − V
V
ICR
− Common-Mode Input Voltage − V
Figure 30
Figure 31
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢃ
ꢄ
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ꢊ
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ꢈ
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ꢊ
ꢋ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢃ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢀ
ꢁ
ꢂ
ꢃ
ꢍꢇꢎ ꢏ ꢁꢐ ꢑꢍ ꢁ ꢑꢒꢈꢓ ꢑꢒ ꢔ ꢕ ꢕꢇ ꢏ ꢁꢈꢀꢑ ꢈꢕꢇꢏ ꢁ ꢏꢖ ꢓꢗꢀ ꢘꢑ ꢗꢀ ꢓꢗ ꢀ
ꢄ
ꢅ
ꢌ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢀ
ꢁꢂ
ꢃ
ꢄ
ꢅ
ꢄ
ꢇ
ꢈ
ꢉ
ꢊ
ꢑ
ꢓ
ꢔ
ꢕ
ꢇ
ꢀ
ꢏ
ꢑ
ꢖ
ꢇ
ꢁ
ꢇ
ꢎ
ꢓ
ꢁ
ꢏ
ꢍ
ꢏ
ꢔ
ꢕ
ꢙ
ꢒ
ꢏ
ꢀꢚ
ꢙ
ꢚ
ꢗ
ꢀ
ꢛ
ꢑ
ꢒ
ꢖ
SGLS008B − MARCH 2003 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION
vs
vs
FREQUENCY
FREQUENCY
0.5
0.1
1
V
V
R
=
1.5 V
= 2 V
DD
O(PP)
L
V
V
=
2.5 V
= 4 V
DD
O(PP)
L
= 10 kΩ
R = 10 kΩ
A
= 100
= 10
= 1
V
0.1
A
V
= 100
= 10
= 1
A
V
A
V
0.010
0.001
A
V
0.010
0.001
A
V
10
100
1k
10k
100k
10
100
1k
10k
100k
f − Frequency − Hz
f − Frequency − Hz
Figure 32
Figure 33
TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
vs
PEAK-TO-PEAK SIGNAL AMPLITUDE
PEAK-TO-PEAK SIGNAL AMPLITUDE
1
1
R
= 250 Ω
V
= 3 V
L
DD
= 1
R
= 250 Ω
A
L
V
TA = 25°C
R
= 2 kΩ
L
R
= 2 kΩ
L
0.1
0.1
R
= 10 kΩ
L
R
= 10 kΩ
L
0.010
0.001
0.010
0.001
R
= 100 kΩ
R
= 100 kΩ
L
L
V
= 5 V
DD
= 1
A
V
A
T
= 25°C
1
1.2 1.4 1.6 1.8
2
2.2 2.4 2.6 2.8
3
3.2
4
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9
Peak-to-Peak Signal Amplitude − V
5
Peak-to-Peak Signal Amplitude − V
Figure 34
Figure 35
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢊ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢌ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄꢅ ꢄꢇ ꢈꢉ ꢊ
ꢍꢇꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑꢒꢈꢓꢑ ꢒ ꢔꢕ ꢕꢇꢏ ꢁ ꢈꢀꢑ ꢈꢕꢇꢏ ꢁ ꢏꢖ ꢓꢗꢀ ꢘ ꢑ ꢗꢀ ꢓꢗ ꢀ
ꢑ ꢓꢔꢕ ꢇꢀ ꢏꢑ ꢖꢇꢁ ꢇꢎ ꢓꢁ ꢏꢍ ꢏꢔ ꢕꢙ ꢒ ꢏꢀ ꢚ ꢙꢚꢗ ꢀꢛ ꢑ ꢒꢖ
SGLS008B − MARCH 2003 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
LOAD CAPACITANCE
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
90
80
70
60
50
40
30
20
10
0
60
55
50
V
T
R
=
2.5 V
DD
A
L
R
C
= 10 kΩ
= 160 pF
L
L
= 25°C
= 10 kΩ
R
= 50 Ω
null
V
V
=
=
2.5 V
1.5 V
DD
45
40
R
= 20 Ω
null
DD
R
= 0 Ω
null
35
30
10
100
1k
10k
100k
−55 −35 −15
5
25
45
65
85 105 125
C
L
− Load Capacitance − pF
T
A
− Free-Air Temperature − °C
Figure 36
Figure 37
GAIN BANDWIDTH PRODUCT
GAIN BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
vs
SUPPLY VOLTAGE
5
5
C
R
= 160 pF
= 10 kΩ
L
L
R
C
= 10 kΩ
= 160 pF
L
L
4.75
f = 10 kHz
4.75
4.5
4.25
4
T
A
= 25°C
V
=
2.5 V
DD
4.5
4.25
4
3.75
3.5
V
DD
= 1.5 V
3.75
3.5
3.25
3
2.5
3
3.5
4
4.5
5
5.5
6
−55 −35 −15
5
25
45
65
85 105 125
V
DD
− Supply Voltage − V
T
A
− Free-Air Temperature − °C
Figure 38
Figure 39
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢂ
ꢃ
ꢄ
ꢅ
ꢊ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢃ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢀ
ꢁ
ꢂ
ꢃ
ꢍꢇꢎ ꢏ ꢁꢐ ꢑꢍ ꢁ ꢑꢒꢈꢓ ꢑꢒ ꢔ ꢕ ꢕꢇ ꢏ ꢁꢈꢀꢑ ꢈꢕꢇꢏ ꢁ ꢏꢖ ꢓꢗꢀ ꢘꢑ ꢗꢀ ꢓꢗ ꢀ
ꢄ
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ꢌ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢀ
ꢁꢂ
ꢃ
ꢄ
ꢅ
ꢄ
ꢇ
ꢈ
ꢉ
ꢊ
ꢑ
ꢓ
ꢔ
ꢕ
ꢇ
ꢀ
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ꢑ
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ꢇ
ꢁ
ꢇ
ꢎ
ꢓ
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SGLS008B − MARCH 2003 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
LARGE SIGNAL FOLLOWER
LARGE SIGNAL FOLLOWER
2.2
2
3.7
3.3
Input
Input
1.8
1.6
1.4
1.2
2.9
2.5
2.1
Output
Output
V
V
= 5 V
DD
I(PP)
V
V
= 3 V
DD
I(PP)
Input
Input
= 2 V
V = 2.5 V
= 1 V
V = 1.5 V
I
R
C
I
R
C
= 10 kΩ
= 160 pF
= 1
L
L
Output
Output
= 10 kΩ
= 160 pF
= 1
L
L
1.7
1.3
A
V
A
1
A
V
A
T
= 25°C
T
= 25°C
0.8
−2
0
2
4
6
8
10 12 14 16 18
−2
0
2
4
6
8
10 12 14 16 18
t − Time − µs
t − Time − µs
Figure 40
Figure 41
SMALL SIGNAL FOLLOWER
SMALL SIGNAL FOLLOWER
1.6
2.6
2.55
2.5
1.55
1.5
Input
Input
Output
Output
1.45
1.4
2.45
2.4
V
V
= 3 V
= 100 mV
V
V
= 5 V
= 100 mV
DD
I(PP)
DD
I(PP)
C
A
T
A
= 160 pF
= 1
= 25°C
C
A
T
A
= 160 pF
= 1
= 25°C
L
V
L
V
V = 1.5 V
V = 2.5 V
I
I
R
= 10 kΩ
R = 10 kΩ
L
L
−0.2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
−0.2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
t − Time − µs
t − Time − µs
Figure 42
Figure 43
20
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ꢍꢇꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑꢒꢈꢓꢑ ꢒ ꢔꢕ ꢕꢇꢏ ꢁ ꢈꢀꢑ ꢈꢕꢇꢏ ꢁ ꢏꢖ ꢓꢗꢀ ꢘ ꢑ ꢗꢀ ꢓꢗ ꢀ
ꢑ ꢓꢔꢕ ꢇꢀ ꢏꢑ ꢖꢇꢁ ꢇꢎ ꢓꢁ ꢏꢍ ꢏꢔ ꢕꢙ ꢒ ꢏꢀ ꢚ ꢙꢚꢗ ꢀꢛ ꢑ ꢒꢖ
SGLS008B − MARCH 2003 − REVISED MAY 2004
TYPICAL CHARACTERISTICS
INVERTING LARGE SIGNAL
Input
INVERTING LARGE SIGNAL
Input
4
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
3.5
3
V
V
= 3 V
= 1 V
V
V
= 5 V
= 2 V
DD
I(PP)
DD
I(PP)
V = 1.5 V
I
V = 2.5 V
I
R
C
= 10 kΩ
= 160 pF
= −1
R
C
= 10 kΩ
= 160 pF
= −1
L
L
L
L
2.5
2
A
A
V
A
V
A
T
= 25°C
T
= 25°C
Output
Output
1.5
1
0.7
0.5
−0.2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
−0.2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
t − Time − µs
t − Time − µs
Figure 44
Figure 45
INVERTING SMALL SIGNAL
INVERTING SMALL SIGNAL
1.6
1.55
1.5
2.6
Input
Input
2.55
2.5
V
V
= 3 V
DD
I(PP)
V
V
= 5 V
DD
I(PP)
= 100 mV
V = 1.5 V
= 100 mV
V = 2.5 V
I
R
C
I
R
C
= 10 kΩ
= 160 pF
= −1
L
L
= 10 kΩ
= 160 pF
= −1
L
L
A
V
A
A
V
A
T
= 25°C
T
= 25°C
1.45
1.4
2.45
2.4
Output
Output
−0.2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
−0.2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
t − Time − µs
t − Time − µs
Figure 46
Figure 47
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢍꢇꢎ ꢏ ꢁꢐ ꢑꢍ ꢁ ꢑꢒꢈꢓ ꢑꢒ ꢔ ꢕ ꢕꢇ ꢏ ꢁꢈꢀꢑ ꢈꢕꢇꢏ ꢁ ꢏꢖ ꢓꢗꢀ ꢘꢑ ꢗꢀ ꢓꢗ ꢀ
ꢄ
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ꢌ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
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ꢁꢂ
ꢃ
ꢄ
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ꢄ
ꢇ
ꢈ
ꢉ
ꢊ
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ꢓ
ꢔ
ꢕ
ꢇ
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ꢇ
ꢎ
ꢓ
ꢁ
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SGLS008B − MARCH 2003 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
R
_
+
null
R
L
C
L
Figure 48
APPLICATION INFORMATION
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series (R
) with the output of the amplifier, as
NULL
shown in Figure 49. A minimum value of 20 Ω should work well for most applications.
R
F
R
G
_
R
NULL
Input
Output
LOAD
+
C
Figure 49. Driving a Capacitive Load
offset voltage
The output offset voltage, (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times
OO
IO
IB
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
R
F
I
IB−
R
G
+
−
+
V
I
V
O
R
S
I
IB+
R
R
F
F
V
+ V
1 ) ǒ Ǔ " I
R
1 ) ǒ Ǔ " I
R
ǒ Ǔ ǒ Ǔ
OO
IO
IB)
S
IB–
F
R
R
G
G
Figure 50. Output Offset Voltage Model
22
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ꢍꢇꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑꢒꢈꢓꢑ ꢒ ꢔꢕ ꢕꢇꢏ ꢁ ꢈꢀꢑ ꢈꢕꢇꢏ ꢁ ꢏꢖ ꢓꢗꢀ ꢘ ꢑ ꢗꢀ ꢓꢗ ꢀ
ꢑ ꢓꢔꢕ ꢇꢀ ꢏꢑ ꢖꢇꢁ ꢇꢎ ꢓꢁ ꢏꢍ ꢏꢔ ꢕꢙ ꢒ ꢏꢀ ꢚ ꢙꢚꢗ ꢀꢛ ꢑ ꢒꢖ
SGLS008B − MARCH 2003 − REVISED MAY 2004
APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 51).
R
R
F
G
−
V
1
O
+
V
I
R1
V
C1
f
+
–3dB
2pR1C1
R
O
F
1
ǒ
Ǔ
+
ǒ
1 )
Ǔ
V
R
1 ) sR1C1
I
G
Figure 51. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
+
_
V
I
1
R1
R2
f
+
–3dB
2pRC
C2
R
F
1
R
=
G
R
F
2 −
)
R
(
Q
G
Figure 52. 2-Pole Low-Pass Sallen-Key Filter
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢈ
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ꢊ
ꢋ
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ꢂ
ꢃ
ꢄ
ꢅ
ꢃ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢀ
ꢁ
ꢂ
ꢃ
ꢍꢇꢎ ꢏ ꢁꢐ ꢑꢍ ꢁ ꢑꢒꢈꢓ ꢑꢒ ꢔ ꢕ ꢕꢇ ꢏ ꢁꢈꢀꢑ ꢈꢕꢇꢏ ꢁ ꢏꢖ ꢓꢗꢀ ꢘꢑ ꢗꢀ ꢓꢗ ꢀ
ꢄ
ꢅ
ꢌ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢀ
ꢁꢂ
ꢃ
ꢄ
ꢅ
ꢄ
ꢇ
ꢈ
ꢉ
ꢊ
ꢑ
ꢓ
ꢔ
ꢕ
ꢇ
ꢀ
ꢏ
ꢑ
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ꢇ
ꢁ
ꢇ
ꢎ
ꢓ
ꢁ
ꢏ
ꢍ
ꢏ
ꢔ
ꢕ
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ꢒ
ꢏ
ꢀꢚ
ꢙ
ꢚ
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ꢀ
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SGLS008B − MARCH 2003 − REVISED MAY 2004
APPLICATION INFORMATION
shutdown function
Three members of the TLV246x family (TLV2460/3/5) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied low, the supply current is reduced to 0.3 µA/channel,
the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the
shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care
should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place
the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to V /2.
DD
Therefore, when operating the device with split supply voltages (e.g. 2.5 V), the shutdown terminal needs to
be pulled to V − (not GND) to disable the operational amplifier.
DD
The amplifier’s output with a shutdown pulse is shown in Figures 22, 23, 24, and 25. The amplifier is powered
with a single 5-V supply and configured as a noninverting configuration with a gain of 5. The amplifier turnon
and turnoff times are measured from the 50% point of the shutdown pulse to the 50% point of the output
waveform. The times for the single, dual, and quad are listed in the data tables.
circuit layout considerations
To achieve the levels of high performance of the TLV246x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
D
Ground planes − It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D
Proper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D
D
Sockets − Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
Short trace runs/compact part placements − Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at
the input of the amplifier.
D
Surface-mount passive components − Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
24
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ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢊ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢌ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄꢅ ꢄꢇ ꢈꢉ ꢊ
ꢍꢇꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑꢒꢈꢓꢑ ꢒ ꢔꢕ ꢕꢇꢏ ꢁ ꢈꢀꢑ ꢈꢕꢇꢏ ꢁ ꢏꢖ ꢓꢗꢀ ꢘ ꢑ ꢗꢀ ꢓꢗ ꢀ
ꢑ ꢓꢔꢕ ꢇꢀ ꢏꢑ ꢖꢇꢁ ꢇꢎ ꢓꢁ ꢏꢍ ꢏꢔ ꢕꢙ ꢒ ꢏꢀ ꢚ ꢙꢚꢗ ꢀꢛ ꢑ ꢒꢖ
SGLS008B − MARCH 2003 − REVISED MAY 2004
APPLICATION INFORMATION
general power dissipation considerations
For a given θ , the maximum power dissipation is shown in Figure 53 and is calculated by the following formula:
JA
T
–T
MAX
A
P
+
ǒ Ǔ
D
q
JA
Where:
P
= Maximum power dissipation of THS246x IC (watts)
= Absolute maximum junction temperature (150°C)
= Free-ambient air temperature (°C)
D
T
MAX
T
A
θ
= θ + θ
JA
JC CA
θ
θ
= Thermal coefficient from junction to case
JC
= Thermal coefficient from case to ambient air (°C/W)
CA
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
2
T
= 150°C
PDIP Package
J
Low-K Test PCB
1.75
θ
= 104°C/W
JA
1.5
1.25
1
MSOP Package
Low-K Test PCB
SOIC Package
Low-K Test PCB
θ
= 260°C/W
JA
θ
= 176°C/W
JA
0.75
0.5
SOT-23 Package
Low-K Test PCB
0.25
0
θ
= 324°C/W
JA
−55−40 −25 −10
5
20 35 50 65 80 95 110 125
T
A
− Free-Air Temperature − °C
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 53. Maximum Power Dissipation vs Free-Air Temperature
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SGLS008B − MARCH 2003 − REVISED MAY 2004
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts Release 8, the model generation
software used with Microsim PSpice. The Boyle macromodel (see Note 2) and subcircuit in Figure 54 are
generated using the TLV246x typical electrical and operating characteristics at T = 25°C. Using this
A
information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most
cases):
D
D
D
D
D
D
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
D
D
D
D
D
D
Unity-gain frequency
Common-mode rejection ratio
Phase margin
Quiescent power dissipation
Input bias current
DC output resistance
AC output resistance
Short-circuit output current limit
Open-loop voltage amplification
NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Intergrated Circuit Operational Amplifiers”, IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
99
EGND
+
−
FB
RO2
C2
R2
VB
6
3
7
V
DD+
+
+
−
9
VLIM
RSS
VD
ISS
CSS
+
−
−
8
GA
GCM
RP
53
10
2
1
IN −
IN+
DC
RO1
J1
J2
OUT
5
DLN
DE
11
12
92
54
C1
91
90
DP
+
−
+
+
+
RD1
RD2
DLP
VLP
VLN
VE
HLIM
−
−
−
4
GND
.SUBCKT TLV246X 1 2 3 4 5
RD1
RD2
R01
R02
RP
3
11
12
5
2.8964E3
2.8964E3
5.6000
C1
11
6
12
7
2.46034E−12
3
C2
10.0000E−12
8
CSS
DC
10
5
99
53
5
91
90
3
0
99
443.21E−15
7
99
4
6.2000
DY
DY
DX
DX
DX
3
8.9127
10.610E6
DC 0
DC .7836
DC .7436
DC 0
DC 117
DC 117
DE
54
90
92
4
RSS
VB
10
9
99
0
DLP
DLN
DP
VC
VE
VLIM
VLP
VLN
3
53
4
54
7
EGND
FB
99
7
POLY (2) (3,0) (4,0) 0 .5 .5
POLY (5) VB VC VE VLP
8
91
0
0
+ VLN 0 21.600E6 −1E3 1E3 22E6 −22E6
92
GA
6
0
6
4
0
2
1
9
11
10
12 345.26E−6
99 15.4226E−9
.MODEL DX D (IS=800.00E−18)
GCM
ISS
HLIM
J1
0
.MODEL DY D (IS=800.00E−18 Rs = 1m Cjo=10p)
10
90
11
12
6
DC 18.850E−6
VLIM 1K
10 JX1
10 JX2
100.00E3
.MODEL JX1 NJF (IS=1.0000E−12 BETA=6.3239E−3
+ VTO=−1)
.MODEL JX2 NJF (IS=1.0000E−12 BETA=6.3239E−3
J2
R2
+ VTO=−1)
.ENDS
Figure 54. Boyle Macromodels and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢊ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢃ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢌ ꢇꢈꢉ ꢊ ꢋ ꢀ ꢁꢂꢃ ꢄꢅ ꢄꢇ ꢈꢉ ꢊ
ꢍꢇꢎ ꢏꢁꢐ ꢑ ꢍ ꢁ ꢑꢒꢈꢓꢑ ꢒ ꢔꢕ ꢕꢇꢏ ꢁ ꢈꢀꢑ ꢈꢕꢇꢏ ꢁ ꢏꢖ ꢓꢗꢀ ꢘ ꢑ ꢗꢀ ꢓꢗ ꢀ
ꢑ ꢓꢔꢕ ꢇꢀ ꢏꢑ ꢖꢇꢁ ꢇꢎ ꢓꢁ ꢏꢍ ꢏꢔ ꢕꢙ ꢒ ꢏꢀ ꢚ ꢙꢚꢗ ꢀꢛ ꢑ ꢒꢖ
SGLS008B − MARCH 2003 − REVISED MAY 2004
macromodel information (continued)
.subckt TLV_246Y 1 2 3 4 5 6
rp
3
71
99
4
8.9127
10.610E6
1G
c1
11
72
10
70
54
90
92
4
12
7
2.4603E−12
rss
rs1
rs2
rs3
rs4
s1
10
6
c2
10.000E−12
css
dc
99
53
70
91
90
3
443.21E−15
6
4
1G
dy
dy
dx
dx
dx
6
4
1G
1G
6 4 s1x
6 4 s1x
6 4 s1x
6 4 s2x
dc 0
dc .7836
dc .7436
dc 0
dc 117
dc 117
de
6
4
dlp
dln
dp
71
70
10
74
9
4
s2
5
s3
74
4
egnd
fb
99
7
0
poly(2) (3,0) (4,0) 0 .5 .5
poly(5) vb vc ve vlp vln 0
s4
99
vb
0
21.600E6 −1E3 1E3 22E6 −22E6
vc
3
53
4
ga
72
0
0
11 12 345.26E−6
10 99 15.422E−9
dc 18.850E−6
vlim 1K
10 jx1
10 jx2
ve
54
7
gcm
iss
hlim
j1
72
4
vlim
vlp
vln
8
74
90
11
12
72
3
91
0
0
0
92
2
.model dx D(Is=800.00E−18)
j2
r2
rd1
rd2
ro1
ro2
1
.model dy D(Is=800.00E−18 Rs=1m Cjo=10p)
.model jx1 NJF(Is=1.0000E−12 Beta=6.3239E−3 Vto=−1)
.model jx2 NJF(Is=1.0000E−12 Beta=6.3239E−3 Vto=−1)
.model s1x VSWITCH(Roff=1E8 Ron=1.0 Voff=2.5 Von=0.0)
.model s2x VSWITCH(Roff=1E8 Ron=1.0 Voff=0 Von=2.5)
.ends
9
100.00E3
2.8964E3
2.8964E3
5.6000
11
12
70
99
3
8
7
6.2000
Figure 54. Boyle Macromodels and Subcircuit (Continued)
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TLV2460AQDRQ1
ACTIVE
SOIC
D
8
2500
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2460AQPWRQ1
TLV2460QDRQ1
ACTIVE
ACTIVE
TSSOP
SOIC
PW
D
8
8
2000
2500
None
CU NIPDAU Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2460QPWRQ1
TLV2461AQDRQ1
ACTIVE
ACTIVE
TSSOP
SOIC
PW
D
8
8
2000
2500
None
CU NIPDAU Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2461AQPWRQ1
TLV2461QDRQ1
ACTIVE
ACTIVE
TSSOP
SOIC
PW
D
8
8
2000
2500
None
CU NIPDAU Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2461QPWRQ1
TLV2462AQDRQ1
ACTIVE
ACTIVE
TSSOP
SOIC
PW
D
8
8
2000
2500
None
CU NIPDAU Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2462AQPWRQ1
TLV2462QDRQ1
ACTIVE
ACTIVE
TSSOP
SOIC
PW
D
8
8
2000
2500
None
CU NIPDAU Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2462QPWRQ1
TLV2463AQDRQ1
ACTIVE
ACTIVE
TSSOP
SOIC
PW
D
8
2000
2500
None
CU NIPDAU Level-1-220C-UNLIM
14
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2463AQPWRQ1
TLV2463QDRQ1
ACTIVE
ACTIVE
TSSOP
SOIC
PW
D
14
14
2000
2500
None
CU NIPDAU Level-1-250C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2463QPWRQ1
TLV2464AQPWRQ1
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
14
14
2000
2000
None
None
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 2005, Texas Instruments Incorporated
相关型号：
TLV2463CDGSRG4
FAMILY OF LOW-POWER RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH SHUTDOWN
TI
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