TLV2541_14 [TI]

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN;


型号：	TLV2541_14
厂家：	TEXAS INSTRUMENTS
描述：	2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
文件：	总31页 (文件大小：1132K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

Maximum Throughput . . . 140/200 KSPS

− TLV2542: Dual Channels With

Autosweep

− TLV2545: Single Channel With

Pseudo-Differential Input

Built-In Conversion Clock

INL/DNL: 1 LSB Max, SINAD: 72 dB,

SFDR: 85 dB, f = 20 kHz

Low Power With Autopower Down

− Operating Current: 1 mA at 2.7 V, 1.5 mA

at 5 V

SPI/DSP-Compatible Serial Interface

Single Supply: 2.7 Vdc to 5.5 Vdc

Rail-to-Rail Analog Input With 500 kHz BW

Autopower Down: 2 μA at 2.7 V, 5 μA

at 5 V

Three Options Available:

− TLV2541: Single Channel Input

Small 8-Pin MSOP and SOIC Packages

TOP VIEW

TLV2541

TOP VIEW

TLV2542

TOP VIEW

TLV2545

V_REF

GND

AIN

SDO

V_DD

SCLK

V_REF

GND

AIN0

SDO

SCLK

V_DD

V_REF

GND

SDO

SCLK

V_DD

AIN1

AIN(+)

AIN(−)

description

The TLV2541, TLV2542, and TLV2545 are a family of high performance, 12-bit, low power, miniature, CMOS

analog-to-digital converters (ADC). The TLV254x family operates from a single 2.7-V to 5.5-V supply. Devices

are available with single, dual, or single pseudo-differential inputs. Each device has a chip select (CS), serial

clock (SCLK), and serial data output (SDO) that provides a direct 3-wire interface to the serial port of most

popular host microprocessors (SPI interface). When interfaced with a TMS320t DSP, a frame sync signal (FS)

can be used to indicate the start of a serial data frame on CS for all devices or FS for the TLV2541.

TLV2541, TLV2542, and TLV2545 are designed to operate with very low power consumption. The power saving

feature is further enhanced with an autopower-down mode. This product family features a high-speed serial link

to modern host processors with SCLK up to 20 MHz. The maximum SCLK frequency is dependent upon the

mode of operation (see Table 1). The TLV254x family uses the built-in oscillator as the conversion clock,

providing a 3.5-μs conversion time.

AVAILABLE OPTIONS

PACKAGED DEVICES

8-MSOP

(DGK)

8-SOIC

(D)

TLV2541CDGK (AGZ)

TLV2542CDGK (AHB)

TLV2545CDGK (AHD)

TLV2541IDGK (AHA)

TLV2542IDGK (AHC)

TLV2545IDGK (AHE)

0°C to 70°C

TLV2541ID

TLV2542ID

TLV2545ID

−40°C to 85°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS320 is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

functional block diagram

TLV2541

TLV2542

REF

AIN0

AIN1

Mux

LOW POWER

12-BIT

S/H

AIN

SDO

SAR ADC

LOW POWER

SAR ADC

S/H

SDO

OSC

Conversion

Clock

OSC

Conversion

Clock

SCLK

CONTROL

LOGIC

CONTROL

LOGIC

SCLK

GND

TLV2545

REF

AIN (+)

LOW POWER

12-BIT

SAR ADC

S/H

SDO

AIN (−)

OSC

Conversion

Clock

CONTROL

LOGIC

SCLK

GND

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

Terminal Functions

TLV2541

TERMINAL

I/O

DESCRIPTION

NAME

AIN

NO.

Analog input channel

Chip select. A high-to-low transition on the CS input removes SDO from 3-state within a maximum setup time.

CS can be used as the FS pin when a dedicated DSP serial port is used.

DSP frame sync input. Indication of the start of a serial data frame. Tie this terminal to V if not used.

GND

SCLK

SDO

Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.

Output serial clock. This terminal receives the serial SCLK from the host processor.

The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state until CS falling edge

or FS rising edge, whichever occurs first. The output format is MSB first.

When FS is not used (FS = 1 at the falling edge of CS): The MSB is presented to the SDO pin after CS falling edge

and output data is valid on the first falling edge of SCLK.

When CS and FS are both used (FS = 0 at the falling edge of CS): The MSB is presented to the SDO pin after the

falling edge of CS. When CS is tied/held low, the MSB is presented on SDO after the rising FS. Output data is valid

on the first falling edge of SCLK. (This is typically used with an active FS from a DSP using a dedicated serial port.)

Positive supply voltage

External reference input

REF

TLV2542/45

TERMINAL

I/O

DESCRIPTION

NAME

AIN0 /AIN(+)

AIN1/AIN (−)

NO.

Analog input channel 0 for TLV2542—Positive input for TLV2545.

Analog input channel 1 for TLV2542—Inverted input for TLV2545.

Chip select. A high-to-low transition on CS removes SDO from 3-state within a maximum delay time. This pin can

be connected to the frame sync of a DSP using a dedicated serial port.

GND

SCLK

SDO

Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.

Output serial clock. This terminal receives the serial SCLK from the host processor.

The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state when CS is high

and presents output data after the CS falling edge until the LSB is presented. The output format is MSB first. SDO

returns to the Hi-Z state after the 16th SCLK. Output data is valid on the falling SCLK edge.

Positive supply voltage

External reference input

REF

detailed description

The TLV2541, TLV2542, and TLV2545 are successive approximation (SAR) ADCs utilizing a charge

redistribution DAC. Figure 1 shows a simplified version of the ADC.

The sampling capacitor acquires the signal on AIN during the sampling period. When the conversion process

starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge

from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is

balanced, the conversion is complete and the ADC output code is generated.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

detailed description (continued)

Charge

Redistribution

DAC

AIN

Control

Logic

ADC Code

GND/AIN(−)

Figure 1. Simplified SAR Circuit

serial interface

OUTPUT DATA FORMAT

MSB

LSB

D15−D4

Conversion result (OD11−OD0)

D3−D0

Don’t care

The output data format is binary (unipolar straight binary).

binary

Zero-scale code = 000h, Vcode = GND

Full-scale code = FFFh, Vcode = V

− 1 LSB

REF

pseudo-differential inputs

The TLV2545 operates in pseudo-differential mode. The inverted input is available on pin 5. It can have a

maximum input ripple of 0.2 V. This is normally used for ground noise rejection.

control and timing

start of the cycle

Each cycle may be started by either CS, FS, or a combination of both. The internal state machine requires one

SCLK high-to-low transition to determine the state of these control signals so internal blocks can be powered

up in an active cycle. Special care to SPI mode is necessary. Make sure there is at least one SCLK whenever

CS (pin 1) is high to ensure proper operation.

TLV2541

Control via CS ( FS = 1 at the falling edge of CS)—The falling edge of CS is the start of the cycle. The MSB

should be read on the first falling SCLK edge after CS is low. Output data changes on the rising edge of

SCLK. This is typically used for a microcontroller with an SPI interface, although it can also be used for a

DSP. The microcontroller SPI interface should be programmed for CPOL = 0 (serial clock referenced to

ground) and CPHA = 1 (data is valid on the falling edge of the serial clock). At least one falling edge transition

on SCLK is needed whenever CS is brought high.

Control via FS (CS is tied/held low)—The MSB is presented after the rising edge of FS. The falling edge

of FS is the start of the cycle. The MSB should be read on the first falling edge of SCLK after FS is low. This

is the typical configuration when the ADC is the only device on the DSP serial port.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

control and timing (continued)

Control via both CS and FS—The MSB is presented after the falling edge of CS. The falling edge of FS is

the start of the sampling cycle. The MSB should be read on the first falling SCLK edge after FS is low. Output

data changes on the rising edge of SCLK. This configuration is typically used for multiple devices connected

to a TMS320 DSP.

TLV2542/5

All control is provided using CS (pin 1) on the TLV2542 and TLV2545. The cycle is started on the falling edge

transition provided by either a CS signal from an SPI microcontroller or FS signal from a TMS320 DSP. Timing

is similar to the TLV2541, with control via CS only.

TLV2542 channel MUX reset cycle

The TLV2542 uses CS to reset the analog input multiplexer. A short active CS cycle (4 to 7 SCLKs) resets the

MUX to AIN0. When the CS cycle time is greater than 7 SCLKs in duration, as in the case for a complete

conversion cycle (CS is low for 16 SCLKs plus maximum conversion time), the MUX toggles to the next channel

(see Figure 4 for timing). One dummy conversion cycle is recommended after power up before attempting to

reset the MUX.

sampling

The converter sample time is 12 SCLKs in duration, beginning on the fifth SCLK received after the converter

has received a high-to-low CS transition (or a high-to-low FS transition for the TLV2541).

conversion

The TLV2541, TLV2542, and TLV2545 complete conversions in the following manner. The conversion is started

after the 16th SCLK falling edge and takes 3.5 μs to complete. Enough time (for conversion) should be allowed

before a rising CS or FS edge so that no conversion is terminated prematurely.

TLV2542 input channel selection is toggled on each rising CS edge. The MUX channel can be reset to AIN0

via CS as described in the earlier section and in Figure 4. The input is sampled for 12 SCLKs, converted, and

the result is presented on SDO during the next cycle. Care should also be taken to allow enough time between

samples to avoid prematurely terminating the cycle, which occurs on a rising CS transition if the conversion is

not complete.

The SDO data presented during a cycle is the result of the conversion of the sample taken during the previous

cycle.

timing diagrams/conversion cycles

SCLK

(powerdown)

(sample)

OD11 OD10 OD9

OD8

OD7

OD6

OD5

OD0

SDO

Figure 2. TLV2541 Timing: Control via CS (FS = 1)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

timing diagrams/conversion cycles (continued)

SCLK

(powerdown)

(sample)

OD11

OD10 OD9

OD8

OD7

OD6

OD0

SDO

Figure 3. TLV2541 Timing: Control via CS and FS or FS Only

SCLK

>8 SCLKs, MUX Toggles to AIN1

<8 SCLKs, MUX

Resets to AIN0

(powerdown)

(sample)

AIN0 Result

OD11

OD0

SDO

Figure 4. TLV2542 Reset Timing

SCLK

(powerdown)

(sample)

OD11

OD10

OD9

OD8

OD7

OD6

OD5

OD0

OD10

OD9

OD11

SDO

Figure 5. TLV2542 and TLV2545 Timing

using CS as the FS input

When interfacing the TLV2541 with the TMS320 DSP, the FSR signal from the DSP may be connected to the

CS input if this is the only device on the serial port. This saves one output terminal from the DSP. (Output data

changes on the falling edge of SCLK. This is the default configuration for the TLV2542 and TLV2545.)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

using CS as the FS input (continued)

SCLK and conversion speed

The input frequency of SCLK can range from 100 kHz to 20 MHz maximum. The ADC conversion uses a

separate internal oscillator with a minimum frequency of 4 MHz. The conversion cycle takes 14 internal oscillator

clocks to complete. This leads to a 3.5-μs conversion time. For a 20-MHz SCLK, the minimum total cycle time

is given by: 16x(1/20M)+14x(1/4M)+one SCLK = 4.35 μs. An additional SCLK is added to account for the

required CS and/or FS high time. These times specify the minimum cycle time for an active CS or FS signal.

If violated, the conversion terminates, invalidating the next data output cycle. Table 1 gives the maximum SCLK

frequency for a given supply voltage and operational mode.

control via pin 1 (CS, SPI interface)

All devices are compatible with this mode operation. A falling CS initiates the cycle (for TLV2541, the FS input

is tied to V ). CS remains low for the entire cycle time (sample+convert+one SCLK) and can then be released.

NOTE:

IMPORTANT: A single SCLK is required whenever CS is high.

control via pin 1 (CS, DSP interface)

All devices are compatible with this mode of operation. The FS signal from a DSP is connected directly to the

CS input of the ADC. A falling edge on the CS input initiates the cycle. (For the TLV2541, the FS input can be

tied to V , although better performance can be achieved when using the FS input for control. Refer to the next

section.) The CS input should remain low for the entire cycle time (sample+convert+one SCLK) and can then

be released.

NOTE:

IMPORTANT: A single SCLK is required whenever CS is high. This should be of little consequence,

since SCLK is normally always present when interfacing with a DSP.

control via pin 1 and pin 7 (CS and FS or FS only, DSP interface)

Only the TLV2541 is compatible with this mode of operation. The CS input to the ADC can be controlled via a

general-purpose I/O pin from the DSP. The FS signal from the DSP is connected directly to the FS input of the

ADC. A falling edge on CS, if used, releases the MSB on the SDO output. When CS is not used, the rising FS

edge releases the MSB. The falling edge on the FS input while SCLK is high initiates the cycle. The CS and

FS inputs should remain low for the entire cycle time (sample+convert+one SCLK) and can then be released.

reference voltage

An external reference is applied via V . The voltage level applied to this pin establishes the upper limit of the

REF

analog inputs to produce a full-scale reading. The value of V

and the analog input should not exceed the

REF

positive supply or be less than GND, consistent with the specified absolute maximum ratings. The digital output

is at full scale when the input signal is equal to or higher than V

to or lower than GND.

and at zero when the input signal is equal

REF

power down and power up

Autopower down is built into these devices in order to reduce power consumption. The actual power savings

depends on the inactive time between cycles and the power supply (loading) decoupling/storage capacitors.

Power-down takes effect immediately after the conversion is complete. This is fast enough to provide some

power savings between cycles with longer than 1 SCLK inactive time. The device power goes down to 5 μA

within 0.5 μs. To achieve the lowest power-down current (deep powerdown) of 1 μA requires 2-ms inactive time

between cycles. The power-down state is initiated at the end of conversion. These devices wake up immediately

at the next falling edge of CS or the rising edge of FS.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

With 1-μF/0.1-μF Capacitor Between Supply and Ground

= 5 V

= 2.7 V

0.5 μS

2 mS

1.5 mA

0.95 mA

5 μA

1 μA

2 μA

1 μA

− Powerdown time − S

(Powerdown)

Table 1. Modes of Operation and Data Throughput

APPROXIMATE

CONVERSION

THROUGHPUT

(ksps)

MAX SCLK (MHz)

(50/50 duty cycle)

CONTROL PIN(s)/DEVICE

= 2.7 V

= 4.5 V

= 2.7 V

V = 4.5 V

CS control only (TLV2541 only)

†

For SPI interface

175

140

200

175

‡

For DSP interface (Use CS as FS)

CS and FS control (TLV2541 only)

DSP interface

200

†

‡

See Figure 29(a).

See Figure 29(b).

See Figure 29(c).

absolute maximum ratings over operating free-air temperature (unless otherwise noted)^¶

Supply voltage range, GND to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.5 V

Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.3 V

Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V + 0.3 V

Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.3 V

Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C

Operating free-air temperature range, T : C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

Storage temperature range, T

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

recommended operating conditions

MIN NOM

MAX

UNIT

Supply voltage, V

2.7

3.3

5.5

Positive external reference voltage input, V

Analog input voltage (see Note 1)

(see Note 1)

REFP

High level control input voltage, V

2.1

Low-level control input voltage, V

0.6

= REF = 4.5 V

= REF = 2.7 V

Setup time, CS falling edge before first SCLK falling edge,

su(CSL-SCLKL)

Hold time, CS falling edge after SCLK falling edge, t

h(SCLKL-CSL)

Delay time, delay from CS falling edge to FS rising edge, t

(TLV2541 only)

0.5

0.35

SCLKs

d(CSL-FSH)

Setup time, FS rising edge before SCLK falling edge, t

su(FSH-SCLKL)

Hold time, FS high after SCLK falling edge, t

(TLV2541 only)

0.65 SCLKs

h(SCLKL-FSL)

Pulse width CS high time, t

Pulse width FS high time, t

100

0.75

w(H_CS)

(TLV2541 only)

SCLKs

w(H_FS)

SCLK cycle time, V = 3.6 V to 2.7 V, t

(maximum tolerance of 40/60 duty cycle)

10000

c(SCLK)

SCLK cycle time, V = 5.5 V to 4.5 V, t

c(SCLK)

Pulse width low time, t

0.4

0.6 SCLK

w(L_SCLK)

Pulse width high time, t

w(H_SCLK)

Hold time, hold from end of conversion to CS high, t

(EOC is internal, indicates end of conversion

h(EOC-CSH)

0.05

μs

time, t )

Active CS cycle time to reset internal MUX to AIN0, t

(TLV2542 only)

SCLKs

(reset cycle)

= REF = 4.5 V, 25-pF load

= REF = 2.7 V, 25-pF load

= REF = 4.5 V, 25-pF load

= REF = 2.7 V, 25-pF load

= REF = 4.5 V, 25-pF load

= REF = 2.7 V, 25-pF load

= REF = 4.5 V, 25-pF load

= REF = 2.7 V, 25-pF load

Delay time, delay from CS falling edge to SDO valid, t

d(CSL-SDOV)

Delay time, delay from FS falling edge to SDO valid, t

(TLV2541 only)

d(FSL-SDOV)

Delay time, delay from SCLK rising edge to SDO valid,

d(SCLKH-SDOV)

Delay time, delay from 17th SCLK rising edge to SDO 3-state,

d(SCLK17H-SDOZ)

Conversion clock = internal

oscillator

Conversion time, t

2.1

2.6

3.5

μs

Sampling time, t

See Note 2

300

(sample)

TLV2541/2/5C

TLV2541/2/5I

Operating free-air temperature, T

°C

−40

NOTES: 1. Analog input voltages greater than that applied to V

to GND convert as all zeros(000000000000).

convert as all ones (111111111111), while input voltages less than that applied

REF

2. Minimal t

is given by 0.9 × 50 pF × (R + 0.5 kΩ), where R is the source output impedance.

(sample)

S S

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

electrical characteristics over recommended operating free-air temperature range,

= V

= 2.7 V to 5.5 V (unless otherwise noted)

REF

†

PARAMETER

TEST CONDITIONS

= 5.5 V, I = −0.2 mA at 30-pF load

MIN

2.4

TYP

MAX

UNIT

High-level output voltage

Low-level output voltage

= 2.7 V, I = -20 μA at 30-pF load

−0.2

= 5.5 V, I = 0.8 mA at 30-pF load

0.4

0.1

= 2.7 V, I = 20 μA at 30-pF load

= V

−1

2.5

Off-state output current

(high-impedance-state)

CS = V

μA

= 0

−2.5

2.5

High-level input current

Low-level input current

V = V

0.005

−0.00

V = 0 V

2.5

= 4.5 V to 5.5 V

= 2.7 V to 3.3 V

1.3

1.5

Operating supply current

CS at 0 V

0.85

0.95

For all digital inputs,

0≤ V ≤ 0.3 V or V ≥ V − 0.3 V,

Autopower-down current

μA

SCLK = 0, V = 4.5 V to 5.5 V, Ext ref

≥ 0.5 μs

(powerdown)

= 2.7 V to 3.3 V, Ext ref

CC(AUTOPWDN)

For all digital inputs,

0≤ V ≤ 0.3 V or V ≥ V − 0.3 V,

Deep autopower-down current

≥ 2 ms

μA

SCLK = 0, V = 4.5 V to 5.5 V, Ext ref

(powerdown)

= 2.7 V to 3.3 V

Selected channel at V

Selected analog input channel

leakage current

μA

Selected channel at 0 V

Analog inputs

−1

Input capacitance

Control Inputs

= 5.5 V

= 2.7 V

500

600

Input on resistance

Autopower down

0.5

SCLK

†

All typical values are at V = 5 V, T = 25°C.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

ac specifications (f_i= 20 kHz)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

200 KSPS, V = V

= 5.5 V

= 2.7 V

= 5.5 V

= 2.7 V

= 5.5 V

= 2.7 V

= 5.5 V

= 2.7 V

REF

SINAD

THD

Signal-to-noise ratio +distortion

150 KSPS, V = V

200 KSPS, V = V

−84

11.8

11.6

−84

−80

Total harmonic distortion

Effective number of bits

Spurious free dynamic range

Bits

150 KSPS, V = V

200 KSPS, V = V

ENOB

SFDR

150 KSPS, V = V

200 KSPS, V = V

−80

150 KSPS, V = V

Analog Input

Full-power bandwidth, −3 dB

MHz

kHz

Full-power bandwidth, −1 dB

500

external reference specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Reference input voltage

= 2.7 V to 5.5 V

CS = 1, SCLK = 0

100

MΩ

kΩ

= 5.5 V

CS = 0, SCLK = 20 MHz

CS = 1, SCLK = 0

Reference input impedance

Reference current

100

MΩ

kΩ

= 2.7 V

CS = 0, SCLK = 20 MHz

CS = 1, SCLK = 0

100

= V

= 5.5 V,

= 2.7 V,

400

200

REF

μA

REF

= V

= 5.5 V

= 2.7 V

REF

CS = 0, SCLK = 20 MHz

CS = 1, SCLK = 0

Reference input capacitance

= V

CS = 0, SCLK = 20 MHz

REF

Reference voltage

= 2.7 V to 5.5 V

dc specification, V = V

= 2.7 V to 5.5 V, SCLK frequency = 20 MHz at 5 V, 15 MHz at 3 V (unless otherwise

REF

noted)

PARAMETER

Integral linearity error (see Note 4)

Differential linearity error

TEST CONDITIONS

MIN

TYP

0.6

MAX

UNIT

LSB

INL

DNL

See Note 3

0.5

TLV2541/42

TLV2545

1.5

2.5

Offset error (see Note 5)

See Note 3

LSB

TLV2541/42

TLV2545

Gain error (see Note 5)

TLV2541/42

TLV2545

Total unadjusted error (see Note 6)

NOTES: 3. Analog input voltages greater than that applied to V

convert as all ones (111111111111).

REF

4. Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.

5. Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the difference

between 111111111111 and the converted output for full-scale input voltage.

6. Total unadjusted error comprises linearity, zero, and full-scale errors.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

PARAMETER MEASUREMENT INFORMATION

(sample)

w(H_SCLK)

SCLK

w(L_SCLK)

(powerdown)

su(CSL-SCLKL)

h(SCLKL-FSL)

w(H_CS)

su(FSH-SCLKL)

h(EOC-CSH)

d(CSL-FSH)

d(SCLKH-SDOV)

d(SCLK17H-SDOZ)

w(H_FS)

OD11

OD8

OD0

SDO

d(CSL-SDOV)

Figure 6. TLV2541 Critical Timing (Control via CS and FS or FS only)

(sample)

su(CSL−SCLKL)

SCLK

(powerdown)

d(SCLK17H-SDOZ)

d(SCLKH-SDOV)

OD11

OD10

OD9

OD0

SDO

h(EOC−CSH)

d(CSL-SDOV)

Figure 7. TLV2541 Critical Timing (Control via CS only, FS = 1)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

PARAMETER MEASUREMENT INFORMATION

(sample)

SCLK

(reset cycle)

MUX = AIN0

w(H_CS)

h(EOC-CSH)

d(SCLKH-SDOV)

d(CSL-SDOV)

OD11

OD0

OD11

SDO

d(SCLK17H-SDOZ)

d(CSL-SDOV)

Figure 8. TLV2542 Reset Cycle Critical Timing

(sample)

w(H_SCLK)

SCLK

w(L_SCLK)

h(SCLKL-CSL)

(powerdown)

su(CSL-SCLKL)

w(H_CS)

h(EOC-CSH)

d(SCLKH-SDOV)

d(SCLK17H-SDOZ)

OD11

OD8

OD0

SDO

d(CSL-SDOV)

Figure 9. TLV2542 and TLV2545 Conversion Cycle Critical Timing

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

TYPICAL CHARACTERISTICS

INTEGRAL NONLINEARITY

FREE-AIR TEMPERATURE

INTEGRAL NONLINEARITY

FREE-AIR TEMPERATURE

0.7

0.65

0.6

= REF = 2.7 V

150 KSPS

= REF = 5.5 V

200 KSPS

0.55

0.5

−40

− Free-Air Temperature − °C

Figure 10

Figure 11

DIFFERENTIAL NONLINEARITY

FREE-AIR TEMPERATURE

0.35

0.6

0.5

= REF = 5.5 V

= REF = 2.7 V

150 KSPS

200 KSPS

0.4

0.3

0.2

0.3

0.1

0.25

−40

− Free-air Temperature − °C

− Free-Air Temperature − °C

Figure 12

Figure 13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

TYPICAL CHARACTERISTICS

OFFSET ERROR

FREE-AIR TEMPERATURE

GAIN ERROR

FREE-AIR TEMPERATURE

0.5

0.4

0.3

0.2

0.9

= REF = 2.7 V

150 KSPS

= REF = 5.5 V

200 KSPS

0.85

0.1

0.8

−40

− Free-Air Temperature − °C

Figure 14

Figure 15

SUPPLY CURRENT

FREE-AIR TEMPERATURE

1.5

= REF = 5.5 V

200 KSPS

1.4

1.3

1.2

−40

− Free-Air Temperature − °C

Figure 16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

TYPICAL CHARACTERISTICS

INTEGRAL NONLINEARITY ERROR

DIGITAL OUTPUT CODES

= REF = 2.7 V

150 KSPS

0.5

−0.5

−1

4095

Digital Output Codes

Figure 17

DIFFERENTIAL NONLINEARITY ERROR

DIGITAL OUTPUT CODES

= REF = 2.7 V

150 KSPS

0.5

−0.5

−1

4095

Digital Output Codes

Figure 18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

TYPICAL CHARACTERISTICS

INTEGRAL NONLINEARITY ERROR

DIGITAL OUTPUT CODES

= REF = 5.5 V

200 KSPS

0.5

−0.5

−1

4095

Digital Output Codes

Figure 19

DIFFERENTIAL NONLINEARITY ERROR

DIGITAL OUTPUT CODES

= REF = 5.5 V

200 KSPS

0.5

−0.5

−1

4095

Digital Output Codes

Figure 20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

TYPICAL CHARACTERISTICS

2048 POINTS FAST FOURIER TRANSFORM (FFT)

= REF = 2.7 V

150 KSPS

−20

−40

f = 20 kHz

−60

−80

−100

−120

−140

100

f − Input Frequency − KHz

Figure 21

2048 POINTS FAST FOURIER TRANSFORM (FFT)

= REF = 5.5 V

200 KSPS

−20

f = 20 kHz

−40

−60

−80

−100

−120

−140

100

f − Input Frequency − KHz

Figure 22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

TYPICAL CHARACTERISTICS

SIGNAL-TO-NOISE + DISTORTION

INPUT FREQUENCY

= REF = 5.5 V

200 KSPS

= REF = 2.7 V

150 KSPS

100

f − Input Frequency − KHz

Figure 23

Figure 24

EFFECTIVE NUMBER OF BITS

INPUT FREQUENCY

11.8

11.6

11.4

= REF = 2.7 V

150 KSPS

= REF = 5.5 V

200 KSPS

11.9

11.8

11.7

11.6

11.5

11.4

11.3

11.2

11.1

100

f − Input Frequency − KHz

Figure 25

Figure 26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

TYPICAL CHARACTERISTICS

TOTAL HARMONIC DISTORTION

INPUT FREQUENCY

−75

= REF = 2.7 V

150 KSPS

−76

−77

−78

−79

−80

−81

−82

−83

−84

−85

f − Input Frequency − KHz

Figure 27

TOTAL HARMONIC DISTORTION

INPUT FREQUENCY

−70

−72

−74

−76

−78

−80

−82

= REF = 5.5 V

200 KSPS

−84

−86

−88

−90

100

f − Input Frequency − KHz

Figure 28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

APPLICATION INFORMATION

10 kΩ

TLV2541

SDO

MISO

AIN

SCLK

GND

SCLK

REF

SPI PORT

EXT

Reference

(a)

10 kΩ

TLV2541

SDO

CLKX

AIN

CLKR

SCLK

FSX

FSR

GND

REF

DSP

EXT

Reference

(b)

TLV2541

FSX

FSR

SDO

AIN

CLKX

CLKR

GPIO

SCLK

REF

GND

DSP

EXT

Reference

(c)

Figure 29. Typical TLV2541 Interface to a TMS320 DSP

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

APPLICATION INFORMATION

EXT

Reference

TMS320

FSX

10 kΩ

SDO

SCLK

FSR

CLKR

REF

CLKX

TLV2542/45

GND

DSP

†

AIN 0/AIN (+)

AIN 1/AIN (−)

†

For TLV2545 only

Figure 30. Typical TLV2542/45 Interface to a TMS320 DSP

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

PACKAGE OPTION ADDENDUM

www.ti.com

31-Oct-2013

PACKAGING INFORMATION

Orderable Device

TLV2541CDGK

TLV2541CDGKG4

TLV2541CDGKR

TLV2541CDGKRG4

TLV2541ID

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

0 to 70

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

ACTIVE

VSSOP

SOIC

DGK

Green (RoHS

& no Sb/Br)

CU NIPDAUAG

CU NIPDAU

Level-1-260C-UNLIM

AGZ

2541I

AHA

2541I

AHB

2542I

ACTIVE

DGK

2500

Green (RoHS

& no Sb/Br)

0 to 70

Green (RoHS

& no Sb/Br)

0 to 70

Green (RoHS

& no Sb/Br)

0 to 70

Green (RoHS

& no Sb/Br)

-40 to 85

0 to 70

TLV2541IDG4

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

TLV2541IDGK

VSSOP

SOIC

DGK

Green (RoHS

& no Sb/Br)

CU NIPDAUAG

CU NIPDAU

TLV2541IDGKG4

TLV2541IDGKR

TLV2541IDGKRG4

TLV2541IDR

Green (RoHS

& no Sb/Br)

2500

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TLV2541IDRG4

TLV2542CDGK

TLV2542CDGKG4

TLV2542CDGKR

TLV2542CDGKRG4

TLV2542ID

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

VSSOP

SOIC

DGK

Green (RoHS

& no Sb/Br)

CU NIPDAUAG

CU NIPDAU

Green (RoHS

& no Sb/Br)

0 to 70

2500

Green (RoHS

& no Sb/Br)

0 to 70

Green (RoHS

& no Sb/Br)

0 to 70

Green (RoHS

& no Sb/Br)

-40 to 85

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

31-Oct-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

0 to 70

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

TLV2542IDG4

TLV2542IDGK

TLV2542IDGKG4

TLV2542IDGKR

TLV2542IDGKRG4

TLV2542IDR

ACTIVE

SOIC

VSSOP

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

CU NIPDAUAG

CU NIPDAU

Level-1-260C-UNLIM

2542I

AHC

2542I

AHD

2545I

AHE

ACTIVE

DGK

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

2500

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TLV2542IDRG4

TLV2545CDGK

TLV2545CDGKG4

TLV2545ID

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

VSSOP

SOIC

DGK

Green (RoHS

& no Sb/Br)

CU NIPDAUAG

CU NIPDAU

Green (RoHS

& no Sb/Br)

0 to 70

Green (RoHS

& no Sb/Br)

-40 to 85

TLV2545IDG4

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

TLV2545IDGK

TLV2545IDGKG4

VSSOP

DGK

Green (RoHS

& no Sb/Br)

CU NIPDAUAG

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

31-Oct-2013

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Aug-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV2541CDGKR

TLV2541IDGKR

TLV2541IDR

VSSOP

SOIC

DGK

2500

330.0

12.4

5.3

6.4

5.3

6.4

3.4

5.2

3.4

5.2

1.4

2.1

1.4

2.1

8.0

12.0

TLV2542CDGKR

TLV2542IDGKR

TLV2542IDR

VSSOP

SOIC

DGK

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Aug-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLV2541CDGKR

TLV2541IDGKR

TLV2541IDR

VSSOP

SOIC

DGK

2500

367.0

35.0

TLV2542CDGKR

TLV2542IDGKR

TLV2542IDR

VSSOP

SOIC

DGK

Pack Materials-Page 2

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TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

Medical

Logic

Security

www.ti.com/security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense

Video and Imaging

www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TLV2541_14 [TI]

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