TLV2548IPWG4 [TI]

12 位 200kSPS ADC 系列输出、自动断电(软件和硬件)、低功耗、8 x FIFO 和 8 通道 | PW | 20 | -40 to 85;
TLV2548IPWG4
型号: TLV2548IPWG4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

12 位 200kSPS ADC 系列输出、自动断电(软件和硬件)、低功耗、8 x FIFO 和 8 通道 | PW | 20 | -40 to 85

先进先出芯片 光电二极管 转换器 模数转换器
文件: 总39页 (文件大小:648K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
Maximum Throughput 200 KSPS  
Analog Input Range 0 V to Supply Voltage  
with 500 kHz BW  
Built-In Reference, Conversion Clock and  
8× FIFO  
Hardware Controlled and Programmable  
Sampling Period  
Differential/Integral Nonlinearity Error:  
±1 LSB  
Low Operating Current (1 mA at 2.7 V,  
1.2 mA at 5.5 V External Ref,  
1.6 mA at 2.7 V,  
Signal-to-Noise and Distortion Ratio:  
69 dB, f = 12 kHz  
i
2.1 mA at 5.5 V, Internal Ref)  
Spurious Free Dynamic Range: 75 dB,  
Power Down: Software/Hardware  
Power-Down Mode (1 µA Max, Ext Ref),  
Auto Power-Down Mode (1 µA, Ext Ref)  
f = 12 kHz  
i
SPI/DSP-Compatible Serial Interfaces With  
SCLK up to 20 MHz  
Programmable Auto-Channel Sweep  
Single Wide Range Supply 2.7 Vdc to  
5.5 Vdc  
D OR PW PACKAGE  
(TOP VIEW)  
DW OR PW PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
20 CS  
SDO  
SDI  
CS  
SDO  
SDI  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
19  
18  
17  
16  
15  
14  
13  
12  
11  
REFP  
REFM  
FS  
REFP  
REFM  
FS  
SCLK  
SCLK  
EOC/(INT)  
EOC/(INT)  
V
PWDN  
GND  
V
PWDN  
GND  
CSTART  
A7  
CC  
CC  
A0  
A1  
A2  
A0  
A1  
A2  
A3  
A4  
10 CSTART  
A3  
9
A6  
A5  
description  
The TLV2548 and TLV2544 are a family of high performance, 12-bit low power, 3.6 µs, CMOS analog-to-digital  
converters (ADC) which operate from a single 2.7 V to 5.5 V power supply. These devices have three digital  
inputs and a 3-state output [chip select (CS), serial input-output clock (SCLK), serial data input (SDI) and serial  
data output (SDO)] that provide a direct 4-wire interface to the serial port of most popular host microprocessors  
(SPI interface). When interfaced with a DSP, a frame sync (FS) signal is used to indicate the start of a serial data  
frame.  
In addition to a high-speed A/D converter and versatile control capability, these devices have an on-chip analog  
multiplexer that can select any analog inputs or one of three internal self-test voltages. The sample-and-hold  
function is automatically started after the fourth SCLK edge (normal sampling) or can be controlled by a special  
pin, CSTART, to extend the sampling period (extended sampling). The normal sampling period can also be  
programmed as short (12 SCLKs) or as long (24 SCLKs) to accommodate faster SCLK operation popular  
among high-performance signal processors. The TLV2548 and TLV2544 are designed to operate with very low  
power consumption. The power-saving feature is further enhanced with software/hardware/auto power down  
modes and programmable conversion speeds. The conversion clock (OSC) and reference are built-in. The  
converter can use the external SCLK as the source of the conversion clock to achieve higher (up to 3.6 µs when  
a 20 MHz SCLK is used) conversion speed. Two different internal reference voltages are available. An optional  
external reference can also be used to achieve maximum flexibility.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
functional block diagram  
V
CC  
4/2 V  
Reference  
REFP  
REFM  
FIFO  
12 Bit × 8  
2548 2544  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A0  
Low Power  
12-BIT  
SAR ADC  
X
A1  
X
A2  
X
S/H  
OSC  
Conversion  
Clock  
Command  
Decode  
A3  
X
M
U
X
SDO  
CFR  
SDI  
CMR (4 MSBs)  
SCLK  
CS  
FS  
Control Logic  
EOC/(INT)  
CSTART  
PWDN  
GND  
AVAILABLE OPTIONS  
PACKAGED DEVICES  
T
A
20-TSSOP  
(PW)  
20-SOIC  
(DW)  
16-SOIC  
(D)  
16-TSSOP  
(PW)  
0°C to 70°C  
TLV2548CPW  
TLV2548CDW  
TLV2548IDW  
TLV2544CD  
TLV2544ID  
TLV2544CPW  
TLV2544IPW  
40°C to 85°C TLV2548IPW  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
Terminal Functions  
TERMINAL  
NO.  
TLV2544 TLV2548  
I/O  
DESCRIPTION  
NAME  
A0  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
6
7
8
9
6
7
8
I
Analog signal inputs. The analog inputs are applied to these terminals and are internally  
multiplexed. The driving source impedance should be less than or equal to 1 k.  
A1  
A2  
A3  
For a source impedance greater than 1 k, use the asynchronous conversion start signal CSTART  
(CSTART low time controls the sampling period) or program long sampling period to increase the  
sampling time.  
9
10  
11  
12  
13  
CS  
16  
10  
20  
14  
I
I
Chip select. A high-to-low transition on the CS input resets the internal 4-bit counter, enables SDI,  
and removes SDO from 3-state within a maximum setup time. SDI is disabled within a setup time  
after the 4-bit counter counts to 16 (clock edges) or a low-to-high transition of CS whichever  
happens first. SDO is 3-stated after the rising edge of CS.  
CS can be used as the FS pin when a dedicated serial port is used.  
CSTART  
This terminal controls the start of sampling of the analog input from a selected multiplex channel.  
A high-to-low transition starts sampling of the analog input signal. A low-to-high transition puts the  
S/H in hold mode and starts the conversion. This input is independent from SCLK and works when  
CS is high (inactive). The low time of CSTART controls the duration of the sampling period of the  
converter (extended sampling).  
Tie this terminal to V  
if not used.  
CC  
EOC/(INT)  
4
4
O
End of conversion or interrupt to host processor.  
[PROGRAMMED AS EOC]: This output goes from a high-to-low logic level at the end of the  
sampling period and remains low until the conversion is complete and data are ready for transfer.  
EOC is used in conversion mode 00 only.  
[PROGRAMMED AS INT]: This pin can also be programmed as an interrupt output signal to the  
host processor. The falling edge of INT indicates data are ready for output. The following CSor  
FSclears INT. The falling edge of INT puts SDO back to 3-state even if CS is still active.  
FS  
13  
17  
I
DSP frame sync input. Indication of the start of a serial data frame in or out of the device. If FS  
remains low after the falling edge of CS, SDI is not enabled until an active FS is presented. A  
high-to-low transition on the FS input resets the internal 4-bit counter and enables SDI within a  
maximum setup time. SDI is disabled within a setup time after the 4-bit counter counts to 16 (clock  
edges) or a low-to-high transition of CS whichever happens first. SDO is 3-stated after the 16th bit  
is presented.  
Tie this terminal to V  
if not used.  
CC  
GND  
11  
12  
3
15  
16  
3
I
I
I
Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with  
respect to GND.  
PWDN  
SCLK  
Both analog and reference circuits are powered down when this pin is at logic zero. The device can  
be restarted by active CS or CSTART after this pin is pulled back to logic one.  
Input serial clock. This terminal receives the serial SCLK from the host processor. SCLK is used to  
clock the input SDI to the input register. When programmed, it may also be used as the source of  
the conversion clock.  
SDI  
2
2
I
Serial data input. The input data is presented with the MSB (D15) first. The first 4-bit MSBs,  
D(15–12) are decoded as one of the 16 commands (12 only for the TLV2544). All trailing blanks are  
filled with zeros. The configure write commands require an additional 12 bits of data.  
When FS is not used (FS =1), the first MSB (D15) is expected after the falling edge of CS and is  
shifted in on the rising edges of SCLK (after CS).  
When FS is used (typical with an active FS from a DSP) the first MSB (D15) is expected after the  
falling edge of FS and is shifted in on the falling edges of SCLK.  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
Terminal Functions (Continued)  
TERMINAL  
NO.  
I/O  
DESCRIPTION  
NAME  
SDO  
TLV2544 TLV2548  
1
1
O
The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state  
when CS is high and after the CS falling edge and until the MSB (D15) is presented. The output  
format is MSB (D15) first.  
When FS is not used (FS = 1 at the falling edge of CS), the MSB (D15) is presented to the SDO pin  
after the CS falling edge, and successive data are available at the rising edge of SCLK.  
When FS is used (FS = 0 at the falling edge of CS), the MSB (D15) is presented to SDO after the  
fallingedge of CS and FS = 0 is detected. Successive data are available at the falling edge of SCLK.  
(This is typically used with an active FS from a DSP.)  
For conversion and FIFO read cycles, the first 12 bits are result from previous conversion (data)  
followed by 4 trailing zeros. The first four bits from SDO for CFR read cycles should be ignored. The  
register content is in the last 12 bits. SDO is 3 stated after the 16th bit.  
REFM  
REFP  
14  
15  
18  
19  
I
I
External reference input or internal reference decoupling.  
External reference input or internal reference decoupling. (Shunt capacitors of 10 µF and 0.1 µF  
between REFP and REFM.) The maximum input voltage range is determined by the difference  
between the voltage applied to this terminal and the REFM terminal when an external reference is  
used.  
V
CC  
5
5
I
Positive supply voltage  
detailed description  
analog inputs and internal test voltages  
The 4/8 analog inputs and three internal test inputs are selected by the analog multiplexer depending on the  
command entered. The input multiplexer is a break-before-make type to reduce input-to-input noise injection  
resulting from channel switching.  
converter  
The TLV2544/48 uses a 12-bit successive approximation ADC utilizing a charge redistribution DAC. Figure 1  
shows a simplified version of the DAC.  
The sampling capacitor acquires the signal on Ain during the sampling period. When the conversion process  
starts, theSARcontrollogicandchargeredistributionDACareusedtoaddandsubtractfixedamountsofcharge  
from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is  
balanced, the conversion is complete and the ADC output code is generated.  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
detailed description (continued)  
Charge  
Redistribution  
DAC  
_
+
Ain  
Control  
Logic  
ADC Code  
REFM  
Figure 1. Simplified Model of the Successive-Approximation System  
serial interface  
INPUT DATA FORMAT  
MSB  
D15–D12  
Command  
LSB  
D11–D0  
Configuration data field  
Input data is binary. All trailing blanks can be filled with zeros.  
OUTPUT DATA FORMAT READ CFR  
MSB  
LSB  
D15–D12  
Don’t care  
D11–D0  
Register content  
OUTPUT DATA FORMAT CONVERSION/READ FIFO  
MSB LSB  
D15–D4  
D3–D0  
All zeros  
Conversion result  
The output data format is binary (unipolar straight binary).  
binary  
Zero scale code = 000h, Vcode = VREFM  
Full scale code = FFFh, Vcode = VREFP – 1 LSB  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
control and timing  
start of the cycle:  
When FS is not used ( FS = 1 at the falling edge of CS), the falling edge of CS is the start of the cycle. Input  
data is shifted in on the rising edge of SCLK, and output data changes on the falling edge of SCLK. This  
is typically used for a SPI microcontroller although it can also be used for a DSP.  
When FS is used ( FS is an active signal from a DSP), the falling edge of FS is the start of the cycle. Input  
data is shifted in on the falling edge, and output data changes on the rising edge of SCLK. This is typically  
used for a TMS320 DSP.  
first 4-MSBs: the command register (CMR)  
The TLV2544/TLV2548 have a 4-bit command set (see Table 1) plus a 12-bit configuration data field. Most of  
the commands require only the first 4 MSBs, i.e. without the 12-bit data field.  
NOTE:  
The device requires a write CFR (configuration register) with 000h data (write A000h to the serial  
input) at power up to initialize host select mode.  
The valid commands are listed in Table 1.  
Table 1. TLV2544/TLV2548 Command Set  
SDI D(15–12) BINARY, HEX  
TLV2548 COMMAND  
Select analog input channel 0  
Select analog input channel 1  
Select analog input channel 2  
Select analog input channel 3  
Select analog input channel 4  
Select analog input channel 5  
Select analog input channel 6  
Select analog input channel 7  
SW power down (analog + reference)  
TLV2544 COMMAND  
0000b  
0001b  
0010b  
0011b  
0100b  
0101b  
0110b  
0111b  
1000b  
1001b  
0000h  
1000h  
2000h  
3000h  
4000h  
5000h  
6000h  
7000h  
8000h  
9000h  
Select analog input channel 0  
N/A  
Select analog input channel 1  
N/A  
Select analog input channel 2  
N/A  
Select analog input channel 3  
N/A  
Read CFR register data shown as SDO D(11–0)  
Write CFR followed by 12-bit data, e.g., 0A100h means external reference,  
short sampling, SCLK/4, single shot, INT  
1010b  
A000h plus data  
1011b  
1100b  
1101b  
1110b  
1111b  
B000h  
C000h  
D000h  
E000h  
Select test, voltage = (REFP+REFM)/2  
Select test, voltage = REFM  
Select test, voltage = REFP  
FIFO read, FIFO contents shown as SDO D(15–4), D(3–0) = 0000  
F000h plus data Reserved  
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
control and timing (continued)  
configuration  
Configuration data is stored in one 12-bit configuration register (CFR) (see Table 2 for CFR bit definitions). Once  
configured after first power up, the information is retained in the H/W or S/W power down state. When the device  
is being configured, a write CFR cycle is issued by the host processor. This is a 16-bit write. If the SCLK stops  
after the first 8 bits are entered, then the next eight bits can be taken after the SCLK is resumed. The status of  
the CFR can be read with a read CFR command when the device is programmand for one-shot conversion  
mode (CFR D[6,5] = 00).  
Table 2. TLV2544/TLV2548 Configuration Register (CFR) Bit Definitions  
BIT  
D11  
DEFINITION  
Reference select  
0: External  
1: internal  
D10  
D9  
Internal reference voltage select  
0: Internal ref = 4 V 1: internal ref = 2 V  
Sample period select  
0: Short sampling 12 SCLKs (1x sampling time)  
1: Long sampling 24 SCLKs (2x sampling time)  
D(8–7)  
D(6,5)  
Conversion clock source select  
00: Conversion clock = internal OSC  
01: Conversion clock = SCLK  
10: Conversion clock = SCLK/4  
11: Conversion clock = SCLK/2  
Conversion mode select  
00: Single shot mode  
01: Repeat mode  
10: Sweep mode  
11: Repeat sweep mode  
D(4,3)  
TLV2548  
TLV2544  
Sweep auto sequence select  
00: 0–1–2–3–4–5–6–7  
01: 0–2–4–6–0–2–4–6  
10: 0–0–2–2–4–4–6–6  
11: 0–2–0–2–0–2–0–2  
Sweep auto sequence select  
00: N/A  
01: 0–1–2–3–0–1–2–3  
10: 0–0–1–1–2–2–3–3  
11: 0–1–0–1–0–1–0–1  
D2  
EOC/INT – pin function select  
0: Pin used as INT  
1: Pin used as EOC  
D(1,0)  
FIFO trigger level (sweep sequence length)  
00: Full (INT generated after FIFO level 7 filled)  
01: 3/4 (INT generated after FIFO level 5 filled)  
10: 1/2 (INT generated after FIFO level 3 filled)  
11: 1/4 (INT generated after FIFO level 1 filled)  
These bits only take effect in conversion modes 10 and 11.  
sampling  
The sampling period starts after the first 4 input data are shifted in if they are decoded as one of the conversion  
commands. These are select analog input (channel 0 through 7) and select test (channel 1 through 3).  
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
normal sampling  
When the converter is using normal sampling, the sampling period is programmable. It can be 12 SCLKs (short  
sampling) or 24 SCLKs (long sampling). Long sampling helps the input analog signal sampled to settle to 0.5  
LSB accuracy when SCLK is faster than 10 MHz or when input source resistance is high.  
extended sampling  
An asynchronous (to the SCLK) signal, via dedicated hardware pin CSTART, can be used in order to have total  
control of the sampling period and the start of a conversion. This is extended sampling. The falling edge of  
CSTART is the start of the sampling period. The rising edge of CSTART is the end of the sampling period and  
the start of the conversion. This function is useful for an application that requires:  
The use of an extended sampling period to accommodate different input source impedance.  
The use of a faster I/O clock on the serial port but not enough sampling time is available due to the fixed  
number of SCLKs. This could be due to a high input source impedance or due to higher MUX ON resistance  
at lower supply voltage (refer to application information).  
Once the conversion is complete, the processor can initiate a read cycle using either the read FIFO command  
to read the conversion result or simply select the next channel number for conversion. Since the device has a  
valid conversion result in the output buffer, the conversion result is simply presented at the serial data output.  
TLV2544/TLV2548 conversion modes  
The TLV2544 and TLV2548 have four different conversion modes (mode 00, 01, 10, 11). The operation of each  
mode is slightly different, depending on how the converter performs the sampling and which host interface is  
used. The trigger for a conversion can be an active CSTART (extended sampling), CS (normal sampling, SPI  
interface), or FS (normal sampling, TMS320 DSP interface). When FS is used as the trigger, CS can be held  
active, i.e. CS does not need to be toggled through the trigger sequence. Different types of triggers should not  
be mixed throughout the repeat and sweep operations. When CSTART is used as the trigger, the conversion  
starts on the rising edge of CSTART. The minimum low time for CSTART is 800 ns. If an active CS or FS is used  
as the trigger, the conversion is started after the 16th or 28th SCLK edge. Enough time (for conversion) should  
be allowed between consecutive triggers so that no conversion is terminated prematurely.  
one shot mode (mode 00)  
One shot mode (mode 00) does not use the FIFO, and the EOC is generated as the conversion is in progress  
(or INT is generated after the conversion is done).  
repeat mode (mode 01)  
Repeat mode (mode 01) uses the FIFO. Once the programmed FIFO threshold is reached, the FIFO must be  
read, or the data is lost and the sequence starts over again. This allows the host to set up the converter and  
continue monitoring a fixed input and come back to get a set of samples when preferred. The first conversion  
must start with a select command so an analog input channel can be selected.  
sweep mode (mode 10)  
Sweep mode (mode 10) also uses the FIFO. Once it is programmed in this mode, all of the channels listed in  
the selected sweep sequence are visited in sequence. The results are converted and stored in the FIFO. This  
sweep sequence may not be completed if the FIFO threshold is reached before the list is completed. This allows  
the system designer to change the sweep sequence length. Once the FIFO has reached its programmed  
threshold, aninterrupt(INT)isgenerated. ThehostmustissueareadFIFOcommandtoreadandcleartheFIFO  
before the next sweep can start.  
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
TLV2544/TLV2548 conversion modes (continued)  
repeat sweep mode (mode 11)  
Repeat sweep mode (mode 11) works the same way as mode 10 except the operation has an option to continue  
even if the FIFO threshold is reached. Once the FIFO has reached its programmed threshold, an interrupt (INT)  
is generated. Then two things may happen:  
1. The host may choose to act on it (read the FIFO) or ignore it. If the next cycle is a read FIFO cycle, all of  
the data stored in the FIFO is retained until it has been read in order.  
2. If the next cycle is not a read FIFO cycle, or another CSTART is generated, all of the content stored in the  
FIFO is cleared before the next conversion result is stored in the FIFO, and the sweep is continued.  
Table 3. TLV2544/TLV2548 Conversion Mode  
CONVERSION  
MODE  
CFR  
D(6,5)  
SAMPLING  
TYPE  
OPERATION  
Single conversion from a selected channel  
CS or FS to start select/sampling/conversion/read  
One INT or EOC generated after each conversion  
One shot  
00  
Normal  
Host must serve INT by selecting channel, and converting and reading the previous output.  
Extended  
Single conversion from a selected channel  
CS to select/read  
CSTART to start sampling and conversion  
One INT or EOC generated after each conversion  
Host must serve INT by selecting next channel and reading the previous output.  
Repeat  
01  
Normal  
Repeated conversions from a selected channel  
CS or FS to start sampling/conversion  
One INT generated after FIFO is filled up to the threshold  
Host must serve INT by either 1) (FIFO read) reading out all of the FIFO contents up to the  
threshold, then repeat conversions from the same selected channel or 2) writing another  
command(s) to change the conversion mode. If the FIFO is not read when INT is served, it is  
cleared.  
Extended  
Normal  
Same as normal sampling except CSTART starts each sampling and conversion when CS is  
high.  
Sweep  
10  
11  
One conversion per channel from a sequence of channels  
CS or FS to start sampling/conversion  
One INT generated after FIFO is filled up to the threshold  
Host must serve INT by (FIFO read) reading out all of the FIFO contents up to the threshold, then  
write another command(s) to change the conversion mode.  
Extended  
Normal  
Same as normal sampling except CSTART starts each sampling and conversion when CS is  
high.  
Repeat sweep  
Repeated conversions from a sequence of channels  
CS or FS to start sampling/conversion  
One INT generated after FIFO is filled up to the threshold  
Host must serve INT by either 1) (FIFO read) reading out all of the FIFO contents up to the  
threshold, then repeat conversions from the same selected channel or 2) writing another  
command(s) to change the conversion mode. If the FIFO is not read when INT is served it is  
cleared.  
Extended  
Same as normal sampling except CSTART starts each sampling and conversion when CS is  
high.  
NOTE: Programming the EOC/INT pin as the EOC signal works for mode 00 only. The other three modes automatically generate an INT signal  
irrespective of whether EOC/INT is programmed.  
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TLV2544, TLV2548  
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SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
timing diagrams  
The timing diagrams can be categorized into two major groups: non conversion and conversion. The  
nonconversion cycles are read and write (configuration). None of these cycles carry a conversion. Conversion  
cycles are those four modes of conversion.  
read cycle (read FIFO or read CFR)  
read CFR cycle:  
The read command is decoded in the first 4 clocks. SDO outputs the contents of the CFR after the 4th SCLK.  
16  
7
12 13  
14 15  
1
2
3
4
5
6
1
SCLK  
CS  
FS  
ID15 ID14 ID13 ID12  
ID15  
SDI  
INT  
EOC  
SDO  
OD11 OD10 OD9  
OD4 OD3 OD2 OD1 OD0  
Figure 2. TLV2544/TLV2548 Read CFR Cycle (FS active)  
16  
7
12 13 14 15  
1
2
3
4
5
6
1
SCLK  
CS  
FS  
ID15  
ID14 ID13 ID12  
ID15 ID14  
SDI  
INT  
EOC  
SDO  
OD11 OD10 OD9  
OD4 OD3 OD2 OD1 OD0  
Figure 3. TLV2544/TLV2548 Read CFR Cycle (FS = 1)  
10  
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TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
read cycle (read FIFO or read CFR) (continued)  
FIFO read cycle  
The first command in the active cycle after INT is generated, if the FIFO is used, is assumed as the FIFO read  
command. The first FIFO content is output immediately before the command is decoded. If this command is  
not a FIFO read, then the output is terminated but the first data in the FIFO is retained until a valid FIFO read  
command is decoded. Use of more layers of the FIFO reduces the time taken to read multiple data. This is  
because the read cycle does not generate EOC or INT nor does it carry out any conversion.  
16  
7
12 13 14 15  
1
2
3
4
5
6
1
SCLK  
CS  
FS  
ID15  
ID14 ID13 ID12  
ID15 ID14  
SDI  
INT  
EOC  
SDO  
OD11 OD10 OD9 OD8 OD7 OD6 OD5  
OD0  
Figure 4. TLV2544/TLV2548 Continuous FIFO Read Cycle (FS = 1)  
(controlled by SCLK, SCLK can stop between each 16 SCLKs)  
11  
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SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
write cycle (write CFR)  
The write cycle is used to write to the configuration register CFR (with 12-bit register content). The write cycle  
does not generate an EOC or INT nor does it carry out any conversion.  
16  
7
12 13 14 15  
1
2
3
4
5
6
1
SCLK  
CS  
FS  
ID11 ID10  
ID9  
ID4  
ID3  
ID2  
ID1  
ID0  
ID15 ID14 ID13 ID12  
ID15  
SDI  
INT  
EOC  
SDO  
Figure 5. TLV2544/TLV2548 Write Cycle (FS active)  
16  
7
12 13 14 15  
1
2
3
4
5
6
1
SCLK  
CS  
FS  
ID11 ID10  
ID9  
ID4  
ID3  
ID2  
ID1  
ID0  
ID15 ID14 ID13 ID12  
ID15 ID14  
SDI  
INT  
EOC  
SDO  
Figure 6. TLV2544/TLV2548 Write Cycle (FS = 1)  
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SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
conversion cycles  
DSP/normal sampling  
1
2
3
4
5
6
7
12  
13  
14  
15  
16  
28  
1
SCLK  
CS  
FS  
ID15 ID14 ID13 ID12  
ID15  
SDI  
INT  
t
(Long)  
sample  
t
t
(Short)  
conv  
sample  
EOC  
SDO  
t
conv  
OD11  
OD10 OD9 OD8 OD7 OD6 OD5  
OD0  
Figure 7. Mode 00 Single Shot/Normal Sampling (FS signal used)  
1
2
3
4
5
6
7
12  
13  
14  
15  
16  
28  
1
SCLK  
CS  
FS  
ID15 ID14 ID13 ID12  
ID15 ID14  
SDI  
INT  
t
(Long)  
sample  
t
t
(Short)  
conv  
sample  
EOC  
SDO  
t
conv  
OD11 OD10 OD9 OD8 OD7 OD6 OD5  
OD0  
Figure 8. Mode 00 Single Shot/Normal Sampling (FS = 1, FS signal not used)  
13  
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SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
conversion cycles (continued)  
Select/Read  
Cycle  
Select/Read  
Cycle  
CS  
t
sample  
CSTART  
FS  
t
convert  
SDI  
INT  
EOC  
SDO  
Previous Conversion  
Result  
Previous Conversion  
Result  
Hi-Z  
Hi-Z  
Hi-Z  
This is one of the single shot commands. Conversion starts on next rising edge of CSTART.  
Figure 9. Mode 00 Single Shot/Extended Sampling (FS signal used, FS pin connected to TMS320 DSP)  
CS used as FS input  
When interfacing with the TMS320 DSP using conversion mode 00, the FSR signal from the DSP may be  
connected to the CS input if this is the only device on the serial port. This will save one output pin from the DSP.  
Output data is made available on the rising edge of SCLK and input data is latched on the rising edge of SCLK  
in this case.  
modes using the FIFO: modes 01, 10, 11 timing  
Modes 01, 10, and 11 timing are very similar except for how and when the FIFO is read, how the device is  
configured, and how channel(s) are selected.  
Mode 01 (repeat mode) requires a two-cycle configuration where the first one sets the mode and the second  
one selects the channel. Once the FIFO is filled up to the threshold programmed, it has the option to either read  
the FIFO or configure for other modes. Therefore, the sequence is either configure: select : triggered  
conversions : FIFO read : select : triggered conversions : FIFO read or configure : select : triggered conversions  
: configure : .... Each configure clears the FIFO and the action that follows the configure command depends on  
the mode setting of the device.  
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SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
modes using the FIFO: modes 01, 10, 11 timing (continued)  
Conversion #1  
Configure Select From Channel 2  
Conversion #4  
From Channel 2  
Select  
CS  
FS  
t
sample  
t
t
sample  
t
sample  
t
convert  
t
convert  
convert  
CSTART  
§
§
SDI  
INT  
Hi-Z  
Hi-Z  
SDO  
Read FIFO  
#1  
#2  
#3  
#4  
Next #1  
Top of FIFO  
§
Command = Configure write for mode 01, FIFO threshold = 1/2  
Command = Read FIFO, 1st FIFO read  
Command = Select ch2.  
Figure 10. TLV2544/TLV2548 Mode 01 DSP Serial Interface (Conversions triggered by FS)  
Conversion #1  
Conversion #4  
From Channel 2  
From Channel 2  
Configure Select  
Select  
CS  
FS  
(DSP)  
t
(2)  
sample  
t
(3)  
sample  
t
(1)  
sample  
t
(4)  
sample  
CSTART  
t
(1)  
convert  
t
(4)  
convert  
t
(2)  
convert  
t
(3)  
convert  
§
§
SDI  
INT  
Hi-Z  
Hi-Z  
SDO  
Read FIFO  
First FIFO Read  
#1  
#2  
#3  
#4  
Next #1  
t
(i) > = MIN(t  
)
Sample  
Sample  
§
Command = Configure write for mode 01, FIFO threshold = 1/2  
Command = Read FIFO, 1st FIFO read  
Command = Select ch2.  
Figure 11. TLV2544/TLV2548 Mode 01 µp/DSP Serial Interface (Conversions triggered by CSTART)  
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SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
modes using the FIFO: modes 01, 10, 11 timing (continued)  
Mode 10 (sweep mode) requires reconfiguration at the start of each new sweep sequence. Once the FIFO is  
filled up to the programmed threshold, the host has the option to either read the FIFO or configure for other  
modes. Once the FIFO is read, the host must reconfigure the device before the next sweep sequence can be  
started. So the sequence is either configure : triggered conversions : FIFO read : configure. or configure :  
triggered conversions : configure : .... Each configure clears the FIFO and the action that follows the configure  
command depends on the mode setting of the device.  
Mode 11 (repeat sweep mode) requires one cycle configuration. This sweep sequence can be repeated without  
reconfiguration. Once the FIFO is filled up to the programmed threshold, the host has the option to either read  
the FIFO or configure for other modes. So the sequence is either configure : triggered conversions : FIFO read  
: triggered conversions : FIFO read ... or configure : triggered conversions : configure : .... Each configure clears  
the FIFO and the action that follows the configure command depends on the mode setting of the device.  
Conversion  
Conversion  
Conversion  
From Channel 3  
Conversion  
From Channel 0  
From Channel 3  
Configure  
From Channel 0  
CS  
t
(3)  
sample  
t
(2)  
sample  
t
(4)  
sample  
t
(1)  
sample  
FS  
(DSP)  
t
convert  
t
convert  
CSTART  
SDI  
t
(i) > = MIN(t  
)
Sample  
Sample  
INT  
SDO  
Read FIFO #1  
#2  
#3  
#4  
Read FIFO #1  
Repeat  
Repeat  
Top of FIFO  
First FIFO Read  
Second FIFO Read  
Command = Configure write for mode 10 or 11, FIFO threshold = 1/2, sweep seq = 0–1–2–3.  
Command = Read FIFO  
Figure 12. TLV2544/TLV2548 Mode 10/11 DSP Serial Interface (Conversions triggered by FS)  
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SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
modes using the FIFO: modes 01, 10, 11 timing (continued)  
Conversion  
Conversion  
Conversion  
Conversion  
From Channel 0  
From Channel 3  
From Channel 3  
From Channel 0  
Configure  
CS  
FS  
t
(i) >= MIN (t  
)
sample  
sample  
(DSP)  
CSTART  
t
(1)  
sample  
t
(2)  
sample  
t
(3)  
sample  
t
(4)  
sample  
t
convert  
t
convert  
SDI  
INT  
SDO  
Read FIFO #1  
#2  
#3  
#4  
Read FIFO  
#1  
Repeat  
Repeat  
Top of FIFO  
First FIFO Read  
Second FIFO Read  
Command = Configure write for mode 10 or 11, FIFO threshold = 1/2, sweep seq = 0–1–2–3.  
Command = Read FIFO  
Figure 13. TLV2544/TLV2548 Mode 10/11 DSP Serial Interface (Conversions triggered by CSTART)  
Conversion  
Conversion  
Conversion  
From Channel 0  
Conversion  
From Channel 0  
From Channel 3  
From Channel 3  
Configure  
CS  
t
(1)  
sample  
t
(2)  
sample  
t
(3)  
t
sample  
(4)  
sample  
t
t
convert  
convert  
t
(i) > = MIN(t  
)
Sample  
Sample  
CSTART  
SDI  
INT  
SDO  
Read FIFO #1  
#2  
#3  
#4  
Read FIFO  
#1  
Repeat  
Repeat  
Top of FIFO  
First FIFO Read  
Second FIFO Read  
Command = Configure write for mode 10 or 11, FIFO threshold = 1/2, sweep seq = 0–1–2–3.  
Command = Read FIFO  
Figure 14. TLV2544/TLV2548 Mode 00/11 µp Serial Interface (Conversions triggered by CS)  
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SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
FIFO operation  
Serial  
OD  
12-BIT×8  
FIFO  
ADC  
7
6
5
4
3
2
1
0
FIFO Full  
FIFO 1/2 Full  
FIFO 3/4 Full  
FIFO 1/4 Full  
FIFO Threshold Pointer  
Figure 15. TLV2544/TLV2548 FIFO  
The device has an 8 layer FIFO that can be programmed for different thresholds. An interrupt is sent to the host  
after the preprogrammed threshold is reached. The FIFO can be used to store data from either a fixed channel  
or a series of channels based on a preprogrammed sweep sequence. For example, an application may require  
eight measurements from channel 3. In this case, the FIFO is filled with 8 data sequentially taken from channel  
3. Another application may require data from channel 0, channel 2, channel 4, and channel 6 in an orderly  
manner. Therefore, the threshold is set for 1/2 and the sweep sequence 0–2–4–6–0–2–4–6 is chosen. An  
interrupt is sent to the host as soon as all four data are in the FIFO.  
SCLK and conversion speed  
There are multiple ways to adjust the conversion speed.  
The SCLK can be used as the source of the conversion clock.  
The onboard OSC is approximately 4 MHz and 13 conversion clocks are required to complete a conversion.  
This leads to a 3 µs conversion time plus 0.5 µs overhead. The devices can operate with an SCLK up to 20  
MHz for the supply voltage range specified. When a more accurate conversion time is desired, the SCLK  
can be used as the source of the conversion clock. The clock divider provides speed options appropriate for  
an application where a high speed SCLK is used for faster I/O. The total conversion time is 13 × (DIV/f  
)
SCLK  
where DIV is 1, 2, or 4. For example a 20 MHz SCLK with the divide by 4 option produces a {13 × (4/20 M) +  
0.5 µs} = 3.1 µs conversion time. When an external serial clock (SCLK) is used as the source of the  
conversion clock, the maximum equivalent conversion clock (f  
/DIV) should not exceed 6 MHz.  
SCLK  
Auto power down can be used. This mode is always on. If the device is not accessed (by CS or CSTART),  
the converter is powered down to save power. The built-in reference is left on in order to quickly resume  
operation within one half SCLK period. This provides unlimited choices to trade speed with power savings.  
reference voltage  
The device has a built-in reference with a programmable level of 2 V or 4 V. If the internal reference is used,  
REFP is set to 2 V or 4 V and REFM is set to 0 V. An external reference can also be used through two reference  
input pins, REFP and REFM, if the reference source is programmed as external. The voltage levels applied to  
these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale  
reading respectively. The values of REFP, REFM, and the analog input should not exceed the positive supply  
or be lower than GND consistent with the specified absolute maximum ratings. The digital output is at full scale  
when the input signal is equal to or higher than REFP and at zero when the input signal is equal to or lower than  
REFM.  
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SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
FIFO operation (continued)  
power down  
Writing 8000h to the device puts the device into a software power down state. For a hardware powerdown, the  
dedicated PWDN pin provides another way to power down the device asynchronously. These two power down  
modes power down the entire device including the built-in reference to save power. It requires 20 ms to resume  
from either a software or hardware power down.  
Auto power down mode is always enabled. This mode maintains the built-in reference if an internal reference  
is used so resumption is fast enough to be used between cycles.  
The configuration register is not affected by any of the power down modes but the sweep operation sequence  
has to be started over again. All FIFO contents are cleared by the power down modes.  
power up and initialization  
Initialization requires:  
1. Determine processor type by writing A000h to the TLV2544/48  
2. Configure the device  
The first conversion after power up or resuming from power down is not valid.  
absolute maximum ratings over operating free-air temperature (unless otherwise noted)  
Supply voltage range, GND to V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V  
CC  
Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V  
Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V  
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V  
+ 0.3 V  
+ 0.3 V  
+ 0.3 V  
CC  
CC  
CC  
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 150°C  
J
Operating free-air temperature range, T : TLV2544/48C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C  
A
TLV2544/48I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C  
Storage temperature range, T  
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C  
stg  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
recommended operating conditions  
MIN NOM  
MAX  
UNIT  
V
Supply voltage, V  
CC  
2.7  
2
3.3  
5.5  
Positive external reference voltage input, V  
REFP  
(see Note 1)  
(note Note 1)  
V
CC  
2
V
Negative external reference voltage input, V  
REFM  
0
V
Differential reference voltage input, V  
– V  
(see Note 1)  
2
V
CC  
V +0.2  
CC  
V
REFP  
REFM  
Analog input voltage (see Note 1)  
0
V
CC  
V
High level control input voltage, V  
2.1  
V
IH  
Low-level control input voltage, V  
0.6  
V
IL  
Rise time, for CS, CSTART SDI at 0.5 pF, t  
4.76  
2.91  
2.43  
2.3  
ns  
ns  
ns  
ns  
r(I/O)  
Fall time, for CS, CSTART SDI at 0.5 pF, t  
f(I/O)  
Rise time, for INT, EOC, SDO at 30 pF, t  
r(Output)  
Fall time, for INT, EOC, SDO at 30 pF, t  
f(Output)  
NOTE 1: When binary output format is used, analog input voltages greater than that applied to REFP convert as all ones (111111111111), while  
input voltages less than that applied to REFM convert as all zeros (000000000000). The device is functional with reference down to  
2 V (V  
– V  
–1); however, the electrical specifications are no longer applicable.  
REFP  
REFM  
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SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
recommended operating conditions (continued)  
MIN NOM  
0.5  
MAX  
UNIT  
Transition time, for FS, SCLK, SDI, t  
SCLK  
t(SCLK)  
Setuptime,CSfallingedgebeforeSCLKrisingedge(FS=1)orbeforeSCLKfallingedge(whenFSisactive),  
0.5  
5
SCLK  
ns  
t
su(CS-SCLK)  
Hold time, CS rising edge after SCLK rising edge (FS=1) or after SCLK falling edge (when FS is active),  
t
h(SCLK-CS)  
Delay time, delay from CS falling edge to FS rising edge, t  
0.5  
0.5  
0.25  
0.25  
100  
67  
7
SCLKs  
SCLKs  
d(CSL-FSH)  
Delay time, delay time from 16th SCLK falling edge to CS rising edge (FS is active), t  
d(SCLK16L-CSH)  
Setup time, FS rising edge before SCLK falling edge, t  
su(FSH-SCLKL)  
0.75 SCLKs  
Hold time, FS hold high after SCLK falling edge, t  
h(FSH-SCLKL)  
0.75 SCLKs  
Pulse width, CS high time, t  
wH(CS)  
ns  
ns  
ns  
SCLK cycle time, V  
= 2.7 V to 3.6V, t  
c(SCLK)  
CC  
CC  
SCLK cycle time, V  
= 4.5 V to 5.5V, t  
50  
c(SCLK)  
Pulse width, SCLK low time, t  
20  
30  
30  
ns  
ns  
wL(SCLK)  
Pulse width, SCLK high time, t  
20  
wH(SCLK)  
Setup time, SDI valid before falling edge of SCLK (FS is active) or the rising edge of SCLK (FS=1),  
25  
5
ns  
ns  
t
su(DI-SCLK)  
Hold time, SDI hold valid after falling edge of SCLK (FS is active) or the rising edge of SCLK (FS=1),  
t
h(DI-SCLK)  
Delay time, delay from CS falling edge to SDO valid, t  
1
1
1
1
25  
25  
25  
25  
ns  
ns  
ns  
ns  
d(CSL-DOV)  
d(FSL-DOV)  
Delay time, delay from FS falling edge to SDO valid, t  
Delaytime,delayfromSCLKrisingedge(FSisactive)orSCLKfallingedge(FS=1)SDOvalid,t  
d(SCLK-DOV)  
Delay time, delay from CS rising edge to SDO 3-stated, t  
d(CSH-DOZ)  
Delay time, delay from 16th SCLK falling edge (FS is active) or the 16th rising edge (FS=1) to EOC falling  
edge, t  
1
1
25  
50  
ns  
ns  
µs  
d(SCLK-EOCL)  
Delay time, delay from EOC rising edge to SDO 3-stated if CS is low, t  
d(EOCH-DOZ)  
Delay time, delay from 16th SCLK rising edge to INT falling edge (FS =1) or from the 16th falling edge SCLK  
to INT falling edge (when FS active), t  
3.5  
50  
d(SCLK-INTL)  
Delay time, delay from CS falling edge to INT rising edge, t  
1
100  
1
ns  
ns  
ns  
µs  
ns  
µs  
µs  
d(CSL-INTH)  
Delay time, delay from CS rising edge to CSTART falling edge, t  
d(CSH-CSTARTL)  
Delay time, delay from CSTART rising edge to EOC falling edge, t  
50  
50  
d(CSTARTH-EOCL)  
Pulse width, CSTART low time, t (CSTART)  
wL  
0.8  
1
Delay time, delay from CS rising edge to EOC rising edge, t  
d(CSH-EOCH)  
Delay time, delay from CSTART rising edge to CSTART falling edge, t  
d(CSTARTH-CSTARTL)  
3.6  
3.5  
0
Delay time, delay from CSTART rising edge to INT falling edge, t  
d(CSTARTH-INTL)  
TLV2544C/TLV2548C  
70  
85  
Operating free-air temperature, T  
C
A
TLV2544I/TLV2548I  
–40  
NOTE 2: This is the time required for the clock input signal to fall from V max or to rise from V max to V min. In the vicinity of normal room  
IH  
IL  
IH  
temperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition applications where the  
sensor and A/D converter are placed several feet away from the controlling microprocessor.  
20  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
electrical characteristics over recommended operating free-air temperature range, V = V  
CC  
5.5 V, SCLK frequency = 20 MHz at 5 V, 15 MHz at 3 V (unless otherwise noted)  
= 2.7 V to  
REFP  
PARAMETER  
TEST CONDITIONS  
MIN  
2.4  
TYP†  
MAX  
UNIT  
V
V
V
V
V
V
= 5.5 V, I  
= 2.7 V, I  
= –0.2 mA at 30 pF load  
CC  
CC  
CC  
CC  
OH  
OH  
V
V
I
High-level output voltage  
V
OH  
= -20 µA at 30 pF load  
V
CC  
–0.2  
= 5.5 V, I = 0.8 mA at 30 pF load  
0.4  
0.1  
2.5  
-2.5  
2.5  
2.5  
1.3  
0.95  
2
OL  
Low-level output voltage  
V
OL  
= 2.7 V, I = 20 µA at 30 pF load  
OL  
= V  
1
–1  
O
O
CC  
Off-state output current  
(high-impedance-state)  
µA  
CS = V  
CC  
OZ  
= 0  
I
I
High-level input current  
Low-level input current  
V = V  
I CC  
0.005  
–0.005  
µA  
µA  
IH  
V = 0 V  
I
IL  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 4.5 V to 5.5 V  
= 2.7 V to 3.3 V  
= 4.5 V to 5.5 V  
= 2.7 V to 3.3 V  
= 4.5 V to 5.5 V  
= 2.7 V to 3.3 V  
= 4.5 V to 5.5 V  
= 2.7 V to 3.3 V  
CS at 0 V, Ext ref  
CS at 0 V, Int ref  
CS at 0 V, Ext ref  
CS at 0 V, Int ref  
mA  
mA  
mA  
mA  
mA  
Operating supply current, normal  
sampling (short)  
I
I
CC  
1.6  
1.9  
1.5  
2
Operating supply current, extended  
sampling  
CC  
1.6  
CS at 0 V, V = 4.5 V to 5.5 V  
0.8  
0.6  
CC  
Internal reference supply current  
Power-down supply current  
V
CC  
= 2.7 V to 3.3 V  
For all digital inputs,  
0V 0.3 V or V V – 0.3 V,  
I
I
CC  
0.1  
0.1  
1
1
SCLK = 0, V = 4.5 V to 5.5 V,  
CC  
I
I
µA  
µA  
CC(PD)  
Ext clock  
V
CC  
= 2.7 V to 3.3 V, Ext clock  
For all digital inputs,  
0V 0.3 V or V V – 0.3 V,  
I
I
CC  
1
SCLK = 0, V = 4.5 V to 5.5 V,  
CC  
Auto power down current  
CC(AUTOPWDN)  
Ext clock, Ext ref  
V
= 2.7 V to 3.3 V,  
CC  
§
1
Ext ref, Ext clock  
Selected channel at V  
1
CC  
Selected channel leakage current  
µA  
µA  
Selected channel at 0 V  
= V = 5.5 V, V = GND  
REFM  
–1  
Maximum static analog reference  
current into REFP (use external  
reference)  
V
REFP  
1
CC  
Analog inputs  
Control Inputs  
45  
5
50  
25  
C
i
Input capacitance  
pF  
V
CC  
V
CC  
= 5.5 V  
= 2.7 V  
500  
600  
Z
Input MUX ON resistance  
i
§
All typical values are at V  
CC  
= 5 V, T = 25°C.  
A
800 µA if internal reference is used, 165 µA if internal clock is used.  
800 µA if internal reference is used, 116 µA if internal clock is used.  
21  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
ac specifications  
PARAMETER  
Signal-to-noise ratio +distortion  
Total harmonic distortion  
TEST CONDITIONS  
f = 12 kHz at 200 KSPS  
MIN  
TYP  
71  
MAX  
–76  
UNIT  
dB  
SINAD  
THD  
69  
I
f = 12 kHz at 200 KSPS  
I
–82  
11.6  
–84  
dB  
ENOB  
SFDR  
Effective number of bits  
f = 12 kHz at 200 KSPS  
I
Bits  
dB  
Spurious free dynamic range  
f = 12 kHz at 200 KSPS  
I
–91  
–75  
Analog input  
Full power bandwidth, –3 dB  
Full-power bandwidth, –1 dB  
1
MHz  
kHz  
500  
reference specifications (0.1 µF and 10 µF between REFP and REFM pins)  
PARAMETER  
TEST CONDITIONS  
= 2.7 V to 5.5 V  
MIN  
TYP  
MAX  
UNIT  
V
Reference input voltage, REFP  
V
V
V
CC  
CC  
CS = 1, SCLK = 0, (off)  
100  
20  
MΩ  
kΩ  
= 5.5 V  
CC  
CS = 0, SCLK = 20 MHz (on)  
CS = 1, SCLK = 0 (off)  
25  
25  
Input impedance  
100  
20  
MΩ  
kΩ  
V
V
= 2.7 V  
CC  
CS = 0, SCLK = 20 MHz (on)  
Input voltage difference,  
REFP – REFM  
= 2.7 V to 5.5 V  
2
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 5.5 V  
= 5.5 V  
= 2.7 V  
VREFSELECT = 4 V  
VREFSELECT = 2 V  
VREFSELECT = 2 V  
3.85  
1.925  
1.925  
4
2
4.15  
2.075  
2.075  
V
V
Internal reference voltage,  
REFP – REFM  
2
V
Internal reference start up time  
= 5.5 V, 2.7 V 10 µF  
20  
16  
ms  
Reference temperature coefficient  
= 2.7 V to 5.5 V  
40 PPM/°C  
22  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
operating characteristics over recommended operating free-air temperature range, V  
5.5 V, SCLK frequency = 20 MHz (unless otherwise noted)  
= V  
= 2.7 V to  
CC  
REFP  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
±1  
UNIT  
LSB  
LSB  
LSB  
LSB  
LSB  
Integral linearity error (INL) (see Note 4)  
Differential linearity error (DNL)  
Offset error (see Note 5)  
See Note 3  
±1  
±1.5  
±1.6  
±2  
E
O
E
G
E
T
See Note 3  
See Note 3  
Gain error (see Note 5)  
±1.1  
Total unadjusted error (see Note 6)  
800h  
SDI = B000h  
SDI = C000h  
(2048D)  
000h  
(0D)  
Self-test output code (see Table 1 and Note 7)  
FFFh  
(4095D)  
SDI = D000h  
Internal OSC  
External SCLK  
OSC = 4 MHz to 6 MHz  
2.17  
600  
2.6  
3.6  
µs  
t
Conversion time  
conv  
(13XDIV)  
SCLK  
f
t
t
t
Sampling time  
At 1 kΩ  
ns  
ns  
ns  
sample  
Transition time for EOC, INT  
Transition time for SDI, SDO  
50  
25  
t(I/O)  
t(CLK)  
All typical values are at T = 25°C.  
A
NOTES: 3. Analog input voltages greater than that applied to REFP convert as all ones (111111111111), while input voltages less than that  
applied to REFM convert as all zeros (0000000000). The device is functional with reference down to 2 V (VREFP – VREFM);  
however, the electrical specifications are no longer applicable.  
4. Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.  
5. Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the difference  
between 111111111111 and the converted output for full-scale input voltage.  
6. Total unadjusted error comprises linearity, zero, and full-scale errors.  
7. Both the input data and the output codes are expressed in positive logic.  
23  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
PARAMETER MEASUREMENT INFORMATION  
t
t
t(I/O)  
t(I/O)  
V
V
90%  
IH  
50%  
CS  
FS  
10%  
IL  
t
wH(CS)  
t
d(CSL-FSH)  
V
V
IH  
IL  
t
t
su(FSH-SCLKL)  
h(FSH-SCLKL)  
t
d(SCLK16L-CSH)  
t
wH(SCLK)  
t
wL(SCLK)  
t
h(SCLK-CS)  
t
su(CS-SCLK)  
1
16  
V
V
IH  
SCLK  
IL  
t
c(SCLK)  
t
su(DI-SCLK)  
t
h(DI-SCLK)  
V
V
IH  
SDI  
SDO  
EOC  
ID15 ID1  
IL  
t
t
d(SCLK-DOV)  
d(FSL-DOV)  
d(CSL-DOV)  
t
V
OH  
Hi-Z  
V
OL  
t
t
d(EOCH–DOZ)  
d(SCLK-EOCL)  
V
OH  
V
OL  
t
t
d(CSL-INTH)  
d(SCLK-INTL)  
V
OH  
INT  
V
OL  
Figure 16. Critical Timing (Normal Sampling, FS is active)  
24  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
PARAMETER MEASUREMENT INFORMATION  
V
V
IH  
CS  
IL  
t
d(CSH-CSTARTL)  
t
wL(CSTART)  
V
V
IH  
CSTART  
IL  
t
d(CSH-EOCH)  
t
t(I/O)  
t
t(I/O)  
t
convert  
V
OH  
EOC  
INT  
V
OL  
t
d(CSTARTH-EOCL)  
t
d(EOCH-INTL)  
t
d(CSL-INTH)  
V
OH  
V
OL  
Figure 17. Critical Timing (Extended Sampling, Single Shot)  
V
V
IH  
CS  
t
wL(CSTART)  
IL  
t
t
d(CSL-CSTARTL)  
CSTART  
d(CSTARTH–CSTARTL)  
V
V
IH  
90%  
50%  
10%  
IL  
t
d(CSH-EOCH)  
t
t(I/O)  
t
t(I/O)  
V
OH  
EOC  
V
OL  
t
d(CSTARTH-EOCL)  
t
d(CSTARTH-INTL)  
t
d(CSL-INTH)  
V
OH  
INT  
V
OL  
Figure 18. Critical Timing (Extended Sampling, Repeat/Sweep/Repeat Sweep)  
25  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
PARAMETER MEASUREMENT INFORMATION  
t
t
t(I/O)  
t(I/O)  
V
V
IH  
CS  
IL  
t
wH(CS)  
t
su(CS-SCLK)  
wL(SCLK)  
wH(SCLK)  
t
d(SCLK16F-CSH)  
t
t
t(CLK)  
16  
t
1
V
V
IH  
SCLK  
IL  
t
c(SCLK)  
t
t
h(DI-CLK)  
su(DI-CLK)  
V
V
IH  
SDI  
ID15  
ID1  
IL  
t
t
d(CLK-DOV)  
d(CSL-DOV)  
Hi-Z  
V
OH  
Hi-Z  
SDO  
OD15 OD1  
OD0  
V
OL  
t
d(EOCH-DOZ)  
t
d(CLK-EOCL)  
V
OH  
ECO  
INT  
V
OL  
t
t
d(SCLK-INTL)  
d(CSL-INTH)  
V
OH  
V
OL  
Figure 19. Critical Timing (Normal Sampling, FS = 1)  
26  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
TYPICAL CHARACTERISTICS  
INTEGRAL NONLINEARITY  
INTEGRAL NONLINEARITY  
vs  
vs  
TEMPERATURE  
TEMPERATURE  
0.53  
0.52  
0.51  
0.6  
0.595  
0.59  
0.585  
0.5  
0.58  
0.575  
0.49  
V
= 2.7 V, Internal Reference = 2 V,  
CC  
Internal Oscillator, Single Shot,  
Short Sample, Mode 00 µP Mode  
0.57  
0.565  
0.56  
V
= 5.5 V, Internal Reference = 2 V,  
CC  
0.48  
0.47  
Internal Oscillator, Single Shot,  
Short Sample, Mode 00 µP Mode  
–40  
25  
85  
–40  
25  
85  
T
A
– Temperature – °C  
T
A
– Temperature – °C  
Figure 20  
Figure 21  
DIFFERENTIAL NONLINEARITY  
DIFFERENTIAL NONLINEARITY  
vs  
vs  
TEMPERATURE  
TEMPERATURE  
0.496  
0.494  
0.492  
0.49  
0.48  
0.47  
0.46  
0.45  
0.44  
0.43  
0.42  
0.488  
0.486  
0.484  
0.482  
V
= 5.5 V, Internal Reference = 2 V,  
CC  
V
= 2.7 V, Internal Reference = 2 V,  
CC  
Internal Oscillator, Single Shot,  
Internal Oscillator, Single Shot,  
Short Sample, Mode 00 µP Mode  
Short Sample, Mode 00 µP Mode  
0.48  
0.478  
–40  
25  
85  
–40  
25  
85  
T
A
– Temperature – °C  
T
A
– Temperature – °C  
Figure 22  
Figure 23  
27  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
TYPICAL CHARACTERISTICS  
OFFSET ERROR  
vs  
GAIN ERROR  
vs  
TEMPERATURE  
TEMPERATURE  
1.2  
1
0.5  
0
0.8  
–0.5  
0.6  
0.4  
–1  
–1.5  
V
CC  
= 5 V, Internal Reference = 4 V,  
V
CC  
= 5 V, Internal Reference = 4 V,  
External Oscillator = SCLK/4,  
Single Shot, Long Sample,  
Mode 00 µP Mode  
External Oscillator = SCLK/4,  
Single Shot, Long Sample,  
Mode 00 µP Mode  
0.2  
0
–2  
–2.5  
–40  
25  
85  
–40  
25  
85  
T
A
– Temperature – °C  
T – Temperature – °C  
A
Figure 24  
Figure 25  
SUPPLY CURRENT  
vs  
POWER DOWN CURRENT  
vs  
TEMPERATURE  
TEMPERATURE  
1.4  
0.4  
0.2  
External Reference = 4 V, Internal Oscillator,  
Single Shot, Short Sample, Mode 00 µP Mode  
Long Sample  
V
CC  
= 5 V  
1.2  
1
0
–0.2  
Short Sample  
–0.4  
–0.6  
V
= 2.7 V  
CC  
0.8  
0.6  
V
CC  
= 5.5 V  
V
= 5 V, External Reference = 4 V,  
CC  
Internal Oscillator, Single Shot,  
Short Sample, Mode 00 µP Mode  
–0.8  
–1  
–40  
25  
85  
–40  
25  
– Temperature – °C  
85  
T
A
– Temperature – °C  
T
A
Figure 26  
Figure 27  
28  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
TYPICAL CHARACTERISTICS  
INTEGRAL NONLINEARITY  
vs  
SAMPLES  
1.0  
0.5  
V
= 2.7 V, Internal Reference = 2 V, Internal Oscillator,  
CC  
Single Shot, Short Sample, Mode 00 µP Mode  
0.0  
–0.5  
–1.0  
0
4097.00  
Samples  
Figure 28  
DIFFERENTIAL NONLINEARITY  
vs  
SAMPLES  
1.0  
0.5  
V
= 2.7 V, Internal Reference = 2 V, Internal Oscillator,  
CC  
Single Shot, Short Sample, Mode 00 µP Mode  
0.0  
–0.5  
–1.0  
0
4097.00  
Samples  
Figure 29  
29  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
TYPICAL CHARACTERISTICS  
INTEGRAL NONLINEARITY  
vs  
SAMPLES  
1.0  
V
= 5 V, Internal Reference = 2 V, Internal Oscillator,  
CC  
Single Shot, Short Sample, Mode 00 µP Mode  
0.5  
0.0  
–0.5  
–1.0  
0
4097.00  
Samples  
Figure 30  
DIFFERENTIAL NONLINEARITY  
vs  
SAMPLES  
1.0  
0.5  
V
= 5 V, Internal Reference = 2 V, Internal Oscillator,  
CC  
Single Shot, Short Sample, Mode 00 µP Mode  
0.0  
–0.5  
–1.0  
0
4097.00  
Samples  
Figure 31  
30  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
TYPICAL CHARACTERISTICS  
100%  
160  
150  
140  
130  
120  
110  
100  
90  
V
= 5 V, External Reference = 4 V,  
Internal Oscillator , Single Shot, Long Sample, Mode 00 µP  
CC  
Mode @ 200 KSPS  
80  
70  
60  
50  
40  
30  
20  
10  
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100  
f – Frequency – kHz  
Figure 32  
31  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
TYPICAL CHARACTERISTICS  
EFFECTIVE NUMBER OF BITS  
SIGNAL-TO-NOISE + DISTORTION  
vs  
vs  
INPUT FREQUENCY  
INPUT FREQUENCY  
12  
11.7  
11.4  
11.1  
10.8  
80  
75  
70  
65  
10.5  
10.2  
9.9  
60  
55  
50  
9.6  
9.3  
9
V
= 5 V, External Reference = 4 V,  
CC  
8.7  
8.4  
8.1  
7.8  
7.5  
Internal Oscillator, Single Shot,  
Long Sample, Mode 00 µP Mode  
V
= 5 V, External Reference = 4 V,  
CC  
Internal Oscillator, Single Shot,  
Long Sample, Mode 00 µP Mode  
45  
40  
1
250  
500  
1
250  
500  
f – Frequency – kHz  
f – Frequency – kHz  
Figure 33  
Figure 34  
TOTAL HARMONIC DISTORTION  
SPURIOUS FREE DYNAMIC RANGE  
vs  
vs  
INPUT FREQUENCY  
INPUT FREQUENCY  
–60  
0
–20  
–40  
–60  
V
= 5 V, External Reference = 4 V,  
CC  
V
= 5 V, External Reference = 4 V,  
CC  
Internal Oscillator, Single Shot,  
Long Sample, Mode 00 µP Mode  
–65  
–70  
Internal Oscillator, Single Shot,  
Long Sample, Mode 00 µP Mode  
–75  
–80  
–80  
–85  
–90  
–100  
1
50  
100  
1
50  
100  
f – Frequency – kHz  
f – Frequency – kHz  
Figure 35  
Figure 36  
32  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
PRINCIPLES OF OPERATION  
4095  
1111111111  
1111111110  
1111111101  
V
FS  
See Notes A and B  
4094  
4093  
V
FS Nom  
V
FT  
= V  
– 1/2 LSB  
FS  
2049  
2048  
1000000001  
1000000000  
V
ZT  
=V  
+ 1/2 LSB  
ZS  
2047  
0111111111  
V
ZS  
2
1
0
0000000010  
0000000001  
0000000000  
0
0.0012 0.0024  
2.4564 2.4576 2.4588  
V – Analog Input Voltage – V  
4.9056  
4.9104 4.9152  
I
NOTES: A. This curve is based on the assumption that V  
ref+  
and V have been adjusted so that the voltage at the transition from digital 0 to  
ref–  
1 (V ) is 0.0006 V, and the transition to full scale (V ) is 4.9134 V, 1 LSB = 1.2 mV.  
ZT FT  
B. The full scale value (V ) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (V ) is  
FS  
ZS  
the step whose nominal midstep value equals zero.  
Figure 37. Ideal 12-Bit ADC Conversion Characteristics  
v
cc  
10 kΩ  
V
DD  
XF  
TXD  
RXD  
CS  
SDI  
SDO  
A
IN  
CLKR  
CLKX  
SCLK  
TLV2544/  
TLV2548  
TMS320 DSP  
BIO  
INT  
FSR  
FSX  
FS  
GND  
Figure 38. Typical Interface to a TMS320 DSP  
33  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
PRINCIPLES OF OPERATION  
simplified analog input analysis  
Using the equivalent circuit in Figure 39, the time required to charge the analog input capacitance from 0 to VS  
within 1/2 LSB can be derived as follows.  
The capacitance charging voltage is given by:  
–tc  
Rt Ci  
Vc  
Vs 1–EXP  
(1)  
Where  
Rt = Rs + Zi  
tc = Cycle time  
The input impedance Zi is 0.5 kat 5 V, and is higher (~ 0.6 k) at 2.7 V. The final voltage to 1/2 LSB is given  
by:  
VS  
8192  
VC (1 2 LSB)  
VS–  
(2)  
(3)  
Equating equation 1 to equation 2 and solving for cycle time tc gives:  
VS  
–tc  
Rt Ci  
Vs–  
Vs 1–EXP  
8192  
and time to change to 1/2 LSB (minimum sampling time) is:  
tch (1 2 LSB)  
Rt Ci In(8192)  
Where  
In(8192) = 9.011  
Therefore, with the values given, the time for the analog input signal to settle is:  
(4)  
(
)
tch (1 2 LSB)  
Rs 0.5 k  
Ci In(8192)  
This time must be less than the converter sample time shown in the timing diagrams. This is 12× SCLKs (if the  
sampling mode is short normal sampling mode).  
1
(5)  
(6)  
tch (1 2 LSB)  
12  
f(SCLK)  
Therefore the maximum SCLK frequency is:  
12  
12  
(
)
max f SCLK  
[ (  
In 8192  
)
]
Rt Ci  
tch 1 2 LSB  
34  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
PRINCIPLES OF OPERATION  
Driving Source  
TLV2544/48  
V
V
R
= Input Voltage at AIN  
= External Driving Source Voltage  
= Source Resistance  
= Input Resistance (MUX on Resistance)  
= Input Capacitance  
= Capacitance Charging Voltage  
I
S
s
R
r
i
s
V
I
V
S
V
r
C
i
C
V
i
C
C
i
Driving source requirements:  
Noise and distortion for the source must be equivalent to the resolution of the converter.  
R must be real at the input frequency.  
s
Figure 39. Equivalent Input Circuit Including the Driving Source  
maximum conversion throughput  
For a supply voltage of 5 V, if the source impedance is less than 1 k, and the ADC analog input capacitance  
Ci is less than 50 pF, this equates to a minimum sampling time tch(0.5 LSB) of 0.676 µs ( 1µs). Since the  
sampling time requires 12 SCLKs, the fastest SCLK frequency is 12/tch = 12 MHz.  
The minimal total cycle time is given as:  
1
1
(
)
tc  
tcommand tch tconv td EOCH–CSL  
4
12  
3.6  
s
0.1  
s
f(SCLK)  
f(SCLK)  
1
16  
3.7  
s
5.03  
s
12MHz  
This is equivalent to a maximum throughput of 200 KSPS. The throughput can be even higher with a smaller  
source impedance.  
When source impedance is 100 , the minimum sampling time becomes:  
tch (1 2 LSB)  
Rt Ci In(8192)  
0.27  
s
The maximum SCLK frequency possible is 12/tch = 44 MHz. Then a 20 MHz clock (maximum SCLK frequency  
for the TLV2544/2548 ) can be used. The minimal total cycle time is then reduced to:  
1
1
(
)
tc  
tcommand tch tconv td EOCH–CSL  
0.8 3.6 0.1 4.5  
The maximum throughput is 1/4.5 µs = 222 KSPS for this case.  
4
12  
3.6  
s
0.1  
s
f(SCLK)  
f(SCLK)  
s
s
s
s
35  
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TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
PRINCIPLES OF OPERATION  
700  
600  
500  
400  
300  
200  
5.5  
5
4.5  
4
3.5  
3
2.7  
V
CC  
– Supply Voltage – V  
Figure 40. Input MUX Impedance vs Supply Voltage  
power down calculations  
i(AVERAGE) = (f /f  
) × i(ON) + (1–f /f  
) × i(OFF)  
S SMAX  
S SMAX  
CASE 1: If V  
= 3.3 V, auto power down, and an external reference is used:  
DD  
f
10 kHz  
S
f
200 kHz  
SMAX  
i(ON)  
1 mA operating current and i(OFF)  
1
A auto powerdown current  
so  
i(AVERAGE)  
0.05 1000  
A
0.95  
1
A
51  
A
CASE 2: Now if software power down is used, another cycle is needed to shut it down.  
f
20 kHz  
S
f
200 kHz  
SMAX  
i(ON)  
1 mA operating current and i(OFF)  
1
A powerdown current  
so  
i(AVERAGE)  
0.1 1000 0.9 101  
A
1
A
A
Inrealitythiswillbelesssincethesecondconversionneverhappened. Itisonlytheadditionalcycletoshutdown  
the ADC.  
36  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
PRINCIPLES OF OPERATION  
CASE 3: Now if the hardware power down is used.  
f
10 kHz  
S
f
200 kHz  
SMAX  
i(ON)  
1 mA operating current and i(OFF)  
1
A powerdown current  
so  
i(AVERAGE)  
0.05 1000  
A
0.95  
1
A
51  
A
difference between modes of conversion  
The major difference between sweep mode (mode 10) and repeat sweep mode (mode 11) is that the sweep  
sequence ends after the FIFO is filled up to the programmed threshold. The repeat sweep can either dump the  
FIFO (by ignoring the FIFO content but simply reconfiguring the device) or read the FIFO and then repeat the  
conversions on the the same sequence of the channel as before.  
FIFO reads are expected after the FIFO is filled up to the threshold in each case. Mode 10 – the device allows  
only FIFO read or CFR read or CFR write to be executed. Any conversion command is ignored. In the case of  
mode 11, in addition to the above commands, conversion commands are also executed , i.e. the FIFO is cleared  
and the sweep sequence is restarted.  
Both single shot and repeat modes require selection of a channel after the device is configured for these modes.  
Single shot mode does not use the FIFO, but repeat mode does. When the device is operating in repeat mode,  
the FIFO can be dumped (by ignoring the FIFO content and simply reconfiguring the device) or the FIFO can  
be read and then the conversions repeated on the same channel as before. However, the channel has to be  
selected first before any conversion can be carried out. The devices can be programmed with the following  
sequences for operating in the different modes that use a FIFO:  
37  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLV2544, TLV2548  
2.7 V TO 5.5 V, 12-BIT, 200 KSPS, 4/8 CHANNEL, LOW POWER,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN  
SLAS198A –FEBRUARY 1999– REVISED AUGUST 1999  
PRINCIPLES OF OPERATION  
difference between modes of conversion (continued)  
REPEAT:  
Configure FIFO Depth=4 /CONV Mode 01  
Select Channel/  
1st Conv (CS or CSTART)  
2nd Conv (CS or CSTART)  
3rd Conv (CS or CSTART)  
4th Conv (CS or CSTART  
FIFO READ 1  
FIFO READ 2  
FIFO READ 3  
FIFO READ 4  
Select Channel  
1st Conv (CS or CSTART)  
2nd Conv (CS or CSTART)  
3rd Conv (CS or CSTART)  
4th Conv (CS or CSTART  
SWEEP:  
Configure FIFO Depth=4 SEQ=1–2–3–4/CONV Mode 10  
conv ch 1 (CS/CSTART)  
conv ch 2 (CS/CSTART)  
conv ch 3 (CS/CSTART)  
conv ch 4 (CS/CSTART  
FIFO READ ch 1 result  
FIFO READ ch 2 result  
FIFO READ ch 3 result  
FIFO READ ch 4 result  
Configure (not required if same sweep sequence is to be used again)  
REPEAT SWEEP:  
Configure FIFO Depth=4 SWEEP SEQ=1-2-3-4/CONV Mode 11  
conv ch 1 (CS/CSTART)  
conv ch 2 (CS/CSTART)  
conv ch 3 (CS/CSTART)  
conv ch 4 (CS/CSTART  
FIFO READ ch 1 result  
FIFO READ ch 2 result  
FIFO READ ch 3 result  
FIFO READ ch 4 result  
conv ch 1 (CS/CSTART)  
conv ch 2 (CS/CSTART)  
conv ch 3 (CS/CSTART)  
conv ch 4 (CS/CSTART  
38  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue  
any product or service without notice, and advise customers to obtain the latest version of relevant information  
to verify, before placing orders, that information being relied on is current and complete. All products are sold  
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those  
pertaining to warranty, patent infringement, and limitation of liability.  
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent  
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily  
performed, except those mandated by government requirements.  
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF  
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL  
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR  
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER  
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO  
BE FULLY AT THE CUSTOMER’S RISK.  
In order to minimize risks associated with the customer’s applications, adequate design and operating  
safeguards must be provided by the customer to minimize inherent or procedural hazards.  
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent  
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other  
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Copyright 1999, Texas Instruments Incorporated  

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