TLV2553IPWRQ1 [TI]
具有断电功能的汽车类 12 位 200KSPS 11 通道低功耗串行 ADC | PW | 20 | -40 to 85;型号: | TLV2553IPWRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有断电功能的汽车类 12 位 200KSPS 11 通道低功耗串行 ADC | PW | 20 | -40 to 85 光电二极管 转换器 模数转换器 |
文件: | 总28页 (文件大小:401K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TLV2553-Q1
www.ti.com ..................................................................................................................................................................................................... SLAS579–APRIL 2009
12-BIT 200-KSPS 11-CHANNEL LOW-POWER SERIAL ADC
1
FEATURES
APPLICATIONS
•
•
•
•
Process Control
•
Qualified for Automotive Applications
Portable Data Logging
Battery-Powered Instruments
Automotive
•
12-Bit-Resolution Analog-to-Digital Converter
(ADC)
•
Up to 200-KSPS (150-KSPS for 3 V)
Throughput Over Operating Temperature
Range With 12-Bit Output Mode
DW PACKAGE
(TOP VIEW)
•
•
•
•
•
•
•
11 Analog Input Channels
VCC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
GND
Three Built-In Self-Test Modes
Inherent Sample and Hold Function
Linearity Error of +1 LSB (Max)
On-Chip Conversion Clock
EOC
I/O CLOCK
DATA IN
DATA OUT
CS
Unipolar or Bipolar Output Operation
REF+
Programmable Most Significant Bit (MSB) or
Least Significant Bit (LSB) First
REF–
AIN10
AIN9
•
•
•
Programmable Power Down
Programmable Output Data Length
SPI Compatible Serial Interface With I/O Clock
Frequencies up to 15 MHz (CPOL=0, CPHA=0)
DESCRIPTION\ORDERING INFORMATION
The TLV2553 is a 12-bit switched-capacitor successive-approximation analog-to-digital converter (ADC). The
ADC has three control inputs [chip select (CS), the input-output clock, and the address/control input (DATAIN)]
designed for communication with the serial port of a host processor or peripheral through a serial 3-state output.
In addition to the high-speed converter and versatile control capability, the device has an on-chip 14-channel
multiplexer that can select any one of 11 inputs or any one of three internal self-test voltages using configuration
register 1. The sample-and-hold function is automatic. At the end of conversion, when programmed as EOC, the
pin 19 output goes high to indicate that conversion is complete. The converter incorporated in the device features
differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog
circuitry from logic and supply noise. A switched-capacitor design allows low-error conversion over the full
operating temperature range.
The TLV2553I is characterized for operation from TA = –40°C to 85°C.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TLV2553IQ1
–40°C to 85°C
SOP – DW
Reel of 2000
TLV2553IDWRQ1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TLV2553-Q1
SLAS579–APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
FUNCTIONAL BLOCK DIAGRAM
V
20
REF+
14
REF−
13
CC
3
Self Test
Reference CTRL
1
2
3
4
5
6
7
8
9
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
14-Channel
Analog
Multiplexer
Low Power
12-Bit
SAR ADC
Sample
and Hold
19
EOC
12
4
Input Address
Register
11
12
12
Output Data
Register
12-to-1
Data
Selector
and Driver
16
DATA
OUT
17
15
18
4
DATA IN
CS
Control Logic
and I/O
Counters
Internal OSC
I/O CLOCK
10
GND
2
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TLV2553-Q1
www.ti.com ..................................................................................................................................................................................................... SLAS579–APRIL 2009
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AIN0–AIN10
1–9, 11, 12
I
Analog input. These 11 analog-signal inputs are internally multiplexed.
Chip select. A high-to-low transition on CS resets the internal counters and controls and
enables DATA OUT, DATA IN, and I/O CLOCK. A low-to-high transition disables DATA IN and
I/O CLOCK within a setup time.
CS
15
17
I
Serial data input. The 4-bit serial data can be used as address selects the desired analog input
channel or test voltage to be converted next, or a command to activate other other features.
The input data is presented with the MSB (D7) first and is shifted in on the first four rising
edges of the I/O CLOCK. After the four address/command bits are read into the command
register CMR, I/O CLOCK clocks the remaining four bits of configuration in.
DATA IN
I
3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state
when CS is high and active when CS is low. With a valid CS, DATA OUT is removed from the
high-impedance state and is driven to the logic level corresponding to the MSB/LSB value of
the previous conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the
logic level corresponding to the next MSB/LSB, and the remaining bits are shifted out in order.
DATA OUT
16
O
O
End-of-convertions status. Used to indicate the end of conversion (EOC) to the host processor.
EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and
remains low until the conversion is complete and the data is ready for transfer.
EOC
GND
19
10
Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all
voltage measurements are with respect to GND.
Input /output clock. I/O CLOCK receives the serial input and performs the following four
functions:
1. It clocks the eight input data bits into the input data register on the first eight rising edges
of I/O CLOCK with the multiplexer address available after the fourth rising edge.
2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected
multiplexer input begins charging the capacitor array and continues to do so until the last
falling edge of I/O CLOCK.
I/O CLOCK
18
I
3. The remaining 11 bits of the previous conversion data are shifted out on DATA OUT.
Data changes on the falling edge of I/O CLOCK.
4. Control of the conversion is transferred to the internal state controller on the falling edge
of the last I/O CLOCK.
Positive reference voltage The upper reference voltage value (nominally VCC) is applied to
REF+. The maximum analog input voltage range is determined by the difference between the
voltage applied to terminals REF+ and REF–.
REF+
14
I/O
I/O
Negative reference voltage. The lower reference voltage value (nominally ground) is applied to
REF–. This pin is connected to analog ground (GND of the ADC) when internal reference is
used.
REF–
VCC
13
20
Positive supply voltage
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ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
VCC
VI
Supply voltage range(2)
–0.5 V to 6.5 V
–0.3 V to VCC + 0.3
–0.3 V to VCC + 0.3
–0.3 V to VCC + 0.3
–0.3 V to VCC + 0.3
±20 mA
Input voltage range (any input)
VO
Output voltage range
Vref+
Vref–
II
Positive reference voltage range
Negative reference voltage range
Peak input current (any input)
Peak total input current (all inputs)
Operating virtual junction temperature range
Operating free-air temperature range
Storage temperature range
±30 mA
TJ
–40°C to 150°C
–40°C to 85°C
–65°C to 150°C
260°C
TA
Tstg
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND terminal with REF– and GND wired together (unless otherwise noted).
RECOMMENDED OPERATING CONDITIONS
MIN
2.7
NOM
MAX UNIT
VCC
Supply voltage
5.5
15
V
16-bit I/O
12-bit I/O
18-bit I/O
0.01
0.01
0.01
0.01
VCC = 4.5 V to 5.5 V
15
I/O CLOCK frequency
MHz
15
VCC = 2.7 to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VCC = 3 V to 3.6 V
VCC = 2.7 V to 3 V
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
10
Tolerable clock jitter, I/O CLOCK
Aperature jitter
0.38
ns
ps
100
0
0
REF+ – REF–
Analog input voltage(1)
V
V
0
2
VIH
High-level control input voltage
2.1
0.8
0.6
85
VIL
TA
Low-level control input voltage
Operating free-air temperature
V
–40
°C
(1) Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than the
voltage applied to REF– convert as all zeros (000000000000).
4
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ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, when VCC = 5 V: VREF+ = 5 V, I/O CLOCK frequency = 15 MHz,
when VCC = 2.7 V: VREF+ = 2.5 V, I/O CLOCK frequency = 10 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC = 4.5 V, IOH = –1.6 mA
VCC = 2.7 V, IOH = –0.2 mA
MIN
TYP(1) MAX UNIT
2.4
VOH
High-level output voltage
30 pF
30 pF
V
VCC = 4.5 V, IOH = –20 µA
VCC = 2.7 V, IOH = –20 µA
VCC – 0.1
VCC = 4.5 V, IOL = –1.6 mA
VCC = 2.7 V, IOL = –0.8 mA
0.4
V
VOL
Low-level output voltage
VCC = 4.5 V, IOL = –20 µA
VCC = 2.7 V, IOL = –20 µA
0.1
VO = VCC, CS = VCC
VO = 0 V, CS = VCC
1
2.5
–2.5
1.2
0.9
1
IOZ
High-impedance off-state output current
Operating supply current
µA
–1
VCC = 5 V
VCC = 2.7 V
CS = 0 V,
External reference
ICC
mA
For all digital inputs, Software power down
0 ≤ VI ≤ 0.5 V or
VI ≥ VCC – 0.5 V,
I/O CLOCK = 0 V
0.1
0.1
ICC(PD) Power-down current
µA
Auto power down
10
IIH
IIL
High-level input current
Low-level input current
VI = VCC
VI = 0 V
0.005
2.5
µA
µA
–0.005
–2.5
Selected channel at VCC
Unselected channel at 0 V
,
1
Ilkg
Selected channel leakage current
Internal oscillator frequency
µA
Selected channel at 0 V,
Unselected channel at VCC
–1
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
3.27
2.56
fOSC
MHz
4.15
5.54
4.1
Conversion time
(13.5 × (1/fOSC) + 25 ns)
tconvert
µs
V
Internal oscillator frequency voltage
3.6
VCC = 4.5 V
VCC = 2.7 V
500
600
55
Zi
Input impedance(2)
Analog inputs
Ω
Analog inputs
Control inputs
45
5
Ci
Input capacitance
pF
15
(1) All typical values are at VCC = 5 V, TA = 25°C.
(2) The switch resistance is very nonlinear and varies with input voltage and supply voltage. This is the worst case.
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EXTERNAL REFERENCE SPECIFICATIONS(1)
PARAMETER
TEST CONDITIONS
VCC = 4.5 V to 5.5 V
MIN TYP(2)
MAX UNIT
–0.1
–0.1
2
0
0
0.1
V
VREF– Reference input voltage, REF–
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
0.1
VCC
VREF+ Reference input voltage, REF+
V
2
VCC
1.9
1.9
VCC
External reference input voltage difference
(REF+ – REF–)
V
VCC
VCC = 4.5 V to 5.5 V
0.94
mA
IREF
External reference supply current
CS = 0 V
VCC = 2.7 V to 3.6 V
Static
0.62
1
6
1
6
MΩ
VCC = 5 V
VCC = 2.7 V
During sampling/conversion
Static
9
9
kΩ
MΩ
kΩ
ZREF
Reference input impedance
During sampling/conversion
(1) Add a 0.1-µF capacitor between REF+ and REF– pins when external reference is used.
(2) All typical values are at VCC = 5 V, TA = 25°C.
OPERATING CHARACTERISTICS
over recommended operating free-air temperature range, when VCC = 5 V: VREF+ = 5 V, I/O CLOCK frequency = 15 MHz,
when VCC = 2.7 V: VREF+ = 2.5 V, I/O CLOCK frequency = 10 MHz (unless otherwise noted)
PARAMETER
Integral linearity error(2)
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
INL
DNL
EO
–1
1
1
2
3
LSB
LSB
mV
Differential linearity error
Offset error(3)
Gain error(3)
–1
(4)
(4)
See
See
–2
EG
–3
mV
ET
Total unadjusted error(5)
±1.5
2048
0
LSB
Address data input = 1011
Address data input = 1100
Address data input = 1101
Self-test output code(6) (see Table 2)
4095
(1) All typical values are at VCC = 5 V, TA = 25°C.
(2) Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
(3) Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified gain
point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the nominal
midstep value at the offset point.
(4) Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than the
voltage applied to REF– convert as all zeros (000000000000).
(5) Total unadjusted error comprises linearity, zero-scale errors, and full-scale errors.
(6) Both the input address and the output codes are expressed in positive logic.
6
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TIMING CHARACTERISTICS
over recommended operating free-air temperature range,
VREF+ = 5 V, I/O CLOCK frequency = 15 MHz, VCC = 5 V, Load = 25 pF (unless otherwise noted)
PARAMETER
MIN
26.7
12
0
MAX UNIT
tw1
tsu1
th1
tsu2
th2
th3
th4
th5
Pulse duration I/O CLOCK high or low
100000
ns
ns
ns
ns
ns
ns
ns
ns
Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 26)
Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 26)
Setup time CS low before first rising I/O CLOCK edge(1) (see Figure 27)
Hold time CS pulse duration high time (see Figure 27)
25
100
0
Hold time CS low after last I/O CLOCK falling edge (see Figure 27)
Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 28)
Hold time CS high after EOC rising edge when CS is toggled (see Figure 31)
2
0
Load = 25 pF
Load = 10 pF
28
20
10
20
55
1.5
1
Delay time CS falling edge to DATA OUT valid (MSB or LSB)
(see Figure 25)
td1
ns
td2
td3
td4
td5
tt1
Delay time CS rising edge to DATA OUT high impedance (see Figure 25)
Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 28)
Delay time last I/O CLOCK falling edge to EOC falling edge
Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion
Transition time I/O CLOCK(1) (see Figure 28)
ns
ns
ns
µs
µs
ns
ns
µs
µs
2
tt2
Transition time DATA OUT (see Figure 28)
5
tt3
Transition time EOC, CL = 7 pF (see Figure 30)
2.4
tt4
Transition time DATA IN, CS
Total cycle time (sample, conversion and delays)(1)
10
(2)
tcycle
Source impedance = 25 Ω
600
650
Channel acquisition time (sample) at 1 kΩ(1)
(see Figure 33 through Figure 38)
Source impedance = 100 Ω
Source impedance = 500 Ω
Source impedance = 1 kΩ
tsample
ns
700
1000
(1) I/O CLOCK period = 8 × [1/(I/O CLOCK frequency)] or 12 × [1/(I/O CLOCK frequency)] or 16 × [1/(I/O CLOCK frequency)], depending
on I/O format selected
(2) tconvert(max) + I/O CLOCK period (8/12/16 CLKs)
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TIMING CHARACTERISTICS
over recommended operating free-air temperature range,
VREF+ = 2.5 V, I/O CLOCK frequency = 10 MHz, VCC = 2.7 V, Load = 25 pF (unless otherwise noted)
PARAMETER
MIN
MAX UNIT
tw1
tsu1
th1
tsu2
th2
th3
th4
th5
Pulse duration I/O CLOCK high or low
40 100000
ns
ns
ns
ns
ns
ns
ns
ns
Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 26)
Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 26)
Setup time CS low before first rising I/O CLOCK edge(1) (see Figure 27)
Hold time CS pulse duration high time (see Figure 27)
22
0
33
100
0
Hold time CS low after last I/O CLOCK falling edge (see Figure 27)
Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 28)
Hold time CS high after EOC rising edge when CS is toggled (see Figure 31)
2
0
Load = 25 pF
Load = 10 pF
30
22
10
33
75
1.5
1
Delay time CS falling edge to DATA OUT valid (MSB or LSB)
(see Figure 25)
td1
ns
td2
td3
td4
td5
tt1
Delay time CS rising edge to DATA OUT high impedance (see Figure 25)
Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 28)
Delay time last I/O CLOCK falling edge to EOC falling edge
Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion
Transition time I/O CLOCK(1) (see Figure 28)
ns
ns
ns
µs
µs
ns
ns
µs
µs
2
tt2
Transition time DATA OUT (see Figure 28)
5
tt3
Transition time EOC, CL = 7 pF (see Figure 30)
4
tt4
Transition time DATA IN, CS
Total cycle time (sample, conversion and delays)(1)
10
(2)
tcycle
Source impedance = 25 Ω
800
850
Channel acquisition time (sample), at 1 kΩ(1)
(see Figure 33 through Figure 38)
Source impedance = 100 Ω
Source impedance = 500 Ω
Source impedance = 1 kΩ
tsample
ns
1000
1600
(1) I/O CLOCK period = 8 × [1/(I/O CLOCK frequency)] or 12 × [1/(I/O CLOCK frequency)] or 16 × [1/(I/O CLOCK frequency)], depending
on I/O format selected
(2) tconvert(max) + I/O CLOCK period (8/12/16 CLKs)
8
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
EXTERNAL REFERENCE CURRENT
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
0.625
0.620
0.615
0.610
0.605
0.600
0.595
0.590
0.585
0.580
0.43
0.42
0.41
0.40
0.39
0.38
0.37
0.36
0.35
0.34
0.33
V
V
V
= 3.3 V
V
V
V
= 3.3 V
CC
CC
= 2.5 V
= 0 V
= 2.5 V
REF+
REF−
REF+
= 0 V
REF−
I/O CLOCK = 10 MHz
I/O CLOCK = 10 MHz
−40 −25 −10
5
20
35
50
65
80
−40 −25 −10
5
20
35
50
65
80
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 1.
Figure 2.
AUTO POWER DOWN
vs
SOFTWARE POWER DOWN
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.06
0.05
0.04
0.03
0.02
0.01
0.00
V
V
V
= 3.3 V
V
V
V
= 3.3 V
CC
CC
= 2.5 V
= 0 V
= 2.5 V
= 0 V
REF+
REF−
REF+
REF−
I/O CLOCK = 10 MHz
I/O CLOCK = 10 MHz
−40 −25 −10
5
20
35
50
65
80
−40 −25 −10
5
20
35
50
65
80
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 3.
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
MAXIMUM DIFFERENTIAL NONLINEARITY
MINIMUM DIFFERENTIAL NONLINEARITY
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.0
−0.1
−0.2
−0.3
−0.4
−0.5
−0.6
−0.7
−0.8
V
V
V
= 2.7 V
CC
V
V
V
= 2.7 V
CC
= 2.5 V
= 0 V
REF+
REF−
= 2.5 V
= 0 V
REF+
REF−
I/O CLOCK = 10 MHz
I/O CLOCK = 10 MHz
−40 −25 −10
5
20
35
50
65
80
−40 −25 −10
5
20
35
50
65
80
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 5.
Figure 6.
MAXIMUM INTEGRAL NONLINEARITY
MINIMUM INTEGRAL NONLINEARITY
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.0
−0.1
−0.2
−0.3
−0.4
−0.5
−0.6
−0.7
V
V
V
= 2.7 V
CC
V
V
V
= 2.7 V
CC
= 2.5 V
= 0 V
REF+
REF−
= 2.5 V
= 0 V
REF+
REF−
I/O CLOCK = 10 MHz
I/O CLOCK = 10 MHz
−40 −25 −10
5
20
35
50
65
80
−40 −25 −10
5
20
35
50
65
80
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.5
V
CC
= 2.7 V, V
= 2.5 V, V
= 0 V, I/O CLOCK = 10 MHz, T = 25°C
REF+
REF−
A
0.4
0.3
0.2
0.1
0.0
−0.1
−0.2
−0.3
−0.4
−0.5
0
1024
2048
3072
4096
Digital Output Code
Figure 9.
INTEGRAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.8
0.6
V
CC
= 2.7 V, V
= 2.5 V, V = 0 V, I/O CLOCK = 10 MHz, T = 25°C
REF− A
REF+
0.4
0.2
0.0
−0.2
−0.4
−0.6
−0.8
0
1024
2048
3072
4096
Digital Output Code
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
GAIN ERROR
vs
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
0.6
0.5
0.4
0.3
0.2
0.1
0.0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
V
V
V
= 3.3 V
CC
V
V
V
= 3.3 V
CC
= 2.5 V
= 0 V
REF+
REF−
= 2.5 V
= 0 V
REF+
REF−
I/O CLOCK = 10 MHz
I/O CLOCK = 10 MHz
−40 −25 −10 20
5
35
50
65
80
−40 −25 −10
5
20
35
50
65
80
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 11.
Figure 12.
SUPPLY CURRENT
vs
EXTERNAL REFERENCE CURRENT
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
0.98
0.96
0.94
0.92
0.90
0.88
0.86
0.84
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
V
V
V
= 5.5 V
CC
= 4.096 V
= 0 V
REF+
REF−
I/O CLOCK = 15 MHz
V
V
V
= 5.5 V
CC
= 4.096 V
= 0 V
REF+
REF−
I/O CLOCK = 15 MHz
−40 −25 −10
5
20
35
50
65
80
−40 −25 −10 20
5
35
50
65
80
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
SOFTWARE POWER DOWN
vs
AUTO POWER DOWN
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
V
V
V
= 5.5 V
CC
= 4.096 V
REF+
= 0 V
REF−
I/O CLOCK = 15 MHz
V
V
V
= 5.5 V
CC
= 4.096 V
= 0 V
REF+
REF−
I/O CLOCK = 15 MHz
−40 −25 −10
5
20
35
50
65
80
−40 −25 −10 20
5
35
50
65
80
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 15.
Figure 16.
MAXIMUM DIFFERENTIAL NONLINEARITY
MINIMUM DIFFERENTIAL NONLINEARITY
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.00
−0.05
−0.10
−0.15
−0.20
−0.25
−0.30
−0.35
−0.40
−0.45
V
V
V
= 5.5 V
CC
V
V
V
= 5.5 V
CC
= 4.096 V
= 0 V
REF+
REF−
= 4.096 V
= 0 V
REF+
REF−
I/O CLOCK = 15 MHz
I/O CLOCK = 15 MHz
−40 −25 −10
5
20
35
50
65
80
−40 −25 −10
5
20
35
50
65
80
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
MAXIMUM INTEGRAL NONLINEARITY
MINIMUM INTEGRAL NONLINEARITY
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
0.90
0.88
0.86
0.84
0.82
0.80
0.78
0.76
0.74
−0.329
−0.330
−0.331
−0.332
−0.333
−0.334
−0.335
−0.336
−0.337
−0.338
V
V
V
= 5.5 V
CC
V
V
V
= 5.5 V
CC
= 4.096 V
= 0 V
REF+
REF−
= 4.096 V
= 0 V
REF+
REF−
I/O CLOCK = 15 MHz
I/O CLOCK = 15 MHz
−40 −25 −10
5
20
35
50
65
80
−40 −25 −10
5
20
35
50
65
80
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 19.
Figure 20.
DIFFERENTIAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.3
0.2
V
CC
= 5.5 V, V
= 4.096 V, V
= 0 V, I/O CLOCK = 15 MHz, T = 25°C
REF+
REF−
A
0.1
0.0
−0.1
−0.2
−0.3
0
1024
2048
3072
4096
Digital Output Code
Figure 21.
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TYPICAL CHARACTERISTICS (continued)
INTEGRAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.8
0.6
0.4
0.2
0.0
−0.2
−0.4
−0.6
V
CC
= 5.5 V, V
= 4.096 V, V = 0 V, I/O CLOCK = 15 MHz, T = 25°C
REF− A
REF+
−0.8
0
1024
2048
3072
4096
Digital Output Code
Figure 22.
OFFSET ERROR
vs
GAIN ERROR
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
0.00
−0.05
−0.10
−0.15
−0.20
−0.25
−0.30
−0.35
−0.40
−0.45
−0.50
0.0
−0.1
−0.2
−0.3
−0.4
−0.5
−0.6
−0.7
−0.8
−0.9
−1.0
V
V
V
= 5.5 V
V
V
V
= 5.5 V
CC
CC
= 4.096 V
= 4.096 V
= 0 V
REF+
REF+
REF−
= 0 V
REF−
I/O CLOCK = 15 MHz
I/O CLOCK = 15 MHz
−40 −25 −10
5
20
35
50
65
80
−40 −25 −10
5
20
35
50
65
80
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 23.
Figure 24.
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Parameter Measurement Information
V
IH
Data Valid
CS
V
IL
V
V
IH
DATA IN
V
IL
t
d1
t
d2
t
h1
V
V
OH
Data Out
t
su1
OL
IH
IL
I/O
CLOCK
V
Figure 25. DATA OUT to Hi-Z Voltage Waveforms
Figure 26. DATA IN and I/O CLOCK Voltage
t
t1
V
IH
CS
t
t1
V
IL
V
IH
I/O
CLOCK
t
h2
V
IL
t
h3
t
su2
I/O CLK Period
V
IH
t
d3
I/O
CLOCK
Last
Clock
V
IL
t
h4
V
V
OH
Data Out
OL
t
t2
Figure 27. CS and I/O CLOCK Voltage Waveforms
Figure 28. I/O CLOCK and DATA OUT Voltage
Waveforms
V
V
IH
t
t3
t3
I/O
CLOCK
V
V
OH
Last
EOC
IL
Clock
OL
t
convert
t
t
d2
V
OH
V
V
OH
EOC
Data Out
V
OL
OL
t
t3
MSB
Valid
Figure 29. I/O CLOCK and EOC Voltage Waveforms
Figure 30. EOC and DATA OUT Voltage Waveforms
1
V
IH
V
IH
CS
V
IL
V
IL
I/O
CLOCK
t
h5
V
V
OH
V
V
EOC
OH
EOC
OL
OL
Figure 31. CS and EOC Waveforms
Figure 32. I/O CLOCK and DATA OUT Voltage
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Parameter Measurement Information (continued)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Sample Cycle
Cycle
1
3
4
7
2
5
6
8
9
10
11
12
3
1
2
I/O
CLOCK
Previous Conversion Data
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1 LSB
Hi−Z State
DATA
OUT
MSB MSB−1 MSB−2
Channel
Address
Output Data
Format
DATA
IN
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
A/D Conversion Interval
t
CONV
EOC
Initialize
Initialize
Figure 33. Timing for 12-Clock Transfer Using CS With DATA OUT Set for MSB First
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Sample Cycle
Cycle
1
3
4
2
5
6
7
8
9
10
11
12
3
1
2
I/O
CLOCK
Previous Conversion Data
DATA
OUT
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1
LSB
MSB
MSB−1 MSB−2
Low Level
Channel
Address
Output Data
Format
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
DATA IN
EOC
A/D Conversion Interval
t
CONV
Initialize
Initialize
NOTE: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 34. Timing for 12-Clock Transfer Not Using CS With DATA OUT Set for MSB First
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Parameter Measurement Information (continued)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Cycle
Sample Cycle
1
3
4
7
2
5
6
8
4
7
1
3
5
6
2
I/O
CLOCK
Previous Conversion Data
Hi−Z State
DATA
OUT
MSB
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 LSB+1
LSB
D0
MSB−5 MSB−6
MSB−1 MSB−2 MSB−3 MSB−4
MSB
Channel
Address
Output Data
Format
D7
D6
D5
D4
D3
D2
D1
D7
D6
D5
D4
D3
D2
D1
DATA IN
EOC
A/D Conversion Interval
t
CONV
Initialize
Initialize
Figure 35. Timing for 8-Clock Transfer Using CS With DATA OUT Set for MSB First
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Sample Cycle
Cycle
1
3
4
7
2
5
6
8
1
2
3
4
5
7
6
I/O
CLOCK
Previous Conversion Data
DATA
OUT
MSB
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 LSB+1
LSB
MSB−2 MSB−3 MSB−4 MSB−5
MSB−6
MSB
MSB−1
Low Level
Channel
Address
Output Data
Format
D7
D6
D5
D4
D3
D2
D1
D0
D7
D4
D3
D2
D1
D6
D5
DATA IN
EOC
A/D Conversion Interval
t
CONV
Initialize
Initialize
NOTE: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 36. Timing for 8-Clock Transfer Not Using CS With DATA OUT Set for MSB First
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Parameter Measurement Information (continued)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access Cycle
Sample Cycle
10
1
3
4
7
2
5
6
8
9
11
12
16
1
I/O
CLOCK
Pad
Zeros
Previous Conversion Data
Hi−Z State
DATA
OUT
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1
LSB
MSB
Channel
Address
Output Data
Format
D7
D6
D5
D4
D3
D2
D1
D0
D7
DATA IN
EOC
A/D Conversion Interval
t
CONV
Initialize
Initialize
Figure 37. Timing for 16-Clock Transfer Using CS With DATA OUT Set for MSB First
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access Cycle
Sample Cycle
1
3
4
7
2
5
6
8
9
10
11
12
16
1
I/O
CLOCK
Pad
Zeros
Previous Conversion Data
DATA
OUT
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1
LSB
MSB
Low Level
Channel
Address
Output Data
Format
D7
D6
D5
D4
D3
D2
D1
D0
D7
DATA IN
EOC
A/D Conversion Interval
t
CONV
Initialize
Initialize
NOTE: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 38. Timing for 16-Clock Transfer Not Using CS With DATA OUT Set for MSB First
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PRINCIPLES OF OPERATION
Detailed Description
Initially, with chip select (CS) high, I/O CLOCK and DATA IN are disabled and DATA OUT is in the
high-impedance state. CS going low begins the conversion sequence by enabling I/O CLOCK and DATA IN and
removes DATA OUT from the high-impedance state. The input data is an 8-bit data stream consisting of a 4-bit
address or command (D7–D4) and a 4-bit configuration data (D3–D0). Configuration register 1 (CFGR1), which
controls output data format configuration, consists of a 2-bit data length select (D3–D2), an output MSB or LSB
first bit (D1), and a unipolar or bipolar output select bit (D0) that are applied to any command (from DATA IN)
except for command 1111b. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data to
the input data register. During this transfer, the I/O CLOCK sequence also shifts the previous conversion result
from the output data register to DATA OUT. I/O CLOCK receives the input sequence of 8, 12, or 16 clock cycles
long depending on the data-length selection in the input data register. Sampling of the analog input begins on the
fourth falling edge of the input I/O CLOCK sequence and is held after the last falling edge of the I/O CLOCK
sequence. The last falling edge of the I/O CLOCK sequence also takes EOC low and begins the conversion.
Converter Operation
The operation of the converter is organized as a succession of three distinct cycles: 1) the data I/O cycle, 2) the
sampling cycle, and 3) the conversion cycle. The first two are partially overlapped.
Data I/O Cycle
The data I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods,
depending on the selected output data length. During the I/O cycle, the following two operations take place
simultaneously. An 8-bit data stream consisting of address/command and configuration information is provided to
DATA IN. This data is shifted into the device on the rising edge of the first eight I/O CLOCK clocks. DATA INPUT
is ignored after the first eight clocks during 12- or 16-clock I/O transfers. The data output, with a length of 8, 12,
or 16 bits, is provided serially on DATA OUT. When CS is held low, the first output data bit occurs on the rising
edge of EOC. When CS is toggled between conversions, the first output data bit occurs on the falling edge of
CS. This data is the result of the previous conversion period, and after the first output data bit, each succeeding
bit is clocked out on the falling edge of each succeeding I/O CLOCK.
Sampling Cycle
During the sampling cycle, one of the analog inputs is internally connected to the capacitor array of the converter
to store the analog input signal. The converter starts sampling the selected input immediately after the four
address/command bits have been clocked into the input data register. Sampling starts on the fourth falling edge
of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling edge of
the I/O CLOCK depending on the data-length selection.
After the 8-bit data stream has been clocked in, DATA IN should be held at a fixed digital level until EOC goes
high (indicating that the conversion is complete) to maximize the sampling accuracy and minimize the influence
of external digital noise.
Conversion Cycle
A conversion cycle is started only after the I/O cycle is completed, which minimizes the influence of external
digital noise on the accuracy of the conversion. This cycle is transparent to the user because it is controlled by
an internal clock (oscillator). The total conversion time is equal to 13.5 OSC clocks plus a small delay (~25 ns) to
start the OSC. During the conversion period, the device performs a successive-approximation conversion on the
analog input voltage.
EOC goes low at the start of the conversion cycle and goes high when the conversion is complete and the output
data register is latched. After EOC goes low, the analog input can be changed without affecting the conversion
result. Since the delay from the falling edge of the last I/O CLOCK to the falling edge of EOC is fixed, any
time-varying analog input signals can be digitized at a fixed rate without introducing systematic harmonic
distortion or noise due to timing uncertainty.
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Power Up and Initialization
After power up, CS must be taken from high to low to begin an I/O cycle. The EOC pin is initially high, and the
configuration register is set to all zeroes. The contents of the output data register are random, and the first
conversion result should be ignored. To initialize during operation, CS is taken high and is then returned low to
begin the next I/O cycle. The first conversion after the device has returned from the power-down state may not
read accurately due to internal device settling.
Table 1. Operational Terminology
The entire I/O CLOCK sequence that transfers address and control data into the data register and
Current (N) I/O cycle
clocks the digital result from the previous conversion from DATA OUT
The conversion cycle starts immediately after the current I/O cycle. The end of the current I/O cycle
Current (N) conversion cycle
is the last clock falling edge in the I/O CLOCK sequence. The current conversion result is loaded
into the output register when conversion is complete.
Current (N) conversion result
Previous (N – 1) conversion cycle
Next (N + 1) I/O cycle
The current conversion result is serially shifted out on the next I/O cycle.
The conversion cycle just prior to the current I/O cycle
The I/O period that follows the current conversion cycle
Example
In 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during the
next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even when this
corrupts the output data from the previous conversion. The current conversion is begun immediately after the
twelfth falling edge of the current I/O cycle.
Data Input
The data input is internally connected to an 8-bit serial-input address and control register. The register defines
the operation of the converter and the output data length. The host provides the input data byte with the MSB
first. Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 2 for the data
input-register format).
Table 2. Command Set (CMR) and Configuration
SDI D[7:4]
CFGR1
COMMAND
CONFIGURATION
01: 8-bit output length
X0: 12-bit output length(1)
11: 16-bit output length
0: MSB out first
BINARY
HEX
0
SDI D[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
SELECT analog input channel 0
SELECT analog input channel 1
SELECT analog input channel 2
SELECT analog input channel 3
SELECT analog input channel 4
SELECT analog input channel 5
SELECT analog input channel 6
SELECT analog input channel 7
SELECT analog input channel 8
SELECT analog input channel 9
SELECT analog input channel 10
1
D[3:2]
2
3
D1
D0
4
1: LSB out first
5
0: Unipolar binary
6
1: Bipolar 2s complement
7
8
9
A
SELECT TEST,
Voltage = (VREF+ + VREF–)/2
1011
B
1100
1101
1110
1111
C
D
E
F
SELECT TEST, Voltage = REFM
SELECT TEST, Voltage = REFP
SW POWERDOWN (analog + reference)
Reserved
(1) Select 12-bit output mode to achieve 200-KSPS sampling rate.
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Data Input – Address/Command Bits
The four MSBs (D7–D4) of the input data register are the address or command. These can be used to address
one of the 11 input channels, address one of three reference-test voltages, or activate software power-down
mode. All address/command bits affect the current conversion, which is the conversion that immediately follows
the current I/O cycle. They also have access to CFGR1 except for command 1111b, which is reserved.
Data Output Length
CFGR1 bits (D3 and D2) of the data register select the output data length. The data-length selection is valid for
the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the current
I/O cycle, allows device start-up without losing I/O synchronization. A data length of 8, 12, or 16 bits can be
selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested.
With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current
conversion is output as a 12-bit serial data stream during the next I/O cycle. The current I/O cycle must be
exactly 12 bits long for proper synchronization, even when this means corrupting the output data from a previous
conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle.
With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication
with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial
data stream during the next I/O cycle with the four LSBs always reset to 0 (pad bits). The current I/O cycle must
be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the
previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current
I/O cycle.
With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit
serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial data stream
during the next I/O cycle. The current I/O cycle must be exactly eight bits long to maintain synchronization, even
when this means corrupting the output data from the previous conversion. The four LSBs of the conversion result
are truncated and discarded. The current conversion is started immediately after the eighth falling edge of the
current I/O cycle.
Since the D3 and D2 register settings take effect on the I/O cycle when the data length is programmed, there can
be a conflict with the previous cycle if the data-word length was changed. This may occur when the data format
is selected to be least significant bit first, since at the time the data length change becomes effective (six rising
edges of I/O CLOCK), the previous conversion result has already started shifting out. In actual operation, when
different data lengths are required within an application and the data length is changed between two conversions,
no more than one conversion result can be corrupted and only when it is shifted out in LSB-first format.
LSB Out First
D1 in the CFGR1 controls the direction of the output (binary) data transfer. When D1 is reset to 0, the conversion
result is shifted out MSB first. When set to 1, the data is shifted out LSB first. Selection of MSB first or LSB first
always affects the next I/O cycle and not the current I/O cycle. When changing from one data direction to
another, the current I/O cycle is never disrupted.
Bipolar Output Format
D0 in the CFGR1 controls the binary data format used to represent the conversion result. When D0 is cleared to
0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the conversion result of an
input voltage equal to or less than VREF– is a code with all zeros (000...0) and the conversion result of an input
voltage equal to or greater than VREF+ is a code of all ones (111...1). The conversion result of (VREF+ + VREF–)/2 is
a code of a one followed by zeros (100...0).
When D0 is set to 1, the conversion result is represented as bipolar (signed binary) data. Nominally, conversion
of an input voltage equal to or less than VREF– is a code of a one followed by zeros (100...0), and the conversion
of an input voltage equal to or greater than VREF+ is a code of a zero followed by all ones (011...1). The
conversion result of (VREF+ + VREF–)/2 is a code of all zeros (000...0). The MSB is interpreted as the sign bit. The
bipolar data format is related to the unipolar format in that the MSBs are always each other's complement.
22
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Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output
during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the
current I/O cycle is not affected.
Reference
An external reference can be used through two reference input pins, REF+ and REF–. The voltage levels applied
to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale
reading respectively. The values of REF+, REF–, and the analog input should not exceed the positive supply or
be lower than GND consistent with the specified absolute maximum ratings. The digital output is at full scale
when the input signal is equal to or higher than REF+ and at zero when the input signal is equal to or lower than
REF–.
Analog
Supply
V
CC
REF+
REF−
Sample
Convert
50 pF
CDAC
C1
0.1 µF
Decoupling Cap
GND
Figure 39. Reference Block
EOC Output
Pin 19 outputs the status of the ADC conversion. When programmed as EOC, the output indicates the beginning
and the end of conversion. In the reset state, EOC is always high. During the sampling period (beginning after
the fourth falling edge of the I/O CLOCK sequence), EOC remains high until the internal sampling switch of the
converter is safely opened. The opening of the sampling switch occurs after the eighth, twelfth, or sixteenth I/O
CLOCK falling edge, depending on the data-length selection in the input data register. After the EOC signal goes
low, the analog input signal can be changed without affecting the conversion result.
The EOC signal goes high again after the conversion is completed and the conversion result is latched into the
output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins.
On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When
CS is toggled between conversions, the first bit of the current conversion result occurs on DATA OUT at the
falling edge of CS.
Chip-Select Input (CS)
CS enables and disables the device. During normal operation, CS should be low. Although the use of CS is not
necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data
transfer of several devices sharing the same bus.
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When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing its
output data line to other devices that may share it. After an internally generated debounce time, I/O CLOCK is
inhibited, thus preventing any further change in the internal state.
When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce
time before the reset operation takes effect. After CS is debounced low, I/O CLOCK must remain inactive (low)
for a minimum time before a new I/O cycle can start.
CS can interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low long enough
before the end of the current conversion cycle, the previous conversion result is saved in the internal output
buffer and shifted out during the next I/O cycle.
When CS is held low continuously for multiple cycles, the first data bit of the newly completed conversion occurs
on DATA OUT on the rising edge of EOC. Note that the first cycle in the series still requires a transition CS from
high to low. When a new conversion is started after the last falling edge of I/O CLOCK, EOC goes low and the
serial output is forced low until EOC goes high again.
When CS is toggled between conversions, the first data bit occurs on DATA OUT on the falling edge of CS. On
each subsequent falling edge of I/O CLOCK after the first data bit appears, the data is changed to the next bit in
the serial conversion result until the required number of bits has been output.
Power-Down Features
When command (D7–D4) 1110b is clocked into the input data register during the first four I/O CLOCK cycles, the
software power-down mode is selected. Software power down is activated on the falling edge of the fourth I/O
CLOCK pulse.
During software power-down, all internal circuitry is put in a low-current standby mode. No conversions is
performed. The internal output buffer keeps the previous conversion cycle data results, provided that all digital
inputs are held above VCC – 0.5 V or below 0.5 V. The I/O logic remains active so the current I/O cycle must be
completed even when the power-down mode is selected. Upon power-on reset and before the first I/O cycle, the
converter normally begins in the power-down mode. The device remains in the software power-down mode until
a valid input address (other than command 1110b or 1111b) is clocked in. Upon completion of that I/O cycle, a
normal conversion is performed with the results being shifted out during the next I/O cycle.
The ADC also has an auto power-down mode. This is transparent to users. The ADC gets into auto power-down
within one I/O CLOCK cycle after the conversion is complete and resumes, with a small delay, after an active CS
is sent to the ADC. The resumption is fast enough to be used between cycles.
Analog MUX
The 11 analog inputs, 3 internal voltages, and power-down mode are selected by the input multiplexer according
to the input addresses shown in Table 2. The input multiplexer is a break-before-make type to reduce
input-to-input noise rejection resulting from channel switching. Sampling of the analog input starts on the falling
edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held on the
falling edge of the last I/O CLOCK pulse. The three internal test inputs are applied to the multiplexer, then
sampled and converted in the same manner as the external analog inputs. The first conversion after the device
has returned from the power-down state may not read accurately due to internal device settling.
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Dec-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TLV2553IDWRQ1
ACTIVE
SOIC
DW
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV2553-Q1 :
Catalog: TLV2553
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
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