TLV2770CDGKRG4 [TI]
FAMILY OF 2.7-HIGH-SLEW-RATE RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS WITH SHUTDOWN; 家庭的2.7高转换率轨至轨输出运算放大器，带有关断
| 型号： | TLV2770CDGKRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | FAMILY OF 2.7-HIGH-SLEW-RATE RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS WITH SHUTDOWN |
| 文件： | 总65页 (文件大小：1493K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂꢃ ꢄ ꢄ ꢅ ꢆ ꢀꢁꢂ ꢃꢄ ꢄꢅ ꢇ
ꢈꢇ ꢉꢊ ꢁꢋ ꢌ ꢈ ꢃ ꢍꢄ ꢎꢂ ꢏꢊ ꢐꢏ ꢎꢑꢁ ꢒꢓꢎꢔꢇꢀ ꢒ ꢔꢇꢊ ꢁ ꢎꢀꢌ ꢎꢔꢇꢊ ꢁ ꢌ ꢕꢀ ꢖ ꢕꢀ
ꢌ ꢖꢒꢔ ꢇꢀ ꢊꢌ ꢗꢇꢁ ꢇꢉ ꢖꢁ ꢊꢈ ꢊꢒ ꢔꢑ ꢓ ꢊꢀ ꢏ ꢑꢏꢕ ꢀꢘ ꢌ ꢓꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
D
D
D
D
D
D
High Slew Rate . . . 10.5 V/µs Typ
D
D
D
D
D
2 pA Input Bias Current
High-Gain Bandwidth . . . 5.1 MHz Typ
Supply Voltage Range 2.5 V to 5.5 V
Rail-to-Rail Output
Characterized From T = −55°C to 125°C
A
Available in MSOP and SOT-23 Packages
Micropower Shutdown Mode . . . I
Available in Q-Temp Automotive
High Reliability Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards
< 1 µA
DD
360 µV Input Offset Voltage
Low Distortion Driving 600-Ω
0.005% THD+N
D
1 mA Supply Current (Per Channel)
D
17 nV/√Hz Input Noise Voltage
description
The TLV277x CMOS operational amplifier family combines high slew rate and bandwidth, rail-to-rail output
swing, high output drive, and excellent dc precision. The device provides 10.5 V/µs of slew rate and 5.1 MHz
of bandwidth while only consuming 1 mA of supply current per channel. This ac performance is much higher
than current competitive CMOS amplifiers. The rail-to-rail output swing and high output drive make these
devices a good choice for driving the analog input or reference of analog-to-digital converters. These devices
also have low distortion while driving a 600-Ω load for use in telecom systems.
These amplifiers have a 360-µV input offset voltage, a 17 nV/√Hz input noise voltage, and a 2-pA input bias
current for measurement, medical, and industrial applications. The TLV277x family is also specified across an
extended temperature range (−40°C to 125°C), making it useful for automotive systems, and the military
temperature range (−55°C to 125°C), for military systems.
These devices operate from a 2.5-V to 5.5-V single supply voltage and are characterized at 2.7 V and 5 V. The
single-supply operation and low power consumption make these devices a good solution for portable
applications. The following table lists the packages available.
FAMILY PACKAGE TABLE
NUMBER
OF
CHANNELS
PACKAGE TYPES
UNIVERSAL
EVM BOARD
DEVICE
SHUTDOWN
PDIP
CDIP
SOIC SOT-23 TSSOP MSOP LCCC CPAK
TLV2770
TLV2771
TLV2772
TLV2773
TLV2774
TLV2775
1
1
2
2
4
4
8
—
—
8
8
8
—
5
—
—
8
8
—
—
20
—
—
—
—
—
10
—
—
—
Yes
—
—
8
—
8
Refer to the EVM
Selection Guide
(Lit# SLOU060)
8
—
—
—
—
—
14
14
16
—
—
—
14
14
16
—
14
16
10
—
—
Yes
—
Yes
†
A SELECTION OF SINGLE-SUPPLY OPERATIONAL AMPLIFIER PRODUCTS
V
(V)
BW
(MHz)
SLEW RATE
I
(per channel)
(µA)
DD
DD
DEVICE
RAIL-TO-RAIL
(V/µs)
TLV277X
TLV247X
TLV245X
TLV246X
2.5 − 6.0
2.7 − 6.0
2.7 − 6.0
2.7 − 6.0
5.1
2.8
10.5
1.5
1000
600
23
O
I/O
I/O
I/O
0.22
6.4
0.11
1.6
550
†
All specifications measured at 5 V.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 1998−2004, Texas Instruments Incorporated
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ꢌꢖ ꢒ ꢔꢇꢀ ꢊ ꢌꢗ ꢇ ꢁ ꢇꢉ ꢖꢁ ꢊ ꢈꢊ ꢒ ꢔꢑ ꢓ ꢊ ꢀꢏ ꢑ ꢏꢕꢀ ꢘꢌ ꢓ ꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
TLV2770 and TLV2771 AVAILABLE OPTIONS
PACKAGED DEVICES
SOT-23 MSOP
V
IO
max AT 25°C
(mV)
T
A
SMALL OUTLINE
(D)
PLASTIC DIP
(P)
(DBV)
(DGK)
†
TLV2770CD
TLV2771CD
—
TLV2770CDGK
—
TLV2770CP
—
0°C to 70°C
2.5
2.5
1.6
TLV2771CDBV
†
TLV2770ID
TLV2771ID
—
TLV2770IDGK
—
TLV2770IP
—
TLV2771IDBV
−40°C to 125°C
TLV2770AID
TLV2771AID
—
—
—
—
TLV2770AIP
—
†
This device is in the Product Preview stage of development. Please contact your local TI sales office for availability.
TLV2772 and TLV2773 AVAILABLE OPTIONS
PACKAGED DEVICES
V
IO
max AT 25°C
(mV)
T
A
SMALL OUTLINE
(D)
MSOP
(DGK)
MSOP
(DGS)
PLASTIC DIP
(N)
PLASTIC DIP
(P)
TLV2772CD
TLV2773CD
TLV2772CDGK
—
—
—
TLV2772CP
—
0°C to 70°C
2.5
2.5
1.6
TLV2773CDGS
TLV2773CN
TLV2772ID
TLV2773ID
TLV2772IDGK
—
—
—
TLV2772IP
—
TLV2773IDGS
TLV2773IN
−40°C to 125°C
TLV2772AID
TLV2773AID
—
—
—
—
—
TLV2772AIP
—
TLV2773AIN
TLV2774 and TLV2775 AVAILABLE OPTIONS
PACKAGED DEVICES
PLASTIC DIP PLASTIC DIP
(P)
V
IO
max AT 25°C
(mV)
T
A
SMALL OUTLINE
(D)
TSSOP
(PW)
(N)
TLV2774CD
TLV2775CD
—
TLV2774CP
—
TLV2774CPW
TLV2775CPW
0°C to 70°C
2.7
2.7
2.1
TLV2775CN
TLV2774ID
TLV2775ID
—
TLV2774IP
—
TLV2774IPW
TLV2775IPW
TLV2775IN
−40°C to 125°C
TLV2774AID
TLV2775AID
—
TLV2774AIP
—
TLV2774AIPW
TLV2775AIPW
TLV2775AIN
TLV2772M/Q AND TLV2772AM/Q AVAILABLE OPTIONS
PACKAGED DEVICES
SMALL
OUTLINE
(D)
V
IO
max AT 25°C
(mV)
CERAMIC
FLATPACK
(U)
T
A
CHIP CARRIER
(FK)
CERAMIC DIP
(JG)
TSSOP
(PW)
‡
‡
TLV2772QPW
2.5
1.6
2.5
1.6
TLV2772QD
—
—
—
−40°C to 125°C
−55°C to 125°C
‡
‡
TLV2772AQD
—
—
—
TLV2772AQPW
TLV2772MD
TLV2772MFK
TLV2772AMFK
TLV2772MJG
TLV2772AMJG
TLV2772MU
TLV2772AMU
—
—
TLV2772AMD
‡
Available in tape and reel
2
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ꢌ ꢖꢒꢔ ꢇꢀ ꢊꢌ ꢗꢇꢁ ꢇꢉ ꢖꢁ ꢊꢈ ꢊꢒ ꢔꢑ ꢓ ꢊꢀ ꢏ ꢑꢏꢕ ꢀꢘ ꢌ ꢓꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
PACKAGE SYMBOLS
†
PACKAGE TYPE
PINS
PART NUMBER
TLV2771CDBV
TLV2771IDBV
TLV2770CDGK
TLV2770IDGK
TLV2772CDGK
TLV2772IDGK
TLV2773CDGS
TLV2773IDGS
SYMBOL
VAMC
SOT23
5 Pin
VAMI
xxTIABO
xxTIABP
xxTIAAF
xxTIAAG
xxTIABQ
xxTIABR
8 Pin
MSOP
10 Pin
xx represents the device date code.
†
TLV277x PACKAGE PINOUT
TLV2772M AND TLV2772AM
FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
NC
NC
1IN−
NC
4
5
6
7
8
2OUT
NC
17
16
15
14
2IN−
NC
1IN+
NC
9 10 11 12 13
NC − No internal connection
3
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ꢌꢖ ꢒ ꢔꢇꢀ ꢊ ꢌꢗ ꢇ ꢁ ꢇꢉ ꢖꢁ ꢊ ꢈꢊ ꢒ ꢔꢑ ꢓ ꢊ ꢀꢏ ꢑ ꢏꢕꢀ ꢘꢌ ꢓ ꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
(1)
TLV277x PACKAGE PINOUTS
TLV2771
DBV PACKAGE
(TOP VIEW)
TLV2770
D, DGK OR P PACKAGE
(TOP VIEW)
TLV2771
D PACKAGE
(TOP VIEW)
†
1
2
3
5
V
DD
OUT
GND
NC
IN−
SHDN
1
2
3
4
8
7
6
5
NC
IN−
NC
1
2
3
4
8
7
6
5
V
DD
V
DD
IN+
OUT
NC
IN+
OUT
NC
GND
GND
4
IN−
IN+
TLV2772
D, DGK, JG, P, OR PW PACKAGE
(TOP VIEW)
TLV2773
DGS PACKAGE
(TOP VIEW)
TLV2772M AND TLV2772AM
U PACKAGE
(TOP VIEW)
1
1
1OUT
1IN−
1IN+
GND
1SHDN
V
2OUT
2IN−
2IN+
1OUT
1IN−
1IN+
GND
V
1
2
3
4
8
7
6
5
10
NC
1OUT
1IN −
1IN +
GND
NC
V
2OUT
2IN −
2IN +
10
9
DD
DD
2
3
4
5
2
3
4
5
9
8
7
6
2OUT
2IN−
2IN+
+
DD
8
7
2SHDN
6
TLV2775
TLV2773
TLV2774
D, N, OR PW PACKAGE
D OR N PACKAGE
D, N, OR PW PACKAGE
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
1OUT
1IN−
1IN+
4OUT
4IN−
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1OUT
1IN−
1IN+
GND
NC
V
DD
2OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
1
2
3
4
5
6
7
14
13
12
11
10
9
1OUT
1IN−
1IN+
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
4IN+
2IN−
2IN+
NC
V
GND
DD
V
DD
2IN+
2IN−
3IN+
2IN+
2IN−
3IN−
1SHDN
NC
2SHDN
NC
2OUT
3OUT
3/4SHDN
8
8
2OUT
1/2SHDN
†
This device is in the Product Preview stage of development. Please contact your local TI sales office for availability.
(1) SOT−23 may or may not be indicated
TYPICAL PIN 1 INDICATORS
Pin 1
Printed or
Molded Dot
Pin 1
Pin 1
Pin 1
Molded ”U” Shape
Stripe
Bevel Edges
4
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SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V (any input, see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V
V
ID
DD
DD
I
Input current, I (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 mA
I
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
O
Total current into V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
DD+
Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Duration of short-circuit current (at or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Q suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to GND.
2. Differential voltages are at the noninverting input with respect to the inverting input. Excessive current flows when input is brought
below GND − 0.3 V.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T
= 85°C
T = 125°C
A
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
POWER RATING
POWER RATING
145 mW
87 mW
A
D
DBV
DGK
DGS
FK
725 mW
5.8 mW/°C
3.5 mW/°C
3.4 mW/°C
3.4 mW/°C
11.0 mW/°C
8.4 mW/°C
9.2 mW/°C
8.0 mW/°C
5.6 mW/°C
5.4 mW/°C
464 mW
377 mW
437 mW
280 mW
227 mW
424 mW
271 mW
220 mW
85 mW
424 mW
271 mW
220 mW
85 mW
1375 mW
1050 mW
1150 mW
1000 mW
700 mW
672 mW
546 mW
210 mW
275 mW
230 mW
200 mW
140 mW
135 mW
JG
880 mW
714 mW
N
736 mW
598 mW
P
640 mW
520 mW
PW
U
448 mW
364 mW
675 mW
432 mW
350 mW
recommended operating conditions
C SUFFIX
I SUFFIX
Q SUFFIX
M SUFFIX
UNIT
MIN
2.5
MAX
MIN
MAX
MIN
MAX
MIN
2.5
MAX
Supply voltage, V
DD
6
2.5
GND
GND
−40
6
2.5
GND
GND
−40
6
6
V
V
Input voltage range, V
GND
GND
0
V
V
−1.3
V
V
−1.3
V
V
−1.3
GND
GND
−55
V
V
−1.3
I
DD+
DD+
DD+
DD+
Common-mode input voltage, V
IC
−1.3
−1.3
−1.3
−1.3
V
DD+
DD+
DD+
DD+
Operating free-air temperature, T
70
125
125
125
°C
A
5
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ꢏ
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ꢑ
ꢁ
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ꢓ
ꢎ
ꢔ
ꢇ
ꢀ
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ꢔ
ꢇ
ꢊ
ꢁ
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SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, V
= 2.7 V (unless otherwise noted)
DD
TLV277xC
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP
0.48
0.53
0.8
MAX
2.5
25°C
Full range
25°C
TLV2770/1/2
TLV2773/4/5
V
R
= 0,
V
V
= 0,
IC
S
O
2.7
= 50 Ω,
=
1.35 V,
1.35 V
V
IO
Input offset voltage
mV
DD
2.7
No load
Full range
0.86
2.9
Temperature coefficient of input
offset voltage
25°C to
125°C
α
VIO
2
µV/°C
pA
25°C
Full range
25°C
1
2
60
100
60
V
IC
= 0,
V
V
= 0,
=
O
DD
I
IO
Input offset current
Input bias current
R
= 50 Ω
S
2
I
IB
pA
Full range
25°C
6
100
2.6
2.5
2.4
2.1
0.1
0.2
0.21
0.6
380
I
I
= −0.675 mA
= −2.2 mA
= 1.35 V,
OH
Full range
25°C
V
High-level output voltage
Low-level output voltage
V
OH
OL
OH
Full range
25°C
V
V
I
I
= 0.675 mA
IC
OL
Full range
25°C
V
V
= 1.35 V,
= 2.2 mA
IC
OL
Full range
25°C
20
13
Large-signal differential voltage
amplification
V
V
= 1.35 V,
= 0.6 V to 2.1 V
R
= 10 kΩ,
IC
O
L
A
VD
V/mV
Full range
25°C
12
10
r
Differential input resistance
Ω
pF
Ω
i(d)
c
z
Common-mode input capacitance f = 10 kHz
25°C
8
25
84
82
89
84
1
i(c)
o
Closed-loop output impedance
Common-mode rejection ratio
Supply voltage rejection ratio
f = 100 kHz,
A
V
= 10
25°C
25°C
60
60
70
70
V
R
= 0 to 1.5 V,
= 50 Ω
V
O
= V /2,
DD
IC
CMRR
dB
dB
Full range
25°C
S
V
= 2.7 V to 5 V,
V
IC
= V /2,
DD
DD
k
SVR
(∆V
DD
/∆V
IO
)
No load
Full range
25°C
2
2
I
Supply current (per channel)
V
O
= V /2,
DD
No load
mA
DD
Full range
25°C
0.8
1.3
1.5
2
Supply current in shutdown (per
channel)
I
µA
DD(SHDN)
Full range
TLV2770
1.47
1.43
1.40
1.27
1.21
1.20
Turnon voltage
TLV2773
level
V
(ON)
A
= 5
= 5
25°C
25°C
V
V
TLV2775
TLV2770
Turnoff voltage
TLV2773
level
V
(OFF)
A
V
V
TLV2775
†
Full range is 0°C to 70°C.
6
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SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
operating characteristics at specified free-air temperature, V
= 2.7 V (unless otherwise noted)
DD
TLV277xC
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP
MAX
25°C
5
9
V
R
= 0.8 V,
C
= 100 pF,
L
O(PP)
= 10 kΩ
SR
Slew rate at unity gain
V/µs
Full
range
4.7
6
L
f = 1 kHz
25°C
25°C
21
17
nV/√Hz
V
n
Equivalent input noise voltage
f = 10 kHz
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
f = 100 Hz
0.33
V
I
Peak-to-peak equivalent input noise voltage
Equivalent input noise current
25°C
25°C
µV
N(PP)
0.86
0.6
fA/√Hz
n
A
= 1
0.0085%
0.025%
0.12%
V
R
= 600 Ω,
L
A
V
= 10
THD + N Total harmonic distortion plus noise
Gain-bandwidth product
25°C
f = 1 kHz
A
= 100
R = 600 Ω,
L
V
f = 10 kHz,
C
25°C
25°C
25°C
4.8
0.186
0.3
MHz
= 100 pF
L
A
= −1,
V
0.1%
Step = 1 V,
t
s
Settling time
µs
R
C
= 600 Ω,
= 100 pF
L
L
0.01%
φ
m
Phase margin at unity gain
Gain margin
25°C
25°C
46°
R
= 600 Ω,
C = 100 pF
L
L
12
dB
†
Full range is 0°C to 70°C.
7
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ꢀ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
TLV277xC
†
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP MAX
25°C
Full range
25°C
0.5
0.6
2.5
2.7
2.5
2.7
TLV2770/1/2
TLV2773/4/5
V
R
= 0,
= 50 Ω,
V
V
= 0,
IC
S
O
=
2.5 V,
V
IO
Input offset voltage
mV
DD
0.7
No load
Full range
0.78
Temperature coefficient of input
offset voltage
25°C to
125°C
α
2
µV/°C
pA
VIO
25°C
Full range
25°C
1
2
60
100
60
V
= 0,
V
V
= 0,
=
IC
O
DD
I
IO
Input offset current
Input bias current
2.5 V
R
= 50 Ω
S
2
I
IB
pA
Full range
25°C
6
100
4.9
4.8
4.7
4.4
0.1
0.2
0.21
0.6
450
I
I
= −1.3 mA
= −4.2 mA
= 2.5 V,
OH
Full range
25°C
V
High-level output voltage
Low-level output voltage
V
OH
OL
OH
Full range
25°C
V
V
I
I
= 1.3 mA
IC
OL
Full range
25°C
V
V
= 2.5 V,
= 4.2 mA
IC
OL
Full range
25°C
20
13
Large-signal differential voltage
amplification
V
V
= 2.5 V,
= 1 V to 4 V
R
= 10 kΩ,
IC
O
L
A
VD
V/mV
Full range
25°C
12
10
r
Differential input resistance
Ω
pF
Ω
i(d)
c
z
Common-mode input capacitance
Closed-loop output impedance
f = 10 kHz
25°C
8
20
96
93
89
84
1
i(c)
o
f = 100 kHz,
A
V
= 10
25°C
25°C
70
70
70
70
V
R
= 0 to 3.7 V,
= 50 Ω
V
O
= V /2,
DD
IC
CMRR
Common-mode rejection ratio
dB
dB
Full range
25°C
S
Supply voltage rejection ratio
V
= 2.7 V to 5 V,
V
IC
= V /2,
DD
DD
k
SVR
(∆V
DD
/∆V
IO
)
No load
Full range
25°C
2
2
I
Supply current (per channel)
V
O
= V
/2,
No load
mA
DD
DD
Full range
25°C
0.8
1.3
1.5
2
Supply current in shutdown (per
channel)
I
µA
DD(SHDN)
Full range
TLV2770
2.59
2.47
2.48
2.41
2.32
2.29
TLV2773
TLV2775
TLV2770
TLV2773
TLV2775
V
Turnon voltage level
Turnoff voltage level
A
= 5
= 5
25°C
25°C
V
(ON)
V
V
(OFF)
A
V
V
†
Full range is 0°C to 70°C.
8
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ꢈꢇ ꢉꢊ ꢁꢋ ꢌ ꢈ ꢃ ꢍꢄ ꢎꢂ ꢏꢊ ꢐꢏ ꢎꢑꢁ ꢒꢓꢎꢔꢇꢀ ꢒ ꢔꢇꢊ ꢁ ꢎꢀꢌ ꢎꢔꢇꢊ ꢁ ꢌ ꢕꢀ ꢖ ꢕꢀ
ꢌ ꢖꢒꢔ ꢇꢀ ꢊꢌ ꢗꢇꢁ ꢇꢉ ꢖꢁ ꢊꢈ ꢊꢒ ꢔꢑ ꢓ ꢊꢀ ꢏ ꢑꢏꢕ ꢀꢘ ꢌ ꢓꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
operating characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
TLV277xC
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP MAX
25°C
5
10.5
V
R
= 2 V,
C
= 100 pF,
L
O(PP)
= 10 kΩ
SR
Slew rate at unity gain
V/µs
Full
range
4.7
6
L
f = 1 kHz
25°C
25°C
17
12
nV/√Hz
V
n
Equivalent input noise voltage
f = 10 kHz
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
f = 100 Hz
0.33
0.86
0.6
V
I
Peak-to-peak equivalent input noise voltage
Equivalent input noise current
25°C
25°C
µV
N(PP)
fA/√Hz
n
A
= 1
0.005%
V
R
= 600 Ω,
L
A
V
= 10
0.016%
0.095%
THD + N Total harmonic distortion plus noise
Gain-bandwidth product
25°C
f = 1 kHz
A
= 100
R = 600 Ω,
L
V
f = 10 kHz,
C
25°C
25°C
25°C
5.1
0.335
0.6
MHz
= 100 pF
L
A
= −1,
V
0.1%
Step = 2 V,
t
s
Settling time
µs
R
C
= 600 Ω,
= 100 pF
L
L
0.01%
φ
m
Phase margin at unity gain
Gain margin
25°C
25°C
46°
12
R
= 600 Ω,
C = 100 pF
L
L
dB
TLV2770
TLV2773
TLV2775
TLV2770
TLV2773
TLV2775
1.2
2.4
1.9
335
444
345
A
= 5,
R = Open,
L
V
t
t
Amplifier turnon time
Amplifier turnoff time
25°C
25°C
µs
(ON)
Measured to 50% point
A
= 5
R = Open,
L
V
ns
(OFF)
Measured to 50% point
†
Full range is 0°C to 70°C.
9
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SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, V
= 2.7 V (unless otherwise noted)
DD
TLV277xI
TLV277xAI
MIN TYP MAX
†
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP MAX
25°C
Full range
25°C
0.48
0.53
0.8
2.5
2.7
2.7
2.9
0.48
0.53
0.8
1.6
1.9
2.1
2.2
V
= 0,
V
= 0,
IC
= 50 Ω
O
TLV2770/1/2
TLV2773/4/5
R
V
Input offset
voltage
S
V
IO
mV
=
1.35 V,
DD
No load
Full range
0.86
0.86
Temperature coefficient of input
offset voltage
25°C to
125°C
α
2
2
µV/°C
pA
VIO
25°C
Full range
25°C
1
2
60
125
60
1
2
60
125
60
V
= 0,
V
= 0,
IC
O
I
IO
Input offset current
Input bias current
R
= 50 Ω
S
2
2
I
IB
pA
Full range
25°C
6
350
6
350
2.6
2.5
2.4
2.1
0.1
0.2
0.21
0.6
2.6
2.5
2.4
2.1
0.1
0.2
0.21
0.6
I
I
= −0.675 mA
= −2.2 mA
OH
Full range
25°C
V
High-level output voltage
Low-level output voltage
V
OH
OH
Full range
25°C
V
I
= 1.35 V,
= 0.675 mA
IC
OL
Full range
25°C
V
A
V
OL
V
= 1.35 V,
= 2.2 mA
IC
I
Full range
OL
V
R
= 1.35 V,
= 10 kΩ,
= 0.6 V to 2.1 V
25°C
20
13
380
20
13
380
IC
Large-signal differential voltage
amplification
V/mV
L
VD
Full range
V
O
12
10
12
10
r
Differential input resistance
25°C
Ω
i(d)
Common-mode input
capacitance
c
z
f = 10 kHz,
25°C
25°C
8
8
pF
i(c)
o
f = 100 kHz,
Closed-loop output impedance
25
25
Ω
A
V
= 10
V
V
R
= 0 to 1.5 V,
25°C
Full range
25°C
60
60
70
70
84
82
89
60
60
70
70
84
82
89
IC
O
S
= V
DD
= 50 Ω
/2,
CMRR
Common-mode rejection ratio
Supply voltage rejection ratio
dB
V
V
= 2.7 V to 5 V,
DD
IC
= V
/2,
k
dB
DD
SVR
(∆V
/∆V )
DD
IO
Full range
84
1
84
1
No load
25°C
Full range
25°C
2
2
2
2
V
= V /2,
DD
O
I
I
Supply current (per channel)
mA
DD
No load
0.8
1.3
1.5
2
0.8
1.3
1.5
2
Supply current in shutdown (per
channel)
µA
DD(SHDN)
Full range
†
Full range is − 40°C to 125°C.
10
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SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, V
(continued)
= 2.7 V (unless otherwise noted)
DD
TLV277xI
TYP MAX
TLV277xAI
MIN TYP MAX
TEST
CONDITIONS
†
PARAMETER
T
A
UNIT
MIN
TLV2770
TLV2773
TLV2775
TLV2770
TLV2773
TLV2775
1.47
1.43
1.40
1.27
1.21
1.20
1.47
1.43
1.4
V
V
Turnon voltage level
A
= 5
= 5
25°C
25°C
V
(ON)
V
1.27
1.21
1.2
Turnoff voltage level
A
V
V
(OFF)
†
Full range is − 40°C to 125°C.
operating characteristics at specified free-air temperature, V
= 2.7 V (unless otherwise noted)
DD
TLV277xI
TYP MAX
TLV277xAI
TYP MAX
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
MIN
25°C
5
9
5
9
V
R
= 0.8 V,
C
= 100 pF,
L
O(PP)
= 10 kΩ
SR
Slew rate at unity gain
V/µs
Full
range
4.7
6
4.7
6
L
f = 1 kHz
25°C
25°C
21
17
21
17
Equivalent input noise
voltage
nV/√Hz
V
n
f = 10 kHz
Peak-to-peak
equivalent input noise
voltage
f = 0.1 Hz to 1 Hz
25°C
25°C
0.33
0.86
0.33
0.86
µV
µV
V
I
N(PP)
f = 0.1 Hz to 10 Hz
f = 100 Hz
Equivalent input noise
current
25°C
0.6
0.6
fA/√Hz
n
A
= 1
0.0085%
0.025%
0.12%
0.0085%
0.025%
0.12%
V
Total harmonic
distortion plus noise
R = 600 Ω,
L
A
V
= 10
THD + N
25°C
f = 1 kHz
A
= 100
R = 600 Ω,
L
V
Gain-bandwidth
product
f = 10 kHz,
25°C
25°C
4.8
4.8
MHz
C
= 100 pF
L
A
V
= −1,
0.1%
0.186
0.186
Step = 0.85 V to
1.85 V,
t
s
Settling time
µs
R
C
= 600 Ω,
= 100 pF
L
L
0.01%
25°C
3.92
3.92
Phase margin at unity
gain
φ
m
25°C
25°C
46°
46°
R
= 600 Ω,
C = 100 pF
L
L
Gain margin
12
12
dB
†
Full range is −40°C to 125°C.
11
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SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
TLV277xI
TLV277xAI
MIN TYP MAX
TEST
CONDITIONS
†
PARAMETER
T
A
UNIT
MIN
TYP MAX
25°C
Full range
25°C
0.5
0.6
2.5
2.7
2.5
2.7
0.5
0.6
1.6
1.9
2.1
2.2
V
V
= 0, No load
= 0,
IC
TLV2770/1/2
TLV2773/4/5
O
V
IO
Input offset voltage
mV
R
= 50 Ω,
= 2.5 V
0.7
0.7
S
V
DD
Full range
0.78
0.78
Temperature coefficient of input
offset voltage
25°C to
125°C
α
2
2
µV/°C
pA
VIO
V
V
= 0,
= 0,
IC
25°C
Full range
25°C
1
2
60
125
60
1
2
60
125
60
O
I
IO
Input offset current
Input bias current
R
= 50 Ω,
= 2.5 V
S
V
DD
2
2
I
IB
pA
Full range
25°C
6
350
6
350
4.9
4.8
4.7
4.4
0.1
0.2
0.21
0.6
4.9
4.8
4.7
4.4
0.1
0.2
0.21
0.6
I
I
= −1.3 mA
= −4.2 mA
OH
Full range
25°C
V
High-level output voltage
Low-level output voltage
V
OH
OH
Full range
25°C
V
I
= 2.5 V,
= 1.3 mA
IC
OL
Full range
25°C
V
A
V
OL
V
= 2.5 V,
= 4.2 mA
IC
I
Full range
OL
V
R
= 2.5 V,
= 10 kΩ,
= 1 V to 4 V
25°C
20
13
450
20
13
450
IC
Large-signal differential voltage
amplification
V/mV
L
VD
Full range
V
O
12
10
12
10
r
Differential input resistance
25°C
25°C
Ω
i(d)
c
Common-mode input capacitance f = 10 kHz
8
8
pF
i(c)
o
f = 100 kHz,
z
Closed-loop output impedance
25°C
20
20
Ω
A
= 10
V
V
V
R
= 0 to 3.7 V,
25°C
Full range
25°C
60
60
70
70
96
93
89
70
70
70
70
96
93
89
IC
O
S
= V
DD
= 50 Ω
/2,
CMRR
Common-mode rejection ratio
Supply voltage rejection ratio
dB
V
V
= 2.7 V to 5 V,
DD
IC
= V
/2,
k
dB
mA
µA
DD
SVR
(∆V
DD
/∆V )
IO
Full range
84
1
84
1
No load
25°C
Full range
25°C
2
2
2
2
V
O
= V /2,
DD
I
I
Supply current (per channel)
DD
No load
0.8
1.3
1.5
2
0.8
1.3
1.5
2
Supply current shutdown (per
channel)
DD(SHDN)
Full range
†
Full range is − 40°C to 125°C.
12
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SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, V
(continued)
= 5 V (unless otherwise noted)
DD
TLV277xI
TLV277xAI
MIN TYP MAX
TEST
CONDITIONS
†
PARAMETER
T
UNIT
A
MIN
TYP MAX
2.59
TLV2770
TLV2773
TLV2775
TLV2770
TLV2773
TLV2775
2.59
2.47
2.48
2.41
2.32
2.29
2.47
V
V
Turnon voltage level
A
= 5
= 5
25°C
25°C
V
(ON)
V
2.48
2.41
2.32
Turnoff voltage level
A
V
V
(OFF)
2.29
†
Full range is − 40°C to 125°C.
operating characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
TLV277xI
TYP MAX
TLV277xAI
TYP MAX
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
MIN
25°C
5
10.5
5
10.5
V
R
= 1.5 V,
C
= 100 pF,
L
O(PP)
= 10 kΩ
SR
Slew rate at unity gain
V/µs
Full
range
4.7
6
4.7
6
L
f = 1 kHz
25°C
25°C
17
12
17
12
Equivalent input noise
voltage
nV/√Hz
V
n
f = 10 kHz
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
25°C
25°C
0.33
0.86
0.33
0.86
µV
µV
V
I
N(PP)
f = 0.1 Hz to 10 Hz
f = 100 Hz
Equivalent input noise
current
25°C
0.6
0.6
fA/√Hz
n
A
= 1
0.005%
0.016%
0.095%
0.005%
0.016%
0.095%
V
Total harmonic
distortion plus noise
R = 600 Ω,
L
A
V
= 10
THD + N
25°C
f = 1 kHz
A
= 100
R = 600 Ω,
L
V
Gain-bandwidth
product
f = 10 kHz,
25°C
25°C
5.1
5.1
MHz
C
= 100 pF
L
A
V
= −1,
0.1%
0.134
0.134
Step = 1.5 V to
3.5 V,
t
s
Settling time
µs
R
C
= 600 Ω,
= 100 pF
L
L
0.01%
25°C
1.97
1.97
Phase margin at unity
gain
φ
25°C
25°C
46°
46°
m
R
= 600 Ω,
C = 100 pF
L
L
Gain margin
12
1.2
12
1.2
dB
TLV2770
Amplifier
TLV2773
turnon
A
= 5,
= Open,
V
t
25°C
25°C
2.4
2.4
µs
R
(ON)
L
Measured to 50% point
time
TLV2775
1.9
1.9
TLV2770
Amplifier
TLV2773
turnoff
335
444
345
335
444
345
A
= 5,
= Open,
V
t
ns
R
(OFF)
L
Measured to 50% point
time
TLV2775
†
Full range is −40°C to 125°C.
13
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SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, V
= 2.7 V (unless otherwise noted)
DD
TLV2772Q
TLV2772M
TLV2772AQ
TLV2772AM
†
PARAMETER
TEST CONDITIONS
T
UNIT
mV
A
MIN TYP MAX
MIN
TYP MAX
25°C
0.44
0.47
2.5
2.7
0.44
0.47
1.6
1.9
V
IO
Input offset voltage
Full range
Temperature
coefficient of input
offset voltage
25°C
to
125°C
α
VIO
2
2
µV/°C
V
V
R
=
= 0,
= 50 Ω
1.35 V,
DD
IC
S
V
O
= 0,
25°C
Full range
25°C
1
2
2
6
60
125
60
1
2
2
6
60
125
60
I
I
Input offset current
Input bias current
pA
pA
IO
IB
Full range
350
350
0
to
1.4
−0.3
to
1.7
0
to
1.4
−0.3
to
1.7
25°C
Common-mode
input voltage range
V
CMRR > 60 dB,
R
= 50 Ω
V
V
ICR
S
0
to
1.4
−0.3
to
1.7
0
to
1.4
−0.3
to
1.7
Full range
25°C
Full range
25°C
2.6
2.4
2.6
2.4
I
I
= −0.675 mA
= −2.2 mA
= 1.35 V,
OH
2.45
2.1
2.45
2.1
High-level output
voltage
V
V
OH
OH
Full range
25°C
0.1
0.1
V
V
I
I
= 0.675 mA
= 2.2 mA
IC
OL
Full range
25°C
0.2
0.6
0.2
0.6
Low-level output
voltage
V
OL
0.21
0.21
= 1.35 V,
IC
OL
Full range
Large-signal
differential voltage
amplification
25°C
20
13
380
20
13
380
‡
V
IC
V
O
= 1.35 V,
= 0.6 V to 2.1 V
R
= 10 kΩ,
L
A
VD
V/mV
Full range
Differential input
resistance
12
10
12
10
Ω
pF
Ω
r
25°C
25°C
25°C
i(d)
Common-mode
input capacitance
c
z
f = 10 kHz,
8
8
i(c)
o
Closed-loop
output impedance
f = 100 kHz,
A
V
= 10
25
25
25°C
60
60
84
82
60
60
84
82
Common-mode
rejection ratio
V
R
= V (min),
ICR
V
= 1.5 V,
IC
S
O
CMRR
dB
dB
= 50 Ω
Full range
Supply voltage
rejection ratio
25°C
70
70
89
70
70
89
V
= 2.7 V to 5 V,
V
IC
= V /2,
DD
DD
k
SVR
No load
Full range
84
1
84
1
(∆V
/∆V )
DD
IO
25°C
2
2
2
2
Supply current
(per channel)
I
V
O
= 1.5 V,
No load
mA
DD
Full range
†
‡
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 1.35 V
14
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ꢈꢇ ꢉꢊ ꢁꢋ ꢌ ꢈ ꢃ ꢍꢄ ꢎꢂ ꢏꢊ ꢐꢏ ꢎꢑꢁ ꢒꢓꢎꢔꢇꢀ ꢒ ꢔꢇꢊ ꢁ ꢎꢀꢌ ꢎꢔꢇꢊ ꢁ ꢌ ꢕꢀ ꢖ ꢕꢀ
ꢌ ꢖꢒꢔ ꢇꢀ ꢊꢌ ꢗꢇꢁ ꢇꢉ ꢖꢁ ꢊꢈ ꢊꢒ ꢔꢑ ꢓ ꢊꢀ ꢏ ꢑꢏꢕ ꢀꢘ ꢌ ꢓꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
operating characteristics at specified free-air temperature, V
= 2.7 V (unless otherwise noted)
DD
TLV2772Q
TLV2772M
TLV2772AQ
TLV2772AM
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP MAX
MIN
TYP MAX
25°C
5
9
5
9
V
R
= 0.8 V,
C
= 100 pF,
L
O(PP)
= 10 kΩ
SR
Slew rate at unity gain
V/µs
Full
range
4.7
6
4.7
6
L
f = 1 kHz
25°C
25°C
21
17
21
17
Equivalent input
noise voltage
nV/√Hz
V
n
f = 10 kHz
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
25°C
25°C
0.33
0.86
0.33
0.86
µV
µV
V
I
N(PP)
f = 0.1 Hz to 10 Hz
f = 100 Hz
Equivalent input
noise current
25°C
0.6
0.6
fA/√Hz
n
A
= 1
0.0085%
0.025%
0.12%
0.0085%
0.025%
0.12%
V
Total harmonic
distortion plus noise
R = 600 Ω,
L
A
V
= 10
THD + N
25°C
f = 1 kHz
A
= 100
R = 600 Ω,
L
V
Gain-bandwidth
product
f = 10 kHz,
25°C
25°C
4.8
4.8
MHz
C
= 100 pF
L
A
V
= −1,
0.1%
0.186
0.186
Step = 0.85 V to
1.85 V,
t
s
Settling time
µs
R
C
= 600 Ω,
= 100 pF
L
L
0.01%
25°C
3.92
3.92
Phase margin at
unity gain
φ
m
25°C
25°C
46°
46°
R
= 600 Ω,
C = 100 pF
L
L
Gain margin
12
12
dB
†
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
15
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SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
TLV2772Q
TLV2772M
TLV2772AQ
TLV2772AM
†
PARAMETER
TEST CONDITIONS
T
UNIT
mV
A
MIN TYP MAX
MIN
TYP MAX
25°C
0.36
0.4
2.5
2.7
0.36
0.4
1.6
1.9
V
IO
Input offset voltage
Full range
Temperature
coefficient of input
offset voltage
25°C
to
125°C
α
VIO
2
2
µV/°C
V
V
=
2.5 V,
V
R
= 0,
= 50 Ω
DD
= 0,
O
S
IC
25°C
Full range
25°C
1
2
2
6
60
125
60
1
2
2
6
60
125
60
I
I
Input offset current
Input bias current
pA
pA
IO
IB
Full range
350
350
0
to
3.7
−0.3
to
3.8
0
to
3.7
−0.3
to
3.8
25°C
Common-mode
input voltage range
V
CMRR > 60 dB,
R
= 50 Ω
S
V
V
ICR
0
to
3.7
−0.3
to
3.8
0
to
3.7
−0.3
to
3.8
Full range
25°C
Full range
25°C
4.9
4.7
4.9
4.7
I
I
= −1.3 mA
= −4.2 mA
= 2.5 V,
OH
4.8
4.4
4.8
4.4
High-level output
voltage
V
V
OH
OH
Full range
25°C
0.1
0.1
V
V
I
I
= 1.3 mA
= 4.2 mA
IC
OL
Full range
25°C
0.2
0.6
0.2
0.6
Low-level output
voltage
V
OL
0.21
0.21
= 2.5 V,
IC
OL
Full range
Large-signal
differential voltage
amplification
25°C
20
13
450
20
13
450
‡
V
IC
V
O
= 2.5 V,
= 1 V to 4 V
R
= 10 kΩ,
L
A
VD
V/mV
Full range
Differential input
resistance
12
10
12
10
Ω
pF
Ω
r
25°C
25°C
25°C
i(d)
Common-mode
input capacitance
c
z
f = 10 kHz,
8
8
i(c)
o
Closed-loop
output impedance
f = 100 kHz,
A
V
= 10
20
20
25°C
60
60
96
93
60
60
96
93
Common-mode
rejection ratio
V
R
= V (min),
ICR
V
= 3.7 V,
IC
S
O
CMRR
dB
dB
= 50 Ω
Full range
Supply voltage
rejection ratio
25°C
70
70
89
70
70
89
V
= 2.7 V to 5 V,
V
IC
= V /2,
DD
DD
k
SVR
No load
Full range
84
1
84
1
(∆V
/∆V )
DD
IO
25°C
2
2
2
2
Supply current
(per channel)
I
V
O
= 1.5 V,
No load
mA
DD
Full range
†
‡
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 2.5 V
16
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ꢌ ꢖꢒꢔ ꢇꢀ ꢊꢌ ꢗꢇꢁ ꢇꢉ ꢖꢁ ꢊꢈ ꢊꢒ ꢔꢑ ꢓ ꢊꢀ ꢏ ꢑꢏꢕ ꢀꢘ ꢌ ꢓꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
operating characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
TLV2772Q
TLV2772M
TLV2772AQ
TLV2772AM
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP MAX
MIN
TYP MAX
25°C
5
10.5
5
10.5
V
R
= 1.5 V,
C
= 100 pF,
L
O(PP)
= 10 kΩ
SR
Slew rate at unity gain
V/µs
Full
range
4.7
6
4.7
6
L
f = 1 kHz
25°C
25°C
17
12
17
12
Equivalent input
noise voltage
nV/√Hz
V
n
f = 10 kHz
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
25°C
25°C
0.33
0.86
0.33
0.86
µV
µV
V
I
N(PP)
f = 0.1 Hz to 10 Hz
f = 100 Hz
Equivalent input
noise current
25°C
0.6
0.6
fA/√Hz
n
A
= 1
0.005%
0.016%
0.095%
0.005%
0.016%
0.095%
V
Total harmonic
distortion plus noise
R = 600 Ω,
L
A
V
= 10
THD + N
25°C
f = 1 kHz
A
= 100
R = 600 Ω,
L
V
Gain-bandwidth
product
f = 10 kHz,
25°C
25°C
5.1
5.1
MHz
C
= 100 pF
L
A
V
= −1,
0.1%
0.134
0.134
Step = 1.5 V to
3.5 V,
t
s
Settling time
µs
R
C
= 600 Ω,
= 100 pF
L
L
0.01%
25°C
1.97
1.97
Phase margin at unity
gain
φ
m
25°C
25°C
46°
46°
R
= 600 Ω,
C = 100 pF
L
L
Gain margin
12
12
dB
†
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
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ꢌꢖ ꢒ ꢔꢇꢀ ꢊ ꢌꢗ ꢇ ꢁ ꢇꢉ ꢖꢁ ꢊ ꢈꢊ ꢒ ꢔꢑ ꢓ ꢊ ꢀꢏ ꢑ ꢏꢕꢀ ꢘꢌ ꢓ ꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Distribution
vs Common-mode input voltage
Distribution
1,2
3,4
5,6
V
IO
Input offset voltage
I
/I
Input bias and input offset currents
High-level output voltage
vs Free-air temperature
vs High-level output current
vs Low-level output current
vs Frequency
7
IB IO
V
V
V
8,9
OH
Low-level output voltage
10,11
12,13
OL
Maximum peak-to-peak output voltage
O(PP)
vs Supply voltage
vs Free-air temperature
14
15
I
Short-circuit output current
Output voltage
OS
V
vs Differential input voltage
16
O
A
VD
Large-signal differential voltage amplification and phase margin vs Frequency
17,18
vs Load resistance
vs Free-air temperature
19
20,21
A
Differential voltage amplification
Output impedance
VD
o
z
vs Frequency
22,23
vs Frequency
vs Free-air temperature
24
25
CMRR
Common-mode rejection ratio
k
Supply-voltage rejection ratio
Supply current (per channel)
vs Frequency
26,27
28
SVR
I
vs Supply voltage
DD
vs Load capacitance
vs Free-air temperature
29
30
SR
Slew rate
V
V
V
V
V
Voltage-follower small-signal pulse response
Voltage-follower large-signal pulse response
Inverting small-signal pulse response
Inverting large-signal pulse response
Equivalent input noise voltage
31,32
33,34
35,36
37,38
39,40
41
O
O
O
O
n
vs Frequency
Noise voltage (referred to input)
Total harmonic distortion plus noise
Gain-bandwidth product
Over a 10-second period
vs Frequency
THD + N
42,43
44
vs Supply voltage
vs Load capacitance
B
1
Unity-gain bandwidth
45
φ
m
Phase margin
Gain margin
vs Load capacitance
vs Load capacitance
46
47
Amplifier with shutdown pulse turnon/off characteristics
Supply current with shutdown pulse turnon/off characteristics
Shutdown supply current
48 − 50
51 − 53
54
vs Free-air temperature
vs Frequency
Shutdown forward/reverse isolation
55, 56
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ꢈꢇ ꢉꢊ ꢁꢋ ꢌ ꢈ ꢃ ꢍꢄ ꢎꢂ ꢏꢊ ꢐꢏ ꢎꢑꢁ ꢒꢓꢎꢔꢇꢀ ꢒ ꢔꢇꢊ ꢁ ꢎꢀꢌ ꢎꢔꢇꢊ ꢁ ꢌ ꢕꢀ ꢖ ꢕꢀ
ꢌ ꢖꢒꢔ ꢇꢀ ꢊꢌ ꢗꢇꢁ ꢇꢉ ꢖꢁ ꢊꢈ ꢊꢒ ꢔꢑ ꢓ ꢊꢀ ꢏ ꢑꢏꢕ ꢀꢘ ꢌ ꢓꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLV2772
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLV2772
INPUT OFFSET VOLTAGE
40
40
V
R
T
A
= 2.7 V
= 10 kΩ
= 25°C
DD
L
V
= 5 V
DD
L
R = 10 kΩ
T = 25°C
A
35
30
35
30
25
20
25
20
15
10
5
15
10
5
0
0
−2.5 −2 −1.5 −1 −0.5
0
0.5
1
1.5
2
2.5
−2.5 −2 −1.5 −1 −0.5
0
0.5
1
1.5
2
2.5
V
IO
− Input Offset Voltage − mV
V
IO
− Input Offset Voltage − mV
Figure 1
Figure 2
INPUT OFFSET VOLTAGE
vs
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
COMMON-MODE INPUT VOLTAGE
2
2
V
T
A
= 2.7 V
DD
= 25°C
V
T
= 5 V
DD
= 25°C
1.5
1
A
1.5
1
0.5
0
0.5
0
−0.5
−1
−0.5
−1
−1.5
−2
−1.5
−2
−1 −0.5
−1 −0.5
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
V
IC
− Common-Mode Input Voltage − V
V
IC
− Common-Mode Input Voltage − V
Figure 3
Figure 4
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ꢈꢇ ꢉꢊ ꢁꢋ ꢌꢈ ꢃ ꢍꢄ ꢎꢂ ꢏꢊ ꢐ ꢏꢎꢑ ꢁꢒ ꢓꢎꢔꢇꢀꢒ ꢔꢇꢊ ꢁ ꢎꢀꢌ ꢎꢔꢇꢊ ꢁ ꢌ ꢕꢀ ꢖꢕꢀ
ꢌꢖ ꢒ ꢔꢇꢀ ꢊ ꢌꢗ ꢇ ꢁ ꢇꢉ ꢖꢁ ꢊ ꢈꢊ ꢒ ꢔꢑ ꢓ ꢊ ꢀꢏ ꢑ ꢏꢕꢀ ꢘꢌ ꢓ ꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLV2772
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLV2772
INPUT OFFSET VOLTAGE
35
30
35
30
V
T
A
= 2.7 V
DD
= 25°C to 125°C
V
= 5 V
DD
T = 25°C to 125°C
A
25
20
15
25
20
15
10
5
10
5
0
0
−6
−3
0
3
6
9
12
−6
−3
0
3
6
9
12
α
VIO
− Temperature Coefficient − µV/°C
α
VIO
− Temperature Coefficient − µV/°C
Figure 5
Figure 6
INPUT BIAS AND OFFSET CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
0.20
0.15
0.10
3
V
V
V
= 5 V
= 0
= 0
= 50 Ω
DD
IC
O
V
= 2.7 V
DD
2.5
R
S
I
IB
2
T
A
= −40°C
1.5
T
A
= 125°C
1
0.05
0
T
= 25°C
A
I
IO
0.5
0
T
= 85°C
A
−75 −50
−25
0
25
50
75
100 125
0
5
10
15
20
25
T
A
− Free-Air Temperature − °C
I
− High-Level Output Current − mA
OH
Figure 7
Figure 8
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ꢈꢇ ꢉꢊ ꢁꢋ ꢌ ꢈ ꢃ ꢍꢄ ꢎꢂ ꢏꢊ ꢐꢏ ꢎꢑꢁ ꢒꢓꢎꢔꢇꢀ ꢒ ꢔꢇꢊ ꢁ ꢎꢀꢌ ꢎꢔꢇꢊ ꢁ ꢌ ꢕꢀ ꢖ ꢕꢀ
ꢌ ꢖꢒꢔ ꢇꢀ ꢊꢌ ꢗꢇꢁ ꢇꢉ ꢖꢁ ꢊꢈ ꢊꢒ ꢔꢑ ꢓ ꢊꢀ ꢏ ꢑꢏꢕ ꢀꢘ ꢌ ꢓꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT CURRENT
5
4.5
4
3
V
T
A
= 5 V
DD
= 25°C
V
DD
= 2.7 V
2.5
T
= 125°C
A
T
A
= −40°C
3.5
3
T
A
= 85°C
T
A
= 25°C
2
2.5
1.5
T
A
= 125°C
2
T
A
= 25°C
1
1.5
T
A
= 85°C
1
T
A
= −40°C
0.5
0
0.5
0
0
5
10 15 20 25 30 35 40 45 50 55
0
5
10
15
20
25
30
I
− High-Level Output Current − mA
OH
I
− Low-Level Output Current − mA
OL
Figure 9
Figure 10
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
3
2.5
2
5
4
V
DD
= 5 V
R = 10 kΩ
L
V
= 5 V
T
= 125°C
DD
1% THD
A
T
A
= 85°C
3
2
1
0
1.5
1
V
= 2.7 V
DD
2% THD
T
= 25°C
A
T
A
= −40°C
0.5
0
0
10
20
30
40
50
100
1000
10000
I
− Low-Level Output Current − mA
OL
f − Frequency − kHz
Figure 12
Figure 11
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ꢈꢇ ꢉꢊ ꢁꢋ ꢌꢈ ꢃ ꢍꢄ ꢎꢂ ꢏꢊ ꢐ ꢏꢎꢑ ꢁꢒ ꢓꢎꢔꢇꢀꢒ ꢔꢇꢊ ꢁ ꢎꢀꢌ ꢎꢔꢇꢊ ꢁ ꢌ ꢕꢀ ꢖꢕꢀ
ꢌꢖ ꢒ ꢔꢇꢀ ꢊ ꢌꢗ ꢇ ꢁ ꢇꢉ ꢖꢁ ꢊ ꢈꢊ ꢒ ꢔꢑ ꢓ ꢊ ꢀꢏ ꢑ ꢏꢕꢀ ꢘꢌ ꢓ ꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
SHORT-CIRCUIT OUTPUT CURRENT
vs
vs
FREQUENCY
SUPPLY VOLTAGE
5
4.5
4
60
THD = 5%
V
V
T
A
= V
DD
DD
= 25°C
/2
/2
O
IC
R
T
A
= 600 Ω
= 25°C
L
= V
45
30
V
ID
= −100 mV
3.5
3
V
DD
= 5 V
15
0
2.5
2
V
DD
= 2.7 V
−15
1.5
1
−30
−45
−60
V
= 100 mV
ID
0.5
0
100
1000
f − Frequency − kHz
10000
2
3
4
5
6
7
V
DD
− Supply Voltage − V
Figure 13
Figure 14
SHORT-CIRCUIT OUTPUT CURRENT
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
60
40
5
4
3
R
T
A
= 600 Ω
= 25°C
L
V
DD
= 5 V
V
ID
= −100 mV
20
V
V
= 5 V
DD
= 2.5 V
V
DD
= 2.7 V
0
O
2
1
0
−20
−40
−60
V
= 100 mV
ID
−75 −50
−25
0
25
50
75 100
125
−1000 −750 −500 −250
0
250 500 750 1000
T
A
− Free-Air Temperature − °C
V
ID
− Differential Input Voltage − µV
Figure 15
Figure 16
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SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION
AND PHASE MARGIN
vs
FREQUENCY
100
300
240
180
120
60
V
= 2.7 V
= 600 Ω
= 600 pF
= 25°C
DD
L
L
R
C
T
80
60
A
A
VD
40
Phase
20
0
0
−20
−40
−60
−90
100
1k
10k
100k
1M
10M
f − Frequency − Hz
Figure 17
LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION
AND PHASE MARGIN
vs
FREQUENCY
100
300
V
R
C
= 5 V
= 600 Ω
= 600 pF
= 25°C
DD
L
L
80
60
240
180
120
60
T
A
A
VD
40
Phase
20
0
0
−20
−40
−60
−90
100
1k
10k
100k
1M
10M
f − Frequency − Hz
Figure 18
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ꢌꢖ ꢒ ꢔꢇꢀ ꢊ ꢌꢗ ꢇ ꢁ ꢇꢉ ꢖꢁ ꢊ ꢈꢊ ꢒ ꢔꢑ ꢓ ꢊ ꢀꢏ ꢑ ꢏꢕꢀ ꢘꢌ ꢓ ꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
DIFFERENTIAL VOLTAGE AMPLIFICATION
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
vs
LOAD RESISTANCE
FREE-AIR TEMPERATURE
250
200
150
100
50
1000
100
10
T
A
= 25°C
R
= 10 kΩ
L
R
= 1 MΩ
= 600 Ω
L
V
DD
= 2.7 V
V
= 5 V
DD
R
L
1
V
V
V
= 2.7 V
= 1.35 V
DD
IC
O
= 0.6 V to 2.1 V
0
0.1
−75 −50
0.1
1
10
100
1000
−25
0
25
50
75 100
125
R
− Load Resistance − kΩ
L
T
A
− Free-Air Temperature − °C
Figure 20
Figure 19
DIFFERENTIAL VOLTAGE AMPLIFICATION
OUTPUT IMPEDANCE
vs
vs
FREE-AIR TEMPERATURE
FREQUENCY
1000
100
10
100
R
= 10 kΩ
V
T
A
= 2.7 V
= 25°C
L
DD
R
= 1 MΩ
L
10
1
A
V
= 100
R
= 600 Ω
L
A
= 10
= 1
V
A
V
1
0.10
0.01
V
V
V
= 5 V
= 2.5 V
= 1 V to 4 V
DD
IC
O
0.1
−75 −50
−25
0
25
50
75 100
125
100
1k
10k
100k
1M
T
A
− Free-Air Temperature − °C
f − Frequency − Hz
Figure 21
Figure 22
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ꢌ ꢖꢒꢔ ꢇꢀ ꢊꢌ ꢗꢇꢁ ꢇꢉ ꢖꢁ ꢊꢈ ꢊꢒ ꢔꢑ ꢓ ꢊꢀ ꢏ ꢑꢏꢕ ꢀꢘ ꢌ ꢓꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
OUTPUT IMPEDANCE
COMMON-MODE REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
100
10
90
80
70
60
50
40
V
T
= 2.5 V
= 25°C
V
= 1.35 V
DD
A
V
= 2.7 V
IC
and 2.5 V
DD
T
A
= 25°C
V
DD
= 5 V
A
v
= 100
1
A
= 10
= 1
v
A
v
0.1
0.01
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
10M
f − Frequency − Hz
f − Frequency − Hz
Figure 23
Figure 24
COMMON-MODE REJECTION RATIO
SUPPLY-VOLTAGE REJECTION RATIO
vs
vs
FREE-AIR TEMPERATURE
FREQUENCY
120
115
120
100
V
T
A
= 2.7 V
= 25°C
DD
k
SVR+
110
105
100
95
k
SVR−
80
60
V
DD
= 2.7 V
40
90
V
DD
= 5 V
20
0
85
80
−40 −20
0
20
40 60
80 100 120 140
10
100
1k
10k
100k
1M
10M
T
A
− Free-Air Temperature − °C
f − Frequency − Hz
Figure 25
Figure 26
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ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢄꢄ ꢅ ꢇ
ꢈꢇ ꢉꢊ ꢁꢋ ꢌꢈ ꢃ ꢍꢄ ꢎꢂ ꢏꢊ ꢐ ꢏꢎꢑ ꢁꢒ ꢓꢎꢔꢇꢀꢒ ꢔꢇꢊ ꢁ ꢎꢀꢌ ꢎꢔꢇꢊ ꢁ ꢌ ꢕꢀ ꢖꢕꢀ
ꢌꢖ ꢒ ꢔꢇꢀ ꢊ ꢌꢗ ꢇ ꢁ ꢇꢉ ꢖꢁ ꢊ ꢈꢊ ꢒ ꢔꢑ ꢓ ꢊ ꢀꢏ ꢑ ꢏꢕꢀ ꢘꢌ ꢓ ꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
SUPPLY VOLTAGE REJECTION RATIO
SUPPLY CURRENT (PER CHANNEL)
vs
vs
FREQUENCY
SUPPLY VOLTAGE
120
100
1.6
1.4
1.2
1
V
T
A
= 5 V
= 25°C
DD
T
= 125°C
= 85°C
A
k
SVR+
T
A
k
T
A
= 25°C
SVR−
80
60
40
T
A
= 0°C
T
A
= −40°C
0.8
0.6
0.4
20
0
0.2
0
10
100
1 k
10 k
100 k
1 M
10 M
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
f − Frequency − Hz
V
DD
− Supply Voltage − V
Figure 27
Figure 28
SLEW RATE
vs
LOAD CAPACITANCE
SLEW RATE
vs
FREE-AIR TEMPERATURE
16
14
14
13
12
11
10
9
V
= 5 V
= −1
= 25°C
DD
SR+
SR−
V
R
C
= 2.7 V
DD
L
L
A
V
A
= 10 kΩ
= 100 pF
= 1
T
A
V
12
10
8
6
4
2
0
8
10
100
1k
10k
100k
−75 −50
−25
0
25
50
75 100
125
C
− Load Capacitance − pF
L
T
A
− Free-Air Temperature − °C
Figure 29
Figure 30
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ꢀ ꢁꢂꢃ ꢄ ꢄ ꢅ ꢆ ꢀꢁꢂ ꢃꢄ ꢄꢅ ꢇ
ꢈꢇ ꢉꢊ ꢁꢋ ꢌ ꢈ ꢃ ꢍꢄ ꢎꢂ ꢏꢊ ꢐꢏ ꢎꢑꢁ ꢒꢓꢎꢔꢇꢀ ꢒ ꢔꢇꢊ ꢁ ꢎꢀꢌ ꢎꢔꢇꢊ ꢁ ꢌ ꢕꢀ ꢖ ꢕꢀ
ꢌ ꢖꢒꢔ ꢇꢀ ꢊꢌ ꢗꢇꢁ ꢇꢉ ꢖꢁ ꢊꢈ ꢊꢒ ꢔꢑ ꢓ ꢊꢀ ꢏ ꢑꢏꢕ ꢀꢘ ꢌ ꢓꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
VOLTAGE-FOLLOWER
SMALL-SIGNAL PULSE RESPONSE
VOLTAGE-FOLLOWER
SMALL-SIGNAL PULSE RESPONSE
100
80
60
40
20
0
100
80
60
40
20
0
V
R
C
= 2.7 V
V
R
C
= 5 V
DD
L
L
DD
L
L
= 600 Ω
= 100 pF
= 1
= 600 Ω
= 100 pF
= 1
AV
AV
T
= 25°C
T
= 25°C
A
A
−20
−20
−40
−60
−40
−60
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
t − Time − µs
t − Time − µs
Figure 31
Figure 32
VOLTAGE-FOLLOWER
LARGE-SIGNAL PULSE RESPONSE
VOLTAGE-FOLLOWER
LARGE-SIGNAL PULSE RESPONSE
3
2.5
2
6
5
4
3
2
1
0
V
R
C
= 2.7 V
V
R
C
= 5 V
DD
L
L
DD
L
L
= 600 Ω
= 100 pF
= 1
= 600 Ω
= 100 pF
= 1
AV
AV
T
= 25°C
T
= 25°C
A
A
1.5
1
0.5
0
−0.5
−1
−1
−2
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
t − Time − µs
t − Time − µs
Figure 33
Figure 34
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ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢄꢄ ꢅ ꢇ
ꢈꢇ ꢉꢊ ꢁꢋ ꢌꢈ ꢃ ꢍꢄ ꢎꢂ ꢏꢊ ꢐ ꢏꢎꢑ ꢁꢒ ꢓꢎꢔꢇꢀꢒ ꢔꢇꢊ ꢁ ꢎꢀꢌ ꢎꢔꢇꢊ ꢁ ꢌ ꢕꢀ ꢖꢕꢀ
ꢌꢖ ꢒ ꢔꢇꢀ ꢊ ꢌꢗ ꢇ ꢁ ꢇꢉ ꢖꢁ ꢊ ꢈꢊ ꢒ ꢔꢑ ꢓ ꢊ ꢀꢏ ꢑ ꢏꢕꢀ ꢘꢌ ꢓ ꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
INVERTING SMALL-SIGNAL
PULSE RESPONSE
INVERTING SMALL-SIGNAL
PULSE RESPONSE
100
80
60
40
20
0
100
80
60
40
20
0
V
R
C
= 2.7 V
DD
L
L
V
R
C
= 5 V
DD
L
L
= 600 Ω
= 100 pF
= −1
= 600 Ω
= 100 pF
= −1
AV
AV
T
= 25°C
A
T
= 25°C
A
−20
−20
−40
−60
−40
−60
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
t − Time − µs
t − Time − µs
Figure 35
Figure 36
INVERTING LARGE-SIGNAL
PULSE RESPONSE
INVERTING LARGE-SIGNAL
PULSE RESPONSE
3
2.5
2
4
3.5
3
1.5
1
2.5
2
0.5
0
1.5
1
V
R
C
= 2.7 V
DD
L
L
V
R
C
= 5 V
DD
L
L
= 600 Ω
= 100 pF
= −1
= 600 Ω
= 100 pF
= −1
−0.5
−1
0.5
1
AV
AV
T
= 25°C
A
T
= 25°C
A
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
t − Time − µs
t − Time − µs
Figure 37
Figure 38
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ꢀ ꢁꢂꢃ ꢄ ꢄ ꢅ ꢆ ꢀꢁꢂ ꢃꢄ ꢄꢅ ꢇ
ꢈꢇ ꢉꢊ ꢁꢋ ꢌ ꢈ ꢃ ꢍꢄ ꢎꢂ ꢏꢊ ꢐꢏ ꢎꢑꢁ ꢒꢓꢎꢔꢇꢀ ꢒ ꢔꢇꢊ ꢁ ꢎꢀꢌ ꢎꢔꢇꢊ ꢁ ꢌ ꢕꢀ ꢖ ꢕꢀ
ꢌ ꢖꢒꢔ ꢇꢀ ꢊꢌ ꢗꢇꢁ ꢇꢉ ꢖꢁ ꢊꢈ ꢊꢒ ꢔꢑ ꢓ ꢊꢀ ꢏ ꢑꢏꢕ ꢀꢘ ꢌ ꢓꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
EQUIVALENT INPUT NOISE VOLTAGE
EQUIVALENT INPUT NOISE VOLTAGE
vs
vs
FREQUENCY
FREQUENCY
160
140
120
100
80
140
120
100
80
V
R
T
A
= 2.7 V
= 20 Ω
= 25°C
DD
S
V
R
S
T
A
= 5 V
= 20 Ω
= 25°C
DD
60
40
20
0
60
40
20
0
10
100
1k
10k
10
100
1k
10k
f − Frequency − Hz
f − Frequency − Hz
Figure 39
Figure 40
NOISE VOLTAGE
OVER A 10 SECOND PERIOD
V
= 5 V
DD
f = 0.1 Hz to 10 Hz
300
200
100
T
A
= 25°C
GND
−100
−200
−300
0
1
2
3
4
5
6
7
8
9
10
t − Time − s
Figure 41
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ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢄꢄ ꢅ ꢇ
ꢈꢇ ꢉꢊ ꢁꢋ ꢌꢈ ꢃ ꢍꢄ ꢎꢂ ꢏꢊ ꢐ ꢏꢎꢑ ꢁꢒ ꢓꢎꢔꢇꢀꢒ ꢔꢇꢊ ꢁ ꢎꢀꢌ ꢎꢔꢇꢊ ꢁ ꢌ ꢕꢀ ꢖꢕꢀ
ꢌꢖ ꢒ ꢔꢇꢀ ꢊ ꢌꢗ ꢇ ꢁ ꢇꢉ ꢖꢁ ꢊ ꢈꢊ ꢒ ꢔꢑ ꢓ ꢊ ꢀꢏ ꢑ ꢏꢕꢀ ꢘꢌ ꢓ ꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
vs
FREQUENCY
FREQUENCY
10
1
10
1
V
R
T
A
= 2.7 V
= 600 Ω
= 25°C
V
R
L
= 5 V
= 600 Ω
T = 25°C
A
DD
L
DD
A
= 100
= 10
v
A = 100
v
0.1
0.1
A
v
A
= 10
= 1
v
A
v
= 1
0.01
0.01
A
v
0.001
0.001
10
100
1k
10k
100k
10
100
1k
10k
100k
f − Frequency − Hz
f − Frequency − Hz
Figure 42
Figure 43
GAIN-BANDWIDTH PRODUCT
UNITY-GAIN BANDWIDTH
vs
LOAD CAPACITANCE
vs
SUPPLY VOLTAGE
5.2
5
5
4
3
2
1
0
R
C
= 600 Ω
= 100 pF
L
L
V
= 5 V
= 600 Ω
= 25°C
DD
L
R
T
f = 10 kHz
T
A
A
= 25°C
4.8
4.6
4.4
4.2
4
R
= 100
= 50
null
R
null
R
= 20
1k
null
R
= 0
null
2
2.5
3
3.5
4
4.5
5
5.5
6
10
100
10k
100k
V
DD
− Supply Voltage − V
C
− Load Capacitance − pF
L
Figure 44
Figure 45
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ꢀ ꢁꢂꢃ ꢄ ꢄ ꢅ ꢆ ꢀꢁꢂ ꢃꢄ ꢄꢅ ꢇ
ꢈꢇ ꢉꢊ ꢁꢋ ꢌ ꢈ ꢃ ꢍꢄ ꢎꢂ ꢏꢊ ꢐꢏ ꢎꢑꢁ ꢒꢓꢎꢔꢇꢀ ꢒ ꢔꢇꢊ ꢁ ꢎꢀꢌ ꢎꢔꢇꢊ ꢁ ꢌ ꢕꢀ ꢖ ꢕꢀ
ꢌ ꢖꢒꢔ ꢇꢀ ꢊꢌ ꢗꢇꢁ ꢇꢉ ꢖꢁ ꢊꢈ ꢊꢒ ꢔꢑ ꢓ ꢊꢀ ꢏ ꢑꢏꢕ ꢀꢘ ꢌ ꢓꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
GAIN MARGIN
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
90
80
70
60
50
40
30
20
10
0
0
V
R
T
A
= 5 V
= 600 Ω
= 25°C
V
= 5 V
DD
L
DD
L
R = 600 Ω
T = 25°C
A
5
10
15
20
R
= 100 Ω
null
R
= 50 Ω
null
R
= 0
null
R
= 20 Ω
null
R
= 100 Ω
null
25
30
R
= 50 Ω
= 20 Ω
null
R
= 0
null
R
null
35
40
10
100
1k
10k
100K
10
100
1k
10k
100K
C
− Load Capacitance − pF
C
− Load Capacitance − pF
L
L
Figure 47
Figure 46
TLV2770
TLV2773
AMPLIFIER WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
AMPLIFIER WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
8
7
6
4
8
7
8
6
SHDN = V
DD
SHDN = V
DD
6
5
2
0
6
5
4
2
V
= 5 V
= 5
= 25°C
DD
SHDN = GND
SHDN = GND
A
V
A
4
3
2
1
0
−2
−4
−6
−8
4
3
2
1
0
V
= 5 V
0
DD
= 5
T
A
V
A
Channel 1 Switched
T
= 25°C
−2
−4
−6
Channel 2 SHDN MODE
Channel 1
V
O
V
O
−10
−12
−8
−1
14
−10
−2.5
−1
15
−4 −2
0
2
4
6
8
10
12
0
2.5
5
7.5
10
12.5
t − Time − µs
t − Time − µs
Figure 48
Figure 49
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ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢄꢄ ꢅ ꢇ
ꢈꢇ ꢉꢊ ꢁꢋ ꢌꢈ ꢃ ꢍꢄ ꢎꢂ ꢏꢊ ꢐ ꢏꢎꢑ ꢁꢒ ꢓꢎꢔꢇꢀꢒ ꢔꢇꢊ ꢁ ꢎꢀꢌ ꢎꢔꢇꢊ ꢁ ꢌ ꢕꢀ ꢖꢕꢀ
ꢌꢖ ꢒ ꢔꢇꢀ ꢊ ꢌꢗ ꢇ ꢁ ꢇꢉ ꢖꢁ ꢊ ꢈꢊ ꢒ ꢔꢑ ꢓ ꢊ ꢀꢏ ꢑ ꢏꢕꢀ ꢘꢌ ꢓ ꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
TLV2775 − CHANNEL 1
TLV2770
AMPLIFIER WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
SUPPLY CURRENT WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
6
8
7
24
21
8
6
SHDN = V
DD
4
2
SHDN = V
DD
6
5
18
15
4
2
0
V
= 5 V
= 5
= 25°C
DD
SHDN = GND
SHDN = GND
A
V
A
4
3
2
12
9
0
−2
−4
−6
−8
T
Channel 1/2 Switched
V
= 5 V
DD
= 5
−2
−4
−6
Channel 3/4 SHDN MODE
A
V
A
T
= 25°C
6
Channel 1
1
3
I
V
O
DD
0
0
−8
−10
−12
−10
−2.5
−1
15
−3
14
0
2.5
5
7.5
10
12.5
−4 −2
0
2
4
6
8
10 12
t − Time − µs
t − Time − µs
Figure 50
Figure 51
TLV2773
TLV2775
SUPPLY CURRENT WITH SHUTDOWN PULSE
SUPPLY CURRENT WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
6
TURNON/OFF CHARACTERISTICS
6
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
SHDN = V
SHDN = V
DD
DD
3
3
0
0
SHDN = GND
SHDN = GND
−3
−3
V
= 5 V
V
= 5 V
DD
= 5
DD
= 5
A
A
V
A
−6
−9
−6
−9
V
A
T
= 25°C
T
= 25°C
Channel 1/2 Switched
Channel 3/4 SHDN MODE
Channel 1 Switched
Channel 2 SHDN MODE
−12
−15
−18
−12
−15
−18
I
I
DD
DD
0
−3
15
−3
15
−5 −2.5
0
2.5
5
7.5
10 12.5
−5 −2.5
0
2.5
5
7.5
10 12.5
t − Time − µs
t − Time − µs
Figure 52
Figure 53
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ꢀ ꢁꢂꢃ ꢄ ꢄ ꢅ ꢆ ꢀꢁꢂ ꢃꢄ ꢄꢅ ꢇ
ꢈꢇ ꢉꢊ ꢁꢋ ꢌ ꢈ ꢃ ꢍꢄ ꢎꢂ ꢏꢊ ꢐꢏ ꢎꢑꢁ ꢒꢓꢎꢔꢇꢀ ꢒ ꢔꢇꢊ ꢁ ꢎꢀꢌ ꢎꢔꢇꢊ ꢁ ꢌ ꢕꢀ ꢖ ꢕꢀ
ꢌ ꢖꢒꢔ ꢇꢀ ꢊꢌ ꢗꢇꢁ ꢇꢉ ꢖꢁ ꢊꢈ ꢊꢒ ꢔꢑ ꢓ ꢊꢀ ꢏ ꢑꢏꢕ ꢀꢘ ꢌ ꢓꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
SHUTDOWN SUPPLY CURRENT
TLV2770
vs
SHUTDOWN FORWARD ISOLATION
FREE-AIR TEMPERATURE
vs
7
6
5
4
3
FREQUENCY
140
A
R
= 5
= OPEN
SHDN = GND
V
L
V
I(PP)
= 2.7 V
120
100
80
V
I(PP)
= 0.1 V
V
DD
5 V
60
40
20
2
SHDN MODE
= 1
V
2.7 V
50
A
V
DD
V
R
C
T
= 2.7 V
DD
L
L
1
0
= 10 kΩ
= 20 pF
= 25°C
0
A
−75 −50
−25
0
25
75 100
125
−20
2
10
3
10
4
10
5
10
10
10
6
T
A
− Free-Air Temperature − °C
f − Frequency − Hz
Figure 54
Figure 55
TLV2770
SHUTDOWN REVERSE ISOLATION
vs
FREQUENCY
140
120
100
80
V
= 2.7 V
I(PP)
V
I(PP)
= 0.1 V
60
40
20
SHDN MODE
= 1
A
V
V
R
C
= 2.7 V
DD
L
L
= 10 kΩ
= 20 pF
= 25°C
0
T
A
−20
2
10
3
4
5
10
10
10
10
10
6
f − Frequency − Hz
Figure 56
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ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢄꢄ ꢅ ꢇ
ꢈꢇ ꢉꢊ ꢁꢋ ꢌꢈ ꢃ ꢍꢄ ꢎꢂ ꢏꢊ ꢐ ꢏꢎꢑ ꢁꢒ ꢓꢎꢔꢇꢀꢒ ꢔꢇꢊ ꢁ ꢎꢀꢌ ꢎꢔꢇꢊ ꢁ ꢌ ꢕꢀ ꢖꢕꢀ
ꢌꢖ ꢒ ꢔꢇꢀ ꢊ ꢌꢗ ꢇ ꢁ ꢇꢉ ꢖꢁ ꢊ ꢈꢊ ꢒ ꢔꢑ ꢓ ꢊ ꢀꢏ ꢑ ꢏꢕꢀ ꢘꢌ ꢓ ꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
PARAMETER MEASUREMENT INFORMATION
R
_
+
null
R
L
C
L
Figure 57
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series (R
) with the output of the amplifier, as
NULL
shown in Figure 58. A minimum value of 20 Ω should work well for most applications.
R
F
R
G
_
R
NULL
Input
Output
LOAD
+
C
Figure 58. Driving a Capacitive Load
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ꢀ ꢁꢂꢃ ꢄ ꢄ ꢅ ꢆ ꢀꢁꢂ ꢃꢄ ꢄꢅ ꢇ
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ꢌ ꢖꢒꢔ ꢇꢀ ꢊꢌ ꢗꢇꢁ ꢇꢉ ꢖꢁ ꢊꢈ ꢊꢒ ꢔꢑ ꢓ ꢊꢀ ꢏ ꢑꢏꢕ ꢀꢘ ꢌ ꢓꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
offset voltage
The output offset voltage, (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times
OO
IO
IB
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
R
F
R
R
I
IB−
F
F
V
+ V
1 ) ǒ Ǔ " I
R
1 ) ǒ Ǔ " I
R
ǒ Ǔ ǒ Ǔ
R
G
OO
IO
IB)
S
IB–
F
R
R
G
G
+
−
+
V
I
V
O
R
S
I
IB+
Figure 59. Output Offset Voltage Model
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 60).
R
R
F
G
1
f
+
–3dB
2pR1C1
−
V
O
V
R
F
+
O
1
V
I
ǒ
Ǔ
+
ǒ
1 )
Ǔ
R1
V
R
1 ) sR1C1
I
G
C1
Figure 60. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
+
_
V
I
1
R1
R2
f
+
–3dB
2pRC
C2
R
F
1
R
=
G
R
F
2 −
)
R
(
Q
G
Figure 61. 2-Pole Low-Pass Sallen-Key Filter
35
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ꢈꢇ ꢉꢊ ꢁꢋ ꢌꢈ ꢃ ꢍꢄ ꢎꢂ ꢏꢊ ꢐ ꢏꢎꢑ ꢁꢒ ꢓꢎꢔꢇꢀꢒ ꢔꢇꢊ ꢁ ꢎꢀꢌ ꢎꢔꢇꢊ ꢁ ꢌ ꢕꢀ ꢖꢕꢀ
ꢌꢖ ꢒ ꢔꢇꢀ ꢊ ꢌꢗ ꢇ ꢁ ꢇꢉ ꢖꢁ ꢊ ꢈꢊ ꢒ ꢔꢑ ꢓ ꢊ ꢀꢏ ꢑ ꢏꢕꢀ ꢘꢌ ꢓ ꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
using the TLV2772 as an accelerometer interface
The schematic, shown in Figure 62, shows the ACH04-08-05 interfaced to the TLV1544 10-bit analog-to-digital
converter (ADC).
The ACH04-08-05 is a shock sensor designed to convert mechanical acceleration into electrical signals. The
sensor contains three piezoelectric sensing elements oriented to simultaneously measure acceleration in three
orthogonal, linear axes (x, y, z). The operating frequency is 0.5 Hz to 5 kHz. The output is buffered with an
internal JFET and has a typical output voltage of 1.80 mV/g for the x and y axis and 1.35 mV/g for the z axis.
Amplification and frequency shaping of the shock sensor output is done by the TLV2772 rail-to-rail operational
amplifier. The TLV2772 is ideal for this application as it offers high input impedance, good slew rate, and
excellent dc precision. The rail-to-rail output swing and high output drive are perfect for driving the analog input
of the TLV1544 ADC.
C2
2.2 nF
1.23 V R3
10 kΩ
R4
100 kΩ
3 V
R2
1 MΩ
1 Axis ACH04−08−05
3 V
R5
1 kΩ
C1
0.22 µF
8
2
3
+
_
1
Output to
TLV1544 (ADC)
1/2
TLV2772
C3
0.22 µF
4
R1
100 kΩ
Signal Conditioning
3 V
R6
2.2 kΩ
1.23 V
Shock Sensor
1.23 V
C
TLV431
R
A
Voltage Reference
Figure 62. Accelerometer Interface Schematic
The sensor signal must be amplified and frequency-shaped to provide a signal the ADC can properly convert
into the digital domain. Figure 62 shows the topology used in this application for one axis of the sensor. This
system is powered from a single 3-V supply. Configuring the TLV431 with a 2.2-kΩ resistor produces a reference
voltage of 1.23 V. This voltage is used to bias the operational amplifier and the internal JFETs in the shock
sensor.
36
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ꢌ ꢖꢒꢔ ꢇꢀ ꢊꢌ ꢗꢇꢁ ꢇꢉ ꢖꢁ ꢊꢈ ꢊꢒ ꢔꢑ ꢓ ꢊꢀ ꢏ ꢑꢏꢕ ꢀꢘ ꢌ ꢓꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
gain calculation
Since the TLV2772 is capable of rail-to-rail output using a 3-V supply, V = 0 (min) to 3 V (max). With no signal
O
from the sensor, nominal V = reference voltage = 1.23 V. Therefore, the maximum negative swing from nominal
O
is 0 V − 1.23 V = −1.23 V and the maximum positive swing is 3 V − 1.23 V = 1.77 V. By modeling the shock sensor
as a low impedance voltage source with output of 2.25 mV/g (max) in the x and y axis and 1.70 mV/g (max) in
the z axis, the gain of the circuit is calculated by equation 1.
Output Swing
Sensor Signal Acceleration
Gain +
(1)
To avoid saturation of the operational amplifier, the gain calculations are based on the maximum negative swing
of −1.23 V and the maximum sensor output of 2.25 mV/g (x and y axis) and 1.70 mV/g (z axis).
* 1.23 V
2.25 mVńg * 50 g
Gain (x, y) +
+ 10.9
(2)
and
–1.23 V
1.70 mVńg –50 g
Gain (z) +
+ 14.5
(3)
By selecting R3 = 10 kΩ and R4 = 100 kΩ, in the x and y channels, a gain of 11 is realized. By selecting
R3 = 7.5 kΩ and R4 = 100 kΩ, in the z channel, a gain of 14.3 is realized. The schematic shows the configuration
for either the x- or y-axis.
bandwidth calculation
To calculate the component values for the frequency shaping characteristics of the signal conditioning circuit,
1 Hz and 500 Hz are selected as the minimum required 3-dB bandwidth.
To minimize the value of the input capacitor (C1) required to set the lower cutoff frequency requires a large value
resistor for R2 is required. A 1-MΩ resistor is used in this example. To set the lower cutoff frequency, the required
capacitor value for C1 is:
1
C1 +
+ 0.159 µF
(4)
2p f
R
2
LOW
Using a value of 0.22 µF, a more common value of capacitor, the lower cutoff frequency is 0.724 Hz.
To minimize the phase shift in the feedback loop caused by the input capacitance of the TLV2772, it is best to
minimize the value of the feedback resistor R4. However, to reduce the required capacitance in the feedback
loop a large value for R4 is required. Therefore, a compromise for the value of R4 must be made. In this circuit,
a value of 100 kΩ has been selected. To set the upper cutoff frequency, the required capacitor value for C2 is:
1
C2 +
+ 3.18 µF
(5)
2p f
R
4
HIGH
Using a 2.2-nF capacitor, the upper cutoff frequency is 724 Hz.
R5 and C3 also cause the signal response to roll off. Therefore, it is beneficial to design this roll-off point to begin
at the upper cutoff frequency. Assuming a value of 1 kΩ for R5, the value for C3 is calculated to be
0.22 µF.
37
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ꢌꢖ ꢒ ꢔꢇꢀ ꢊ ꢌꢗ ꢇ ꢁ ꢇꢉ ꢖꢁ ꢊ ꢈꢊ ꢒ ꢔꢑ ꢓ ꢊ ꢀꢏ ꢑ ꢏꢕꢀ ꢘꢌ ꢓ ꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high performance of the TLV277x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
D
Ground planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D
Proper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D
D
Sockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
Short trace runs/compact part placements—Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at
the input of the amplifier.
D
Surface-mount passive components—Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
38
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ꢌ ꢖꢒꢔ ꢇꢀ ꢊꢌ ꢗꢇꢁ ꢇꢉ ꢖꢁ ꢊꢈ ꢊꢒ ꢔꢑ ꢓ ꢊꢀ ꢏ ꢑꢏꢕ ꢀꢘ ꢌ ꢓꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
general power dissipation considerations
For a given θ , the maximum power dissipation is shown in Figure 63 and is calculated by the following formula:
JA
T
–T
MAX
q
A
P
+
ǒ Ǔ
D
JA
Where:
P
= Maximum power dissipation of TLV277x IC (watts)
= Absolute maximum junction temperature (150°C)
= Free-ambient air temperature (°C)
D
T
MAX
T
A
θ
= θ + θ
JA
JC CA
θ
θ
= Thermal coefficient from junction to case
JC
= Thermal coefficient from case to ambient air (°C/W)
CA
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
2
T
= 150°C
PDIP Package
J
Low-K Test PCB
1.75
θ
= 104°C/W
JA
1.5
1.25
1
MSOP Package
Low-K Test PCB
SOIC Package
Low-K Test PCB
θ
= 260°C/W
JA
θ
= 176°C/W
JA
0.75
0.5
SOT-23 Package
Low-K Test PCB
0.25
0
θ
= 324°C/W
JA
−55−40 −25 −10
5
20 35 50 65 80 95 110 125
T
A
− Free-Air Temperature − °C
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 63. Maximum Power Dissipation vs Free-Air Temperature
39
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ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢄꢄ ꢅ ꢇ
ꢈꢇ ꢉꢊ ꢁꢋ ꢌꢈ ꢃ ꢍꢄ ꢎꢂ ꢏꢊ ꢐ ꢏꢎꢑ ꢁꢒ ꢓꢎꢔꢇꢀꢒ ꢔꢇꢊ ꢁ ꢎꢀꢌ ꢎꢔꢇꢊ ꢁ ꢌ ꢕꢀ ꢖꢕꢀ
ꢌꢖ ꢒ ꢔꢇꢀ ꢊ ꢌꢗ ꢇ ꢁ ꢇꢉ ꢖꢁ ꢊ ꢈꢊ ꢒ ꢔꢑ ꢓ ꢊ ꢀꢏ ꢑ ꢏꢕꢀ ꢘꢌ ꢓ ꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
shutdown function
Three members of the TLV277x family (TLV2770/3/5) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied low, the supply current is reduced to 0.8 µA/channel,
the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the
shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care
needs to be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place
the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to V /2.
DD
Therefore, when operating the device with split supply voltages (e.g. 2.5 V), the shutdown terminal needs to
be pulled to V − (not GND) to disable the operational amplifier.
DD
The amplifier’s output with a shutdown pulse is shown in Figures 48, 49, and 50. The amplifier is powered with
a single 5-V supply and configured as a noninverting configuration with a gain of 5. The amplifier turnon and
turnoff times are measured from the 50% point of the shutdown pulse to the 50% point of the output waveform.
The times for the single, dual, and quad are listed in the data tables. The bump on the rising edge of the TLV2770
output waveform is due to the start-up circuit on the bias generator. For the dual and quad (TLV2773/5), this
bump is attributed to the bias generator’s start-up circuit as well as the crosstalk between the other channel(s),
which are in shutdown.
Figures 55 and 56 show the amplifier’s forward and reverse isolation in shutdown. The operational amplifier is
powered by 1.35-V supplies and configured as a voltage follower (A = 1). The isolation performance is plotted
V
across frequency for both 0.1 V and 2.7 V input signals. During normal operation, the amplifier would not
PP
PP
be able to handle a 2.7-V input signal with a supply voltage of 1.35 V since it exceeds the common-mode
PP
ICR
input voltage range (V
a worst case scenario.
). However, this curve illustrates that the amplifier remains in shutdown even under
40
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ꢀ ꢁꢂꢃ ꢄ ꢄ ꢅ ꢆ ꢀꢁꢂ ꢃꢄ ꢄꢅ ꢇ
ꢈꢇ ꢉꢊ ꢁꢋ ꢌ ꢈ ꢃ ꢍꢄ ꢎꢂ ꢏꢊ ꢐꢏ ꢎꢑꢁ ꢒꢓꢎꢔꢇꢀ ꢒ ꢔꢇꢊ ꢁ ꢎꢀꢌ ꢎꢔꢇꢊ ꢁ ꢌ ꢕꢀ ꢖ ꢕꢀ
ꢌ ꢖꢒꢔ ꢇꢀ ꢊꢌ ꢗꢇꢁ ꢇꢉ ꢖꢁ ꢊꢈ ꢊꢒ ꢔꢑ ꢓ ꢊꢀ ꢏ ꢑꢏꢕ ꢀꢘ ꢌ ꢓꢗ
SLOS209G − JANUARY 1998 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts Release 8, the model generation
software used with Microsim PSpice. The Boyle macromodel (see Note 4) and subcircuit in Figure 64 are
generated using the TLV2772 typical electrical and operating characteristics at T = 25°C. Using this
A
information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most
cases):
D
D
D
D
D
D
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
D
D
D
D
D
D
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
Open-loop voltage amplification
NOTE 4: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
99
dln
3
egnd
+
−
V
DD+
92
9
fb
css
dp
rss
+
91
90
iss
ro2
hlim
−
+
−
+
vb
dlp
rp
2
vlp
vln
−
+
−
10
+
−
vc
IN−
IN+
r2
C2
j1
j2
7
6
53
+
−
1
vlim
11
dc
12
ga
gcm
8
5
C1
ro1
rd1
rd2
−
de
54
4
GND
+
ve
OUT
dc
* TLV2772 operational amplifier macromodel subcircuit
* created using Parts release 8.0 on 12/12/97 at 10:08
* Parts is a MicroSim product.
iss
3
10
0
145.50E−6
hlim
j1
90
11
12
6
vlim 1K
10 jx1
2
*
j2
r2
rd1
rd2
ro1
ro2
rp
rss
vb
vc
ve
vlim
vlp
vln
.model
.model dy
.model jx1
1
9
10 jx2
* connections: noninverting input
100.00E3
5.3052E3
5.3052E3
17.140
17.140
4.5455E3
1.3746E6
dc 0
*
|
inverting input
4
11
12
5
*
| | positive power supply
| | | negative power supply
| | | | output
4
*
8
*
7
99
4
*
| | | | |
1 2 3 4 5
3
.subckt TLV2772
10
9
99
0
*
c1
11
6
12
7
99
53
5
91
90
3
0
99
2.8868E-12
3
53
4
dc .82001
dc .82001
dc 0
c2
10.000E−12
54
7
css
dc
10
5
2.6302E−12
8
dy
91
0
0
dc 47
dc 47
de
dlp
dln
dp
egnd
fb
54
90
92
4
99
7
dy
92
dx
dx
D(Is=800.00E−18)
dx
D(Is=800.00E−18 Rs=1m Cjo=10p)
PJF(Is=2.2500E−12 Beta=244.20E−6
+ Vto=−.99765)
dx
poly(2) (3,0) (4,0) 0 .5 .5
poly(5) vb vc ve vlp vln 0
.model jx2
.ends
PJF(Is=1.7500E−12 Beta=244.20E−6
+ Vto=−1.002350)
15.513E6 −1E3 1E3 16E6 −16E6
11 12 188.50E−6
ga
gcm
6
0
0
6
10 99 9.4472E−9
*$
Figure 64. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
41
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CFP
Drawing
5962-9858801Q2A
5962-9858801QHA
5962-9858801QPA
5962-9858802Q2A
5962-9858802QHA
5962-9858802QPA
TLV2770AID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
U
20
10
8
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
CDIP
LCCC
CFP
JG
FK
U
20
10
8
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
CDIP
SOIC
JG
D
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2770AIDG4
TLV2770AIP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
PDIP
PDIP
SOIC
SOIC
D
P
P
D
D
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLV2770AIPE4
TLV2770CD
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2770CDG4
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2770CDGKG4
TLV2770CDGKRG4
TLV2770CDR
ACTIVE
ACTIVE
ACTIVE
MSOP
MSOP
SOIC
DGK
DGK
D
8
8
8
TBD
TBD
Call TI
Call TI
Call TI
Call TI
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2770CDRG4
TLV2770CP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
PDIP
PDIP
SOIC
SOIC
MSOP
MSOP
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
D
P
8
8
8
8
8
8
8
8
8
8
8
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLV2770CPE4
TLV2770ID
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2770IDG4
TLV2770IDGKR
TLV2770IDGKRG4
TLV2770IDR
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGK
DGK
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2770IDRG4
TLV2770IP
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLV2770IPE4
TLV2771AIDR
TLV2771AIDRG4
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2007
Orderable Device
TLV2771CD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
5
5
5
5
8
8
8
8
5
5
5
5
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2771CDBVR
TLV2771CDBVRG4
TLV2771CDBVT
TLV2771CDBVTG4
TLV2771CDG4
TLV2771CDR
SOT-23
SOT-23
SOT-23
SOT-23
SOIC
DBV
DBV
DBV
DBV
D
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2771CDRG4
TLV2771ID
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2771IDBVR
TLV2771IDBVRG4
TLV2771IDBVT
TLV2771IDBVTG4
TLV2771IDG4
SOT-23
SOT-23
SOT-23
SOT-23
SOIC
DBV
DBV
DBV
DBV
D
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2771IDR
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2771IDRG4
TLV2772AID
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2772AIDG4
TLV2772AIDR
TLV2772AIDRG4
TLV2772AIP
SOIC
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
P
50
50
75
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-1-220C-UNLIM
TLV2772AIPE4
PDIP
P
Pb-Free
(RoHS)
TLV2772AMD
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
TBD
TLV2772AMDG4
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2772AMDR
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
2500
TBD
Call TI
Call TI
TLV2772AMDRG4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2772AMFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE N / A for Pkg Type
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2007
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CFP
Drawing
TLV2772AMJGB
TLV2772AMUB
TLV2772AQD
ACTIVE
ACTIVE
NRND
JG
U
8
10
8
1
1
TBD
TBD
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
SOIC
D
75
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2772AQDG4
ACTIVE
SOIC
D
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2772AQDR
NRND
SOIC
SOIC
D
D
8
8
2500
TBD
Call TI
Call TI
TLV2772AQDRG4
ACTIVE
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2772AQPW
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
8
8
150
TBD
CU NIPDAU Level-1-220C-UNLIM
TLV2772AQPWG4
150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2772AQPWR
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
8
8
2000
TBD
Call TI
Call TI
TLV2772AQPWRG4
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2772CD
TLV2772CDG4
TLV2772CDGK
TLV2772CDGKG4
TLV2772CDGKR
TLV2772CDGKRG4
TLV2772CDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
MSOP
MSOP
MSOP
MSOP
SOIC
SOIC
PDIP
D
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGK
DGK
DGK
DGK
D
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2772CDRG4
TLV2772CP
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLV2772CPE4
TLV2772ID
PDIP
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SOIC
SOIC
MSOP
MSOP
MSOP
MSOP
SOIC
SOIC
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2772IDG4
TLV2772IDGK
TLV2772IDGKG4
TLV2772IDGKR
TLV2772IDGKRG4
TLV2772IDR
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGK
DGK
DGK
DGK
D
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2772IDRG4
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2007
Orderable Device
TLV2772IP
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PDIP
P
8
50
50
75
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-1-220C-UNLIM
TLV2772IPE4
PDIP
P
8
Pb-Free
(RoHS)
TLV2772MD
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
TBD
TLV2772MDG4
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2772MDR
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
2500
TBD
Call TI
Call TI
TLV2772MDRG4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2772MFKB
TLV2772MJGB
TLV2772MUB
TLV2772QD
ACTIVE
ACTIVE
ACTIVE
NRND
LCCC
CDIP
CFP
FK
JG
U
20
8
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
10
8
1
SOIC
D
75
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2772QDG4
ACTIVE
SOIC
D
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2772QDR
NRND
SOIC
SOIC
D
D
8
8
1500
TBD
Call TI
Call TI
TLV2772QDRG4
ACTIVE
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2772QPW
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
8
8
150
TBD
CU NIPDAU Level-1-220C-UNLIM
TLV2772QPWG4
150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2772QPWR
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
8
8
2000
TBD
Call TI
Call TI
TLV2772QPWRG4
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2773AIN
TLV2773AINE4
TLV2773CD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
PDIP
N
N
14
14
14
14
10
10
10
10
14
14
10
10
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SOIC
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2773CDG4
TLV2773CDGS
TLV2773CDGSG4
TLV2773CDGSR
TLV2773CDGSRG4
TLV2773CDR
SOIC
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP
MSOP
MSOP
MSOP
SOIC
DGS
DGS
DGS
DGS
D
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2773CDRG4
TLV2773IDGS
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP
MSOP
DGS
DGS
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2773IDGSG4
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2007
Orderable Device
TLV2773IDGSR
TLV2773IDGSRG4
TLV2773IDR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
MSOP
DGS
10
10
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP
SOIC
SOIC
PDIP
DGS
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2773IDRG4
TLV2773IN
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLV2773INE4
TLV2774AID
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SOIC
SOIC
SOIC
SOIC
PDIP
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2774AIDG4
TLV2774AIDR
TLV2774AIDRG4
TLV2774AIN
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS &
no Sb/Br)
Call TI
Level-1-260C-UNLIM
D
2500 Green (RoHS &
no Sb/Br)
Call TI
Level-1-260C-UNLIM
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
TLV2774AINE4
TLV2774AIPW
TLV2774AIPWG4
TLV2774CD
PDIP
N
25
Pb-Free
(RoHS)
TSSOP
TSSOP
SOIC
SOIC
SOIC
SOIC
PDIP
PW
PW
D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2774CDG4
TLV2774CDR
TLV2774CDRG4
TLV2774CN
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLV2774CNE4
TLV2774CPW
TLV2774CPWG4
TLV2774CPWR
TLV2774CPWRG4
TLV2774ID
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
SOIC
PW
PW
PW
PW
D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS &
no Sb/Br)
Call TI
Level-1-260C-UNLIM
TLV2774IDG4
D
50 Green (RoHS &
no Sb/Br)
Call TI
Level-1-260C-UNLIM
Addendum-Page 5
PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2007
Orderable Device
TLV2774IDR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
14
14
14
14
14
14
14
14
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2500 Green (RoHS &
no Sb/Br)
Call TI
Level-1-260C-UNLIM
TLV2774IDRG4
TLV2774IN
SOIC
PDIP
D
N
2500 Green (RoHS &
no Sb/Br)
Call TI
Level-1-260C-UNLIM
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
TLV2774INE4
TLV2774IPW
PDIP
N
25
Pb-Free
(RoHS)
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
PW
D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2774IPWG4
TLV2774IPWR
TLV2774IPWRG4
TLV2775AIDR
TLV2775AIDRG4
TLV2775AIN
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLV2775AINE4
TLV2775AIPW
TLV2775AIPWG4
TLV2775AIPWR
TLV2775AIPWRG4
TLV2775CD
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
PW
D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2775CDG4
TLV2775CN
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLV2775CNE4
TLV2775ID
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2775IDG4
TLV2775IDR
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2775IDRG4
TLV2775IN
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLV2775INE4
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
Addendum-Page 6
PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2007
Orderable Device
TLV2775IPW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
16
16
16
16
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2775IPWG4
TLV2775IPWR
TLV2775IPWRG4
TSSOP
TSSOP
TSSOP
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 7
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jul-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jul-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
180
180
330
180
180
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330
330
(mm)
12
12
12
12
9
TLV2770CDR
TLV2770IDGKR
TLV2770IDR
D
DGK
D
8
8
TAI
HNT
TAI
6.4
5.3
6.4
6.4
3.15
3.15
6.4
3.15
3.15
6.4
6.4
5.3
6.4
6.4
5.3
6.4
5.3
6.5
5.3
6.5
6.5
6.5
6.5
6.5
7.0
7.0
5.2
3.4
5.2
5.2
3.2
3.2
5.2
3.2
3.2
5.2
5.2
3.4
5.2
5.2
3.4
5.2
3.4
9.0
3.4
9.0
9.0
9.0
9.0
10.3
5.6
5.6
2.1
1.4
2.1
2.1
1.4
1.4
2.1
1.4
1.4
2.1
2.1
1.4
2.1
2.1
1.4
2.1
1.4
2.1
1.4
2.1
2.1
2.1
2.1
2.1
1.6
1.6
8
8
8
8
4
4
8
4
4
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
12
12
12
12
8
Q1
NONE
Q1
8
TLV2771AIDR
TLV2771CDBVR
TLV2771CDBVT
TLV2771CDR
TLV2771IDBVR
TLV2771IDBVT
TLV2771IDR
D
8
TAI
Q1
DBV
DBV
D
5
LEN
LEN
TAI
NONE
NONE
Q1
5
9
8
8
12
9
12
8
DBV
DBV
D
5
LEN
LEN
TAI
NONE
NONE
Q1
5
9
8
8
12
12
12
12
0
12
12
12
12
12
12
12
12
16
12
16
16
16
16
16
12
12
TLV2772AIDR
TLV2772CDGKR
TLV2772CDR
TLV2772CDR
TLV2772IDGKR
TLV2772IDR
D
8
TAI
Q1
DGK
D
8
HNT
TAI
NONE
Q1
8
D
8
FMX
HNT
TAI
Q1
DGK
D
8
12
12
12
16
12
16
16
16
0
NONE
Q1
8
TLV2773CDGSR
TLV2773CDR
TLV2773IDGSR
TLV2773IDR
DGS
D
10
14
10
14
14
14
14
16
16
16
HNT
TAI
NONE
Q1
DGS
D
HNT
TAI
NONE
Q1
TLV2774CDR
TLV2774IDR
D
TAI
Q1
D
TAI
Q1
TLV2774IDR
D
FMX
TAI
Q1
TLV2775IDR
D
16
12
12
Q1
TLV2775IPWR
TLV2775IPWRG4
PW
PW
MLA
MLA
Q1
Q1
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jul-2007
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
TLV2770CDR
TLV2770IDGKR
TLV2770IDR
D
DGK
D
8
8
TAI
HNT
TAI
346.0
358.0
346.0
346.0
182.0
182.0
346.0
182.0
182.0
346.0
346.0
358.0
346.0
342.9
358.0
346.0
358.0
346.0
358.0
346.0
346.0
346.0
342.9
346.0
552.0
552.0
346.0
335.0
346.0
346.0
182.0
182.0
346.0
182.0
182.0
346.0
346.0
335.0
346.0
336.6
335.0
346.0
335.0
346.0
335.0
346.0
346.0
346.0
336.6
346.0
346.0
346.0
29.0
35.0
29.0
29.0
20.0
20.0
29.0
20.0
20.0
29.0
29.0
35.0
29.0
20.64
35.0
29.0
35.0
33.0
35.0
33.0
33.0
33.0
28.58
33.0
36.0
36.0
8
TLV2771AIDR
TLV2771CDBVR
TLV2771CDBVT
TLV2771CDR
TLV2771IDBVR
TLV2771IDBVT
TLV2771IDR
D
8
TAI
DBV
DBV
D
5
LEN
LEN
TAI
5
8
DBV
DBV
D
5
LEN
LEN
TAI
5
8
TLV2772AIDR
TLV2772CDGKR
TLV2772CDR
TLV2772CDR
TLV2772IDGKR
TLV2772IDR
D
8
TAI
DGK
D
8
HNT
TAI
8
D
8
FMX
HNT
TAI
DGK
D
8
8
TLV2773CDGSR
TLV2773CDR
TLV2773IDGSR
TLV2773IDR
DGS
D
10
14
10
14
14
14
14
16
16
16
HNT
TAI
DGS
D
HNT
TAI
TLV2774CDR
TLV2774IDR
D
TAI
D
TAI
TLV2774IDR
D
FMX
TAI
TLV2775IDR
D
TLV2775IPWR
TLV2775IPWRG4
PW
PW
MLA
MLA
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jul-2007
Pack Materials-Page 4
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.063 (1,60)
0.015 (0,38)
0.020 (0,51) MIN
0.200 (5,08) MAX
0.130 (3,30) MIN
Seating Plane
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
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Products
Amplifiers
Data Converters
DSP
Applications
Audio
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/audio
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Digital Control
Military
www.ti.com/automotive
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www.ti.com/digitalcontrol
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interface.ti.com
logic.ti.com
Logic
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power.ti.com
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microcontroller.ti.com
www.ti-rfid.com
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Telephony
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Wireless
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
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