TLV2772-Q1 [TI]
汽车级、双路、5.5V、5.1MHz、高压摆率 (10.5V/μs) 运算放大器;
| 型号： | TLV2772-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车级、双路、5.5V、5.1MHz、高压摆率 (10.5V/μs) 运算放大器 放大器 高压 运算放大器 放大器电路 |
| 文件： | 总41页 (文件大小：828K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢋꢊ ꢌꢍ ꢁꢎ ꢏ ꢋ ꢃ ꢐꢄ ꢆꢂ ꢑꢍ ꢒꢑ ꢆꢓꢁ ꢔꢕꢆꢖꢊꢀ ꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘ ꢗꢀ
ꢏ ꢘꢔꢖ ꢊꢀ ꢍꢏ ꢙꢊꢁ ꢊꢌ ꢘꢁ ꢍꢋ ꢍꢔ ꢖꢓ ꢕ ꢍꢀ ꢑ ꢓꢑꢗ ꢀꢚ ꢏ ꢕꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
D
D
Qualified for Automotive Applications
D
D
D
Rail-to-Rail Output
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
360 µV Input Offset Voltage
Low Distortion Driving 600-Ω
0.005% THD+N
D
D
D
High Slew Rate . . . 10.5 V/µs Typ
High-Gain Bandwidth . . . 5.1 MHz Typ
Supply Voltage Range 2.5 V to 5.5 V
D
D
D
D
D
D
1 mA Supply Current (Per Channel)
17 nV/√Hz Input Noise Voltage
2 pA Input Bias Current
Characterized From T = −55°C to 125°C
A
Available in MSOP and SOT-23 Packages
Micropower Shutdown Mode . . . I
< 1 µA
DD
description
The TLV277x CMOS operational amplifier family combines high slew rate and bandwidth, rail-to-rail output
swing, high output drive, and excellent dc-precision. The device provides 10.5 V/µs of slew rate and 5.1 MHz
of bandwidth while only consuming 1 mA of supply current per channel. This ac-performance is much higher
than current competitive CMOS amplifiers. The rail-to-rail output swing and high output drive make these
devices a good choice for driving the analog input or reference of analog-to-digital converters. These devices
also have low distortion while driving a 600-Ω load for use in telecom systems.
These amplifiers have a 360-µV input offset voltage, a 17 nV/√Hz input noise voltage, and a 2-pA input bias
current for measurement, medical, and industrial applications. The TLV277x family is also specified across an
extended temperature range (−40°C to 125°C), making it useful for automotive systems.
These devices operate from a 2.5-V to 5.5-V single supply voltage and are characterized at 2.7 V and 5 V. The
single-supply operation and low power consumption make these devices a good solution for portable
applications. The following table lists the packages available.
FAMILY PACKAGE TABLE
NUMBER
OF
CHANNELS
PACKAGE TYPES
UNIVERSAL
EVM BOARD
DEVICE
SHUTDOWN
SOIC TSSOP SOT−23
TLV2770
TLV2771
TLV2772
TLV2773
TLV2774
TLV2775
1
1
2
2
4
4
8
8
—
—
8
—
5
Yes
—
See the EVM
Selection Guide
(SLOU060)
8
—
—
—
—
—
14
14
16
—
14
16
Yes
—
Yes
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2005 Texas Instruments Incorporated
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1
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ꢋꢊꢌ ꢍ ꢁꢎ ꢏꢋ ꢃ ꢐ ꢄꢆꢂ ꢑꢍ ꢒ ꢑꢆꢓ ꢁꢔ ꢕꢆꢖꢊꢀꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗꢀ
ꢏꢘ ꢔ ꢖꢊꢀ ꢍ ꢏꢙ ꢊ ꢁ ꢊꢌ ꢘꢁ ꢍ ꢋꢍ ꢔ ꢖꢓ ꢕ ꢍ ꢀꢑ ꢓ ꢑꢗꢀ ꢚꢏ ꢕ ꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
†
A SELECTION OF SINGLE-SUPPLY OPERATIONAL AMPLIFIER PRODUCTS
V
(V)
BW
(MHz)
SLEW RATE
I
(per channel)
(µA)
DD
DD
DEVICE
RAIL-TO-RAIL
(V/µs)
TLV277X
TLV247X
TLV245X
TLV246X
2.5 − 6
2.7 − 6
2.7 − 6
2.7 − 6
5.1
2.8
10.5
1.5
1000
600
23
O
I/O
I/O
I/O
0.22
6.4
0.11
1.6
550
†
All specifications measured at 5 V.
ORDERING INFORMATION
V
max
IO
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
T
A
AT 25°C
PACKAGE
(mV)
§
2.5
1.6
2.5
2.5
1.6
SOIC (D)
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
TLV2770QDRQ1
−40°C to 125°C
−40°C to 125°C
§
SOIC (D)
TLV2770AQDRQ1
SOT−23
TLV2771QDBVRQ1
VBPQ
§
TLV2771QDRQ1
SOIC (D)
§
SOIC (D)
TLV2771AQDRQ1
SOIC (D)
TLV2772QDRQ1
TLV2772QI
TLV2772QI
TLV2772AQ
TLV2772AQ
2.5
1.6
TSSOP (PW)
SOIC (D)
TLV2772QPWRQ1
TLV2772AQDRQ1
TLV2772AQPWRQ1
−40°C to 125°C
−40°C to 125°C
−40°C to 125°C
TSSOP (PW)
SOIC (D)
§
TLV2773QDRQ1
2.5
1.6
§
TLV2773AQDRQ1
SOIC (D)
§
TLV2774QDRQ1
SOIC (D)
2.7
2.1
2.7
2.1
§
TLV2774QPWRQ1
TSSOP (PW)
SOIC (D)
§
TLV2774AQDRQ1
§
§
TSSOP (PW)
SOIC (D)
TLV2774AQPWRQ1
§
TLV2775QDRQ1
§
TLV2775QPWRQ1
TSSOP (PW)
SOIC (D)
−40°C to 125°C
§
TLV2775AQDRQ1
TSSOP (PW)
TLV2775AQPWRQ1
‡
§
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
at www.ti.com/sc/package.
Product Preview
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢋꢊ ꢌꢍ ꢁꢎ ꢏ ꢋ ꢃ ꢐꢄ ꢆꢂ ꢑꢍ ꢒꢑ ꢆꢓꢁ ꢔꢕꢆꢖꢊꢀ ꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗ ꢀ
ꢏ ꢘꢔꢖ ꢊꢀ ꢍꢏ ꢙꢊꢁ ꢊꢌ ꢘꢁ ꢍꢋ ꢍꢔ ꢖꢓ ꢕ ꢍꢀ ꢑ ꢓꢑꢗ ꢀꢚ ꢏ ꢕꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
TLV277x PACKAGE PINOUTS
†
†
TLV2770
TLV2771
TLV2771
DBV PACKAGE
(TOP VIEW)
D PACKAGE
(TOP VIEW)
D PACKAGE
(TOP VIEW)
1
2
3
5
V
DD
OUT
GND
NC
IN−
SHDN
NC
IN−
NC
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
V
DD
DD
IN+
OUT
NC
IN+
OUT
NC
GND
GND
4
IN−
IN+
†
†
TLV2774
TLV2773
D OR PW PACKAGE
(TOP VIEW)
D PACKAGE
(TOP VIEW)
TLV2772
D OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
1OUT
1IN−
1IN+
GND
NC
V
1OUT
1IN−
1IN+
1
2
3
4
5
6
7
14
13
12
11
10
9
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
DD
2OUT
2IN−
2IN+
NC
1OUT
1IN−
1IN+
GND
V
1
2
3
4
8
7
6
5
DD
2OUT
2IN−
2IN+
V
DD
2IN+
2IN−
1SHDN
NC
2SHDN
NC
8
8
2OUT
†
TLV2775
D OR PW PACKAGE
(TOP VIEW)
1OUT
1IN−
1IN+
4OUT
4IN−
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
4IN+
V
GND
DD
2IN+
2IN−
3IN+
3IN−
2OUT
3OUT
3/4SHDN
1/2SHDN
NC − No internal connection
†
This device is in the Product Preview stage of development. Contact your local Texas Instruments sales office for availability.
3
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ꢏꢘ ꢔ ꢖꢊꢀ ꢍ ꢏꢙ ꢊ ꢁ ꢊꢌ ꢘꢁ ꢍ ꢋꢍ ꢔ ꢖꢓ ꢕ ꢍ ꢀꢑ ꢓ ꢑꢗꢀ ꢚꢏ ꢕ ꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V (any input, see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V
V
ID
DD
DD
I
Input current, I (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 mA
I
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
O
Total current into V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
DD+
Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Duration of short-circuit current (at or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T : Q suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to GND.
2. Differential voltages are at the noninverting input with respect to the inverting input. Excessive current flows when input is brought
below GND − 0.3 V.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
ESD RATING TABLE
Human Body Model
Charged-Device Model
Machine Model
2 (H1C)
1 (C5)
kV
V
(4)
ESD rating
150 (M2)
NOTE 4: ESD protection level per AEC Q100 Classification TLV2771QDBVRQ1
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T
= 85°C
T = 125°C
A
POWER RATING
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
POWER RATING
A
D
725 mW
5.8 mW/°C
3.5 mW/°C
5.6 mW/°C
464 mW
377 mW
145 mW
DBV
PW
437 mW
280 mW
227 mW
87 mW
700 mW
448 mW
364 mW
140 mW
recommended operating conditions
Q SUFFIX
UNIT
MIN
2.5
MAX
Supply voltage, V
DD
6
V
V
Input voltage range, V
GND
GND
−40
V
V
−1.3
I
DD+
Common-mode input voltage, V
IC
−1.3
V
DD+
Operating free-air temperature, T
125
°C
A
4
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ꢏ ꢘꢔꢖ ꢊꢀ ꢍꢏ ꢙꢊꢁ ꢊꢌ ꢘꢁ ꢍꢋ ꢍꢔ ꢖꢓ ꢕ ꢍꢀ ꢑ ꢓꢑꢗ ꢀꢚ ꢏ ꢕꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
electrical characteristics at specified free-air temperature, V
= 2.7 V (unless otherwise noted)
DD
TLV2771-Q1
†
PARAMETER
TEST CONDITIONS
T
UNIT
mV
A
MIN
TYP MAX
25°C
0.48
0.53
2.5
2.7
V
V
= 0, V = 0, R = 50 Ω
IC
O
S
V
IO
Input offset voltage
=
1.35 V, No load
Full range
DD
Temperature coefficient of input
offset voltage
25°C to
125°C
α
2
µV/°C
pA
VIO
25°C
Full range
25°C
1
2
60
125
60
I
IO
Input offset current
Input bias current
V
= 0, V = 0, R = 50 Ω
IC
O
S
2
I
IB
pA
Full range
25°C
6
350
2.6
2.5
2.4
2.1
0.1
0.2
0.21
0.6
380
I
I
= −0.675 mA
= −2.2 mA
OH
Full range
25°C
V
High-level output voltage
Low-level output voltage
V
OH
OL
OH
Full range
25°C
V
V
= 1.35 V, I
= 0.675 mA
IC
OL
OL
Full range
25°C
V
V
= 1.35 V, I
= 2.2 mA
IC
Full range
25°C
}
20
13
Large-signal differential voltage
amplification
V
IC
V
O
= 1.35 V, R = 10 kΩ ,
= 0.6 V to 2.1 V
L
A
VD
V/mV
Full range
25°C
12
10
r
Differential input resistance
Ω
pF
Ω
i(d)
c
z
Common-mode input capacitance
Closed-loop output impedance
f = 10 kHz
f = 100 kHz, A = 10
25°C
8
25
84
82
89
84
1
i(c)
o
25°C
V
25°C
60
60
70
70
V
R
= 0 to 1.5 V, V = V
= 50 Ω
/2,
DD
IC
O
CMRR
Common-mode rejection ratio
Supply voltage rejection ratio
dB
dB
Full range
25°C
S
V
= 2.7 V to 5 V, V = V /2,
IC DD
DD
k
SVR
(∆V
DD
/∆V
IO
)
No load
Full range
25°C
2
2
I
Supply current (per channel)
V
O
= V
DD
/2, No load
mA
DD
Full range
†
‡
Full range is − 40°C to 125°C for Q level part.
Referenced to 1.35 V
5
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ꢗ
ꢀ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
operating characteristics at specified free-air temperature, V
= 2.7 V (unless otherwise noted)
DD
TLV2771-Q1
†
PARAMETER
TEST CONDITIONS
UNIT
V/µs
T
A
MIN
5
TYP MAX
25°C
9
6
SR
Slew rate at unity gain
Equivalent input noise voltage
V
= 0.8 V, C = 100 pF, R = 10 kΩ
O(PP) L L
Full range
25°C
4.7
f = 1 kHz
21
nV/√Hz
V
n
f = 10 kHz
25°C
17
f = 0.1 Hz to 1 Hz
25°C
0.33
0.86
0.6
µV
µV
Peak-to-peak equivalent input
noise voltage
V
I
N(PP)
f = 0.1 Hz to 10 Hz
f = 100 Hz
25°C
Equivalent input noise current
25°C
fA/√Hz
n
A
= 1
0.0085%
V
Total harmonic distortion plus
noise
A
V
= 10
= 100
0.025%
0.12%
4.8
THD + N
R
= 600 Ω, f = 1 kHz
25°C
L
A
V
Gain-bandwidth product
Settling time
25°C
25°C
MHz
f = 10 kHz, R = 600 Ω, C = 100 pF
L
L
A
= −1,
0.1%
0.186
3.92
V
Step = 0.85 V to 1.85 V,
t
s
µs
0.01%
25°C
R
R
= 600 Ω, C = 100 pF
L
L
L
φ
m
Phase margin at unity gain
Gain margin
25°C
25°C
46°
= 600 Ω, C = 100 pF
L
12
dB
†
Full range is −40°C to 125°C.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢀ ꢁꢂꢃ ꢄꢄ ꢅꢊ ꢆꢇ ꢈ
ꢋꢊ ꢌꢍ ꢁꢎ ꢏ ꢋ ꢃ ꢐꢄ ꢆꢂ ꢑꢍ ꢒꢑ ꢆꢓꢁ ꢔꢕꢆꢖꢊꢀ ꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗ ꢀ
ꢏ ꢘꢔꢖ ꢊꢀ ꢍꢏ ꢙꢊꢁ ꢊꢌ ꢘꢁ ꢍꢋ ꢍꢔ ꢖꢓ ꢕ ꢍꢀ ꢑ ꢓꢑꢗ ꢀꢚ ꢏ ꢕꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
electrical characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
TLV2771-Q1
TEST
†
PARAMETER
CONDITIONS
T
UNIT
mV
A
MIN
TYP MAX
25°C
0.5
0.6
2.5
2.7
V
IC
V
O
= 0, No load
V
IO
Input offset voltage
= 0, R = 50 Ω, V
= 2.5 V
Full range
S
DD
Temperature coefficient of input
offset voltage
25°C to
125°C
α
2
µV/°C
pA
VIO
25°C
Full range
25°C
1
2
60
125
60
I
IO
Input offset current
Input bias current
V
= 0, V = 0, R = 50 Ω, V
= 2.5 V
IC
O
S
DD
2
I
IB
pA
Full range
25°C
6
350
4.9
4.8
4.7
4.4
0.1
0.2
0.21
0.6
450
I
I
= −1.3 mA
= −4.2 mA
OH
Full range
25°C
V
High-level output voltage
Low-level output voltage
V
OH
OL
OH
Full range
25°C
V
IC
V
IC
V
IC
= 2.5 V, I
= 2.5 V, I
= 1.3 mA
= 4.2 mA
OL
Full range
25°C
V
V
OL
Full range
25°C
20
13
Large-signal differential voltage
amplification
A
VD
= 2.5 V, R = 10 kΩ , V = 1 V to 4 V
V/mV
L
O
Full range
25°C
12
10
r
Differential input resistance
Ω
pF
Ω
i(d)
c
z
Common-mode input capacitance
Closed-loop output impedance
f = 10 kHz
f = 100 kHz, A = 10
25°C
8
20
96
93
89
84
1
i(c)
o
25°C
V
25°C
60
60
70
70
V
IC
V
O
= 0 to 3.7 V,
CMRR Common-mode rejection ratio
dB
dB
= V
DD
/2, R = 50 Ω
S
Full range
25°C
Supply voltage rejection ratio
V
V
= 2.7 V to 5 V,
DD
IC
k
SVR
(∆V
DD
/∆V
IO
)
= V
/2, No load
Full range
25°C
DD
2
2
I
Supply current (per channel)
V
O
= V
DD
/2, No load
mA
DD
Full range
†
‡
Full range is − 40°C to 125°C for Q level part.
Referenced to 2.5 V
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢆꢇꢈ ꢉ ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢊꢆꢇ ꢈ
ꢋ
ꢊ
ꢌ
ꢍ
ꢁ
ꢎ
ꢏ
ꢋ
ꢃ
ꢐ
ꢄ
ꢆ
ꢂ
ꢑ
ꢍ
ꢒ
ꢑ
ꢆ
ꢓ
ꢁ
ꢔ
ꢕ
ꢆ
ꢖ
ꢊ
ꢀ
ꢔ
ꢖ
ꢊ
ꢍ
ꢁ
ꢏꢘ ꢔ ꢖꢊꢀ ꢍ ꢏꢙ ꢊ ꢁ ꢊꢌ ꢘꢁ ꢍ ꢋꢍ ꢔ ꢖꢓ ꢕ ꢍ ꢀꢑ ꢓ ꢑꢗꢀ ꢚꢏ ꢕ ꢙ
ꢆ
ꢀ
ꢏ
ꢆ
ꢖ
ꢊ
ꢍ
ꢁ
ꢏ
ꢗ
ꢀ
ꢘ
ꢗ
ꢀ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
operating characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
TLV2771-Q1
†
PARAMETER
TEST CONDITIONS
UNIT
V/µs
T
A
MIN
5
TYP MAX
25°C
10.5
6
SR
Slew rate at unity gain
Equivalent input noise voltage
V
= 1.5 V, C = 100 pF, R = 10 kΩ
O(PP) L L
Full range
25°C
4.7
f = 1 kHz
17
nV/√Hz
V
n
f = 10 kHz
25°C
12
f = 0.1 Hz to 1 Hz
25°C
0.33
0.86
0.6
µV
µV
Peak-to-peak equivalent input
noise voltage
V
I
N(PP)
f = 0.1 Hz to 10 Hz
f = 100 Hz
25°C
Equivalent input noise current
25°C
fA/√Hz
n
A
= 1
0.005%
V
Total harmonic distortion plus
noise
R = 600 Ω,
L
A
V
= 10
0.016%
0.095%
5.1
THD + N
25°C
f = 1 kHz
A
V
= 100
Gain-bandwidth product
Settling time
25°C
25°C
MHz
f = 10 kHz, R = 600 Ω, C = 100 pF
L
L
A
V
= −1,
0.1%
0.134
1.97
Step = 1.5 V to 3.5 V,
t
s
µs
0.01%
25°C
R
R
= 600 Ω, C = 100 pF
L
L
L
φ
m
Phase margin at unity gain
Gain margin
25°C
25°C
46°
= 600 Ω, C = 100 pF
L
12
dB
†
Full range is −40°C to 125°C.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢀ ꢁꢂꢃ ꢄꢄ ꢅꢊ ꢆꢇ ꢈ
ꢋꢊ ꢌꢍ ꢁꢎ ꢏ ꢋ ꢃ ꢐꢄ ꢆꢂ ꢑꢍ ꢒꢑ ꢆꢓꢁ ꢔꢕꢆꢖꢊꢀ ꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗ ꢀ
ꢏ ꢘꢔꢖ ꢊꢀ ꢍꢏ ꢙꢊꢁ ꢊꢌ ꢘꢁ ꢍꢋ ꢍꢔ ꢖꢓ ꢕ ꢍꢀ ꢑ ꢓꢑꢗ ꢀꢚ ꢏ ꢕꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
electrical characteristics at specified free-air temperature, V
= 2.7 V (unless otherwise noted)
DD
TLV2772-Q1
TLV2772A-Q1
MIN TYP MAX
†
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP MAX
25°C
0.44
0.47
2.5
2.7
0.44
0.47
1.6
1.9
V
IO
Input offset voltage
mV
Full range
Temperature
coefficient of input
offset voltage
25°C
to
125°C
α
VIO
2
2
µV/°C
V
V
R
=
= 0,
= 50 Ω
1.35 V,
DD
IC
S
V
O
= 0,
25°C
Full range
25°C
1
2
2
6
60
125
60
1
2
2
6
60
125
60
I
I
Input offset current
Input bias current
pA
pA
IO
IB
Full range
350
350
0
to
1.4
−0.3
to
1.7
0
to
1.4
−0.3
to
1.7
25°C
Common-mode
input voltage range
V
CMRR > 60 dB,
R
= 50 Ω
V
V
ICR
S
0
to
1.4
−0.3
to
1.7
0
to
1.4
−0.3
to
1.7
Full range
25°C
Full range
25°C
2.6
2.4
2.6
2.4
I
I
= −0.675 mA
= −2.2 mA
= 1.35 V,
OH
2.45
2.1
2.45
2.1
High-level output
voltage
V
V
OH
OH
Full range
25°C
0.1
0.1
V
V
I
I
= 0.675 mA
= 2.2 mA
IC
OL
Full range
25°C
0.2
0.6
0.2
0.6
Low-level output
voltage
V
OL
0.21
0.21
= 1.35 V,
IC
OL
Full range
Large-signal
differential voltage
amplification
25°C
20
13
380
20
13
380
‡
V
IC
V
O
= 1.35 V,
= 0.6 V to 2.1 V
R
= 10 kΩ,
L
A
VD
V/mV
Full range
Differential input
resistance
12
10
12
10
Ω
pF
Ω
r
25°C
25°C
25°C
i(d)
Common-mode
input capacitance
c
z
f = 10 kHz,
8
8
i(c)
o
Closed-loop
output impedance
f = 100 kHz,
A
V
= 10
25
25
25°C
60
60
84
82
60
60
84
82
Common-mode
rejection ratio
V
R
= V (min),
ICR
V
= 1.5 V,
IC
S
O
CMRR
dB
dB
= 50 Ω
Full range
Supply voltage
rejection ratio
25°C
70
70
89
70
70
89
V
= 2.7 V to 5 V,
V
IC
= V /2,
DD
DD
k
SVR
No load
Full range
84
1
84
1
(∆V
/∆V )
DD
IO
25°C
2
2
2
2
Supply current
(per channel)
I
V
O
= 1.5 V,
No load
mA
DD
Full range
†
‡
Full range is −40°C to 125°C for Q level part.
Referenced to 1.35 V
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢆꢇꢈ ꢉ ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢊꢆꢇ ꢈ
ꢋ
ꢊ
ꢌ
ꢍ
ꢁ
ꢎ
ꢏ
ꢋ
ꢃ
ꢐ
ꢄ
ꢆ
ꢂ
ꢑ
ꢍ
ꢒ
ꢑ
ꢆ
ꢓ
ꢁ
ꢔ
ꢕ
ꢆ
ꢖ
ꢊ
ꢀ
ꢔ
ꢖ
ꢊ
ꢍ
ꢁ
ꢏꢘ ꢔ ꢖꢊꢀ ꢍ ꢏꢙ ꢊ ꢁ ꢊꢌ ꢘꢁ ꢍ ꢋꢍ ꢔ ꢖꢓ ꢕ ꢍ ꢀꢑ ꢓ ꢑꢗꢀ ꢚꢏ ꢕ ꢙ
ꢆ
ꢀ
ꢏ
ꢆ
ꢖ
ꢊ
ꢍ
ꢁ
ꢏ
ꢗ
ꢀ
ꢘ
ꢗ
ꢀ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
operating characteristics at specified free-air temperature, V
= 2.7 V (unless otherwise noted)
DD
TLV2772-Q1
TYP MAX
TLV2772A-Q1
MIN TYP MAX
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
25°C
5
9
5
9
V
R
= 0.8 V,
C
= 100 pF,
L
O(PP)
= 10 kΩ
SR
Slew rate at unity gain
V/µs
Full
range
4.7
6
4.7
6
L
f = 1 kHz
25°C
25°C
21
17
21
17
Equivalent input
noise voltage
nV/√Hz
V
n
f = 10 kHz
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
25°C
25°C
0.33
0.86
0.33
0.86
µV
µV
V
I
N(PP)
f = 0.1 Hz to 10 Hz
f = 100 Hz
Equivalent input
noise current
25°C
0.6
0.6
fA/√Hz
n
A
= 1
0.0085%
0.025%
0.12%
0.0085%
0.025%
0.12%
V
Total harmonic
distortion plus noise
R = 600 Ω,
L
A
V
= 10
THD + N
25°C
f = 1 kHz
A
= 100
R = 600 Ω,
L
V
Gain-bandwidth
product
f = 10 kHz,
25°C
25°C
4.8
4.8
MHz
C
= 100 pF
L
A
V
= −1,
0.1%
0.186
0.186
Step = 0.85 V to
1.85 V,
t
s
Settling time
µs
R
C
= 600 Ω,
= 100 pF
L
L
0.01%
25°C
3.92
3.92
Phase margin at
unity gain
φ
m
25°C
25°C
46°
46°
R
= 600 Ω,
C = 100 pF
L
L
Gain margin
12
12
dB
†
Full range is −40°C to 125°C for Q level part.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢀ ꢁꢂꢃ ꢄꢄ ꢅꢊ ꢆꢇ ꢈ
ꢋꢊ ꢌꢍ ꢁꢎ ꢏ ꢋ ꢃ ꢐꢄ ꢆꢂ ꢑꢍ ꢒꢑ ꢆꢓꢁ ꢔꢕꢆꢖꢊꢀ ꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗ ꢀ
ꢏ ꢘꢔꢖ ꢊꢀ ꢍꢏ ꢙꢊꢁ ꢊꢌ ꢘꢁ ꢍꢋ ꢍꢔ ꢖꢓ ꢕ ꢍꢀ ꢑ ꢓꢑꢗ ꢀꢚ ꢏ ꢕꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
electrical characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
TLV2772-Q1
TLV2772A-Q1
MIN TYP MAX
†
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP MAX
25°C
0.36
0.4
2.5
2.7
0.36
0.4
1.6
1.9
V
IO
Input offset voltage
mV
Full range
Temperature
coefficient of input
offset voltage
25°C
to
125°C
α
VIO
2
2
µV/°C
V
V
=
2.5 V,
V
R
= 0,
= 50 Ω
DD
= 0,
O
S
IC
25°C
Full range
25°C
1
2
2
6
60
125
60
1
2
2
6
60
125
60
I
I
Input offset current
Input bias current
pA
pA
IO
IB
Full range
350
350
0
to
3.7
−0.3
to
3.8
0
to
3.7
−0.3
to
3.8
25°C
Common-mode
input voltage range
V
CMRR > 60 dB,
R
= 50 Ω
S
V
V
ICR
0
to
3.7
−0.3
to
3.8
0
to
3.7
−0.3
to
3.8
Full range
25°C
Full range
25°C
4.9
4.7
4.9
4.7
I
I
= −1.3 mA
= −4.2 mA
= 2.5 V,
OH
4.8
4.4
4.8
4.4
High-level output
voltage
V
V
OH
OH
Full range
25°C
0.1
0.1
V
V
I
I
= 1.3 mA
= 4.2 mA
IC
OL
Full range
25°C
0.2
0.6
0.2
0.6
Low-level output
voltage
V
OL
0.21
0.21
= 2.5 V,
IC
OL
Full range
Large-signal
differential voltage
amplification
25°C
20
13
450
20
13
450
‡
V
IC
V
O
= 2.5 V,
= 1 V to 4 V
R
= 10 kΩ,
L
A
VD
V/mV
Full range
Differential input
resistance
12
10
12
10
Ω
pF
Ω
r
25°C
25°C
25°C
i(d)
Common-mode
input capacitance
c
z
f = 10 kHz,
8
8
i(c)
o
Closed-loop
output impedance
f = 100 kHz,
A
V
= 10
20
20
25°C
60
60
96
93
60
60
96
93
Common-mode
rejection ratio
V
R
= V (min),
ICR
V
= 3.7 V,
IC
S
O
CMRR
dB
dB
= 50 Ω
Full range
Supply voltage
rejection ratio
25°C
70
70
89
70
70
89
V
= 2.7 V to 5 V,
V
IC
= V /2,
DD
DD
k
SVR
No load
Full range
84
1
84
1
(∆V
/∆V )
DD
IO
25°C
2
2
2
2
Supply current
(per channel)
I
V
O
= 1.5 V,
No load
mA
DD
Full range
†
‡
Full range is −40°C to 125°C for Q level part.
Referenced to 2.5 V
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢆꢇꢈ ꢉ ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢊꢆꢇ ꢈ
ꢋ
ꢊ
ꢌ
ꢍ
ꢁ
ꢎ
ꢏ
ꢋ
ꢃ
ꢐ
ꢄ
ꢆ
ꢂ
ꢑ
ꢍ
ꢒ
ꢑ
ꢆ
ꢓ
ꢁ
ꢔ
ꢕ
ꢆ
ꢖ
ꢊ
ꢀ
ꢔ
ꢖ
ꢊ
ꢍ
ꢁ
ꢏꢘ ꢔ ꢖꢊꢀ ꢍ ꢏꢙ ꢊ ꢁ ꢊꢌ ꢘꢁ ꢍ ꢋꢍ ꢔ ꢖꢓ ꢕ ꢍ ꢀꢑ ꢓ ꢑꢗꢀ ꢚꢏ ꢕ ꢙ
ꢆ
ꢀ
ꢏ
ꢆ
ꢖ
ꢊ
ꢍ
ꢁ
ꢏ
ꢗ
ꢀ
ꢘ
ꢗ
ꢀ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
operating characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
TLV2772-Q1
TYP MAX
TLV2772A-Q1
MIN TYP MAX
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
25°C
5
10.5
5
10.5
V
R
= 1.5 V,
C
= 100 pF,
L
O(PP)
= 10 kΩ
SR
Slew rate at unity gain
V/µs
Full
range
4.7
6
4.7
6
L
f = 1 kHz
25°C
25°C
17
12
17
12
Equivalent input
noise voltage
nV/√Hz
V
n
f = 10 kHz
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
25°C
25°C
0.33
0.86
0.33
0.86
µV
µV
V
I
N(PP)
f = 0.1 Hz to 10 Hz
f = 100 Hz
Equivalent input
noise current
25°C
0.6
0.6
fA/√Hz
n
A
= 1
0.005%
0.016%
0.095%
0.005%
0.016%
0.095%
V
Total harmonic
distortion plus noise
R = 600 Ω,
L
A
V
= 10
THD + N
25°C
f = 1 kHz
A
= 100
R = 600 Ω,
L
V
Gain-bandwidth
product
f = 10 kHz,
25°C
25°C
5.1
5.1
MHz
C
= 100 pF
L
A
V
= −1,
0.1%
0.134
0.134
Step = 1.5 V to
3.5 V,
t
s
Settling time
µs
R
C
= 600 Ω,
= 100 pF
L
L
0.01%
25°C
1.97
1.97
Phase margin at unity
gain
φ
m
25°C
25°C
46°
46°
R
= 600 Ω,
C = 100 pF
L
L
Gain margin
12
12
dB
†
Full range is −40°C to 125°C for Q level part.
12
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ꢋꢊ ꢌꢍ ꢁꢎ ꢏ ꢋ ꢃ ꢐꢄ ꢆꢂ ꢑꢍ ꢒꢑ ꢆꢓꢁ ꢔꢕꢆꢖꢊꢀ ꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗ ꢀ
ꢏ ꢘꢔꢖ ꢊꢀ ꢍꢏ ꢙꢊꢁ ꢊꢌ ꢘꢁ ꢍꢋ ꢍꢔ ꢖꢓ ꢕ ꢍꢀ ꢑ ꢓꢑꢗ ꢀꢚ ꢏ ꢕꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Distribution
vs Common-mode input voltage
Distribution
1, 2
3, 4
5, 6
V
IO
Input offset voltage
I
/I
Input bias and input offset currents
High-level output voltage
vs Free-air temperature
vs High-level output current
vs Low-level output current
vs Frequency
7
IB IO
V
V
V
8, 9
OH
Low-level output voltage
10, 11
12, 13
OL
Maximum peak-to-peak output voltage
O(PP)
vs Supply voltage
vs Free-air temperature
14
15
I
Short-circuit output current
Output voltage
OS
V
vs Differential input voltage
16
O
A
VD
Large-signal differential voltage amplification and phase margin vs Frequency
17, 18
vs Load resistance
vs Free-air temperature
19
20, 21
A
Differential voltage amplification
Output impedance
VD
o
z
vs Frequency
22, 23
vs Frequency
vs Free-air temperature
24
25
CMRR
Common-mode rejection ratio
k
Supply-voltage rejection ratio
Supply current (per channel)
vs Frequency
26, 27
28
SVR
I
vs Supply voltage
DD
vs Load capacitance
vs Free-air temperature
29
30
SR
Slew rate
V
V
V
V
V
Voltage-follower small-signal pulse response
Voltage-follower large-signal pulse response
Inverting small-signal pulse response
Inverting large-signal pulse response
Equivalent input noise voltage
31, 32
33, 34
35, 36
37, 38
39, 40
41
O
O
O
O
n
vs Frequency
Noise voltage (referred to input)
Total harmonic distortion plus noise
Gain-bandwidth product
Over a 10-second period
vs Frequency
THD + N
42, 43
44
vs Supply voltage
vs Load capacitance
B
1
Unity-gain bandwidth
45
φ
m
Phase margin
Gain margin
vs Load capacitance
vs Load capacitance
46
47
Amplifier with shutdown pulse turnon/off characteristics
Supply current with shutdown pulse turnon/off characteristics
Shutdown supply current
48−50
51−53
54
vs Free-air temperature
vs Frequency
Shutdown forward/reverse isolation
55, 56
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ꢋꢊꢌ ꢍ ꢁꢎ ꢏꢋ ꢃ ꢐ ꢄꢆꢂ ꢑꢍ ꢒ ꢑꢆꢓ ꢁꢔ ꢕꢆꢖꢊꢀꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗꢀ
ꢏꢘ ꢔ ꢖꢊꢀ ꢍ ꢏꢙ ꢊ ꢁ ꢊꢌ ꢘꢁ ꢍ ꢋꢍ ꢔ ꢖꢓ ꢕ ꢍ ꢀꢑ ꢓ ꢑꢗꢀ ꢚꢏ ꢕ ꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLV2772
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLV2772
INPUT OFFSET VOLTAGE
40
40
V
R
T
A
= 2.7 V
= 10 kΩ
= 25°C
DD
L
V
= 5 V
DD
L
R = 10 kΩ
T = 25°C
A
35
30
35
30
25
20
25
20
15
10
5
15
10
5
0
0
−2.5 −2 −1.5 −1 −0.5
0
0.5
1
1.5
2
2.5
−2.5 −2 −1.5 −1 −0.5
0
0.5
1
1.5
2
2.5
V
IO
− Input Offset Voltage − mV
V
IO
− Input Offset Voltage − mV
Figure 1
Figure 2
INPUT OFFSET VOLTAGE
vs
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
COMMON-MODE INPUT VOLTAGE
2
2
V
T
A
= 2.7 V
DD
= 25°C
V
T
= 5 V
DD
= 25°C
1.5
1
A
1.5
1
0.5
0
0.5
0
−0.5
−1
−0.5
−1
−1.5
−2
−1.5
−2
−1 −0.5
−1 −0.5
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
V
IC
− Common-Mode Input Voltage − V
V
IC
− Common-Mode Input Voltage − V
Figure 3
Figure 4
14
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ꢋꢊ ꢌꢍ ꢁꢎ ꢏ ꢋ ꢃ ꢐꢄ ꢆꢂ ꢑꢍ ꢒꢑ ꢆꢓꢁ ꢔꢕꢆꢖꢊꢀ ꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗ ꢀ
ꢏ ꢘꢔꢖ ꢊꢀ ꢍꢏ ꢙꢊꢁ ꢊꢌ ꢘꢁ ꢍꢋ ꢍꢔ ꢖꢓ ꢕ ꢍꢀ ꢑ ꢓꢑꢗ ꢀꢚ ꢏ ꢕꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLV2772
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLV2772
INPUT OFFSET VOLTAGE
35
30
35
30
V
T
A
= 2.7 V
DD
= 25°C to 125°C
V
= 5 V
DD
T = 25°C to 125°C
A
25
20
15
25
20
15
10
5
10
5
0
0
−6
−3
0
3
6
9
12
−6
−3
0
3
6
9
12
α
VIO
− Temperature Coefficient − µV/°C
α
VIO
− Temperature Coefficient − µV/°C
Figure 5
Figure 6
INPUT BIAS AND OFFSET CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
0.20
0.15
0.10
3
V
V
V
= 5 V
= 0
= 0
= 50 Ω
DD
IC
O
V
= 2.7 V
DD
2.5
R
S
I
IB
2
T
A
= −40°C
1.5
T
A
= 125°C
1
0.05
0
T
= 25°C
A
I
IO
0.5
0
T
= 85°C
A
−75 −50
−25
0
25
50
75
100 125
0
5
10
15
20
25
T
A
− Free-Air Temperature − °C
I
− High-Level Output Current − mA
OH
Figure 7
Figure 8
15
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ꢋꢊꢌ ꢍ ꢁꢎ ꢏꢋ ꢃ ꢐ ꢄꢆꢂ ꢑꢍ ꢒ ꢑꢆꢓ ꢁꢔ ꢕꢆꢖꢊꢀꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗꢀ
ꢏꢘ ꢔ ꢖꢊꢀ ꢍ ꢏꢙ ꢊ ꢁ ꢊꢌ ꢘꢁ ꢍ ꢋꢍ ꢔ ꢖꢓ ꢕ ꢍ ꢀꢑ ꢓ ꢑꢗꢀ ꢚꢏ ꢕ ꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5
4.5
4
3
V
T
A
= 5 V
DD
= 25°C
V
DD
= 2.7 V
2.5
T
= 125°C
A
T
A
= −40°C
3.5
3
T
A
= 85°C
T
A
= 25°C
2
2.5
1.5
T
A
= 125°C
2
T
A
= 25°C
1
1.5
T
A
= 85°C
1
T
A
= −40°C
0.5
0
0.5
0
0
5
10 15 20 25 30 35 40 45 50 55
0
5
10
15
20
25
30
I
− High-Level Output Current − mA
OH
I
− Low-Level Output Current − mA
OL
Figure 9
Figure 10
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
3
2.5
2
5
4
V
DD
= 5 V
R = 10 kΩ
L
V
= 5 V
T
= 125°C
DD
1% THD
A
T
A
= 85°C
3
2
1
0
1.5
1
V
= 2.7 V
DD
2% THD
T
= 25°C
A
T
A
= −40°C
0.5
0
0
10
20
30
40
50
100
1000
10000
I
− Low-Level Output Current − mA
OL
f − Frequency − kHz
Figure 12
Figure 11
16
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ꢋꢊ ꢌꢍ ꢁꢎ ꢏ ꢋ ꢃ ꢐꢄ ꢆꢂ ꢑꢍ ꢒꢑ ꢆꢓꢁ ꢔꢕꢆꢖꢊꢀ ꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗ ꢀ
ꢏ ꢘꢔꢖ ꢊꢀ ꢍꢏ ꢙꢊꢁ ꢊꢌ ꢘꢁ ꢍꢋ ꢍꢔ ꢖꢓ ꢕ ꢍꢀ ꢑ ꢓꢑꢗ ꢀꢚ ꢏ ꢕꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
TYPICAL CHARACTERISTICS
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
SHORT-CIRCUIT OUTPUT CURRENT
vs
FREQUENCY
SUPPLY VOLTAGE
5
60
THD = 5%
V
V
T
= V
DD
DD
= 25°C
/2
/2
O
IC
A
4.5
4
R
T
A
= 600 Ω
= 25°C
L
= V
45
30
V
ID
= −100 mV
3.5
3
V
DD
= 5 V
15
0
2.5
2
V
DD
= 2.7 V
−15
1.5
1
−30
−45
−60
V
= 100 mV
ID
0.5
0
100
1000
f − Frequency − kHz
10000
2
3
4
5
6
7
V
DD
− Supply Voltage − V
Figure 13
Figure 14
SHORT-CIRCUIT OUTPUT CURRENT
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
60
40
5
4
3
R
T
A
= 600 Ω
= 25°C
L
V
DD
= 5 V
V
ID
= −100 mV
20
V
V
= 5 V
DD
= 2.5 V
V
DD
= 2.7 V
0
O
2
1
0
−20
−40
−60
V
= 100 mV
ID
−75 −50
−25
0
25
50
75 100
125
−1000 −750 −500 −250
0
250 500 750 1000
T
A
− Free-Air Temperature − °C
V
ID
− Differential Input Voltage − µV
Figure 15
Figure 16
17
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ꢋꢊꢌ ꢍ ꢁꢎ ꢏꢋ ꢃ ꢐ ꢄꢆꢂ ꢑꢍ ꢒ ꢑꢆꢓ ꢁꢔ ꢕꢆꢖꢊꢀꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗꢀ
ꢏꢘ ꢔ ꢖꢊꢀ ꢍ ꢏꢙ ꢊ ꢁ ꢊꢌ ꢘꢁ ꢍ ꢋꢍ ꢔ ꢖꢓ ꢕ ꢍ ꢀꢑ ꢓ ꢑꢗꢀ ꢚꢏ ꢕ ꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION
AND PHASE MARGIN
vs
FREQUENCY
100
300
240
180
120
60
V
= 2.7 V
= 600 Ω
= 600 pF
= 25°C
DD
L
L
R
C
T
80
60
A
A
VD
40
Phase
20
0
0
−20
−40
−60
−90
100
1k
10k
100k
1M
10M
f − Frequency − Hz
Figure 17
LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION
AND PHASE MARGIN
vs
FREQUENCY
100
300
V
R
C
= 5 V
= 600 Ω
= 600 pF
= 25°C
DD
L
L
80
60
240
180
120
60
T
A
A
VD
40
Phase
20
0
0
−20
−40
−60
−90
100
1k
10k
100k
1M
10M
f − Frequency − Hz
Figure 18
18
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ꢋꢊ ꢌꢍ ꢁꢎ ꢏ ꢋ ꢃ ꢐꢄ ꢆꢂ ꢑꢍ ꢒꢑ ꢆꢓꢁ ꢔꢕꢆꢖꢊꢀ ꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗ ꢀ
ꢏ ꢘꢔꢖ ꢊꢀ ꢍꢏ ꢙꢊꢁ ꢊꢌ ꢘꢁ ꢍꢋ ꢍꢔ ꢖꢓ ꢕ ꢍꢀ ꢑ ꢓꢑꢗ ꢀꢚ ꢏ ꢕꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
TYPICAL CHARACTERISTICS
DIFFERENTIAL VOLTAGE AMPLIFICATION
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
vs
LOAD RESISTANCE
FREE-AIR TEMPERATURE
250
200
150
100
50
1000
100
10
T
A
= 25°C
R
= 10 kΩ
L
R
= 1 MΩ
= 600 Ω
L
V
DD
= 2.7 V
V
= 5 V
DD
R
L
1
V
V
V
= 2.7 V
= 1.35 V
DD
IC
O
= 0.6 V to 2.1 V
0
0.1
−75 −50
0.1
1
10
100
1000
−25
0
25
50
75 100
125
R
− Load Resistance − kΩ
L
T
A
− Free-Air Temperature − °C
Figure 20
Figure 19
DIFFERENTIAL VOLTAGE AMPLIFICATION
OUTPUT IMPEDANCE
vs
vs
FREE-AIR TEMPERATURE
FREQUENCY
1000
100
10
100
R
= 10 kΩ
V
T
A
= 2.7 V
= 25°C
L
DD
R
= 1 MΩ
L
10
1
A
V
= 100
R
= 600 Ω
L
A
= 10
= 1
V
A
V
1
0.10
0.01
V
V
V
= 5 V
= 2.5 V
= 1 V to 4 V
DD
IC
O
0.1
−75 −50
−25
0
25
50
75 100
125
100
1k
10k
100k
1M
T
A
− Free-Air Temperature − °C
f − Frequency − Hz
Figure 21
Figure 22
19
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ꢋꢊꢌ ꢍ ꢁꢎ ꢏꢋ ꢃ ꢐ ꢄꢆꢂ ꢑꢍ ꢒ ꢑꢆꢓ ꢁꢔ ꢕꢆꢖꢊꢀꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗꢀ
ꢏꢘ ꢔ ꢖꢊꢀ ꢍ ꢏꢙ ꢊ ꢁ ꢊꢌ ꢘꢁ ꢍ ꢋꢍ ꢔ ꢖꢓ ꢕ ꢍ ꢀꢑ ꢓ ꢑꢗꢀ ꢚꢏ ꢕ ꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
TYPICAL CHARACTERISTICS
OUTPUT IMPEDANCE
vs
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
FREQUENCY
100
10
90
80
70
60
50
40
V
T
= 2.5 V
= 25°C
V
= 1.35 V
DD
A
V
= 2.7 V
IC
and 2.5 V
DD
T
A
= 25°C
V
DD
= 5 V
A
v
= 100
1
A
= 10
= 1
v
A
v
0.1
0.01
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
10M
f − Frequency − Hz
f − Frequency − Hz
Figure 23
Figure 24
COMMON-MODE REJECTION RATIO
SUPPLY-VOLTAGE REJECTION RATIO
vs
vs
FREE-AIR TEMPERATURE
FREQUENCY
120
115
120
100
V
T
A
= 2.7 V
= 25°C
DD
k
SVR+
110
105
100
95
k
SVR−
80
60
V
DD
= 2.7 V
40
90
V
DD
= 5 V
20
0
85
80
−40 −20
0
20
40 60
80 100 120 140
10
100
1k
10k
100k
1M
10M
T
A
− Free-Air Temperature − °C
f − Frequency − Hz
Figure 25
Figure 26
20
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ꢋꢊ ꢌꢍ ꢁꢎ ꢏ ꢋ ꢃ ꢐꢄ ꢆꢂ ꢑꢍ ꢒꢑ ꢆꢓꢁ ꢔꢕꢆꢖꢊꢀ ꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗ ꢀ
ꢏ ꢘꢔꢖ ꢊꢀ ꢍꢏ ꢙꢊꢁ ꢊꢌ ꢘꢁ ꢍꢋ ꢍꢔ ꢖꢓ ꢕ ꢍꢀ ꢑ ꢓꢑꢗ ꢀꢚ ꢏ ꢕꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
TYPICAL CHARACTERISTICS
SUPPLY VOLTAGE REJECTION RATIO
SUPPLY CURRENT (PER CHANNEL)
vs
vs
FREQUENCY
SUPPLY VOLTAGE
120
100
1.6
1.4
1.2
1
V
T
A
= 5 V
= 25°C
DD
T
= 125°C
= 85°C
A
k
SVR+
T
A
k
T
A
= 25°C
SVR−
80
60
40
T
A
= 0°C
T
A
= −40°C
0.8
0.6
0.4
20
0
0.2
0
10
100
1 k
10 k
100 k
1 M
10 M
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
f − Frequency − Hz
V
DD
− Supply Voltage − V
Figure 27
Figure 28
SLEW RATE
vs
LOAD CAPACITANCE
SLEW RATE
vs
FREE-AIR TEMPERATURE
16
14
14
13
12
11
10
9
V
= 5 V
= −1
= 25°C
DD
SR+
SR−
V
R
C
= 2.7 V
DD
L
L
A
V
A
= 10 kΩ
= 100 pF
= 1
T
A
V
12
10
8
6
4
2
0
8
10
100
1k
10k
100k
−75 −50
−25
0
25
50
75 100
125
C
− Load Capacitance − pF
L
T
A
− Free-Air Temperature − °C
Figure 29
Figure 30
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢆꢇꢈ ꢉ ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢊꢆꢇ ꢈ
ꢋꢊꢌ ꢍ ꢁꢎ ꢏꢋ ꢃ ꢐ ꢄꢆꢂ ꢑꢍ ꢒ ꢑꢆꢓ ꢁꢔ ꢕꢆꢖꢊꢀꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗꢀ
ꢏꢘ ꢔ ꢖꢊꢀ ꢍ ꢏꢙ ꢊ ꢁ ꢊꢌ ꢘꢁ ꢍ ꢋꢍ ꢔ ꢖꢓ ꢕ ꢍ ꢀꢑ ꢓ ꢑꢗꢀ ꢚꢏ ꢕ ꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
TYPICAL CHARACTERISTICS
VOLTAGE-FOLLOWER
SMALL-SIGNAL PULSE RESPONSE
VOLTAGE-FOLLOWER
SMALL-SIGNAL PULSE RESPONSE
100
80
60
40
20
0
100
80
60
40
20
0
V
R
C
= 2.7 V
V
R
C
= 5 V
DD
L
L
DD
L
L
= 600 Ω
= 100 pF
= 1
= 600 Ω
= 100 pF
= 1
AV
AV
T
= 25°C
T
= 25°C
A
A
−20
−20
−40
−60
−40
−60
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
t − Time − µs
t − Time − µs
Figure 31
Figure 32
VOLTAGE-FOLLOWER
LARGE-SIGNAL PULSE RESPONSE
VOLTAGE-FOLLOWER
LARGE-SIGNAL PULSE RESPONSE
3
2.5
2
6
5
4
3
2
1
0
V
R
C
= 2.7 V
V
R
C
= 5 V
DD
L
L
DD
L
L
= 600 Ω
= 100 pF
= 1
= 600 Ω
= 100 pF
= 1
AV
AV
T
= 25°C
T
= 25°C
A
A
1.5
1
0.5
0
−0.5
−1
−1
−2
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
t − Time − µs
t − Time − µs
Figure 33
Figure 34
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢀ ꢁꢂꢃ ꢄꢄ ꢅꢊ ꢆꢇ ꢈ
ꢋꢊ ꢌꢍ ꢁꢎ ꢏ ꢋ ꢃ ꢐꢄ ꢆꢂ ꢑꢍ ꢒꢑ ꢆꢓꢁ ꢔꢕꢆꢖꢊꢀ ꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗ ꢀ
ꢏ ꢘꢔꢖ ꢊꢀ ꢍꢏ ꢙꢊꢁ ꢊꢌ ꢘꢁ ꢍꢋ ꢍꢔ ꢖꢓ ꢕ ꢍꢀ ꢑ ꢓꢑꢗ ꢀꢚ ꢏ ꢕꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
TYPICAL CHARACTERISTICS
INVERTING SMALL-SIGNAL
PULSE RESPONSE
INVERTING SMALL-SIGNAL
PULSE RESPONSE
100
80
60
40
20
0
100
80
60
40
20
0
V
R
C
= 2.7 V
DD
L
L
V
R
C
= 5 V
= 600 Ω
= 100 pF
= −1
DD
L
L
= 600 Ω
= 100 pF
= −1
AV
AV
T
= 25°C
A
T
= 25°C
A
−20
−20
−40
−60
−40
−60
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
t − Time − µs
t − Time − µs
Figure 35
Figure 36
INVERTING LARGE-SIGNAL
PULSE RESPONSE
INVERTING LARGE-SIGNAL
PULSE RESPONSE
3
2.5
2
4
3.5
3
1.5
1
2.5
2
0.5
0
1.5
1
V
R
C
= 2.7 V
DD
L
L
V
R
C
= 5 V
DD
L
L
= 600 Ω
= 100 pF
= −1
= 600 Ω
= 100 pF
= −1
−0.5
−1
0.5
1
AV
AV
T
= 25°C
A
T
= 25°C
A
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
t − Time − µs
t − Time − µs
Figure 37
Figure 38
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢆꢇꢈ ꢉ ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢊꢆꢇ ꢈ
ꢋꢊꢌ ꢍ ꢁꢎ ꢏꢋ ꢃ ꢐ ꢄꢆꢂ ꢑꢍ ꢒ ꢑꢆꢓ ꢁꢔ ꢕꢆꢖꢊꢀꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗꢀ
ꢏꢘ ꢔ ꢖꢊꢀ ꢍ ꢏꢙ ꢊ ꢁ ꢊꢌ ꢘꢁ ꢍ ꢋꢍ ꢔ ꢖꢓ ꢕ ꢍ ꢀꢑ ꢓ ꢑꢗꢀ ꢚꢏ ꢕ ꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
TYPICAL CHARACTERISTICS
EQUIVALENT INPUT NOISE VOLTAGE
EQUIVALENT INPUT NOISE VOLTAGE
vs
vs
FREQUENCY
FREQUENCY
160
140
120
100
80
140
120
100
80
V
R
T
A
= 2.7 V
= 20 Ω
= 25°C
DD
S
V
R
S
T
A
= 5 V
= 20 Ω
= 25°C
DD
60
40
20
0
60
40
20
0
10
100
1k
10k
10
100
1k
10k
f − Frequency − Hz
f − Frequency − Hz
Figure 39
Figure 40
NOISE VOLTAGE
OVER A 10 SECOND PERIOD
V
= 5 V
DD
f = 0.1 Hz to 10 Hz
300
200
100
T
A
= 25°C
GND
−100
−200
−300
0
1
2
3
4
5
6
7
8
9
10
t − Time − s
Figure 41
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢀ ꢁꢂꢃ ꢄꢄ ꢅꢊ ꢆꢇ ꢈ
ꢋꢊ ꢌꢍ ꢁꢎ ꢏ ꢋ ꢃ ꢐꢄ ꢆꢂ ꢑꢍ ꢒꢑ ꢆꢓꢁ ꢔꢕꢆꢖꢊꢀ ꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗ ꢀ
ꢏ ꢘꢔꢖ ꢊꢀ ꢍꢏ ꢙꢊꢁ ꢊꢌ ꢘꢁ ꢍꢋ ꢍꢔ ꢖꢓ ꢕ ꢍꢀ ꢑ ꢓꢑꢗ ꢀꢚ ꢏ ꢕꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
vs
FREQUENCY
FREQUENCY
10
1
10
1
V
R
T
A
= 2.7 V
= 600 Ω
= 25°C
V
R
L
= 5 V
= 600 Ω
T = 25°C
A
DD
L
DD
A
= 100
= 10
v
A = 100
v
0.1
0.1
A
v
A
= 10
= 1
v
A
v
= 1
0.01
0.01
A
v
0.001
0.001
10
100
1k
10k
100k
10
100
1k
10k
100k
f − Frequency − Hz
f − Frequency − Hz
Figure 42
Figure 43
GAIN-BANDWIDTH PRODUCT
UNITY-GAIN BANDWIDTH
vs
LOAD CAPACITANCE
vs
SUPPLY VOLTAGE
5.2
5
5
4
3
2
1
0
R
C
= 600 Ω
= 100 pF
L
L
V
= 5 V
= 600 Ω
= 25°C
DD
L
R
T
f = 10 kHz
T
A
A
= 25°C
4.8
4.6
4.4
4.2
4
R
= 100
= 50
null
R
null
R
= 20
1k
null
R
= 0
null
2
2.5
3
3.5
4
4.5
5
5.5
6
10
100
10k
100k
V
DD
− Supply Voltage − V
C
− Load Capacitance − pF
L
Figure 44
Figure 45
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢆꢇꢈ ꢉ ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢊꢆꢇ ꢈ
ꢋꢊꢌ ꢍ ꢁꢎ ꢏꢋ ꢃ ꢐ ꢄꢆꢂ ꢑꢍ ꢒ ꢑꢆꢓ ꢁꢔ ꢕꢆꢖꢊꢀꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗꢀ
ꢏꢘ ꢔ ꢖꢊꢀ ꢍ ꢏꢙ ꢊ ꢁ ꢊꢌ ꢘꢁ ꢍ ꢋꢍ ꢔ ꢖꢓ ꢕ ꢍ ꢀꢑ ꢓ ꢑꢗꢀ ꢚꢏ ꢕ ꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
GAIN MARGIN
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
90
0
V
R
T
A
= 5 V
= 600 Ω
= 25°C
V
= 5 V
DD
L
DD
L
R = 600 Ω
T = 25°C
A
80
70
60
50
40
30
20
10
0
5
10
15
20
R
= 100 Ω
null
R
= 50 Ω
null
R
= 0
null
R
= 20 Ω
null
R
= 100 Ω
null
25
30
R
= 50 Ω
= 20 Ω
null
R
= 0
null
R
null
35
40
10
100
1k
10k
100K
10
100
1k
10k
100K
C
− Load Capacitance − pF
C
− Load Capacitance − pF
L
L
Figure 47
Figure 46
TLV2770
TLV2773
AMPLIFIER WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
AMPLIFIER WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
8
7
6
4
8
7
8
6
SHDN = V
DD
SHDN = V
DD
6
5
2
0
6
5
4
2
V
= 5 V
= 5
= 25°C
DD
SHDN = GND
SHDN = GND
A
V
A
4
3
2
1
0
−2
−4
−6
−8
4
3
2
1
0
V
= 5 V
0
DD
= 5
T
A
V
A
Channel 1 Switched
T
= 25°C
−2
−4
−6
Channel 2 SHDN MODE
Channel 1
V
O
V
O
−10
−12
−8
−1
14
−10
−2.5
−1
15
−4 −2
0
2
4
6
8
10
12
0
2.5
5
7.5
10
12.5
t − Time − µs
t − Time − µs
Figure 48
Figure 49
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢀ ꢁꢂꢃ ꢄꢄ ꢅꢊ ꢆꢇ ꢈ
ꢋꢊ ꢌꢍ ꢁꢎ ꢏ ꢋ ꢃ ꢐꢄ ꢆꢂ ꢑꢍ ꢒꢑ ꢆꢓꢁ ꢔꢕꢆꢖꢊꢀ ꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗ ꢀ
ꢏ ꢘꢔꢖ ꢊꢀ ꢍꢏ ꢙꢊꢁ ꢊꢌ ꢘꢁ ꢍꢋ ꢍꢔ ꢖꢓ ꢕ ꢍꢀ ꢑ ꢓꢑꢗ ꢀꢚ ꢏ ꢕꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
TYPICAL CHARACTERISTICS
TLV2775 − CHANNEL 1
TLV2770
AMPLIFIER WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
SUPPLY CURRENT WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
6
8
7
24
21
8
6
SHDN = V
DD
4
2
SHDN = V
DD
6
5
18
15
4
2
0
V
= 5 V
= 5
= 25°C
DD
SHDN = GND
SHDN = GND
A
V
A
4
3
2
12
9
0
−2
−4
−6
−8
T
Channel 1/2 Switched
V
= 5 V
DD
= 5
−2
−4
−6
Channel 3/4 SHDN MODE
A
V
A
T
= 25°C
6
Channel 1
1
3
I
V
O
DD
0
0
−8
−10
−12
−10
−2.5
−1
15
−3
14
0
2.5
5
7.5
10
12.5
−4 −2
0
2
4
6
8
10 12
t − Time − µs
t − Time − µs
Figure 50
Figure 51
TLV2773
TLV2775
SUPPLY CURRENT WITH SHUTDOWN PULSE
SUPPLY CURRENT WITH SHUTDOWN PULSE
TURNON/OFF CHARACTERISTICS
6
TURNON/OFF CHARACTERISTICS
6
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
SHDN = V
SHDN = V
DD
DD
3
3
0
0
SHDN = GND
SHDN = GND
−3
−3
V
= 5 V
V
= 5 V
DD
= 5
DD
= 5
A
A
V
A
−6
−9
−6
−9
V
A
T
= 25°C
T
= 25°C
Channel 1/2 Switched
Channel 3/4 SHDN MODE
Channel 1 Switched
Channel 2 SHDN MODE
−12
−15
−18
−12
−15
−18
I
I
DD
DD
0
−3
15
−3
15
−5 −2.5
0
2.5
5
7.5
10 12.5
−5 −2.5
0
2.5
5
7.5
10 12.5
t − Time − µs
t − Time − µs
Figure 52
Figure 53
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢆꢇꢈ ꢉ ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢊꢆꢇ ꢈ
ꢋꢊꢌ ꢍ ꢁꢎ ꢏꢋ ꢃ ꢐ ꢄꢆꢂ ꢑꢍ ꢒ ꢑꢆꢓ ꢁꢔ ꢕꢆꢖꢊꢀꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗꢀ
ꢏꢘ ꢔ ꢖꢊꢀ ꢍ ꢏꢙ ꢊ ꢁ ꢊꢌ ꢘꢁ ꢍ ꢋꢍ ꢔ ꢖꢓ ꢕ ꢍ ꢀꢑ ꢓ ꢑꢗꢀ ꢚꢏ ꢕ ꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
TYPICAL CHARACTERISTICS
SHUTDOWN SUPPLY CURRENT
vs
TLV2770
SHUTDOWN FORWARD ISOLATION
FREE-AIR TEMPERATURE
vs
7
6
5
4
3
FREQUENCY
140
A
R
= 5
= OPEN
V
L
SHDN = GND
V
= 2.7 V
120
100
80
I(PP)
V
I(PP)
= 0.1 V
V
DD
5 V
60
40
20
2
SHDN MODE
= 1
V
2.7 V
50
A
V
DD
V
R
C
T
= 2.7 V
DD
L
L
1
0
= 10 kΩ
= 20 pF
= 25°C
0
A
−75 −50
−25
0
25
75 100
125
−20
2
10
3
10
4
10
5
10
10
10
6
T
A
− Free-Air Temperature − °C
f − Frequency − Hz
Figure 54
Figure 55
TLV2770
SHUTDOWN REVERSE ISOLATION
vs
FREQUENCY
140
120
100
80
V
= 2.7 V
I(PP)
V
I(PP)
= 0.1 V
60
40
20
SHDN MODE
= 1
A
V
V
R
C
= 2.7 V
DD
L
L
= 10 kΩ
= 20 pF
= 25°C
0
T
A
−20
2
10
3
4
5
10
10
10
10
10
6
f − Frequency − Hz
Figure 56
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢄ ꢅ ꢆꢇ ꢈ ꢉ ꢀ ꢁꢂꢃ ꢄꢄ ꢅꢊ ꢆꢇ ꢈ
ꢋꢊ ꢌꢍ ꢁꢎ ꢏ ꢋ ꢃ ꢐꢄ ꢆꢂ ꢑꢍ ꢒꢑ ꢆꢓꢁ ꢔꢕꢆꢖꢊꢀ ꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗ ꢀ
ꢏ ꢘꢔꢖ ꢊꢀ ꢍꢏ ꢙꢊꢁ ꢊꢌ ꢘꢁ ꢍꢋ ꢍꢔ ꢖꢓ ꢕ ꢍꢀ ꢑ ꢓꢑꢗ ꢀꢚ ꢏ ꢕꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
PARAMETER MEASUREMENT INFORMATION
R
_
+
null
R
L
C
L
Figure 57
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device’s
phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than
10 pF, it is recommended that a resistor be placed in series (R
) with the output of the amplifier, as shown
NULL
in Figure 58. A minimum value of 20 Ω should work well for most applications.
R
F
R
G
_
R
NULL
Input
Output
LOAD
+
C
Figure 58. Driving a Capacitive Load
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢆꢇꢈ ꢉ ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ ꢊꢆꢇ ꢈ
ꢋꢊꢌ ꢍ ꢁꢎ ꢏꢋ ꢃ ꢐ ꢄꢆꢂ ꢑꢍ ꢒ ꢑꢆꢓ ꢁꢔ ꢕꢆꢖꢊꢀꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗꢀ
ꢏꢘ ꢔ ꢖꢊꢀ ꢍ ꢏꢙ ꢊ ꢁ ꢊꢌ ꢘꢁ ꢍ ꢋꢍ ꢔ ꢖꢓ ꢕ ꢍ ꢀꢑ ꢓ ꢑꢗꢀ ꢚꢏ ꢕ ꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
APPLICATION INFORMATION
offset voltage
The output offset voltage, (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times
OO
IO
IB
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
R
F
R
R
I
IB−
F
F
V
+ V
1 ) ǒ Ǔ " I
R
1 ) ǒ Ǔ " I
R
ǒ Ǔ ǒ Ǔ
R
G
OO
IO
IB)
S
IB–
F
R
R
G
G
+
−
+
V
I
V
O
R
S
I
IB+
Figure 59. Output Offset Voltage Model
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 60).
R
R
F
G
1
f
+
–3dB
2pR1C1
−
V
O
V
R
F
+
O
1
V
I
ǒ
Ǔ
+
ǒ
1 )
Ǔ
R1
V
R
1 ) sR1C1
I
G
C1
Figure 60. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
+
_
V
I
1
R1
R2
f
+
–3dB
2pRC
C2
R
F
1
R
=
G
R
F
2 −
)
R
(
Q
G
Figure 61. 2-Pole Low-Pass Sallen-Key Filter
30
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ꢋꢊ ꢌꢍ ꢁꢎ ꢏ ꢋ ꢃ ꢐꢄ ꢆꢂ ꢑꢍ ꢒꢑ ꢆꢓꢁ ꢔꢕꢆꢖꢊꢀ ꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗ ꢀ
ꢏ ꢘꢔꢖ ꢊꢀ ꢍꢏ ꢙꢊꢁ ꢊꢌ ꢘꢁ ꢍꢋ ꢍꢔ ꢖꢓ ꢕ ꢍꢀ ꢑ ꢓꢑꢗ ꢀꢚ ꢏ ꢕꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
APPLICATION INFORMATION
using the TLV2772 as an accelerometer interface
The schematic, shown in Figure 62, shows the ACH04-08-05 interfaced to the TLV1544 10-bit analog-to-digital
converter (ADC).
The ACH04-08-05 is a shock sensor designed to convert mechanical acceleration into electrical signals. The
sensor contains three piezoelectric sensing elements oriented to simultaneously measure acceleration in three
orthogonal, linear axes (x, y, z). The operating frequency is 0.5 Hz to 5 kHz. The output is buffered with an
internal JFET and has a typical output voltage of 1.80 mV/g for the x and y axis and 1.35 mV/g for the z axis.
Amplification and frequency shaping of the shock sensor output is done by the TLV2772 rail-to-rail operational
amplifier. The TLV2772 is ideal for this application as it offers high input impedance, good slew rate, and
excellent dc precision. The rail-to-rail output swing and high output drive are perfect for driving the analog input
of the TLV1544 ADC.
C2
2.2 nF
1.23 V R3
10 kΩ
R4
100 kΩ
3 V
R2
1 MΩ
1 Axis ACH04−08−05
3 V
R5
1 kΩ
C1
0.22 µF
8
2
3
+
_
1
Output to
TLV1544 (ADC)
1/2
TLV2772
C3
0.22 µF
4
R1
100 kΩ
Signal Conditioning
3 V
R6
2.2 kΩ
1.23 V
Shock Sensor
1.23 V
C
TLV431
R
A
Voltage Reference
Figure 62. Accelerometer Interface Schematic
The sensor signal must be amplified and frequency-shaped to provide a signal the ADC can properly convert
into the digital domain. Figure 62 shows the topology used in this application for one axis of the sensor. This
system is powered from a single 3-V supply. Configuring the TLV431 with a 2.2-kΩ resistor produces a reference
voltage of 1.23 V. This voltage is used to bias the operational amplifier and the internal JFETs in the shock
sensor.
31
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ꢋꢊꢌ ꢍ ꢁꢎ ꢏꢋ ꢃ ꢐ ꢄꢆꢂ ꢑꢍ ꢒ ꢑꢆꢓ ꢁꢔ ꢕꢆꢖꢊꢀꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗꢀ
ꢏꢘ ꢔ ꢖꢊꢀ ꢍ ꢏꢙ ꢊ ꢁ ꢊꢌ ꢘꢁ ꢍ ꢋꢍ ꢔ ꢖꢓ ꢕ ꢍ ꢀꢑ ꢓ ꢑꢗꢀ ꢚꢏ ꢕ ꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
APPLICATION INFORMATION
gain calculation
Since the TLV2772 is capable of rail-to-rail output using a 3-V supply, V = 0 (min) to 3 V (max). With no signal
O
from the sensor, nominal V = reference voltage = 1.23 V. Therefore, the maximum negative swing from nominal
O
is 0 V − 1.23 V = −1.23 V and the maximum positive swing is 3 V − 1.23 V = 1.77 V. By modeling the shock sensor
as a low impedance voltage source with output of 2.25 mV/g (max) in the x and y axis and 1.7 mV/g (max) in
the z axis, the gain of the circuit is calculated by equation 1.
Output Swing
Sensor Signal Acceleration
Gain +
(1)
To avoid saturation of the operational amplifier, the gain calculations are based on the maximum negative swing
of −1.23 V and the maximum sensor output of 2.25 mV/g (x and y axis) and 1.70 mV/g (z axis).
* 1.23 V
2.25 mVńg * 50 g
Gain (x, y) +
+ 10.9
(2)
and
–1.23 V
1.70 mVńg –50 g
Gain (z) +
+ 14.5
(3)
By selecting R3 = 10 kΩ and R4 = 100 kΩ, in the x and y channels, a gain of 11 is realized. By selecting
R3 = 7.5 kΩ and R4 = 100 kΩ, in the z channel, a gain of 14.3 is realized. The schematic shows the configuration
for either the x- or y-axis.
bandwidth calculation
To calculate the component values for the frequency shaping characteristics of the signal conditioning circuit,
1 Hz and 500 Hz are selected as the minimum required 3-dB bandwidth.
To minimize the value of the input capacitor (C1) required to set the lower cutoff frequency requires a large value
resistor for R2 is required. A 1-MΩ resistor is used in this example. To set the lower cutoff frequency, the required
capacitor value for C1 is:
1
C1 +
+ 0.159 µF
(4)
2p f
R
2
LOW
Using a value of 0.22 µF, a more common value of capacitor, the lower cutoff frequency is 0.724 Hz.
To minimize the phase shift in the feedback loop caused by the input capacitance of the TLV2772, it is best to
minimize the value of the feedback resistor R4. However, to reduce the required capacitance in the feedback
loop a large value for R4 is required. Therefore, a compromise for the value of R4 must be made. In this circuit,
a value of 100 kΩ has been selected. To set the upper cutoff frequency, the required capacitor value for C2 is:
1
C2 +
+ 3.18 µF
(5)
2p f
R
4
HIGH
Using a 2.2-nF capacitor, the upper cutoff frequency is 724 Hz.
R5 and C3 also cause the signal response to roll off. Therefore, it is beneficial to design this roll-off point to begin
at the upper cutoff frequency. Assuming a value of 1 kΩ for R5, the value for C3 is calculated to be
0.22 µF.
32
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ꢋꢊ ꢌꢍ ꢁꢎ ꢏ ꢋ ꢃ ꢐꢄ ꢆꢂ ꢑꢍ ꢒꢑ ꢆꢓꢁ ꢔꢕꢆꢖꢊꢀ ꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗ ꢀ
ꢏ ꢘꢔꢖ ꢊꢀ ꢍꢏ ꢙꢊꢁ ꢊꢌ ꢘꢁ ꢍꢋ ꢍꢔ ꢖꢓ ꢕ ꢍꢀ ꢑ ꢓꢑꢗ ꢀꢚ ꢏ ꢕꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high performance of the TLV277x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
D
Ground planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D
Proper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D
D
Sockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
Short trace runs/compact part placements—Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance at the
input of the amplifier.
D
Surface-mount passive components—Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
33
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ꢋꢊꢌ ꢍ ꢁꢎ ꢏꢋ ꢃ ꢐ ꢄꢆꢂ ꢑꢍ ꢒ ꢑꢆꢓ ꢁꢔ ꢕꢆꢖꢊꢀꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗꢀ
ꢏꢘ ꢔ ꢖꢊꢀ ꢍ ꢏꢙ ꢊ ꢁ ꢊꢌ ꢘꢁ ꢍ ꢋꢍ ꢔ ꢖꢓ ꢕ ꢍ ꢀꢑ ꢓ ꢑꢗꢀ ꢚꢏ ꢕ ꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
APPLICATION INFORMATION
general power dissipation considerations
For a given θ , the maximum power dissipation is shown in Figure 63 and is calculated by the following formula:
JA
T
–T
MAX
q
A
P
+
ǒ Ǔ
D
JA
Where:
P
= Maximum power dissipation of TLV277x IC (watts)
= Absolute maximum junction temperature (150°C)
= Free-ambient air temperature (°C)
D
T
MAX
T
A
θ
= θ + θ
JA
JC CA
θ
θ
= Thermal coefficient from junction-to-case
JC
= Thermal coefficient from case to ambient air (°C/W)
CA
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
2
T
= 150°C
PDIP Package
J
Low-K Test PCB
1.75
θ
= 104°C/W
JA
1.5
1.25
1
MSOP Package
Low-K Test PCB
SOIC Package
Low-K Test PCB
θ
= 260°C/W
JA
θ
= 176°C/W
JA
0.75
0.5
SOT-23 Package
Low-K Test PCB
0.25
0
θ
= 324°C/W
JA
−55−40 −25 −10
5
20 35 50 65 80 95 110 125
T
A
− Free-Air Temperature − °C
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 63.
34
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ꢋꢊ ꢌꢍ ꢁꢎ ꢏ ꢋ ꢃ ꢐꢄ ꢆꢂ ꢑꢍ ꢒꢑ ꢆꢓꢁ ꢔꢕꢆꢖꢊꢀ ꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗ ꢀ
ꢏ ꢘꢔꢖ ꢊꢀ ꢍꢏ ꢙꢊꢁ ꢊꢌ ꢘꢁ ꢍꢋ ꢍꢔ ꢖꢓ ꢕ ꢍꢀ ꢑ ꢓꢑꢗ ꢀꢚ ꢏ ꢕꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
APPLICATION INFORMATION
shutdown function
Three members of the TLV277x family (TLV2770/3/5) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied low, the supply current is reduced to 0.8 µA/channel,
the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the
shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care
needs to be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place
the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to V /2.
DD
Therefore, when operating the device with split supply voltages (e.g. 2.5 V), the shutdown terminal needs to
be pulled to V − (not GND) to disable the operational amplifier.
DD
The amplifier’s output with a shutdown pulse is shown in Figure 48 through Figure 50. The amplifier is powered
with a single 5-V supply and configured as a noninverting configuration with a gain of 5. The amplifier turnon
and turnoff times are measured from the 50% point of the shutdown pulse to the 50% point of the output
waveform. The times for the single, dual, and quad are listed in the data tables. The bump on the rising edge
of the TLV2770 output waveform is due to the start-up circuit on the bias generator. For the dual and quad
(TLV2773/5), this bump is attributed to the bias generator’s start-up circuit as well as the crosstalk between the
other channel(s), which are in shutdown.
Figure 55 and Figure 56 show the amplifier’s forward and reverse isolation in shutdown. The operational
amplifier is powered by 1.35-V supplies and configured as a voltage follower (A = 1). The isolation
V
performance is plotted across frequency for both 0.1-V and 2.7-V input signals. During normal operation,
PP
PP
the amplifier would not be able to handle a 2.7-V input signal with a supply voltage of 1.35 V since it exceeds
PP
the common-mode input voltage range (V
shutdown even under a worst case scenario.
). However, this curve illustrates that the amplifier remains in
ICR
35
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ꢋꢊꢌ ꢍ ꢁꢎ ꢏꢋ ꢃ ꢐ ꢄꢆꢂ ꢑꢍ ꢒ ꢑꢆꢓ ꢁꢔ ꢕꢆꢖꢊꢀꢔ ꢖꢊꢍ ꢁ ꢆꢀꢏ ꢆꢖꢊꢍ ꢁ ꢏ ꢗꢀ ꢘꢗꢀ
ꢏꢘ ꢔ ꢖꢊꢀ ꢍ ꢏꢙ ꢊ ꢁ ꢊꢌ ꢘꢁ ꢍ ꢋꢍ ꢔ ꢖꢓ ꢕ ꢍ ꢀꢑ ꢓ ꢑꢗꢀ ꢚꢏ ꢕ ꢙ
SGLS179B− SEPTEMBER 2003 − REVISED APRIL 2006
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts Release 8, the model generation
software used with Microsim PSpice. The Boyle macromodel (see Note 4) and subcircuit in Figure 64 are
generated using the TLV2772 typical electrical and operating characteristics at T = 25°C. Using this
A
information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most
cases):
D
D
D
D
D
D
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
D
D
D
D
D
D
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
Open-loop voltage amplification
NOTE 5: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
99
dln
3
egnd
+
−
V
DD+
92
9
fb
css
dp
rss
+
91
90
iss
ro2
hlim
−
+
−
+
vb
dlp
rp
2
vlp
vln
−
+
−
10
+
−
vc
IN−
IN+
r2
C2
j1
j2
7
6
53
+
−
1
vlim
11
dc
12
ga
gcm
8
5
C1
ro1
rd1
rd2
−
de
54
4
GND
+
ve
OUT
dc
* TLV2772 operational amplifier macromodel subcircuit
* created using Parts release 8.0 on 12/12/97 at 10:08
* Parts is a MicroSim product.
iss
3
10
0
145.50E−6
hlim
j1
90
11
12
6
vlim 1K
10 jx1
2
*
j2
r2
rd1
rd2
ro1
ro2
rp
rss
vb
vc
ve
vlim
vlp
vln
.model
.model dy
.model jx1
1
9
10 jx2
* connections: noninverting input
100.00E3
5.3052E3
5.3052E3
17.140
17.140
4.5455E3
1.3746E6
dc 0
*
|
inverting input
4
11
12
5
*
| | positive power supply
| | | negative power supply
| | | | output
4
*
8
*
7
99
4
*
| | | | |
1 2 3 4 5
3
.subckt TLV2772
10
9
99
0
*
c1
11
6
12
7
99
53
5
91
90
3
0
99
2.8868E-12
3
53
4
dc .82001
dc .82001
dc 0
c2
10.000E−12
54
7
css
dc
10
5
2.6302E−12
8
dy
91
0
0
dc 47
dc 47
de
dlp
dln
dp
egnd
fb
54
90
92
4
99
7
dy
92
dx
dx
D(Is=800.00E−18)
dx
D(Is=800.00E−18 Rs=1m Cjo=10p)
PJF(Is=2.2500E−12 Beta=244.20E−6
+ Vto=−.99765)
dx
poly(2) (3,0) (4,0) 0 .5 .5
poly(5) vb vc ve vlp vln 0
.model jx2
.ends
PJF(Is=1.7500E−12 Beta=244.20E−6
+ Vto=−1.002350)
15.513E6 −1E3 1E3 16E6 −16E6
11 12 188.50E−6
ga
gcm
6
0
0
6
10 99 9.4472E−9
*$
Figure 64. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
29-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TLV2771QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2772AQDRQ1
TLV2772AQPWRQ1
TLV2772QDRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
TSSOP
SOIC
D
PW
D
8
8
8
8
2500
2000
2500
2000
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
TLV2772QPWRQ1
TSSOP
PW
CU NIPDAU Level-1-220C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Applications
Audio
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/audio
Automotive
Broadband
Digital Control
Military
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
RFID
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lpw
Telephony
Low Power
Wireless
Video & Imaging
Wireless
www.ti.com/wireless
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Copyright © 2007, Texas Instruments Incorporated
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