TLV27L2-Q1 [TI]
汽车级、双路、16V、160kHz 运算放大器;
| 型号： | TLV27L2-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车级、双路、16V、160kHz 运算放大器 放大器 运算放大器 |
| 文件： | 总25页 (文件大小：1535K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV27L2-Q1
ZHCSEH4A –SEPTEMBER 2015–REVISED DECEMBER 2015
TLV27L2-Q1 汽车类微功耗轨到轨输出
运算放大器
1 特性
3 说明
1
•
•
符合汽车应用 要求
具有符合 AEC-Q100 标准的下列结果：
TLV27L2-Q1 单电源运算放大器具有轨到轨输出能
力。TLV27L2-Q1 器件在扩展级工业温度范围内的最
小工作电源电压低至 2.7V，同时还增添了轨到轨输出
摆幅特性。TLV27L2-Q1 器件仅使用 7µA 的超低电流
即可提供 160kHz 带宽。建议的最大电源电压为
16V，这使得器件可以由（±1.35V 至 ±8V 电源）两个
可充电电池供电。
–
器件温度 1 级：-40℃ 至 +125℃ 的环境运行温
度范围
–
–
器件人体放电模式 (HBM) 分类等级 2
器件组件充电模式 (CDM) 分类等级 C6
•
•
•
•
•
•
•
双极金属氧化物半导体 (BiMOS) 轨到轨输出
输入偏置电流：1pA
轨到轨输出使得 TLV27L2-Q1 器件成为 TLC27Lx 系列
器件的良好升级版，能够以更低的静态电流提供更高的
带宽。TLV27L2-Q1 的偏移电压与 TLC27LxA 型号相
同。这些器件还具有经济高效的优点，在偏移和噪声问
题不太重要的情况下，它们是 TLC225x 和 TLV225x
系列器件不错的替代产品。
高带宽 160kHz
高转换率：0.1V/µs
电源电流：7µA（每通道）
输入噪声电压：89nV/√Hz
电源电压范围：2.7V 至 16V
2 应用
TLV27L2-Q1 器件支持商业级温度范围，以便于实现
从等效 TLC27Lx 的轻松迁移。
•
•
•
•
便携式医疗设备
功率监视
TLV27L2-Q1 器件采用 8 引脚 SOIC (D) 封装。
低功耗安全检测系统
烟雾探测器
器件信息(1)
器件型号
封装
SOIC (8)
封装尺寸（标称值）
TLV27L2-Q1
4.90mm x 3.91mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
稳定的低静态电流
应用电路原理图
8
V
CC
V
7
6
CC
R5
R6
œ
+
5
4
I
LOAD
R2
3
–40°C
R1
R3
0°C
+
2
+
V
R
OUT
25°C
SHUNT
V
BUS
œ
œ
1
0
70°C
V
CC
R
L
125°C
14 16
0
2
4
6
8
10 12
Supply Voltage (V)
R4
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLOS922
TLV27L2-Q1
ZHCSEH4A –SEPTEMBER 2015–REVISED DECEMBER 2015
www.ti.com.cn
目录
8.4 Device Functional Modes ....................................... 11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Selection Guide...................................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Typical Characteristics.............................................. 6
Detailed Description ............................................ 11
8.1 Overview ................................................................ 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 11
9
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 16
11.3 General Power Dissipation Considerations .......... 16
12 器件和文档支持 ..................................................... 17
12.1 文档支持................................................................ 17
12.2 社区资源................................................................ 17
12.3 商标....................................................................... 18
12.4 静电放电警告......................................................... 18
12.5 Glossary................................................................ 18
13 机械、封装和可订购信息....................................... 18
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (September 2015) to Revision A
Page
•
本数据表的第一个公开发布版本。.......................................................................................................................................... 1
2
Copyright © 2015, Texas Instruments Incorporated
TLV27L2-Q1
www.ti.com.cn
ZHCSEH4A –SEPTEMBER 2015–REVISED DECEMBER 2015
5 Selection Guide
All DC specifications are maximum values while AC specifications are typical values.
VS
(V)
IQ/ch
(µA)
VICR
(V)
VIO
(mV)
IIB
(pA)
GBW
(MHz)
SLEW RATE
(V/µs)
Vn, 1 kHz
(nV/√Hz)
PART NUMBER
TLV27L2-Q1
OPAx348-Q1
OPAx333-Q1
OPA2314-Q1
OPAx376-Q1
TLV226x-Q1
2.7 to 16
2.1 to 5.5
1.8 to 5.5
1.8 to 5.5
2.2 to 5.5
2.7 to 8
11
65
–0.2 to VS + 1.2
–0.2 to VS + 0.2
–0.1 to VS + 0.1
–0.2 to VS + 0.2
–0.1 to VS + 0.1
–0.3 to VS – 0.8
5
5
60
10
0.18
1
0.06
0.5
89
35
55
14
7.5
12
25
0.01
2.5
200
10
0.35
2.7
0.16
1.5
180
950
500
0.025
0.95
10
5.5
2
60
0.67
0.55
6 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
OUT B
–IN B
+IN B
Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
+IN A
+IN B
–IN A
–IN B
OUT A
OUT B
V+
NO.
3
I
I
Noninverting input, channel A
Noninverting input, channel B
Inverting input, channel A
Inverting input, channel B
Output, channel A
5
2
I
6
I
1
O
O
—
—
7
Output, channel B
8
Positive (highest) power supply
Negative (lowest) power supply
V–
4
(1) I = input, O = output
Copyright © 2015, Texas Instruments Incorporated
3
TLV27L2-Q1
ZHCSEH4A –SEPTEMBER 2015–REVISED DECEMBER 2015
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
16.5
VS
UNIT
V
VS
VI
Supply voltage
Input voltage(2)
V
VID
IO
Differential input voltage
Output current
VS
V
100
mA
See the Thermal
Information Table
Continuous total power dissipation
TJ
Maximum junction temperature
150
°C
°C
°C
°C
TA
Operating free-air temperature
–40
125
300
125
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Storage temperature
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Relative to the V–.
7.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
MIN
±1.35
2.7
MAX
UNIT
Dual supply
±8
16
VS
TA
Supply voltage
V
Single supply
Input common-mode voltage
Operating free-air temperature
–0.2
–40
VS – 1.2
125
V
°C
7.4 Thermal Information
TLV27L2-Q1
D (SOIC)
8 PINS
122.2
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
70.5
62.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
22.3
ψJB
62.0
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
TLV27L2-Q1
www.ti.com.cn
ZHCSEH4A –SEPTEMBER 2015–REVISED DECEMBER 2015
7.5 Electrical Characteristics
at recommended operating conditions, VS = 2.7 V, 5 V, and 10 V (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DC PERFORMANCE
25°C
0.5
5
7
VIC = VS / 2, VO = VS / 2,
RL = 100 kΩ, RS = 50 Ω
VIO
Input offset voltage
mV
µV/°C
dB
Full range
VIC = VS / 2, VO = VS / 2,
RL = 100 kΩ, RS = 50 Ω
αVIO
Offset voltage drift
25°C
1.1
86
25°C
Full range
25°C
71
70
80
77
77
74
CMRR
Common-mode rejection ratio
VIC = 0 V to VS – 1.2 V, RS = 50 Ω
100
82
VS = 2.7 V, 5 V
Full range
25°C
Large-signal differential voltage
amplification
VO(PP) = VS / 2,
RL = 100 kΩ,
AVD
dB
VS = ±5 V
Full range
INPUT CHARACTERISTICS
≤ 25°C
≤ 70°C
≤ 125°C
≤ 25°C
≤ 70°C
≤ 125°C
≤ 25°C
≤ 25°C
1
1
60
100
VIC = VS / 2, VO = VS / 2,
RL = 100 kΩ, RS = 50 Ω
IIO
Input offset current
pA
pA
1000
60
VIC = VS / 2, VO = VS / 2,
RL = 100 kΩ, RS = 50 Ω
IIB
Input bias current
200
1000
ri(d)
CIC
Differential input resistance
1000
8
GΩ
Common-mode input capacitance f = 1 kHz
pF
POWER SUPPLY
25°C
Full range
25°C
7
11
16
IQ
Quiescent current (per channel)
VO = VS/2
µA
dB
74
70
82
Power supply rejection ratio
(ΔVS/ΔVIO
No load, VS = 2.7 V to 16 V,
VIC = VS / 2 V
PSRR
)
Full range
OUTPUT CHARACTERISTICS
25°C
Full range
25°C
160
85
200
220
120
200
120
150
800
900
400
500
VS = 2.7 V
VIC = VS / 2,
IOL = 100 µA
VS = 5 V
VS = ±5 V
VS = 5 V
VS = ±5 V
Full range
25°C
50
VO
Output voltage swing from rail
mV
Full range
25°C
420
200
400
Full range
25°C
VIC = VS / 2,
IOL = 500 µA
Full range
25°C
IO
Output current
VO = 0.5 V from rail, VS = 2.7 V
µA
kHz
V/µs
DYNAMIC PERFORMANCE
GBP
SR
Gain bandwidth product
RL = 100 kΩ, CL = 10 pF, f = 1 kHz
25°C
25°C
160
0.06
0.05
0.8
62
VO(pp) = 1 V, RL = 100 kΩ,
CL = 50 pF
Slew rate at unity gain
–40°C
125°C
25°C
φM
Phase margin
RL = 100 kΩ, CL = 50 pF
°
V(STEP)pp = 1 V, AV = –1, rise
CL = 50 pF, RL = 100 kΩ, fall
62
ts
Settling time (0.1%)
25°C
µs
44
NOISE AND DISTORTION PERFORMANCE
Vn
In
Equivalent input noise voltage
Equivalent input noise current
f = 1 kHz
f = 1 kHz
25°C
25°C
89
nV/√Hz
nV/√Hz
0.6
(1) Full range is –40°C to 125°C for I suffix.
Copyright © 2015, Texas Instruments Incorporated
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TLV27L2-Q1
ZHCSEH4A –SEPTEMBER 2015–REVISED DECEMBER 2015
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7.6 Typical Characteristics
Table 1. Table of Graphs
FIGURE
Figure 1,
Figure 2,
Figure 3
Input offset voltage (VIO
Input bias and offset current (IIB and IIO
High-level output voltage (VOH
)
vs Common-mode input voltage (VIC
)
)
vs Free-air temperature (TA)
Figure 4
Figure 5,
Figure 7,
Figure 9
)
vs High-level output current (IOH)
Figure 6,
Figure 8,
Figure 10
Low-level output voltage (VOL
Quiescent current (IQ)
)
vs Low-level output current (IOL)
vs Supply voltage (VS)
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
vs Free-air temperature (TA)
Supply voltage and supply current ramp up
Differential voltage gain and phase shift (AVD
Gain-bandwidth product (GBP)
Phase margin (φm)
)
vs Frequency (f)
vs Free-air temperature (TA)
vs Load capacitance (CL)
vs Frequency (f)
Common-mode rejection ratio (CMRR)
Power supply rejection ratio (PSRR)
Input referred noise voltage
vs Frequency (f)
vs Frequency (f)
Slew rate (SR)
vs Free-air temperature (TA)
vs Frequency (f)
Peak-to-peak output voltage (VO(PP)
Inverting small-signal response
Inverting large-signal response
Crosstalk
)
vs Frequency (f)
2000
1500
2000
1500
1000
500
1000
500
0
–500
0
–500
–1000
–1000
–1500
–2000
–1500
–2000
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
Common-Mode Input Voltage (V)
Common-Mode Input Voltage (V)
VS = 2.7 V
TA = 25°C
VS = 5 V
TA = 25°C
Figure 1. Input Offset Voltage vs Common-Mode Input
Voltage
Figure 2. Input Offset Voltage vs Common-Mode Input
Voltage
6
Copyright © 2015, Texas Instruments Incorporated
TLV27L2-Q1
www.ti.com.cn
2000
ZHCSEH4A –SEPTEMBER 2015–REVISED DECEMBER 2015
100
I
I
IB
90
1500
IO
80
70
60
50
40
30
20
10
0
1000
500
0
–500
–1000
–1500
–2000
25
45
65
85
105
125
–5.2 –3.6
–2
–0.4
1.2
2.8
4.4
Free-Air Temperature (°C)
Common-Mode Input Voltage (V)
VS = 5 V
VIC = 2.5 V
VO = 2.5 V
VS = ±5 VDC
TA = 25°C
Figure 4. Input Bias And Input Offset Current vs Free-Air
Temperature
Figure 3. Input Offset Voltage vs Common-Mode Input
Voltage
5
5
–40°C
–40°C
4
4
0°C
0°C
3
3
25°C
70°C
125°C
25°C
70°C
125°C
2
1
2
1
0
–1
–2
–3
–4
–5
0
–1
–2
–3
–4
–5
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Low-Level Output Current (mA)
High-Level Output Current (mA)
VS = ±5 V
Figure 6. Low-Level Output Voltage vs Low-Level Output
Current
Figure 5. High-Level Output Voltage vs High-Level Output
Current
5
5
–40°C
–40°C
4.5
4.5
0°C
0°C
4
4
25°C
25°C
70°C
3.5
70°C
3.5
3
125°C
125°C
3
2.5
2.5
2
1.5
1
2
1.5
1
0.5
0.5
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0 5
1
1 5
2 2.5 3 3.5 4 4.5 5 5.5 6
High-Level Output Current (mA)
Low-Level Output Current (mA)
VS = 5 V
VS = 5 V
Figure 7. High-Level Output Voltage vs High-Level Output
Current
Figure 8. Low-Level Output Voltage vs Low-Level Output
Current
Copyright © 2015, Texas Instruments Incorporated
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TLV27L2-Q1
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2.7
2.4
2.1
1.8
1.5
1.2
2.7
–40°C
0°C
–40°C
2.4
0°C
25°C
70°C
125°C
25°C
2.1
70°C
1.8
125°C
1.5
1.2
0.9
0.6
0.9
0.6
0.3
0
0.3
0
0
0.2 0.4
0.6
0.8
1
1.2 1.4
0
0.2
0.4
0.6
0.8
1
1.2 1.4
High-Level Output Current (mA)
Low-Level Output Current (mA)
VS = 2.7 V
VS = 2.7 V
Figure 9. High-Level Output Voltage vs High-Level Output
Current
Figure 10. Low-Level Output Voltage vs Low-Level Output
Current
8
7
6
8
7
6
5
4
3
5
4
3
–40°C
0°C
2.7 V
2
2
25°C
5 V
1
0
70°C
1
10 V
16 V
125°C
14 16
0
–40 –25 –10
0
2
4
6
8
10 12
5
20 35 50 65 80 95 110 125
Supply Voltage (V)
Free-Air Temperature (°C)
Figure 11. Quiescent Current vs Supply Voltage
Figure 12. Quiescent Current vs Free-Air Temperature
40
120
15
10
5
100
80
0°
30°
0
V
V
I
S
60
60°
90°
O
Q
40
15
10
20
0
120°
150°
180°
5
0
–20
0
5
10
15
20
25
30
0.1
1
10
100 1 k 10 k 100 k 1M
Time (ms)
Frequency (Hz)
VS = 0 to 15 V
TA = 25°C
RL = 100 Ω
CL = 10 pF
VS = 5 V
RL = 100 Ω
CL = 10 pF
TA = 25°C
Figure 13. Supply Voltage and Supply Current Ramp Up
Figure 14. Differential Voltage Gain and Phase Shift vs
Frequency
8
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TLV27L2-Q1
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ZHCSEH4A –SEPTEMBER 2015–REVISED DECEMBER 2015
80
70
60
50
40
30
20
10
0
170
160
150
140
130
120
110
100
2.7 V
5 V
–40 –25 –10
5
20 35 50 65 80 95 110 125
10
100
1000
Free-Air Temperature (°C)
Load Capacitance (pF)
RL = 100 kΩ
VS = 5 V
TA = 25°C
Figure 15. Gain-Bandwidth Product vs Free-Air Temperature
Figure 16. Phase Margin vs Load Capacitance
100
120
110
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
10
100
1 k
10 k
100 k
1M
10
100
1 k
10 k
100 k
1M
Frequency (Hz)
Frequency (Hz)
VS = ±2.5 V
TA = 25°C
VS = 5 V
TA = 25°C
Figure 18. Power Supply Rejection Ratio vs Frequency
Figure 17. Common-Mode Rejection Ratio vs Frequency
0.09
250
0.08
0.07
0.06
0.05
200
150
100
0.04
0.03
0.02
50
0
SR+
SR–
0.01
0
1
10
100
1 k
10 k
100 k
–40 –25 –10
5
20 35 50 65 80 95 110 125
Frequency (Hz)
Free-Air Temperature (°C)
G = 1
VS = 5 V
G = 2
RF = 100 kΩ
VS = 5 V
VO = 1 V
RL = 100 kΩ
CL = 50 pF
Figure 19. Input Referred Noise Voltage vs Frequency
Figure 20. Slew Rate vs Free-Air Temperature
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2
16
V
V
V
= 2.7 V
= 5 V
S
S
S
1.5
14
12
10
= 15 V
1
0.5
V = 3 V
I
PP
0
–0.5
–1
8
6
4
V
= 3 V
PP
O
–1.5
–2
2
0
–100
0
100 200 300 400 500 600 700
Time (µs)
10
100
1000
1 k
10 k
Frequency (Hz)
VS = 5 V
G = –1
VO = 3 VPP
f = 1 kHz
RL = 100 kΩ
CL = 10 pF
THD+N ≤ 5%
RL = 100 kΩ
CL = 10 pF
Figure 22. Inverting Small-Signal Response
Figure 21. Peak-to-Peak Output Voltage vs Frequency
0.06
0
–20
0.04
–40
–60
0.02
V = 100 mV
I
PP
0
V
= 100 mV
PP
O
–80
–0.02
–0.04
–0.06
–100
–120
–140
–100
0
100 200 300 400 500 600 700
Time (µs)
10
100
1 k
10 k
100 k
Frequency (Hz)
G = –1
VS = 5 V
G = –1
VO = 100 mVPP
f = 1 kHz
VS = 5 V
TA = 25°C
Channel 1 to 2
RL = 100 kΩ
CL = 10 pF
RL = 2 kΩ
CL = 10 pF
Figure 23. Inverting Large-Signal Response
Figure 24. Crosstalk vs Frequency
10
Copyright © 2015, Texas Instruments Incorporated
TLV27L2-Q1
www.ti.com.cn
ZHCSEH4A –SEPTEMBER 2015–REVISED DECEMBER 2015
8 Detailed Description
8.1 Overview
The TLV27L2-Q1 device is a micropower, rail-to-rail output, operational amplifier. This device operates from 2.7
V to 16 V, is unity-gain stable, and is suitable for a wide range of general-purpose applications. The class AB
output stage is capable of driving ≤ 10-kΩ loads connected to any point between V+ and ground. The input
common-mode voltage range includes the negative rail and allows the TLV27L2-Q1 device to be used in virtually
any single-supply application from 2.7 V to 16 V. The typical supply current of 7 µA makes the TLV27L2-Q1
device an excellent choice for battery operated systems.
8.2 Functional Block Diagram
+IN
PMOS
Input
Stage
-IN
Output
Stage
OUT
NMOS
Input
Stage
8.3 Feature Description
8.3.1 Offset Voltage
The output offset voltage (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. Use the schematic and formula in Figure 25 to calculate the output offset voltage.
R
F
I
IB–
R
G
+
–
æ
ç
R
R
ö
æ
ç
R
R
ö
æ
ç
è
F ö
÷÷
G ø
æ
ç
è
F ö
÷÷
G ø
V
I
VOO = VIO 1 +
è
IIB + RS 1 +
è
IIB RF
-
+
ø
ø
R
S
I
IB+
Figure 25. Output Offset Voltage Model
8.4 Device Functional Modes
The TLV27L2-Q1 device is powered on when the supply is connected. The device can be operated as a single-
supply operational amplifier or a dual-supply amplifier, depending on the application. The TLV27L2-Q1 device
operates from power supplies as low as 2.7 V or as high as 16 V.
Copyright © 2015, Texas Instruments Incorporated
11
TLV27L2-Q1
ZHCSEH4A –SEPTEMBER 2015–REVISED DECEMBER 2015
www.ti.com.cn
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 General Configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way limit the bandwidth is to place an RC filter at the noninverting terminal of the amplifier as
shown in Figure 26.
R
R
F
G
VO
VI
RF
R
1
æ
öæ
֍
ö
÷
ø
= 1+
è
ç
1+sR1C1
G øè
V
DD
/2
–
V
O
1
+
V
I
f-3dB
=
R1
2pR1C1
C1
Figure 26. Single-Pole Low-Pass Filter
If even more attenuation is required, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do select an amplifier with an appropriate bandwidth can result in phase shift of the amplifier.
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
+
_
V
I
1
R1
R2
f
=
3dB
-
C2
2pRC
R
R
F
RF
R
G
RG =
1
æ
ö
2 -
ç
÷
ø
Q
è
V
DD
/2
Figure 27. 2-Pole Low-Pass Sallen-Key Filter
9.2 Typical Application
This single-supply low-side, bi-directional current sensing solution can accurately detect load currents from –1 A
to +1 A. The linear range of the output is from 110 mV to 3.19 V. The design uses the TLV27L2-Q1 device
configured as a difference amplifier and reference voltage buffer.
Low-side current sensing is desirable because the common-mode voltage is near ground. Therefore the current
sensing solution is independent of the bus voltage, VBUS. When sensing bidirectional currents, a reference
voltage must be added to differentiate between positive and negative currents. Figure 28 shows a general circuit
topology for a low-side, bidirectional current-sensing solution. This topology is particularly useful when cost is a
priority at the expense of accuracy and printed circuit board (PCB) space. The shunt voltage (VSHUNT) is created
12
Copyright © 2015, Texas Instruments Incorporated
TLV27L2-Q1
www.ti.com.cn
ZHCSEH4A –SEPTEMBER 2015–REVISED DECEMBER 2015
Typical Application (continued)
by the load current (ILOAD) flowing through the shunt resistor (RSHUNT). The VSHUNT voltage is amplified by an op
amp (U1A) according to the gain set by the ratio of R4 to R3. To achieve the transfer function in Equation 1 and
to minimize errors, set R4 equal to R2 and R3 equal to R1. To provide the reference voltage in this design, divide
down the supply voltage (VCC) using R5 and R6. The reference voltage is then buffered using an additional op
amp (U1B).
VOUT = VSHUNT × GainDiff_Amp + Vref
(1)
V
CC
V
CC
V
ref
R5
R6
œ
+
U1B
I
LOAD
R2
R1
R3
+
+
+
V
V
R
SHUNT
OUT
SHUNT
V
BUS
œ
œ
U1A
œ
V
CC
R
L
R4
Figure 28. Application Schematic ±1-A Single-Supply Low-Side Current Sensing Solution
9.2.1 Design Requirements
The design requirements are as follows:
Supply voltage: 3.3 V
Input: –1 A to +1 A
Output: 110 mV to 3.19 V
Maximum shunt voltage: ±100 mV
9.2.2 Detailed Design Procedure
9.2.2.1 Shunt Resistor (RSHUNT
)
As shown in Figure 28, the value of VSHUNT is the ground potential for the system load. If the value of VSHUNT is
too large, it can cause issues when interfacing with systems with a true ground potential of 0 V. If the value of
VSHUNT is too negative, it can violate the input common-mode voltage of the differential amplifier in addition to
potential interfacing issues. Therefore, limit the voltage across the shunt resistor. Use Equation 2 to calculate the
maximum value of RSHUNT given a maximum shunt voltage of 100 mV.
VSHUNT(MAX)
100 mV
RSHUNT(MAX)
=
=
= 100 mW
1 A
ILOAD(MAX)
(2)
Because cost is a priority in this design, a shunt resistor with a 0.5% tolerance was selected.
Copyright © 2015, Texas Instruments Incorporated
13
TLV27L2-Q1
ZHCSEH4A –SEPTEMBER 2015–REVISED DECEMBER 2015
www.ti.com.cn
Typical Application (continued)
9.2.2.2 Operational Amplifiers
The shunt voltage in this design can range from –100 mV to +100 mV. The shut voltage is divided down by the
resistors, R1 and R2. The op amp configured as a difference amplifier (U1A) must have an input common-mode
that includes this voltage range. Therefore an op amp with rail-to-rail input (RRI) that extends below V– is
recommended. The output swing of the amplifier should also be rail-to-rail output (RRO) to maximize the
dynamic range of the system. Use of a CMOS op amp is recommended because the supply voltage is 3.3 V. The
supply-splitter op amp (U1B) should have low offset voltage. Because this design includes two op amps, a dual
package minimizes the required area. This design uses the TLV27L2-Q1 device because it is a RRO CMOS
device. In addition, the cost versus performance of the device is excellent.
9.2.2.3 Reference Voltage Resistors (R5-R6)
Because the load current range is symmetric (–1 A to +1 A), the resistors that divide down the supply voltage
should be equal so that the reference voltage is the mid supply ([(V+) – (V–)] / 2 or, for this example, (3.3 V – 0
V) / 2 = 1.65 V). Because cost is a priority in this design, the tolerance should be consistent with the shunt
resistor tolerance (0.5%). Finally, select resistors that are large enough to meet the power consumption
requirement of the system. For this design, 10-kΩ resistors were selected.
9.2.2.4 Difference Amplifier Gain Setting Resistors (R1-R4)
Equation 3 and Equation 4 show the input common-mode (VCM) and output voltage range (VOUT) of the
TLV27L2-Q1 device given a 3.3-V supply.
–200 mV < VCM < 2.1 V
100 mV < VOUT < 3.2 V
(3)
(4)
Use Equation 5 to calculate the gain.
VOUT _MAX - VOUT _MIN
3.2 V -100 mV
V
V
GainDiff _ Amp
=
=
= 15.5
RSHUNT ´ I
(
-IMIN
100 mW ´ 1 A - 1 A
( )
)
(
)
MAX
(5)
The selected value for the R1 and R3 resistors was 1 kΩ. The selected value for the R2 and R4 resistors was
15.4 kΩ, which is the nearest 0.1% value to the ideal value of 15.5 kΩ. Therefore, the ideal gain of the difference
amplifier is 15.4 V/V.
9.2.3 Application Curve
Figure 29 shows the measured transfer function of the design.
3.3
y = 1.4471x + 1.6177
1.65
0
-1
-0.5
0
0.5
1
Load Current (A)
D001
Figure 29. Measured Output Voltage vs Load Current (Board 1)
14
Copyright © 2015, Texas Instruments Incorporated
TLV27L2-Q1
www.ti.com.cn
ZHCSEH4A –SEPTEMBER 2015–REVISED DECEMBER 2015
10 Power Supply Recommendations
The TLV27L2-Q1 device is specified for operation from 2.7 V to 16 V (±1.35 V to ±8 V); many specifications
apply from –40°C to +125°C. The Typical Characteristics presents parameters that can exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 16.5 V can permanently damage the device (see the
Absolute Maximum Ratings table).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
Guidelines section.
11 Layout
11.1 Layout Guidelines
To achieve the levels of high performance of the TLV27L2-Q1 device, follow proper printed-circuit board design
techniques. The following list is a general set of guidelines:
•
Ground planes—Using a ground plane on the board is highly recommended to provide all components with a
low inductive-ground connection. However, in the areas of the amplifier inputs and output, the ground plane
can be removed to minimize the stray capacitance.
•
Proper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor
on each supply terminal. Sharing the tantalum capacitor among several amplifiers is possible depending on
the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every
amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As
this distance increases, the inductance in the connecting trace makes the capacitor less effective. The
designer should strive for distances of less than 0.1 inches between the device power terminals and the
ceramic capacitors.
•
•
Sockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board are
the best implementation.
Short trace runs and compact part placements—Optimum high performance is achieved when stray series
inductance has been minimized. To achieve this performance, the circuit layout should be as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. The length should be kept as short as possible which helps minimize stray capacitance
at the input of the amplifier.
•
Surface-mount passive components—Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, keep the lead lengths as short as possible.
Copyright © 2015, Texas Instruments Incorporated
15
TLV27L2-Q1
ZHCSEH4A –SEPTEMBER 2015–REVISED DECEMBER 2015
www.ti.com.cn
11.2 Layout Example
Place components close
to device and to each
other to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
N/C
N/C
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
œIN
+IN
Vœ
V+
OUTPUT
N/C
VIN
GND
GND
VSœ
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Copyright © 2017, Texas Instruments Incorporated
Figure 30. TLV27L2-Q1 Layout Example
11.3 General Power Dissipation Considerations
Use to calculate the maximum power dissipation for a given θJA.
T
MAX -TA
æ
ç
è
ö
÷
ø
PD =
qJA
where
•
•
•
•
PD = Maximum power dissipation of TLV27L2-Q1 IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA = Free-ambient air temperature (°C)
θJA = θJC + θCA
–
–
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
16
版权 © 2015, Texas Instruments Incorporated
TLV27L2-Q1
www.ti.com.cn
ZHCSEH4A –SEPTEMBER 2015–REVISED DECEMBER 2015
General Power Dissipation Considerations (continued)
2
1.75
1.5
Low-K Test PCB
= 176°C/W
1.25
1
θ
JA
0.75
0.5
0.25
0
–55 –40 –25 –10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (°C)
TJ = 150°C
Results are with no air flow and using JEDEC Standard
Low-K test PCB.
Figure 31. Maximum Power Dissipation vs Free-Air Temperature
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
《OPAx348-Q1 1MHz 45μA CMOS 轨到轨运算放大器》，SBOS465
《OPAx333-Q1 1.8V 微功耗 CMOS 运算放大器零漂移系列》，SBOS522
《OPA2314-Q1 3MHz、低功耗、低噪声、RRIO、1.8V CMOS 运算放大器》，SLOS896
《OPAx376-Q1 低噪声、低静态电流、高精度运算放大器 e-trim™ 系列》，SBOS549
《TLV226x-Q1 高级 LinCMOS™ CMOS 运算放大器》，SGLS193
12.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
版权 © 2015, Texas Instruments Incorporated
17
TLV27L2-Q1
ZHCSEH4A –SEPTEMBER 2015–REVISED DECEMBER 2015
www.ti.com.cn
12.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
18
版权 © 2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV27L2QDRQ1
ACTIVE
SOIC
D
8
2500 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
27L2Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV27L2QDRQ1
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
340.5 336.1 25.0
TLV27L2QDRQ1
D
8
2500
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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