TLV316IDBVR [TI]
Single, 5.5-V, 10-MHz, RRIO operational amplifier | DBV | 5 | -40 to 125;
| 型号： | TLV316IDBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Single, 5.5-V, 10-MHz, RRIO operational amplifier | DBV | 5 | -40 to 125 |
| 文件： | 总39页 (文件大小：1804K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV316, TLV2316, TLV4316
ZHCSEN0A –FEBRUARY 2016–REVISED SEPTEMBER 2016
TLVx316
10MHz、轨到轨输入/输出、低电压、1.8V CMOS 运算放大器
1 特性
3 说明
1
•
单位增益带宽：10MHz
低 IQ：每通道 400µA
TLV316（单路）、TLV2316（双路）和 TLV4316（四
路）器件构成了低功耗、通用运算放大器系列。该系列
器件 特有轨到轨输入和输出摆幅，并且兼具低静态电
流（每通道的典型值为 400μA）、10MHz 的较宽带宽
和超低噪声（1kHz 时为 12 nV/√Hz），因此对于要求
在成本和性能间达到良好平衡的各类电池供电 应用 而
言极具吸引力。低输入偏置电流支持在 源阻抗高达兆
欧级的 应用中使用此类运算放大器。
•
–
–
出色的功率带宽比
在温度和电源电压范围内保持稳定的 IQ
•
•
•
•
•
•
•
宽电源电压范围：1.8V 至 5.5V
低噪声：1kHz 时为 12nV/√Hz
低输入偏置电流：±10pA
偏移电压：±0.75mV
单位增益稳定
TLVx316 采用稳健耐用的设计，方便电路设计人员使
用。该器件具有单位增益稳定的集成 RFI/EMI 抑制滤
波器，在过驱条件下不会出现反相，并且具有高静电放
电 (ESD) 保护 (4kV HBM)。
内部射频干扰 (RFI)/电磁干扰 (EMI) 滤波器
扩展温度范围：-40°C 至 +125°C
2 应用范围
此类器件经过优化，适合在 1.8V (±0.9V) 至 5.5V
(±2.75V) 的低电压状态下工作。这些最新补充的低电
压互补金属氧化物半导体 (CMOS) 运算放大器与
TLVx313 和 TLVx314 系列搭配，为用户提供了广泛的
带宽、噪声和功率选择，可以满足各种 应用的需求。
•
电池供电仪器：
–
–
消费类应用、工业应用、医疗应用
笔记本电脑、便携式媒体播放器
•
•
•
•
传感器信号调节
条形码扫描器
有源滤波器
音频
器件信息(1)
器件型号
TLV316
封装
SC70 (5)
封装尺寸（标称值）
1.25mm × 2.00mm
1.60mm x 2.90mm
3.00mm × 3.00mm
3.91mm x 4.90mm
4.40mm × 5.00mm
8.65mm x 3.91mm
SOT-23 (5)
VSSOP (8)
SOIC (8)
TLV2316
TLV4316
TSSOP (14)
SOIC (14)
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
RG
RF
120
100
80
270
225
180
135
90
R1
VOUT
60
VIN
Phase
40
C1
1
2pR1C1
20
45
f
=
-3 dB
V
VS = ±2.75 V
0
0
Gain
VS =±0.9V
VOUT
VIN
RF
œ20
-45
1
1 + sR1C1
=
1 +
(
(
1
10
100
1k
10k
100k
1M
10M 100M
RG
Frequency (Hz)
C006
单极低通滤波器
10MHz 带宽下的低电源电流（400µA/通道）
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS752
TLV316, TLV2316, TLV4316
ZHCSEN0A –FEBRUARY 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
目录
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 System Examples ................................................... 16
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information: TLV316 ................................... 7
7.5 Thermal Information: TLV2316 ................................. 7
7.6 Thermal Information: TLV4316 ................................. 7
7.7 Electrical Characteristics........................................... 8
7.8 Typical Characteristics.............................................. 9
7.9 Typical Characteristics............................................ 10
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 13
9
10 Power Supply Recommendations ..................... 17
10.1 Input and ESD Protection ..................................... 17
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 18
12 器件和文档支持 ..................................................... 19
12.1 文档支持................................................................ 19
12.2 相关链接................................................................ 19
12.3 社区资源................................................................ 19
12.4 商标....................................................................... 19
12.5 静电放电警告......................................................... 20
12.6 Glossary................................................................ 20
13 机械、封装和可订购信息....................................... 20
8
4 修订历史记录
Changes from Original (February 2016) to Revision A
Page
•
•
•
已添加 14 引脚 SOIC 封装信息至器件信息表......................................................................................................................... 1
Added D package to PW package pinout drawing ................................................................................................................ 5
Added D (SOIC) thermal values to Thermal Information: TLV4316 table ............................................................................. 7
2
Copyright © 2016, Texas Instruments Incorporated
TLV316, TLV2316, TLV4316
www.ti.com.cn
ZHCSEN0A –FEBRUARY 2016–REVISED SEPTEMBER 2016
5 Device Comparison Table
PACKAGE-LEADS
NO. OF
DEVICE
TLV316
CHANNELS
DBV
5
DCK
5
D
—
8
DGK
—
PW
—
1
2
4
TLV2316
TLV4316
—
—
8
—
—
—
14
—
14
6 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
DCK Package
5-Pin SC70
Top View
OUT
V-
1
2
3
5
4
V+
+IN
1
2
3
5
4
V+
V-
+IN
-IN
-IN
OUT
Pin Functions: TLV316
PIN
I/O
DESCRIPTION
NAME
–IN
DBV (SOT-23) DCK (SC70)
4
3
1
2
5
3
1
4
2
5
I
Inverting input
Noninverting input
Output
+IN
I
OUT
V–
O
—
—
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
V+
Copyright © 2016, Texas Instruments Incorporated
3
TLV316, TLV2316, TLV4316
ZHCSEN0A –FEBRUARY 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
D, DGK Packages
8-Pin SOIC, VSSOP
Top View
OUT A
-IN A
+IN A
V-
1
2
3
4
8
7
6
5
V+
OUT B
-IN B
+IN B
Pin Functions: TLV2316
PIN
I/O
DESCRIPTION
NO.
2
NAME
–IN A
+IN A
–IN B
+IN B
OUT A
OUT B
V–
I
I
Inverting input, channel A
3
Noninverting input, channel A
Inverting input, channel B
Noninverting input, channel B
Output, channel A
6
I
5
I
1
O
O
—
—
7
Output, channel B
4
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
8
V+
4
Copyright © 2016, Texas Instruments Incorporated
TLV316, TLV2316, TLV4316
www.ti.com.cn
ZHCSEN0A –FEBRUARY 2016–REVISED SEPTEMBER 2016
D, PW Packages
14-Pin SOIC, TSSOP
Top View
OUT A
-IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
A
D
13 -IN D
12 +IN D
11 V-
+IN B
-IN B
OUT B
10 +IN C
9
8
-IN C
B
C
OUT C
Pin Functions: TLV4316
PIN
I/O
DESCRIPTION
NO.
2
NAME
–IN A
+IN A
–IN B
+IN B
–IN C
+IN C
–IN D
+IN D
OUT A
OUT B
OUT C
OUT D
V–
I
I
Inverting input, channel A
3
Noninverting input, channel A
Inverting input, channel B
Noninverting input, channel B
Inverting input, channel C
Noninverting input, channel C
Inverting input, channel D
Noninverting input, channel D
Output, channel A
6
I
5
I
9
I
10
13
12
1
I
I
I
O
O
O
O
—
—
7
Output, channel B
8
Output, channel C
14
11
4
Output, channel D
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
V+
Copyright © 2016, Texas Instruments Incorporated
5
TLV316, TLV2316, TLV4316
ZHCSEN0A –FEBRUARY 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)(1)
MIN
(V–) – 0.5
–10
MAX
7
UNIT
Supply voltage
V
Common-mode
Voltage(2)
(V+) + 0.5
V
Signal input pins
Differential
(V+) – (V–) + 0.2
10
Current(2)
Output short-circuit(3)
Specified, TA
mA
mA
Continuous
–40
125
150
150
Temperature
Junction, TJ
Storage, Tstg
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply
rails to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
over operating free-air temperature range (unless otherwise noted)
VALUE
±4000
±1500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.8
NOM
MAX UNIT
VS
Supply voltage
5.5
V
Specified temperature range
–40
125
°C
6
Copyright © 2016, Texas Instruments Incorporated
TLV316, TLV2316, TLV4316
www.ti.com.cn
ZHCSEN0A –FEBRUARY 2016–REVISED SEPTEMBER 2016
7.4 Thermal Information: TLV316
TLV316
THERMAL METRIC(1)
DBV (SOT-23)
5 PINS
221.7
DCK (SC70)
5 PINS
263.3
75.5
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
144.7
49.7
51.0
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
26.1
1.0
ψJB
49.0
50.3
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).
7.5 Thermal Information: TLV2316
TLV2316
THERMAL METRIC(1)
D (SOIC)
8 PINS
127.2
71.6
DGK (VSSOP)
8 PINS
186.6
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
78.8
68.2
107.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
22.0
15.5
ψJB
67.6
106.3
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).
7.6 Thermal Information: TLV4316
TLV4316
THERMAL METRIC(1)
PW (TSSOP)
14 PINS
117.2
46.2
D (SOIC)
14 PINS
87.0
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
44.4
58.9
41.7
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
4.9
11.6
ψJB
58.3
41.4
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).
Copyright © 2016, Texas Instruments Incorporated
7
TLV316, TLV2316, TLV4316
ZHCSEN0A –FEBRUARY 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
7.7 Electrical Characteristics
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted); VS (total supply
voltage) = (V+) – (V–) = 1.8 V to 5.5 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VS = 5 V
±0.75
±3
VOS
Input offset voltage
mV
VS = 5 V, TA = –40°C to +125°C
VS = 5 V, TA = –40°C to +125°C
VS = 1.8 V – 5.5 V, VCM = (V–)
At dc
±4.5
dVOS/dT Drift
PSRR Power-supply rejection ratio
Channel separation, dc
INPUT VOLTAGE RANGE
±2
±30
100
µV/°C
µV/V
dB
±175
VCM
Common-mode voltage range
VS = 5.5 V
(V–) – 0.2
72
(V+) + 0.2
V
VS = 5.5 V, (V–) – 0.2 V < VCM < (V+) – 1.4 V,
TA = –40°C to +125°C
90
75
CMRR
Common-mode rejection ratio
dB
VS = 5.5 V, VCM = –0.2 V to 5.7 V,
TA = –40°C to +125°C
INPUT BIAS CURRENT
IB
Input bias current
Input offset current
±10
±10
pA
pA
IOS
NOISE
En
Input voltage noise (peak-to-peak)
Input voltage noise density
Input current noise density
VS = 5 V, f = 0.1 Hz to 10 Hz
VS = 5 V, f = 1 kHz
f = 1 kHz
5
12
µVPP
nV/√Hz
fA/√Hz
en
in
1.3
INPUT IMPEDANCE
1016Ω || pF
1011Ω || pF
ZID
ZIC
Differential
2 || 2
2 || 4
Common-mode
OPEN-LOOP GAIN
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
RL = 10 kΩ
100
104
104
AOL
Open-loop voltage gain
dB
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
RL = 2 kΩ
FREQUENCY RESPONSE
GBP
φm
Gain bandwidth product
VS = 5 V, G = +1
10
MHz
Degrees
V/μs
μs
Phase margin
Slew rate
VS = 5 V, G = +1
60
SR
tS
VS = 5 V, G = +1
6
1
Settling time
To 0.1%, VS = 5 V, 2-V step , G = +1, CL = 100 pF
VS = 5 V, VIN × gain = VS
tOR
Overload recovery time
0.8
μs
THD + N Total harmonic distortion + noise(1)
VS = 5 V, VO = 0.5 VRMS, G = +1, f = 1 kHz
0.008%
OUTPUT
VS = 1.8 V to 5.5 V, RL = 10 kΩ,
VS = 1.8 to 5.5 V, RL = 2 kΩ,
VS = 5 V
35
Voltage output swing from supply
rails
VO
mV
125
ISC
ZO
Short-circuit current
±50
250
mA
Open-loop output impedance
VS = 5 V, f = 10 MHz
Ω
POWER SUPPLY
VS
IQ
Specified voltage range
Quiescent current per amplifier
1.8
5.5
V
VS = 5 V, IO = 0 mA, TA = –40°C to 125°C
400
575
µA
TEMPERATURE
TA
Specified
Storage
–40
–65
125
150
°C
°C
Tstg
(1) Third-order filter; bandwidth = 80 kHz at –3 dB.
8
Copyright © 2016, Texas Instruments Incorporated
TLV316, TLV2316, TLV4316
www.ti.com.cn
ZHCSEN0A –FEBRUARY 2016–REVISED SEPTEMBER 2016
7.8 Typical Characteristics
Table 1. Table of Graphs
TITLE
FIGURE
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Offset Voltage Production Distribution
Offset Voltage vs Common-Mode Voltage
Open- Loop Gain and Phase vs Frequency
Input Bias and Offset Current vs Temperature
Input Voltage Noise Spectral Density vs Frequency
Quiescent Current vs Supply Voltage
Small-Signal Overshoot vs Load Capacitance
No Phase Reversal
Small-Signal Step Response
Large-Signal Step Response
Short-Circuit Current vs Temperature
Electromagnetic Interference Rejection Ratio Referred to Noninverting Input vs Frequency
Channel Separation vs Frequency
Figure 12
Figure 13
Copyright © 2016, Texas Instruments Incorporated
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TLV316, TLV2316, TLV4316
ZHCSEN0A –FEBRUARY 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
7.9 Typical Characteristics
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
25
20
15
10
5
2500
2000
1500
1000
500
VCM = 2.95 V
VCM = -2.95 V
0
œ500
œ1000
œ1500
œ2000
œ2500
N-
Channel
P-
Channel
Transition
2
0
0
1
3
œ3
œ2
œ1
VCM (V)
C001
Offset Voltage (mV)
C013
V+ = 2.75 V, V– = –2.75 V, 9 typical units shown
Distribution taken from 12551 amplifiers
Figure 1. Offset Voltage Production Distribution
Figure 2. Offset Voltage vs Common-Mode Voltage
120
100
80
270
100000
IB+
IB -
Ios
225
180
135
90
10000
1000
100
10
60
Phase
40
20
45
VS = ±2.75 V
0
0
Gain
1
VS =±0.9V
œ20
-45
1
10
100
1k
10k
100k
1M
10M 100M
0
Frequency (Hz)
C006
0
25
50
75
100 125 150
œ75 œ50 œ25
VCM < (V+) – 1.4 V
Temperature (°C)
C001
Figure 3. Open-Loop Gain and Phase vs Frequency
Figure 4. Input Bias and Offset Current vs Temperature
1000
100
10
450
425
400
375
350
325
300
275
250
1
0.1
1
10
100
1k
10k
100k
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
C015
Supply Voltage (V)
Frequency (Hz)
C001
Figure 5. Input Voltage Noise Spectral Density vs Frequency
Figure 6. Quiescent Current vs Supply Voltage
10
Copyright © 2016, Texas Instruments Incorporated
TLV316, TLV2316, TLV4316
www.ti.com.cn
ZHCSEN0A –FEBRUARY 2016–REVISED SEPTEMBER 2016
Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
50
VIN
40
VOUT
30
+ 2.75 V
RI = 1 kohm
RF = 1 kohm
+ 2.75 V
œ
20
10
0
Device
VOUT
+
œ
+
+
Device
œ 2.75 V
VIN = 100 mVpp
+
6.1 VPP
Sine Wave
œ
CL
œ
œ 2.75 V
Time (100 ꢀs/div)
0p
100p
200p
300p
C027
Capacitive Load (F)
C025
V+ = 2.75 V, V– = –2.75 V
V+ = 2.75 V, V– = –2.75 V, G = –1 V/V
Figure 8. No Phase Reversal
Figure 7. Small-Signal Overshoot vs Load Capacitance
+
2.75
V
V
CL = 10 pF
œ
Device
CL = 100 pF
+
+
VIN
= 1 Vpp
RL
CL
œ
2.75
œ
VOUT
+ 2.75 V
œ
Device
+
+
VIN = 100 mVpp
RL
CL
œ 2.75 V
œ
VIN
Time (100 ns/div)
Time (200 ns/div)
C030
C031
V+ = 2.75 V, V– = –2.75 V, G = 1 V/V
V+ = 2.75 V, V– = –2.75 V, CL = 100 pF, G = 1 V/V
Figure 9. Small-Signal Step Response
Figure 10. Large-Signal Step Response
70
60
50
40
30
100
80
60
40
20
0
ISC, Source
ISC, Sink
10M
100M
Frequency (Hz)
1G
10G
0
25
50
75
100 125 150
œ75 œ50 œ25
C036
Temperature (°C)
C001
PRF = –10 dBm
Figure 12. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input vs Frequency
Figure 11. Short-Circuit Current vs Temperature
Copyright © 2016, Texas Instruments Incorporated
11
TLV316, TLV2316, TLV4316
ZHCSEN0A –FEBRUARY 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
0
œ20
œ40
œ60
œ80
œ100
œ120
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
C001
V+ = 2.75 V, V– = –2.75 V
Figure 13. Channel Separation vs Frequency
12
Copyright © 2016, Texas Instruments Incorporated
TLV316, TLV2316, TLV4316
www.ti.com.cn
ZHCSEN0A –FEBRUARY 2016–REVISED SEPTEMBER 2016
8 Detailed Description
8.1 Overview
The TLVx316 is a family of low-power, rail-to-rail input and output operational amplifiers. These devices operate
from 1.8 V to 5.5 V, are unity-gain stable, and are suitable for a wide range of general-purpose applications. The
class AB output stage is capable of driving ≤ 10-kΩ loads connected to any point between V+ and ground. The
input common-mode voltage range includes both rails and allows the TLVx316 to be used in virtually any single-
supply application. Rail-to-rail input and output swing significantly increases dynamic range, especially in low-
supply applications, and makes them suitable for driving sampling analog-to-digital converters (ADCs).
The TLVx316 features 10-MHz bandwidth and 6-V/μs slew rate with only 400-μA supply current per channel,
providing good ac performance at very-low power consumption. DC applications are well served with a very-low
input noise voltage of 12 nV/√Hz at 1 kHz, low input bias current (5 pA), and an input offset voltage of 0.5 mV
(typical).
8.2 Functional Block Diagram
V+
Reference
Current
VIN+
VIN-
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V-
(Ground)
Copyright © 2016, Texas Instruments Incorporated
13
TLV316, TLV2316, TLV4316
ZHCSEN0A –FEBRUARY 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
8.3 Feature Description
8.3.1 Operating Voltage
The TLVx316 operational amplifiers are fully specified and ensured for operation from 1.8 V to 5.5 V. In addition,
many specifications apply from –40°C to +125°C. Parameters that vary significantly with operating voltages or
temperature are illustrated in the Typical Characteristics section.
8.3.2 Rail-to-Rail Input
The input common-mode voltage range of the TLVx316 extends 200 mV beyond the supply rails for supply
voltages greater than 2.5 V. This performance is achieved with a complementary input stage: an N-channel input
differential pair in parallel with a P-channel differential pair; see the Functional Block Diagram section. The N-
channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 200 mV above the
positive supply, whereas the P-channel pair is active for inputs from 200 mV below the negative supply to
approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in which both
pairs are on. This 200-mV transition region can vary up to 200 mV with process variation. Thus, the transition
region (both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, up to (V+) – 1 V to (V+) –
0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift, and THD can be
degraded compared to device operation outside this region.
8.3.3 Rail-to-Rail Output
Designed as a low-power, low-voltage operational amplifier, the TLVx316 delivers a robust output drive
capability. A class AB output stage with common-source transistors is used to achieve full rail-to-rail output swing
capability. For resistive loads of 10 kΩ, the output swings typically to within 30 mV of either supply rail regardless
of the power-supply voltage applied. Different load conditions change the ability of the amplifier to swing close to
the rails; see typical characteristic graph Output Voltage Swing vs Output Current ().
8.3.4 Common-Mode Rejection Ratio (CMRR)
CMRR for the TLVx316 is specified in two ways so the best match for a given application can be selected. First,
the Electrical Characteristics table provides the CMRR of the device in the common-mode range below the
transition region [VCM < (V+) – 1.4 V]. This specification is the best indicator of device capability when the
application requires using one of the differential input pairs. Second, the CMRR over the entire common-mode
range is specified at VCM = –0.2 V to 5.7 V for VS = 5.5 V. This last value includes the variations through the
transition region.
8.3.5 Capacitive Load and Stability
The TLVx316 is designed to be used in applications where driving a capacitive load is required. As with all
operational amplifiers, there may be specific instances where the TLVx316 can become unstable. The particular
operational amplifier circuit configuration, layout, gain, and output loading are some of the factors to consider
when establishing whether or not an amplifier is stable in operation. An operational amplifier in the unity-gain
(1 V/V) buffer configuration that drives a capacitive load exhibits a greater tendency to be unstable than an
amplifier operated at a higher noise gain. The capacitive load, in conjunction with the operational amplifier output
resistance, creates a pole within the feedback loop that degrades the phase margin. The degradation of the
phase margin increases when the capacitive loading increases. For a conservative best practice, designing for
25% overshoot (40° phase margin) provides improved stability over process variations. The equivalent series
resistance (ESR) of some very-large capacitors (CL greater than 1 μF) is sufficient to alter the phase
characteristics in the feedback loop such that the amplifier remains stable. Increasing the amplifier closed-loop
gain allows the amplifier to drive increasingly larger capacitance. This increased capability is evident when
observing the overshoot response of the amplifier at higher voltage gains. See typical characteristic graph,
Small-Signal Overshoot vs Capacitive Load (Figure 7, G = –1 V/V).
14
Copyright © 2016, Texas Instruments Incorporated
TLV316, TLV2316, TLV4316
www.ti.com.cn
ZHCSEN0A –FEBRUARY 2016–REVISED SEPTEMBER 2016
Feature Description (continued)
One technique for increasing the capacitive load drive capability of the amplifier operating in a unity-gain
configuration is to insert a small resistor (typically 10 Ω to 20 Ω) in series with the output, as shown in Figure 14.
This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. One possible
problem with this technique, however, is that a voltage divider is created with the added series resistor and any
resistor connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output
that reduces the output swing.
V+
RS
VOUT
Device
VIN
10 W to
20 W
RL
CL
Figure 14. Improving Capacitive Load Drive
8.3.6 EMI Susceptibility and Input Filtering
Operational amplifiers vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If
conducted EMI enters the operational amplifier, the dc offset measured at the amplifier output can shift from its
nominal value when EMI is present. This shift is a result of signal rectification associated with the internal
semiconductor junctions. Although all operational amplifier pin functions can be affected by EMI, the signal input
pins are likely to be the most susceptible. The TLVx316 operational amplifier family incorporates an internal input
low-pass filter that reduces the amplifier response to EMI. This filter provides both common-mode and
differential-mode filtering. The filter is designed for a cutoff frequency of approximately 80 MHz (–3 dB), with a
roll-off of 20 dB per decade.
The immunity of an operational amplifier can be accurately measured and quantified over a broad frequency
spectrum extending from 10 MHz to 6 GHz. The EMI rejection ratio (EMIRR) metric allows operational amplifiers
to be directly compared by the EMI immunity. Figure 12 illustrates the results of this testing on the TLVx316.
Detailed information can be found in EMI Rejection Ratio of Operational Amplifiers (SBOA128), available for
download from www.ti.com.
8.3.7 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, either because of the high input voltage or the high gain. After the
device enters the saturation region, the charge carriers in the output devices require time to return back to the
linear state. After the charge carriers return back to the linear state, the device begins to slew at the specified
slew rate. Thus, the propagation delay in case of an overload condition is the sum of the overload recovery time
and the slew time. The overload recovery time for the TLVx316 is approximately 300 ns.
8.4 Device Functional Modes
The TLVx316 have a single functional mode. These devices are powered on as long as the power-supply voltage
is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
Copyright © 2016, Texas Instruments Incorporated
15
TLV316, TLV2316, TLV4316
ZHCSEN0A –FEBRUARY 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLV316, TLV2316, and TLV4316 are powered on when the supply is connected. The devices can be
operated as a single-supply operational amplifier or a dual-supply amplifier, depending on the application.
9.2 System Examples
When receiving low-level signals, the device often requires limiting the bandwidth of the incoming signals into the
system. The simplest way to establish this limited bandwidth is to place an RC filter at the noninverting pin of the
amplifier, as shown in Figure 15.
RG
RF
R1
VOUT
VIN
C1
1
2pR1C1
f
=
-3 dB
VOUT
VIN
RF
1
1 + sR1C1
=
1 +
(
(
RG
Figure 15. Single-Pole, Low-Pass Filter
If even more attenuation is needed, the device requires a multiple-pole filter. The Sallen-Key filter can be used
for this task, as shown in Figure 16. For best results, the amplifier must have a bandwidth that is eight to ten
times the filter frequency bandwidth. Failure to follow this guideline can result in a phase shift of the amplifier.
C1
R1 = R2 = R
C1 = C2 = C
R1
R2
Q = Peaking factor
(Butterworth Q = 0.707)
VIN
VOUT
C2
1
2pRC
f
=
-3 dB
RF
RF
RG
=
1
2 -
RG
(
(
Q
Figure 16. Two-Pole, Low-Pass, Sallen-Key Filter
16
Copyright © 2016, Texas Instruments Incorporated
TLV316, TLV2316, TLV4316
www.ti.com.cn
ZHCSEN0A –FEBRUARY 2016–REVISED SEPTEMBER 2016
10 Power Supply Recommendations
The TLVx316 is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply from
–40°C to +125°C. Typical Characteristics presents parameters that can exhibit significant variance with regard to
operating voltage or temperature.
CAUTION
Supply voltages larger than 7 V can permanently damage the device (see the Absolute
Maximum Ratings table).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see Layout
Guidelines.
10.1 Input and ESD Protection
The TLVx316 incorporates internal ESD protection circuits on all pins. For input and output pins, this protection
primarily consists of current-steering diodes connected between the input and power-supply pins. These ESD
protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to 10 mA, as
stated in the Absolute Maximum Ratings table. Figure 17 shows how a series input resistor can be added to the
driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and its
value must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA max
VOUT
Device
VIN
5 kW
Figure 17. Input Current Protection
Copyright © 2016, Texas Instruments Incorporated
17
TLV316, TLV2316, TLV4316
ZHCSEN0A –FEBRUARY 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the
operational amplifier. Bypass capacitors reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of the circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to
physically separate digital and analog grounds, paying attention to the flow of the ground current. For
more detailed information, see , Circuit Board Layout Techniques (SLOA089).
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than crossing in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. Keeping RF and RG close to the
inverting input minimizes parasitic capacitance, as shown in Layout Example.
Keep the length of input traces as short as possible. Remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
Place components
Run the input traces close to device and to
as far away from
the supply lines
as possible
each other to reduce
parasitic errors
VS+
RF
N/C
N/C
RG
GND
GND
œIN
+IN
Vœ
V+
OUTPUT
N/C
VIN
Use low-ESR, ceramic
bypass capacitor
GND
VSœ
Use low-ESR,
ceramic bypass
capacitor
VOUT
Ground (GND) plane on another layer
Figure 18. Operational Amplifier Board Layout for a Noninverting Configuration
18
版权 © 2016, Texas Instruments Incorporated
TLV316, TLV2316, TLV4316
www.ti.com.cn
ZHCSEN0A –FEBRUARY 2016–REVISED SEPTEMBER 2016
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档ꢀ
《TLVx313 面向成本敏感型系统的低功耗、轨到轨输入/输出、500μV 典型偏移值、1MHz 运算放大器》（文献编
号：SBOS753）。
《TLVx314 3MHz、低功耗、内部 EMI 滤波器、RRIO、运算放大器》（文献编号：SBOS754）。
《运算放大器的 EMI 抑制比》（文献编号：SBOA128）。
《QFN/SON PCB 连接》（文献编号：SLUA271）。
《四方扁平无引线逻辑器件封装》（文献编号：SCBA017）。
《电路板布局布线技巧》（文献编号：SLOA089）。
《单端输入至差分输出转换电路参考设计》（文献编号：TIPD131）。
12.2 相关链接
表 2
接。
列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买链
表 2. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
请单击此处
TLV316
TLV2316
TLV4316
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
版权 © 2016, Texas Instruments Incorporated
19
TLV316, TLV2316, TLV4316
ZHCSEN0A –FEBRUARY 2016–REVISED SEPTEMBER 2016
www.ti.com.cn
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
20
版权 © 2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV2316IDGKR
TLV2316IDGKT
TLV2316IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
12X6
12X6
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAUAG
NIPDAU
8
2500 RoHS & Green
3000 RoHS & Green
V2316
12C
TLV316IDBVR
TLV316IDBVT
TLV316IDCKR
TLV316IDCKT
TLV4316IDR
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
D
5
NIPDAU | SN
NIPDAU | SN
NIPDAU
5
250
3000 RoHS & Green
250 RoHS & Green
RoHS & Green
12C
5
12D
SC70
5
NIPDAU
12D
SOIC
14
14
2500 RoHS & Green
2000 RoHS & Green
NIPDAU
T4316D
TLV4316
TLV4316IPWR
TSSOP
PW
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2023
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV2316, TLV316, TLV4316 :
Automotive : TLV2316-Q1, TLV316-Q1, TLV4316-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV2316IDGKR
TLV2316IDGKT
TLV2316IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
2500
250
330.0
330.0
330.0
180.0
180.0
178.0
178.0
330.0
330.0
12.4
12.4
12.4
8.4
5.3
5.3
6.4
3.2
3.2
2.4
2.4
6.5
6.9
3.4
3.4
5.2
3.2
3.2
2.5
2.5
9.0
5.6
1.4
1.4
2.1
1.4
1.4
1.2
1.2
2.1
1.6
8.0
8.0
8.0
4.0
4.0
4.0
4.0
8.0
8.0
12.0
12.0
12.0
8.0
Q1
Q1
Q1
Q3
Q3
Q3
Q3
Q1
Q1
8
2500
3000
250
TLV316IDBVR
TLV316IDBVT
TLV316IDCKR
TLV316IDCKT
TLV4316IDR
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
D
5
5
8.4
8.0
5
3000
250
9.0
8.0
SC70
5
9.0
8.0
SOIC
14
14
2500
2000
16.4
12.4
16.0
12.0
TLV4316IPWR
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV2316IDGKR
TLV2316IDGKT
TLV2316IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
2500
250
366.0
366.0
356.0
210.0
210.0
180.0
180.0
340.5
356.0
364.0
364.0
356.0
185.0
185.0
180.0
180.0
336.1
356.0
50.0
50.0
35.0
35.0
35.0
18.0
18.0
32.0
35.0
8
2500
3000
250
TLV316IDBVR
TLV316IDBVT
TLV316IDCKR
TLV316IDCKT
TLV4316IDR
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
D
5
5
5
3000
250
SC70
5
SOIC
14
14
2500
2000
TLV4316IPWR
TSSOP
PW
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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