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TLV3202AQDGKRQ1 [TI]

双路高速低功耗比较器 | DGK | 8 | -40 to 125;
TLV3202AQDGKRQ1
型号： TLV3202AQDGKRQ1
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

双路高速低功耗比较器 | DGK | 8 | -40 to 125

放大器 光电二极管 比较器
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中文：  中文翻译
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TLV3201-Q1, TLV3202-Q1  
ZHCSFZ5A –FEBRUARY 2017–REVISED DECEMBER 2017  
TLV320x-Q1 40ns、微功耗、推挽式输出汽车比较器  
1 特性  
3 说明  
1
•
•
符合汽车应用 标准  
具有符合 AEC Q100 的下列结果：  
TLV3201-Q1 和 TLV3202-Q1 分别属于单通道和双通  
道比较器，它们实现了高速度 (40ns) 与低功耗 (40µA)  
的完美组合，两者均采用极小型封装，具有轨至轨输  
入、低偏移电压 (1mV) 和大输出驱动电流等 特性 。这  
些器件还很容易在响应时间至关重要的多种 应用 中实  
施。  
–
器件温度等级 1：环境工作温度范围为 –40°C  
至 +125°C  
–
–
–
器件 HBM ESD 分类等级 2 (TLV3201-Q1)  
器件 HBM ESD 分类等级 3A (TLV3202-Q1)  
器件 CDM ESD 分类等级 C5  
TLV320x-Q1 系列可提供单通道 (TLV3201-Q1) 和双通  
道 (TLV3202-Q1) 版本，这两个版本的器件都带有推挽  
输出。TLV3201-Q1 采用 5 引脚 SC70 封装。  
•
•
低传播延迟：40ns  
低静态电流：  
每通道 40µA  
TLV3202-Q1 采用 8 引脚 VSSOP 封装。所有器件可  
在 -40°C 至 +125°C 的扩展工业温度范围内运行。  
•
•
•
•
•
输入共模扩展范围扩展到任一电源轨之上 200mV  
低输入偏移电压：1mV  
器件信息(1)  
推挽输出  
电源范围：2.7V 至 5.5V  
器件型号  
TLV3201-Q1  
TLV3202-Q1  
封装  
SC70 (5)  
VSSOP (8)  
封装尺寸（标称值）  
2.00mm × 1.25mm  
3.00mm × 3.00mm  
小型封装：  
5 引脚 SC70 和 8 引脚 VSSOP  
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附  
录。  
2 应用  
•
•
•
•
•
•
•
•
引擎控制单元 (ECU)  
空白  
空白  
空白  
车身控制模块 (BCM)  
电池管理系统 (BMS)  
HEV/EV 逆变器和电机控制  
超声波测距和 LIDAR  
转向和牵引控制器  
乘员检测  
信息娱乐系统  
阈值检测器  
传播延迟与过驱动  
100  
VIN  
VCC  
PDHL: 5 V  
PDLH: 5 V  
90  
PDHL: 2.7 V  
PDLH: 2.7 V  
80  
70  
60  
50  
40  
30  
20  
10  
0
C1  
C2  
R1  
R2  
VOUT  
VREF  
Copyright © 2016, Texas Instruments Incorporated  
20  
30  
40  
50  
60  
70  
80  
90  
100  
Input Overdrive (mV)  
G003  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
English Data Sheet: SBOS856  
 
 
 
TLV3201-Q1, TLV3202-Q1  
ZHCSFZ5A –FEBRUARY 2017–REVISED DECEMBER 2017  
www.ti.com.cn  
目录  
8.4 Device Functional Modes........................................ 11  
Application and Implementation ........................ 12  
9.1 Application Information............................................ 12  
9.2 Typical Applications ................................................ 16  
1
2
3
4
5
6
7
特性.......................................................................... 1  
应用.......................................................................... 1  
说明.......................................................................... 1  
修订历史记录 ........................................................... 2  
Device Comparison Table..................................... 2  
Pin Configuration and Functions......................... 3  
Specifications......................................................... 4  
7.1 Absolute Maximum Ratings ...................................... 4  
7.2 ESD Ratings.............................................................. 4  
7.3 Recommended Operating Conditions....................... 4  
7.4 Thermal Information.................................................. 4  
7.5 Electrical Characteristics: VCC = 5 V......................... 5  
7.6 Electrical Characteristics: VCC = 2.7 V...................... 5  
7.7 Switching Characteristics.......................................... 6  
7.8 Typical Characteristics.............................................. 7  
Detailed Description ............................................ 11  
8.1 Overview ................................................................. 11  
8.2 Functional Block Diagram ....................................... 11  
8.3 Feature Description................................................. 11  
9
10 Power Supply Recommendations ..................... 18  
11 Layout................................................................... 19  
11.1 Layout Guidelines ................................................. 19  
11.2 Layout Example .................................................... 19  
12 器件和文档支持 ..................................................... 20  
12.1 器件支持 ............................................................... 20  
12.2 文档支持 ............................................................... 20  
12.3 相关链接................................................................ 20  
12.4 接收文档更新通知 ................................................. 21  
12.5 社区资源................................................................ 21  
12.6 商标....................................................................... 21  
12.7 静电放电警告......................................................... 21  
12.8 Glossary................................................................ 21  
13 机械、封装和可订购信息....................................... 21  
8
4 修订历史记录  
注：之前版本的页码可能与当前版本有所不同。  
Changes from Original (February 2017) to Revision A  
Page  
•
Changed figure 29 ............................................................................................................................................................... 15  
5 Device Comparison Table  
DEVICE  
DESCRIPTION  
5-µA (maximum) open-drain, 1.8-V to 5.5-V with integrated voltage reference in 1.5-mm × 1.5-mm micro-sized  
packages  
TLV3011  
TLV3012  
TLV3501  
5-µA (maximum) push-pull, 1.8-V to 5.5-V with integrated voltage reference in micro-sized packages  
4.5-ns, rail-to-rail, push-pull comparator in micro-sized packages  
LMV7235  
LMV7239  
LMV7239-Q1  
REF3333  
75-ns, 65-µA, 2.7-V to 5.5-V, rail-to-rail input comparator with open-drain output  
75-ns, 65-µA, 2.7-V to 5.5-V, rail-to-rail input comparator with push-pull output  
Automotive 75-ns, 65-µA, 2.7-V to 5.5-V, rail-to-rail input comparator with push-pull output  
30-ppm/°C drift, 3.9-µA, SOT23-3, SC70-3 voltage reference  
2
Copyright © 2017, Texas Instruments Incorporated  
 
 
TLV3201-Q1, TLV3202-Q1  
www.ti.com.cn  
ZHCSFZ5A –FEBRUARY 2017–REVISED DECEMBER 2017  
6 Pin Configuration and Functions  
TLV3201-Q1 DCK Package  
5-Pin SC70-5  
Top View  
1
2
3
5
4
VCC  
OUT  
GND  
IN+  
IN-  
Pin Functions: TLV3201-Q1  
PIN  
I/O  
DESCRIPTION  
NAME  
GND  
IN–  
NO.  
2
—
I
Negative supply, ground  
4
Negative input  
Positive input  
Output  
IN+  
3
I
OUT  
VCC  
1
O
—
5
Positive supply  
TLV3202-Q1 DGK Package  
8-Pin VSSOP  
Top View  
VCC  
1OUT  
1
2
3
4
8
7
6
5
1IN-  
1IN+  
GND  
2OUT  
2IN-  
2IN+  
Pin Functions: TLV3202-Q1  
PIN  
I/O  
DESCRIPTION  
NAME  
1IN–  
1IN+  
1OUT  
2IN–  
2IN+  
2OUT  
GND  
VCC  
NO.  
2
I
I
Negative input, comparator 1  
Positive input, comparator 1  
Output, comparator 1  
3
1
O
I
6
Negative input, comparator 2  
Positive input, comparator 2  
Output, comparator 2  
5
I
7
O
—
—
4
Negative supply, ground  
Positive supply  
8
Copyright © 2017, Texas Instruments Incorporated  
3
TLV3201-Q1, TLV3202-Q1  
ZHCSFZ5A –FEBRUARY 2017–REVISED DECEMBER 2017  
www.ti.com.cn  
7 Specifications  
7.1 Absolute Maximum Ratings  
over operating free-air temperature range (unless otherwise noted)(1)  
MIN  
MAX  
7
UNIT  
Supply voltage  
Voltage  
V
Signal input pins(2)  
–0.5  
–10  
(VCC) + 0.5  
10  
Signal input pins(2)  
Output short circuit(3)  
Current  
mA  
°C  
100  
Operating  
–55  
–65  
125  
Temperature  
Junction, TJ  
Storage, Tstg  
150  
150  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended  
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be  
current limited to 10 mA or less.  
(3) Short-circuit to ground.  
7.2 ESD Ratings  
VALUE  
UNIT  
TLV3201-Q1  
V(ESD)  
Human-body model (HBM), per AEC Q100-002(1)  
Charged-device model (CDM), per AEC Q100-011  
±3000  
±750  
Electrostatic discharge  
Electrostatic discharge  
V
TLV3202-Q1  
V(ESD)  
Human-body model (HBM), per AEC Q100-002(1)  
Charged-device model (CDM), per AEC Q100-011  
±4000  
±750  
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.  
7.3 Recommended Operating Conditions  
over operating free-air temperature range (unless otherwise noted)  
MIN  
MAX  
UNIT  
VS  
TA  
Supply voltage, VS = (VS+) – (VS–  
)
2.7 (±1.35)  
–40  
5.5 (±2.75)  
125  
V
Specified temperature  
°C  
7.4 Thermal Information  
TLV3201-Q1  
DCK (SC-70)  
5 PINS  
281.9  
TLV3202-Q1  
THERMAL METRIC(1)  
DGK (VSSOP)  
8 PINS  
201.9  
UNIT  
RθJA  
RθJC(top)  
RθJB  
ψJT  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
97.6  
92.5  
68.3  
123.3  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
2.6  
23  
ψJB  
67.3  
212.6  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report.  
4
Copyright © 2017, Texas Instruments Incorporated  
 
TLV3201-Q1, TLV3202-Q1  
www.ti.com.cn  
ZHCSFZ5A –FEBRUARY 2017–REVISED DECEMBER 2017  
7.5 Electrical Characteristics: VCC = 5 V  
at TA = 25°C and VCC = 5 V (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
OFFSET VOLTAGE  
VCM = VCC / 2  
1
5
6
VIO  
Input offset voltage  
mV  
TA = –40°C to 125°C  
dVOS/dT  
PSRR  
Input offset voltage drift  
Power-supply rejection ratio  
Input hysteresis  
TA = –40°C to 125°C  
1
85  
10  
µV/°C  
dB  
VCM = VCC / 2, VCC = 2.5 V to 5.5 V  
65  
1.2  
mV  
INPUT BIAS CURRENT  
VCM = VCC / 2  
1
1
50  
5
pA  
nA  
pA  
nA  
IIB Input bias current  
TA = –40°C to 125°C  
VCM = VCC / 2  
50  
2.5  
IIO  
Input offset current  
TA = –40°C to 125°C  
INPUT VOLTAGE RANGE  
VCM  
Common-mode voltage  
Common-mode rejection ratio  
TA = –40°C to 125°C  
–0.2 V < VCM < 5.2 V  
(VEE) – 0.2  
60  
(VCC) + 0.2  
V
CMRR  
70  
dB  
INPUT IMPEDANCE  
Common mode  
1013 || 2  
1013 || 4  
Ω || pF  
Ω || pF  
Differential  
OUTPUT  
ISINK = 4 mA  
175  
120  
190  
225  
140  
170  
VOL  
Voltage output swing from lower rail  
Voltage output swing from upper rail  
mV  
mV  
TA = –40°C to 125°C  
ISOURCE = 4 mA  
TA = –40°C to 125°C  
ISC sinking  
VOH  
40  
52  
48  
See Figure 14  
60  
TA = –40°C to 125°C  
ISC sourcing  
ISC  
Short-circuit current (per comparator)  
mA  
TA = –40°C to 125°C  
See Figure 14  
POWER SUPPLY  
VCC Specified voltage  
2.7  
5.5  
50  
65  
V
TA = 25°C  
40  
IQ  
Quiescent current  
µA  
TA = –40°C to 125°C  
7.6 Electrical Characteristics: VCC = 2.7 V  
at TA = 25°C and VCC = 2.7 V (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
OFFSET VOLTAGE  
VCM = VCC / 2  
1
5
6
VIO  
Input offset voltage  
mV  
TA = –40°C to 125°C  
dVOS/dT  
PSRR  
Input offset voltage drift  
Power-supply rejection ratio  
Input hysteresis  
TA = –40°C to 125°C  
1
85  
10  
µV/°C  
dB  
VCM = VCC / 2, VCC = 2.5 V to 5.5 V  
65  
1.2  
mV  
INPUT BIAS CURRENT  
VCM = VCC / 2  
1
1
50  
5
pA  
nA  
pA  
nA  
IIB Input bias current  
TA = –40°C to 125°C  
VCM = VCC / 2  
50  
2.5  
IIO  
Input offset current  
TA = –40°C to 125°C  
INPUT VOLTAGE RANGE  
VCM  
Common-mode voltage  
Common-mode rejection ratio  
TA = –40°C to 125°C  
–0.2 V < VCM < 2.9 V  
(VEE) – 0.2  
56  
(VCC) + 0.2  
V
CMRR  
68  
dB  
Copyright © 2017, Texas Instruments Incorporated  
5
TLV3201-Q1, TLV3202-Q1  
ZHCSFZ5A –FEBRUARY 2017–REVISED DECEMBER 2017  
www.ti.com.cn  
Electrical Characteristics: VCC = 2.7 V (continued)  
at TA = 25°C and VCC = 2.7 V (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
INPUT IMPEDANCE  
Common mode  
1013 || 2  
1013 || 4  
Ω || pF  
Ω || pF  
Differential  
OUTPUT  
ISINK = 4 mA  
230  
210  
260  
325  
250  
350  
VOL  
Voltage output swing from lower rail  
Voltage output swing from upper rail  
mV  
mV  
TA = –40°C to 125°C  
ISOURCE = 4 mA  
TA = –40°C to 125°C  
ISC sinking  
VOH  
13  
15  
19  
See Figure 14  
21  
TA = –40°C to 125°C  
ISC sourcing  
ISC  
Short-circuit current (per comparator)  
mA  
TA = –40°C to 125°C  
See Figure 14  
POWER SUPPLY  
VCC Specified voltage  
2.7  
5.5  
46  
60  
V
TA = 25°C  
36  
IQ  
Quiescent current  
µA  
TA = –40°C to 125°C  
7.7 Switching Characteristics  
over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
Propagation delay time  
Propagation delay skew  
TEST CONDITIONS  
MIN  
TYP  
47  
MAX UNIT  
Input overdrive = 20 mV, CL = 15 pF  
Input overdrive = 100 mV, CL = 15 pF  
TA = –40°C to 125°C  
50  
50  
Low to high  
High to low  
42  
55  
ns  
50  
tPD  
Input overdrive = 20 mV, CL = 15 pF  
Input overdrive = 100 mV, CL = 15 pF  
TA = –40°C to 125°C  
40  
38  
50  
55  
ns  
Input overdrive = 20 mV, CL = 15 pF  
2
Propagation delay matching (TLV3202-Q1) High to low or low to high, input overdrive = 20 mV, CL = 15 pF  
5
ns  
ns  
ns  
tR  
tF  
Rise time  
Fall time  
10% to 90%  
10% to 90%  
2.9  
3.7  
6
Copyright © 2017, Texas Instruments Incorporated  
TLV3201-Q1, TLV3202-Q1  
www.ti.com.cn  
ZHCSFZ5A –FEBRUARY 2017–REVISED DECEMBER 2017  
7.8 Typical Characteristics  
at TA = 25°C, VCC = 5 V, and input overdrive (VOD) = 20 mV (unless otherwise noted)  
26  
24  
22  
20  
18  
16  
14  
12  
10  
8
30  
27  
24  
21  
18  
15  
12  
9
6
6
4
3
2
0
0
Offset Voltage (mV)  
Hysteresis (mV)  
G000  
G001  
Figure 1. Offset Voltage Distribution  
Figure 2. Hysteresis Distribution  
5
4
6
5
VCC = 2.7 V  
5 Typical Units Shown  
5 Typical Units Shown  
3
4
2
3
1
2
0
1
−1  
−2  
−3  
−4  
−5  
0
−1  
−2  
−3  
−4  
−40 −25 −10  
5
20 35 50 65 80 95 110 125  
−0.5  
0
0.5  
1
1.5  
2
2.5  
3
Temperature (°C)  
Common−Mode Voltage (V)  
G002  
G003  
Figure 3. Offset Voltage vs Temperature  
Figure 4. Offset Voltage vs Common-Mode Voltage  
6
5
5
VCC = 5.5 V  
5 Typical Units Shown  
8 Typical Units Shown  
4
4
3
2
3
2
1
1
0
0
−1  
−2  
−3  
−4  
−5  
−1  
−2  
−3  
−4  
−0.5  
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
4.5  
5
5.5  
6
2.5  
3
3.5  
4
4.5  
5
5.5  
Common−Mode Voltage (V)  
Supply Voltage (V)  
G004  
G005  
Figure 5. Offset Voltage vs Common-Mode Voltage  
Figure 6. Offset Voltage vs Power Supply  
Copyright © 2017, Texas Instruments Incorporated  
7
 
TLV3201-Q1, TLV3202-Q1  
ZHCSFZ5A –FEBRUARY 2017–REVISED DECEMBER 2017  
www.ti.com.cn  
Typical Characteristics (continued)  
at TA = 25°C, VCC = 5 V, and input overdrive (VOD) = 20 mV (unless otherwise noted)  
110  
100  
90  
10000  
1000  
100  
10  
−IB  
+IB  
IOS  
80  
70  
CMRR at VCC = 2.7 V  
CMRR at VCC = 5.0 V  
PSRR  
1
60  
50  
0.1  
−50  
−40 −25 −10  
5
20 35 50 65 80 95 110 125  
−25  
0
25  
50  
75  
100  
125  
Temperature (°C)  
Temperature (°C)  
G006  
G002  
Figure 7. Common-Mode Rejection Ratio and  
Power-Supply Rejection Ratio vs Temperature  
Figure 8. Input Bias Current and Input Offset Current  
vs Temperature  
30  
25  
20  
VS=2.7V  
+IB  
−IB  
IOS  
VS= 5.5V  
+IB  
−IB  
IOS  
15  
10  
20  
15  
10  
5
5
0
0
−5  
−5  
−10  
−15  
−20  
−25  
−30  
−10  
−15  
−20  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
0
1
2
3
4
5
Common−Mode Input Voltage (V)  
Common−Mode Input Voltage (V)  
G006  
G006  
Figure 9. Input Bias Current and Input Offset Current  
vs Common-Mode Input Voltage  
Figure 10. Input Bias Current and Input Offset Current  
vs Common-Mode Input Voltage  
65  
35  
30  
25  
20  
15  
10  
5
−40°C  
25°C  
125°C  
55  
45  
35  
25  
15  
0
2.5  
3
3.5  
4
4.5  
5
5.5  
Supply Voltage (V)  
G018  
Supply Current (µA)  
G000  
Figure 12. Quiescent Current vs Supply Voltage  
Figure 11. Quiescent Current Distribution  
8
Copyright © 2017, Texas Instruments Incorporated  
TLV3201-Q1, TLV3202-Q1  
www.ti.com.cn  
ZHCSFZ5A –FEBRUARY 2017–REVISED DECEMBER 2017  
Typical Characteristics (continued)  
at TA = 25°C, VCC = 5 V, and input overdrive (VOD) = 20 mV (unless otherwise noted)  
90  
ISC, Source: VCC = 5 V  
ISC, Sink: VCC = 5 V  
ISC, Sink: VCC = 2.7 V  
ISC, Source: VCC = 2.7 V  
80  
70  
60  
50  
40  
30  
20  
10  
−40  
−15  
10  
35  
60  
85  
110 125  
Temperature (°C)  
G014  
Figure 13. Quiescent Current vs Switching Frequency  
Figure 14. Short-Circuit Current vs Temperature  
2.8  
2.4  
2
5.9  
Sourcing Current  
Sourcing Current  
4.9  
3.7  
1.6  
1.2  
2.5  
0.8  
0.4  
0
−0.4  
−0.8  
−1.2  
−1.6  
−2  
1.3  
−40°C  
25°C  
75°C  
−40°C  
25°C  
75°C  
0.1  
VCC = 2.7 V  
VCC = 5.5 V  
−1.1  
−2.3  
−3.5  
−4.7  
−5.9  
125°C  
125°C  
Sinking Current  
−2.4  
−2.8  
Sinking Current  
15  
0
5
10  
20  
0
10  
20  
30  
40  
50  
60  
Output Current (mA)  
Output Current (mA)  
G015  
G017  
Figure 15. Output Voltage vs Output Current  
Figure 16. Output Voltage vs Output Current  
140  
3
140  
3
Output: VOD = 20 mV  
Input: VOD = 20 mV  
Output: VOD = 100 mV  
Input: VOD = 100 mV  
120  
100  
80  
60  
40  
2.6  
2.1  
1.7  
1.3  
0.9  
0.4  
0
120  
100  
80  
60  
40  
2.6  
2.1  
1.7  
1.3  
0.9  
0.4  
0
20  
0
20  
0
−20  
−40  
−60  
−80  
−100  
−120  
−140  
−0.4  
−0.9  
−1.3  
−1.7  
−2.1  
−2.6  
−3  
−20  
−40  
−60  
−80  
−100  
−120  
−140  
−0.4  
−0.9  
−1.3  
−1.7  
−2.1  
−2.6  
−3  
Output: VOD = 20 mV  
Input: VOD = 20 mV  
Output: VOD = 100 mV  
Input: VOD = 100 mV  
20  
40  
60  
80 100 120 140 160 180 200 220  
Time (ns)  
20 40 60 80 100 120 140 160 180 200 220 240  
Time (ns)  
G000  
G019  
Figure 17. Propagation Delay Falling Edge  
Figure 18. Propagation Delay Rising Edge  
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Typical Characteristics (continued)  
at TA = 25°C, VCC = 5 V, and input overdrive (VOD) = 20 mV (unless otherwise noted)  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
50  
48  
46  
44  
42  
40  
38  
36  
34  
32  
30  
PDHL: 5 V  
PDLH: 5 V  
PDHL: 2.7 V  
PDLH: 2.7 V  
Falling Edge  
Rising Edge  
20  
30  
40  
50  
60  
70  
80  
90  
100  
−40 −25 −10  
5
20 35 50 65 80 95 110 125  
Input Overdrive (mV)  
Temperature (°C)  
G003  
G017  
Figure 19. Propagation Delay vs Input Overdrive  
Figure 20. Propagation Delay vs Temperature  
60  
60  
58  
56  
54  
52  
50  
48  
46  
44  
42  
40  
VCC= 2.7V  
VCC= 5.5V  
Falling Edge  
Rising Edge  
Falling Edge  
Rising Edge  
58  
56  
54  
52  
50  
48  
46  
44  
42  
40  
−0.2  
0.2  
0.6  
1
1.4  
1.8  
2.2  
2.6 2.9  
−0.2 0.4  
1
1.6 2.2 2.8 3.4  
4
4.6 5.2 5.7  
Common−Mode Input Voltage (V)  
Common−Mode Input Voltage (V)  
G017  
G017  
Figure 21. Propagation Delay vs Common-Mode Voltage  
Figure 22. Propagation Delay vs Common-Mode Voltage  
60  
60  
PDLH:Vod = 20 mV  
PDHL:Vod = 20 mV  
Falling Edge  
Rising Edge  
58  
PDLH:Vod = 50 mV  
PDHL:Vod = 50 mV  
56  
54  
52  
50  
48  
46  
44  
42  
40  
55  
45  
35  
VCC= 5.5 V  
75 100  
2.5  
3
3.5  
4
4.5  
5
5.5  
0
25  
50  
Capacitive Load (pF)  
Supply Voltage (V)  
G005  
G024  
Figure 23. Propagation Delay vs Supply Voltage  
Figure 24. Propagation Delay vs Capacitive Load  
10  
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TLV3201-Q1, TLV3202-Q1  
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8 Detailed Description  
8.1 Overview  
The TLV3201-Q1 and TLV3202-Q1 devices feature 40-ns response time and include 1.2 mV of internal  
hysteresis for improved noise immunity with an input common-mode range that extends 0.2 V beyond the power-  
supply rails.  
8.2 Functional Block Diagram  
V+  
+IN  
+
OUT  
-
-IN  
V-  
Copyright © 2016, Texas Instruments Incorporated  
8.3 Feature Description  
8.3.1 Operating Voltage  
The TLV3201-Q1 and TLV3202-Q1 comparators are specified for use on a single supply from 2.7 V to 5.5 V (or  
a dual supply from ±1.35 V to ±2.75 V) over a temperature range of −40°C to +125°C. The device continues to  
function below this range, but performance is not specified.  
8.3.2 Input Overvoltage Protection  
The device inputs are protected by electrostatic discharge (ESD) diodes that conduct if the input voltages exceed  
the power supplies by more than approximately 300 mV. Momentary voltages greater than 300 mV beyond the  
power supply can be tolerated if the input current is limited to 10 mA. This limiting is easily accomplished with a  
small input resistor in series with the input to the comparator.  
8.4 Device Functional Modes  
The device is fully functional when powered by rail-to-rail supply voltage greater than 2.7 V.  
Copyright © 2017, Texas Instruments Incorporated  
11  
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9 Application and Implementation  
NOTE  
Information in the following applications sections is not part of the TI component  
specification, and TI does not warrant its accuracy or completeness. TI’s customers are  
responsible for determining suitability of components for their purposes. Customers should  
validate and test their design implementation to confirm system functionality.  
9.1 Application Information  
The TLV3201-Q1 and TLV3202-Q1 are single- and dual-supply (respectively), push-pull comparators featuring  
40 ns of propagation delay on only 40 µA of supply current. This combination of fast response time and minimal  
power consumption make the TLV3201-Q1 and TLV3202-Q1 excellent comparators for portable, battery-  
powered applications as well as fast-switching threshold detection such as pulse-width modulation (PWM) output  
monitors and zero-cross detection.  
9.1.1 Comparator Inputs  
The TLV3201-Q1 and TLV3202-Q1 are rail-to-rail input comparators, with an input common-mode range that  
exceeds the supply rails by 200 mV for both positive and negative supplies. The devices are specified from 2.7 V  
to 5.5 V, with room temperature operation from 2.5 V to 5.5 V. The TLV3201-Q1 and TLV3202-Q1 are designed  
to prevent phase inversion when the input pins exceed the supply voltage. Figure 25 shows the TLV320x-Q1  
response when input voltages exceed the supply, resulting in no phase inversion.  
5
Output Voltage  
Input Voltage  
4
3
2
1
0
−1  
−2  
−3  
−4  
−5  
0
20  
40  
60  
80 100 120 140 160 180 200  
Time (ns)  
G000  
Figure 25. No Phase Inversion: Comparator Response to Input Voltage (Propagation Delay Included)  
The ESD protection input structure of two back-to-back diodes and 1-kΩ series resistors are used to limit the  
differential input voltage applied to the precision input of the comparator by clamping input voltages that exceed  
VCC beyond the specified operating conditions. If potential overvoltage conditions that exceed absolute maximum  
ratings are present, the addition of external bypass diodes and resistors is recommended, as shown in Figure 26.  
Large differential voltages greater than the supply voltage must be avoided to prevent damage to the input stage.  
1 kW  
Clamp  
+In  
Core  
-In  
1 kW  
Copyright © 2016, Texas Instruments Incorporated  
Figure 26. TLV3201-Q1 Equivalent Input structure  
12  
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Application Information (continued)  
9.1.2 External Hysteresis  
The TLV3201-Q1 and TLV3202-Q1 have a hysteresis transfer curve (shown in Figure 27) that is a function of  
three components: VTH, VOS, and VHYST  
.
•
•
VTH: the actual set voltage or threshold trip voltage  
VOS: the internal offset voltage between VIN+ and VIN–. This voltage is added to VTH to form the actual trip  
point at which the comparator must respond to change output states.  
•
VHYST: internal hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise.  
VTH + VOS - VHYST  
VTH + VOS  
VTH + VOS + VHYST  
Figure 27. TLV320x-Q1 Hysteresis Transfer Curve  
9.1.2.1 Inverting Comparator with Hysteresis  
The inverting comparator with hysteresis requires a three-resistor network that is referenced to the comparator  
supply voltage (VCC), as shown in Figure 28. When VIN at the inverting input is less than VA, the output voltage is  
high (for simplicity, assume VO switches as high as VCC). The three network resistors can be represented as R1  
|| R3 in series with R2. The lower input trip voltage (VA1) is defined by Equation 1.  
R2  
VA1 = VCC  
´
(R1 || R3) + R2  
(1)  
When VIN is greater than [VA × (VIN > VA)], the output voltage is low, very close to ground. In this case, the three  
network resistors can be presented as R2 || R3 in series with R1. The upper trip voltage (VA2) is defined by  
Equation 2.  
R2 || R3  
VA2 = VCC  
´
R1 + (R2 || R3)  
(2)  
(3)  
The total hysteresis provided by the network is defined by Equation 3.  
DVA = VA1 - VA2  
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Application Information (continued)  
+VCC  
+5 V  
R1  
1 MW  
VIN  
5 V  
0 V  
RLOAD  
VA  
VO  
100 kW  
VA2  
1.67 V  
VA1  
3.33 V  
R3  
1 MW  
VIN  
R2  
1 MW  
VO High  
+VCC  
VO Low  
+VCC  
R1  
VA1  
R2  
R3  
R1  
VA2  
R2  
R3  
Copyright © 2016, Texas Instruments Incorporated  
Figure 28. TLV3201-Q1 in Inverting Configuration With Hysteresis  
9.1.2.2 Noninverting Comparator With Hysteresis  
A noninverting comparator with hysteresis requires a two-resistor network, as shown in Figure 29 and a voltage  
reference (VREF) at the inverting input. When VIN is low, the output is also low. For the output to switch from low  
to high, VIN must rise up to VIN1. VIN1 is calculated by Equation 4.  
VREF  
VIN1 = R1 ´  
´ VREF  
R2  
(4)  
When VIN is high, the output is also high. In order for the comparator to switch back to a low state, VIN must  
equal VREF before VA is again equal to VREF. VIN can be calculated by Equation 5.  
VREF (R1 + R2) - VCC ´ R1  
VIN2  
=
R2  
(5)  
(6)  
The hysteresis of this circuit is the difference between VIN1 and VIN2, as defined by Equation 6.  
R1  
DVIN = VCC  
´
R2  
14  
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Application Information (continued)  
+VCC  
+5 V  
VREF  
VO  
+2.5 V  
VA  
VIN  
RLOAD  
R1  
330 kW  
R2  
1 MW  
VO High  
+VCC  
VO Low  
VIN1  
5 V  
0 V  
R2  
R1  
VA = VREF  
R2  
VO  
VA = VREF  
R1  
VIN2  
VIN1  
1.675 V 3.325 V  
VIN  
VIN2  
Copyright © 2016, Texas Instruments Incorporated  
Figure 29. TLV3201-Q1 in Noninverting Configuration With Hysteresis  
9.1.3 Capacitive Loads  
The TLV3201-Q1 and TLV3202-Q1 feature a push-pull output. When the output switches, there is a direct path  
between VCC and ground, causing increased output sinking or sourcing current during the transition. Following  
the transition the output current decreases and supply current returns to 40 µA, thus maintaining low power  
consumption. Under reasonable capacitive loads, the TLV3201-Q1 and TLV3202-Q1 maintain specified  
propagation delay (see Typical Characteristics), but excessive capacitive loading under high switching  
frequencies may increase supply current, propagation delay, or induce decreased slew rate.  
Copyright © 2017, Texas Instruments Incorporated  
15  
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9.2 Typical Applications  
9.2.1 TLV3201-Q1 Configured as an AC-Coupled Comparator  
One of the benefits of ac coupling a single-supply comparator circuit is that it can block dc offsets induced by  
ground-loop offsets that could potentially produce either a false trip or a common-mode input violation. Figure 30  
shows the TLV3201-Q1 configured as an ac-coupled comparator.  
R9  
866 W  
R3  
1 kW  
Cable  
C1 1 mF  
VIN+  
R1  
1 kW  
R10  
50 W  
VOUT  
3.3 V  
U2  
TLV3201  
R2  
1 kW  
VIN  
3.3 V  
C2 1 mF  
+
R4  
1 kW  
V2  
3.3 V  
VIN-  
VCM 100 mV  
+
Ground mismatch in signal source  
vs conditioning circuit  
Copyright © 2017, Texas Instruments Incorporated  
Figure 30. TLV3201-Q1 Configured as an AC-Coupled Comparator (Schematic)  
9.2.1.1 Design Requirements  
Design requirements include:  
•
•
Ability to tolerate up to ±100 mV of common-mode signal.  
Trigger only on ac signals (such as zero-cross detection).  
9.2.1.2 Detailed Design Procedure  
Design analysis:  
•
•
•
•
AC-coupled, high-pass frequency  
Large capacitors require longer start-up time from device power on  
Use 1-µF capacitor to achieve high-pass frequency of approximately 159 Hz  
For high-pass equivalent, use CIN = 0.5 µF, RIN = 2 kΩ  
1. Set up input dividers initially for one-half supply (to be in center of acceptable common-mode range).  
2. Adjust either divider slightly upwards or downwards as desired to establish quiescent output condition.  
3. Select coupling capacitors based on lowest expected frequency.  
16  
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Typical Applications (continued)  
9.2.1.3 Application Curve  
4
VIN  
VCM  
VOUT  
3
2
1
0
-1  
0
100m  
Time (s)  
200m  
Figure 31. AC-Coupled Comparator Results  
9.2.2 TLV3201-Q1 and OPA320 Configured as a Fast-Response Output Current Monitor  
Figure 32 shows a single-supply current monitor configured as a difference amplifier with a gain of 50 to trip at  
500µA. The OPA320 was chosen for this circuit because of its gain bandwidth (20 MHz), which allows higher  
speed triggering and monitoring of the current across the shunt resistor followed by the fast response of the  
TLV3201-Q1.  
+
R5  
50 kW  
V3 5  
+
C3  
100 pF  
V2 5  
VF1  
R4  
1 kW  
R7  
1 kW  
U2  
OPA320  
VF2  
VOUT  
U4  
TLV3201  
C1  
500 pF  
RSHUNT  
R6  
1 kW  
+
100 W  
VT 2.6  
V1 5  
C2  
100 pF  
R2  
1 kW  
R1  
50 kW  
IG1  
Copyright © 2016, Texas Instruments Incorporated  
Figure 32. TLV3201-Q1 and OPA320 Configured as a Fast-Response Output Current Monitor  
Copyright © 2017, Texas Instruments Incorporated  
17  
 
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ZHCSFZ5A –FEBRUARY 2017–REVISED DECEMBER 2017  
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Typical Applications (continued)  
9.2.3 TLV3201-Q1 and TMP20 Configured as a Precision Analog Temperature Switch  
Figure 33 shows the TMP20 and TLV3201-Q1 designed as a high-speed temperature switch. The TMP20 is an  
analog output temperature sensor where output voltage decreases with temperature. The comparator output is  
tripped when the output reaches a critical trip threshold.  
C2  
100 nF  
VCC  
U2  
VIN  
TMP20  
4
V+  
1
VOUT  
T(V)  
VOUT  
VTEMP  
3
GND  
GND  
U1  
TLV3201  
2
5
+
VT 1.85  
VCC  
VCC  
+
V3 5  
Copyright © 2016, Texas Instruments Incorporated  
Figure 33. TLV3201-Q1 and TMP20 Configured as a Precision Analog Temperature Switch  
10 Power Supply Recommendations  
The TLV3201-Q1 and TLV3202-Q1 comparators are specified for use on a single supply from 2.7 V to 5.5 V (or  
a dual supply from ±1.35 V to ±2.75 V) over a temperature range of −40°C to +125°C. The device continues to  
function below this range, but performance is not specified. Place bypass capacitors close to the power-supply  
pins to reduce noise coupling in from noisy or high-impedance power supplies. For more detailed information on  
bypass capacitor placement, see Layout Guidelines.  
18  
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ZHCSFZ5A –FEBRUARY 2017–REVISED DECEMBER 2017  
11 Layout  
11.1 Layout Guidelines  
The TLV3201-Q1 and TLV3202-Q1 are fast-switching, high-speed comparators and require high-speed layout  
considerations. For best results, maintain the following layout guidelines:  
•
•
•
Use a printed-circuit board (PCB) with a good, unbroken low-inductance ground plane.  
Place a decoupling capacitor (0.1-µF ceramic, surface-mount capacitor) as close as possible to VCC  
On the inputs and the output, keep lead lengths as short as possible to avoid unwanted parasitic feedback  
around the comparator. Keep inputs away from the output.  
.
•
•
Solder the device directly to the PCB rather than using a socket.  
For slow-moving input signals, take care to prevent parasitic feedback. A small capacitor (1000 pF or less)  
placed between the inputs can help eliminate oscillations in the transition region. This capacitor causes some  
degradation to propagation delay when the impedance is low. The topside ground plane runs between the  
output and inputs.  
•
The ground pin ground trace runs under the device up to the bypass capacitor, shielding the inputs from the  
outputs.  
11.2 Layout Example  
Power supply  
(1.8 V to 5.5 V)  
0.01 µF  
OUT  
10 ꢀF  
V+  
+IN  
œ IN  
Vœ  
OUT  
V+  
1
2
3
5
4
0.01 µF  
10 ꢀF  
Vœ  
Not to scale  
+IN  
œIN  
Copyright © 2016, Texas Instruments Incorporated  
Figure 34. TLV3201-Q1 SOT-23 Board Layout Example  
版权 © 2017, Texas Instruments Incorporated  
19  
TLV3201-Q1, TLV3202-Q1  
ZHCSFZ5A –FEBRUARY 2017–REVISED DECEMBER 2017  
www.ti.com.cn  
12 器件和文档支持  
12.1 器件支持  
12.1.1 开发支持  
12.1.1.1 TINA-TI™ 仿真软件（免费下载）  
TINA-TI™软件基于 SPICE 引擎，是一款简单易用、功能强大的电路仿真程序。TINA-TI 软件是 TINA 软件的一款  
免费的全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI 软件提供所  
有传统的 SPICE 直流、瞬态和频域分析以及其他设计功能。  
TINA-TI 软件可从模拟电子实验室设计中心免费下载，它可提供广泛的后处理功能，使用户能够以多种方式设置结  
果的格式。虚拟仪器提供选择输入波形和探测电路节点、电压和波形的功能，从而创建一个动态的快速入门工具。  
注
这些文件需要安装 TINA 软件（由 DesignSoft™提供）或者 TINA-TI 软件。请从 TINA-TI 文  
件夹 中下载免费的 TINA-TI 软件。  
12.1.1.2 通用运算放大器评估模块 (EVM)  
通用运放 EVM 是一系列通用空白电路板，可简化采用各种 IC 封装类型的电路板原型设计。虽然主要用于运算放大  
器，但引脚排列与 TLV320x-Q1 比较器相同，可用于轻松快速地对比较器电路进行原型设计。共有 5 个模型可供  
选用，每个模型都对应一种特定封装类型。支持 PDIP、SOIC、MSOP、TSSOP 和 SOT23 封装。  
注
这些电路板均为空白电路板，用户必须自行提供 IC。TI 建议您在订购通用运算放大器 EVM  
时申请几个运算放大器器件样品。  
12.1.1.3 TI 高精度设计  
TI 高精度设计的模拟设计方案是由 TI 公司高精度模拟实验室设计 应用 专家创建的模拟解决方案，提供了许多实用  
电路的工作原理、组件选择、仿真、完整印刷电路板 (PCB) 电路原理图和布局布线、物料清单以及性能测量结果。  
欲获取 TI 高精度设计，请访问 http://www.ti.com.cn/ww/analog/precision-designs/。  
12.1.1.4 WEBENCH®滤波器设计器  
WEBENCH® 滤波器设计器是一款简单、功能强大且便于使用的有源滤波器设计程序。WEBENCH Filter Designer  
通过选择 TI 运算放大器以及 TI 供应商合作伙伴的无源组件来构建优化滤波器设计方案。在比较器前放置滤波器可  
以大大提升噪声抑制性能，避免错误触发。WEBENCH® 设计中心以基于网络的工具形式提供 WEBENCH® Filter  
Designer。用户通过该工具可在短时间内完成多级有源滤波器解决方案的设计、优化和仿真。  
12.2 文档支持  
12.2.1 相关文档  
使用 TLV320x-Q1 时，建议参考下列相关文档。除非另外注明，否则这些文档均可从 www.ti.com 下载。  
•
•
•
《使用 UCC28950 和 TLV3201 实现频率抖动》  
《使用 UCC28180 和 TLV3201 实现频率抖动》  
《具有迟滞功能的比较器参考设计》  
12.3 相关链接  
表 1 列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即购买的快速链接。  
表 1. 相关链接  
器件  
产品文件夹  
请单击此处  
立即订购  
技术文档  
工具和软件  
请单击此处  
支持和社区  
请单击此处  
TLV3201-Q1  
请单击此处  
请单击此处  
20  
版权 © 2017, Texas Instruments Incorporated  
 
TLV3201-Q1, TLV3202-Q1  
www.ti.com.cn  
ZHCSFZ5A –FEBRUARY 2017–REVISED DECEMBER 2017  
相关链接 (接下页)  
表 1. 相关链接 (接下页)  
器件  
产品文件夹  
请单击此处  
立即订购  
技术文档  
工具和软件  
请单击此处  
支持和社区  
请单击此处  
TLV3202-Q1  
请单击此处  
请单击此处  
12.4 接收文档更新通知  
如需接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产  
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。  
12.5 社区资源  
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，  
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。  
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在  
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。  
设计支持  
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。  
12.6 商标  
E2E is a trademark of Texas Instruments.  
WEBENCH is a registered trademark of Texas Instruments.  
DesignSoft is a trademark of DesignSoft, Inc.  
TINA-TI is a trademark of Texas Insturments and DesignSoft, Inc..  
All other trademarks are the property of their respective owners.  
12.7 静电放电警告  
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损  
伤。  
12.8 Glossary  
SLYZ022 — TI Glossary.  
This glossary lists and explains terms, acronyms, and definitions.  
13 机械、封装和可订购信息  
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修  
订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。  
版权 © 2017, Texas Instruments Incorporated  
21  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
TLV3201AQDCKRQ1  
TLV3202AQDGKRQ1  
ACTIVE  
ACTIVE  
SC70  
DCK  
DGK  
5
8
3000 RoHS & Green  
2500 RoHS & Green  
NIPDAU  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
-40 to 125  
-40 to 125  
5HF  
VSSOP  
NIPDAUAG  
1C8Q  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
17-Jul-2020  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TLV3201AQDCKRQ1  
TLV3202AQDGKRQ1  
SC70  
DCK  
DGK  
5
8
3000  
2500  
178.0  
330.0  
9.0  
2.4  
5.3  
2.5  
3.4  
1.2  
1.4  
4.0  
8.0  
8.0  
Q3  
Q1  
VSSOP  
12.4  
12.0  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
17-Jul-2020  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TLV3201AQDCKRQ1  
TLV3202AQDGKRQ1  
SC70  
DCK  
DGK  
5
8
3000  
2500  
190.0  
366.0  
190.0  
364.0  
30.0  
50.0  
VSSOP  
Pack Materials-Page 2  
PACKAGE OUTLINE  
DCK0005A  
SOT - 1.1 max height  
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR  
C
2.4  
1.8  
0.1 C  
1.4  
1.1  
B
1.1 MAX  
A
PIN 1  
INDEX AREA  
1
2
5
NOTE 4  
(0.15)  
(0.1)  
2X 0.65  
1.3  
2.15  
1.85  
1.3  
4
3
0.33  
5X  
0.23  
0.1  
0.0  
(0.9)  
TYP  
0.1  
C A B  
0.15  
0.22  
0.08  
GAGE PLANE  
TYP  
0.46  
0.26  
8
0
TYP  
TYP  
SEATING PLANE  
4214834/C 03/2023  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. Refernce JEDEC MO-203.  
4. Support pin may differ or may not be present.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
DCK0005A  
SOT - 1.1 max height  
SMALL OUTLINE TRANSISTOR  
PKG  
5X (0.95)  
1
5
5X (0.4)  
SYMM  
(1.3)  
2
3
2X (0.65)  
4
(R0.05) TYP  
(2.2)  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE:18X  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
METAL  
EXPOSED METAL  
EXPOSED METAL  
0.07 MIN  
ARROUND  
0.07 MAX  
ARROUND  
NON SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
(PREFERRED)  
SOLDER MASK DETAILS  
4214834/C 03/2023  
NOTES: (continued)  
4. Publication IPC-7351 may have alternate designs.  
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
DCK0005A  
SOT - 1.1 max height  
SMALL OUTLINE TRANSISTOR  
PKG  
5X (0.95)  
1
5
5X (0.4)  
SYMM  
(1.3)  
2
3
2X(0.65)  
4
(R0.05) TYP  
(2.2)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 THICK STENCIL  
SCALE:18X  
4214834/C 03/2023  
NOTES: (continued)  
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
7. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
重要声明和免责声明  
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，  
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担  
保。  
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验  
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。  
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。  
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成  
本、损失和债务，TI 对此概不负责。  
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改  
TI 针对 TI 产品发布的适用的担保或担保免责声明。  
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE  
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2023，德州仪器 (TI) 公司  

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