TLV320ADC3100 [TI]
适用于声控系统和便携式音频系统的低功耗立体声模数转换器 (ADC);
| 型号： | TLV320ADC3100 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于声控系统和便携式音频系统的低功耗立体声模数转换器 (ADC) 便携式 转换器 模数转换器 |
| 文件： | 总101页 (文件大小：2656K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV320ADC3100
ZHCSHY2 –MARCH 2018
适用于声控系统和便携式音频的 TLV320ADC3100 低功耗立体声 ADC
1 特性
2 应用
1
•
立体声音频 ADC：
•
•
•
•
•
声控系统
智能扬声器、支持语音的助理
便携式低功耗音频系统
–
–
92dBA 信噪比
支持从 8kHz 到 96kHz 的 ADC 采样率
噪声消除系统
•
具有可编程系数和内置处理块的灵活数字滤波：
适用于数字音频的前端语音或音频处理器
–
–
–
–
针对语音的低延迟无限脉冲响应 (IIR) 滤波器
针对音频的线性相位有限脉冲响应 (FIR) 滤波器
多达 5 个附加的可编程双二阶滤波器
可编程高通滤波器
3 说明
TLV320ADC3100 是一款低功耗、立体声音频模数转
换器 (ADC)，此器件支持 8kHz 至 96kHz 的采样率并
具有一个可提供高达 40dB 模拟增益或自动增益控制
(AGC) 的集成可编程增益放大器。还提供粗糙衰减为
0dB，-6dB，或者关闭的前端输入。此输入在一个单端
组合或者完全差分配置中可编程。通过 I2C 接口可提供
广泛的基于寄存器的功率控制，从而启用单声道或者立
体声录音。TLV320ADC3100 集成了可编程通道增
益、数字音量控制、锁相环 (PLL)、可编程双二阶滤波
器和低延迟滤波模式。利用可以根据具体应用需求进行
选择的预编程内置处理块 (PRB)，可以优化性能和功
耗。TLV320ADC3100 的低功耗和灵活性特性使其非
常适合电池供电便携式设备。TLV320ADC3100 与
TLV320ADC3101 在外形和软件上兼容。
•
•
四个具有可配置自动增益控制 (AGC) 功能的音频输
入：
–
–
在单端或者全差分配置中可编程
可选三态，用于轻松与其他音频器件进行互操作
低功耗并具有广泛模块功率控制：
–
–
–
–
6mW 单声道录制，8kHz
11mW 立体声录制，8kHz
10mW 单声道录制，48kHz
17mW 立体声录制，48kHz
•
•
•
•
可编程麦克风偏置
用于时钟生成的可编程锁相环路 (PLL)
I2C 控制总线
音频串行数据总线支持 I2S、左平衡和右平衡、
DSP、PCM 和 TDM 模式
器件信息(1)
•
电源：
器件型号
封装
VQFN (24)
封装尺寸（标称值）
–
–
模拟：2.7V 至 3.6V
TLV320ADC3100
4.00mm x 4.00mm
数字：内核：1.65V 至 1.95V，
I/O：1.1V–3.6V
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
•
封装：4mm × 4mm，24 引脚 RGE (VQFN)
功能方框图
PLL
MCLK
TLV320ADC3100
Mic Bias
MICBIAS1
ûꢀ
PGA
AGC
Modulator
IN2L (P)
IN2R (P)
GPIO1
I2S,
TDM,
Serial Bus
Interface
DOUT
BCLK
WCLK
Analog
Input
Selects
ADC Digital
Filter Engine
IN3L (M)
IN3R (M)
AGC
PGA
I2C_ADR0
I2C_ADR1
SCL
ûꢀ
Modulator
I2C
Control Bus
RESET
SDA
Current Bias / Reference
AVDD
AVSS
DVDD
IOVDD
DVSS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBAS906
TLV320ADC3100
ZHCSHY2 –MARCH 2018
www.ti.com.cn
目录
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 40
8.5 Programming........................................................... 40
8.6 Register Maps......................................................... 42
Application and Implementation ........................ 87
9.1 Application Information............................................ 87
9.2 Typical Application ................................................. 88
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 6
9
10 Power Supply Recommendations ..................... 92
11 Layout................................................................... 93
11.1 Layout Guidelines ................................................. 93
11.2 Layout Example .................................................... 93
12 器件和文档支持 ..................................................... 94
12.1 文档支持................................................................ 94
12.2 接收文档更新通知 ................................................. 94
12.3 社区资源................................................................ 94
12.4 商标....................................................................... 94
12.5 静电放电警告......................................................... 94
12.6 Glossary................................................................ 94
13 机械、封装和可订购信息....................................... 94
7.6 Timing Requirements: I2S, LJF, RJF Timing in Master
Mode ......................................................................... 8
7.7 Timing Requirements: DSP Timing in Master Mode. 8
7.8 Timing Requirements: I2S, LJF, RJF Timing in Slave
Mode .......................................................................... 8
7.9 Timing Requirements: DSP Timing in Slave Mode... 8
7.10 Typical Characteristics.......................................... 11
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2018 年 3 月
*
最初发布版本。
2
版权 © 2018, Texas Instruments Incorporated
TLV320ADC3100
www.ti.com.cn
ZHCSHY2 –MARCH 2018
5 说明 （续）
AGC 可在宽范围的启动（7ms 至 1.4s）和衰减（50ms 至 22.4s）时间内进行编程。包含一项用于避免噪声抽吸的
可编程噪声门功能。提供了针对语音和电话进行优化的低延迟中断识别寄存器 (IIR) 滤波器，并且提供了针对音频
进行优化的线性相位有限脉冲响应 (FIR) 滤波器。还提供了可编程 IIR 滤波器，这些滤波器可用于声音均衡或者消
除噪声分量。可以对音频串行总线进行编程，以支持 I2S、左平衡、右平衡、数字信号处理器 (DSP)、脉冲编码调
制 (PCM) 和时分多路复用 (TDM) 模式。音频总线可以在主/从模式下运行。
包括一个用于灵活时钟生成的可编程集成 PLL，并且为来自各种可用 MCLK 的所有标准音频速率提供支持，这些
MCLK 的工作频率从 512kHz 到 50MHz 不等，其中包括最常用的 12MHz、13MHz、16MHz、19.2MHz 和
19.68MHz 系统时钟频率。
Copyright © 2018, Texas Instruments Incorporated
3
TLV320ADC3100
ZHCSHY2 –MARCH 2018
www.ti.com.cn
6 Pin Configuration and Functions
RGE Package
24-Pin VQFN With Exposed Thermal Pad
Top View
BCLK
WCLK
1
2
3
4
5
6
18
17
16
15
14
13
SDA
SCL
DOUT
I2C_ADR1
I2C_ADR0
NC
Thermal
Pad
RESET
MICBIAS1
IN3L(M)
IN3R(M)
Not to scale
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
AVDD
NO.
10
P
P
I/O
O
P
P
I/O
I
Analog voltage supply, 2.7 V–3.6 V
Analog ground supply, 0 V
AVSS
9
BCLK
1
Audio serial data bus bit clock
Audio serial data bus data output
DOUT
3
DVDD
22
Digital core voltage supply, 1.65 V–1.95 V
Digital ground supply, 0 V
DVSS
23
GPIO1
I2C_ADR0
I2C_ADR1
IN2L(P)
IN2R(P)
IN3L(M)
IN3R(M)
IOVDD
MCLK
19
General-purpose input/output 1, multifunction pin based on register programming
LSB of I2C bus address
LSB + 1 of I2C bus address
15
16
I
7
I
Microphone or line analog input (left-channel single-ended or differential plus)
12
I
Microphone or line analog input (right-channel single-ended or differential plus)
6
I
Microphone or line analog input (left-channel single-ended or differential minus)
13
I
Microphone or line analog input (right-channel single-ended or differential minus)
21
P
I
I/O voltage supply, 1.1 V–3.6 V
Master clock input
24
MICBIAS1
NC
5
O
—
I
MICBIAS1 bias voltage output
No connection
8, 11, 14, 20
RESET
SCL
4
17
18
2
Reset
I2C serial clock
I2C serial data input/output
Audio serial data bus word clock
Connect the thermal pad to AVSS.
I/O
I/O
I/O
—
SDA
WCLK
Thermal pad
Pad
4
Copyright © 2018, Texas Instruments Incorporated
TLV320ADC3100
www.ti.com.cn
ZHCSHY2 –MARCH 2018
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–40
MAX
UNIT
V
AVDD to AVSS
3.9
3.9
IOVDD to DVSS
V
DVDD to DVSS
2.5
V
Digital input voltage to DVSS
Analog input voltage to AVSS
Operating temperature
IOVDD + 0.3
AVDD + 0.3
85
V
V
°C
°C
W
°C
TJ Max
Tstg
Junction temperature
Power dissipation
105
(TJ Max – TA) / θJA
Storage temperature
–65
125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) ESD complacence tested to EIA/JESD22-A114-B and passed.
7.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX
3.6
UNIT
V
AVDD
DVDD
IOVDD
VI
Analog supply voltage(1)
Digital core supply voltage(1)
Digital I/O supply voltage(1)
2.7
1.65
1.1
3.3
1.8
1.95
3.6
V
1.8
V
Analog full-scale, 0-dB input voltage (AVDD = 3.3 V)
Digital output load capacitance
Operating free-air temperature
0.707
10
Vrms
pF
°C
TA
–40
85
(1) Analog voltage values are with respect to AVSS; digital voltage values are with respect to DVSS.
7.4 Thermal Information
TLV320ADC3100
THERMAL METRIC(1)
RGE (VQFN)
24 PINS
33.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
34.1
11.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ψJB
11.5
RθJC(bot)
3.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2018, Texas Instruments Incorporated
5
TLV320ADC3100
ZHCSHY2 –MARCH 2018
www.ti.com.cn
7.5 Electrical Characteristics
at 25°C, AVDD = 3.3 V, IOVDD = 1.8 V, DVDD = 1.8 V, fS = 48-kHz, and 16-bit audio data (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AUDIO ADC
Input signal level (0-dB)
Single-ended input
0.707
1.35
Vrms
Vrms
Input common-mode voltage
Single-ended input
Signal-to-noise ratio,
A-weighted(1)(2)
fS = 48 kHz, 0-dB PGA gain, IN1 inputs selected
and AC-shorted to ground
SNR
80
92
92
dB
Dynamic range,
A-weighted(1)(2)
fS = 48 kHz; 1-kHz, –60-dB, full-scale input
applied at IN1 inputs; 0-dB PGA gain
dB
–90
0.003%
46
–75 dB
fS = 48 kHz; 1-kHz, –2-dB, full-scale input
applied at IN1 inputs; 0-dB PGA gain
THD
Total harmonic distortion
0.017%
234 Hz, 100 mVPP on AVDD, single-ended input
234 Hz, 100 mVPP on AVDD, differential input
1 kHz, –2-dB IN2L to IN2R
PSRR
Power-supply rejection ratio
dB
68
ADC channel separation
ADC gain error
–73
dB
dB
1 kHz input, 0-dB PGA gain
0.7
ADC programmable-gain
amplifier maximum gain
1-kHz input tone, RSOURCE < 50 Ω
40
0.502
35
dB
dB
ADC programmable-gain
amplifier step size
IN1 inputs, routed to single ADC,
input mix attenuation = 0 dB
IN2 inputs, input mix attenuation = 0 dB
IN1 inputs, input mix attenuation = –6 dB
IN2 inputs, input mix attenuation = –6 dB
35
62.5
62.5
10
Input resistance
kΩ
Input capacitance
pF
dB
Input level control minimum
attenuation setting
0
6
6
Input level control maximum
attenuation setting
dB
dB
Input level control attenuation
step size
(1) Ratio of output level with 1-kHz, full-scale, sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over
a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz, low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics table. The low-pass filter
removes out-of-band noise that, although not audible, may affect dynamic specification values.
6
Copyright © 2018, Texas Instruments Incorporated
TLV320ADC3100
www.ti.com.cn
ZHCSHY2 –MARCH 2018
Electrical Characteristics (continued)
at 25°C, AVDD = 3.3 V, IOVDD = 1.8 V, DVDD = 1.8 V, fS = 48-kHz, and 16-bit audio data (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ADC DIGITAL DECIMATION FILTER (fS = 48 kHz)
Filter gain from 0 fS to 0.39 fS
Filter A, AOSR = 128 or 64
±0.1
–73
dB
dB
s
Filter gain from 0.55 fS to 64 fS Filter A, AOSR = 128 or 64
Filter group delay
Filter A, AOSR = 128 or 64
Filter B, AOSR = 64
17 / fS
±0.1
Filter gain from 0 fS to 0.39 fS
dB
dB
s
Filter gain from 0.60 fS to 32 fS Filter B, AOSR = 64
–46
Filter group delay
Filter B, AOSR = 64
Filter C, AOSR = 32
11 / fS
±0.033
–60
Filter gain from 0 fS to 0.39 fS
dB
dB
s
Filter gain from 0.28 fS to 16 fS Filter C, AOSR = 32
Filter group delay
MICROPHONE BIAS
Filter C, AOSR = 32
11 / fS
2
2.5
Bias voltage
Programmable settings, load = 750 Ω
2.25
–0.3
2.75
4
V
AVDD – 0.2
Current sourcing
Integrated noise
2.5-V setting
mA
BW = 20 Hz to 20 kHz, A-weighted, 1-µF
capacitor between MICBIAS and AGND
µV
rms
3.3
DIGITAL I/O
0.3 ×
IOVDD
VIL
Input low level
IIL = 5 µA
V
V
V
V
0.7 ×
IOVDD
VIH
VOL
VOH
Input high level(3)
Output low level
Output high level
IIH = 5 µA
0.1 ×
IOVDD
IIH = 2 TTL loads
IOH = 2 TTL loads
0.8 ×
IOVDD
SUPPLY CURRENT (fS = 48 kHz, AVDD = 3.3 V, DVDD = IOVDD = 1.8 V)
AVDD
2
1.9
4
Mono record
Stereo record
PLL
PLL and AGC off
PLL and AGC off
mA
mA
mA
µA
DVDD
AVDD
DVDD
AVDD
DVDD
AVDD
DVDD
2.1
1.1
0.8
0.04
0.7
Additional power consumed when
PLL is powered
All supply voltages applied, all blocks
programmed in lowest power state
Power down
(3) When IOVDD < 1.6 V, the minimum VIH is 1.1 V.
Copyright © 2018, Texas Instruments Incorporated
7
TLV320ADC3100
ZHCSHY2 –MARCH 2018
www.ti.com.cn
7.6 Timing Requirements: I2S, LJF, RJF Timing in Master Mode
specified at 25°C, DVDD = 1.8 V, all timing specifications are measured at characterization; see 图 1 for a timing diagram
IOVDD = 1.8 V
MIN MAX
IOVDD = 3.3 V
MIN MAX
UNIT
td(WS)
BCLK, WCLK delay time
BCLK, WCLK to DOUT delay time
BCLK to DOUT delay time
Rise time
20
25
20
20
20
15
20
15
15
15
ns
ns
ns
ns
ns
td(DO-WS)
td(DO-BCLK)
tr
tf
Fall time
7.7 Timing Requirements: DSP Timing in Master Mode
specified at 25°C, DVDD = 1.8 V, all timing specifications are measured at characterization; see 图 2 for a timing diagram
IOVDD = 1.8 V
MIN MAX
IOVDD = 3.3 V
MIN MAX
UNIT
td(WS)
BCLK, WCLK delay time
BCLK to DOUT delay time
Rise time
25
25
20
20
15
15
15
15
ns
ns
ns
ns
td(DO-BCLK)
tr
tf
Fall time
7.8 Timing Requirements: I2S, LJF, RJF Timing in Slave Mode
specified at 25°C, DVDD = 1.8 V, all timing specifications are measured at characterization; see 图 3 for a timing diagram
IOVDD = 1.8 V
IOVDD = 3.3 V
UNIT
MIN
35
MAX
MIN
35
35
6
MAX
tH(BCLK)
tL(BCLK)
ts(WS)
BCLK high period
ns
ns
ns
ns
BCLK low period
35
BCLK, WCLK setup time
BCLK, WCLK hold time
10
th(WS)
10
6
BCLK, WCLK to DOUT delay time
(for LJF mode only)
td(DO-WS)
30
30
ns
td(DO-BCLK)
BCLK to DOUT delay time
Rise time
25
16
16
20
8
ns
ns
ns
tr
tf
Fall time
8
7.9 Timing Requirements: DSP Timing in Slave Mode
specified at 25°C, DVDD = 1.8 V, all timing specifications are measured at characterization; see 图 4 for a timing diagram
IOVDD = 1.8 V
IOVDD = 3.3 V
UNIT
MIN
35
MAX
MIN
35
35
8
MAX
tH(BCLK)
tL(BCLK)
ts(WS)
th(WS)
td(DO-BCLK)
tr
BCLK high period
BCLK low period
BCLK, WCLK setup time
BCLK, WCLK hold time
BCLK to DOUT delay time
Rise time
ns
ns
ns
ns
ns
ns
ns
35
10
10
8
25
15
15
20
8
tf
Fall time
8
8
版权 © 2018, Texas Instruments Incorporated
TLV320ADC3100
www.ti.com.cn
ZHCSHY2 –MARCH 2018
WCLK
BCLK
DOUT
td(WS)
tr
tf
td(DO-WS)
td(DO-BCLK)
图 1. I2S, LJF, RJF Timing in Master Mode
WCLK
BCLK
DOUT
td(WS)
td(WS)
tf
tr
td(DO-BCLK)
图 2. DSP Timing in Master Mode
WCLK
tS(WS)
th(WS)
tH(BCLK)
tr
tf
BCLK
tL(BCLK)
td(DO-WS)
td(DO-BCLK)
DOUT
图 3. I2S, LJF, RJF Timing in Slave Mode
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9
TLV320ADC3100
ZHCSHY2 –MARCH 2018
www.ti.com.cn
(see NOTE)
WCLK
t (WS)
h
t (WS)
h
t (WS)
s
t (WS)
h
t (BCLK)
L
BCLK
DOUT
t (BCLK)
H
t
f
t
r
t (DO-BCLK)
d
NOTE: The WCLK falling edge is arbitrary inside a frame.
图 4. DSP Timing in Slave Mode
10
版权 © 2018, Texas Instruments Incorporated
TLV320ADC3100
www.ti.com.cn
ZHCSHY2 –MARCH 2018
7.10 Typical Characteristics
at 25°C, AVDD = 3.3 V, IOVDD = 1.8 V, DVDD = 1.8 V, fS = 48-kHz, and 16-bit audio data (unless otherwise noted)
0.45
0.4
3.5
3.25
3
MICBIAS = AVDD
MICBIAS = 2.5 V
MICBIAS = 2 V
0.35
0.3
2.75
2.5
2.25
2
0.25
0.2
0.15
0.1
Right Gain Error
Left Gain Error
0.05
0
1.75
0
10
20
30
40
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
PGA Gain Setting (dB)
AVDD (V)
D001
D002
图 5. Single-Ended Gain Error
图 6. MICBIAS Output Voltage vs AVDD
3.2
3
0
-20
MICBIAS = AVDD
2.8
2.6
2.4
2.2
2
MICBIAS = 2.5 V
MICBIAS = 2 V
-40
-60
-80
-100
-120
-140
1.8
-45 -35 -25 -15 -5
5
15 25 35 45 55 65 75 85
0
2
4
6
8
10
12
14
16
18
20
Temperature (èC)
Frequency (kHz)
D003
D004
图 7. MICBIAS Output Voltage vs Ambient Temperature
图 8. Line Input to ADC FFT Plot
17
Left Channel
Right Channel
15
13
11
9
7
5
0
5
10
15
20
25
30
35
40
PGA Gain Setting (dB)
D005
图 9. Input-Referred Noise vs PGA Gain
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8 Detailed Description
8.1 Overview
The TLV320ADC3100 is a flexible, low-power, stereo audio analog-to-digital converter (ADC) with extensive
feature integration, intended for applications in voice-activated systems, portable computing, communication, and
entertainment applications. The device integrates a host of features to reduce cost, board space, and power
consumption in space-constrained, battery-powered, portable applications. The TLV320ADC3100 is form-factor
and software compatible with the more feature-rich TLV320ADC3101, which has additional features such as a
programmable miniDSP.
The TLV320ADC3100 consists of the following blocks:
•
•
•
•
Stereo audio multibit delta-sigma ADC (8 kHz–96 kHz)
Programmable digital filter engines including biquads
Register-configurable combinations of up to four single-ended or two differential audio inputs
Fully programmable phase-locked loop (PLL) with extensive ADC clock-source and divider options for
maximum end-system design flexibility
Communication to the TLV320ADC3100 for control is via a two-wire I2C interface. The I2C interface supports
both standard and fast communication modes.
8.2 Functional Block Diagram
IN2L(P)
IN2L(P)
0 to 40 dB
0.5-dB Steps
Audio Clock
Generation
PLL
IN3L(M)
MCLK
IN3L(M)
ûꢀ
Modulator
IN2L(P)
IN3L(M)
IN2R(P)
IN3R(M)
PGA
AGC
+
GPIO1
I2S,
TDM,
DOUT
BCLK
WCLK
Serial Bus
Interface
ADC Digital
Filter Engine
IN2R(P)
IN3R(M)
IN2R(P)
IN2R(P)
IN3R(M)
AGC
PGA
ûꢀ
Modulator
+
I2C_ADR0
I2C_ADR1
SCL
IN3R(M)
IN2L(P)
0 to 40 dB
I2C
Control Bus
0.5-dB Steps
IN3L(M)
RESET
SDA
Mic Bias
Current Bias / Reference
MICBIAS1
IOVDD DVSS
AVDD
AVSS
DVDD
8.3 Feature Description
8.3.1 Hardware Reset
The TLV320ADC3100 requires a hardware reset after power up for proper operation. After all power supplies are
at their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not
performed, the TLV320ADC3100 may not respond properly to register reads or writes.
8.3.2 PLL Start-up
When the PLL is powered on, a start-up delay of approximately 10 ms occurs after the power-up command of the
PLL and before the clocks are available to the TLV320ADC3100. This delay is to ensure stable operation of the
PLL and clock-divider logic.
12
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Feature Description (接下页)
8.3.3 Software Power Down
By default, all circuit blocks are powered down following a reset condition. Hardware power up of each circuit
block can be controlled by writing to the appropriate control register. This approach allows the lowest power-
supply current for the functionality required. However, when a block is powered down, all register settings are
maintained as long as power is applied to the device.
8.3.4 Audio Data Converters
The TLV320ADC3100 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,
22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters can also operate at
different sampling rates in various combinations, as described in this section.
The TLV320ADC3100 supports a wide range of options for generating clocks for the ADC section as well as the
digital interface section and the other control blocks; see 图 27. The ADC clocks require a source reference
clock. The clock can be provided on the device pins MCLK and BCLK. The source reference clock for the ADC
section can be chosen by programming the ADC_CLKIN value on page 0, register 4, bits 1:0. The ADC_CLKIN
can then be routed through highly flexible clock dividers (see 图 27) to generate various clocks required for the
ADC and programmable digital filter sections. In the event that the desired audio or programmable digital filter
clocks cannot be generated from the external reference clocks on MCLK and BCLK, the TLV320ADC3100 also
provides the option of using an on-chip PLL that supports a wide range of fractional multiplication values to
generate the required system clocks. Starting from ADC_CLKIN, the TLV320ADC3100 provides several
programmable clock dividers to support a variety of sampling rates for the ADC and the clocks for the
programmable digital filter section.
8.3.5 Digital Audio Data Serial Interface
Audio data are transferred between the host processor and the TLV320ADC3100 via the digital-audio serial-data
interface, or audio bus. The audio bus on this device is flexible, including left- or right-justified data options,
support for I2S or pulse code modulation (PCM) protocols, programmable data-length options, a time-division
multiplexing (TDM) mode for multichannel operation, flexible master and slave configurability for each bus clock
line, and the ability to directly communicate with multiple devices within a system.
The audio serial interface on the TLV320ADC3100 has an extensive I/O control for communication with two
independent processors for audio data. The processors can communicate with the device one at a time. This
feature is enabled by register programming of the various pin selections.
The audio bus of the TLV320ADC3100 can be configured for left- or right-justified, I2S, DSP, or TDM modes of
operation, where communication with standard telephony PCM interfaces is supported within the TDM mode.
These modes are all MSB-first, with the data width programmable in 16, 20, 24, or 32 bits by configuring page 0,
register 27, bits 5:4. In addition, the word clock and bit clock can be independently configured in either master or
slave mode for flexible connectivity to a wide variety of processors. The word clock is used to define the
beginning of a frame, and can be programmed as either a pulse or a square-wave signal. The frequency of this
clock corresponds to the maximum-selected ADC sampling frequency.
The bit clock is used to clock in and out the digital audio data across the serial bus. When in master mode, this
signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in page 0, register
30; see 图 27. Accommodating various word lengths as well as supporting the case when multiple
TLV320ADC3100s share the same audio bus may require that the number of bit-clock pulses in a frame be
adjusted.
The TLV320ADC3100 also includes a feature to offset the position of the start of a data transfer with respect to
the word clock. There are two configurations that allow using either a single offset for both channels or to use
separate offsets. The Ch_Offset_1 reference represents the value in page 0, register 28 and Ch_Offset_2
represents the value in page 0, register 37. When page 0, register 38, bit 0 is set to zero (time-slot-based
channel assignment is disabled), the offset of both channels is controlled, in terms of number of bit clocks, by the
programming in page 0, register 28 (Ch_Offset_1). When page 0, register 38, bit 0 = 1 (time-slot-based channel
assignment enabled), the first channel is controlled, in terms of number of bit clocks, by the programming in page
0, register 28 (Ch_Offset_1), and the second channel is controlled, in terms of number of bit clocks, by the
programming in page 0, register 37 (Ch_Offset_2), where register 37 programs the delay between the first word
and the second word. Also, the relative order of the two channels can be swapped, depending on the
programmable register bit (page 0, register 38, bit 4) that enables swapping of the channels.
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Feature Description (接下页)
The TLV320ADC3100 also supports a feature for inverting the bit clock polarity used for transferring the audio
data as compared to the default clock polarity used. This feature can be used independently of the audio
interface mode chosen. The bit clock polarity can be configured by writing to page 0, register 29, bit 3.
The TLV320ADC3100 further includes programmability (page 0, register 27, bit 0) to place DOUT in the high-
impedance state at the end of data transfer (that is, at the end of the bit cycle corresponding to the LSB of a
channel). By combining this capability with the ability to program at what bit clock in a frame the audio data
begins, TDM can be accomplished, resulting in multiple ADCs able to use a single audio serial data bus. To
further enhance the tri-state capability, the TLV320ADC3100 can be put in a high-impedance state a half bit
cycle earlier by setting page 0, register 38, bit 1 to 1. When the audio serial data bus is powered down while
configured in master mode, the pins associated with the interface are put into a high-impedance output state.
Either or both of the two channels can be disabled in LJF, I2S, and DSP modes by using page 0, register 38, bits
3:2. 图 10 shows the interface timing when both channels are enabled and early tri-stating is enabled. 图 11
shows the effect of setting page 0, register 38, bit 2, first channel disabled, and setting page 0, register 27, bit 0
to 1, which enables placing DOUT in the high-impedance state. If placing DOUT in the high-impedance state is
disabled, then the DOUT signal is driven to logic level 0.
1/fs
WCLK
BCLK
N - 1
N - 2
X
N - 1
N - 2
X
N - 3
N - 3
1
0
2
1
0
DOUT
DOUT_Tristate
图 10. Both Channels Enabled, Early Tri-Stating Enabled
1/fs
WCLK
BCLK
Frame Time / 2
”0‘
”0‘
X
R-1
R-2
X
”0‘
”0‘
2
1
0
DOUT
DOUT_Tristate
图 11. First Channel Disabled, Second Channel Enabled, Tri-Stating Enabled
The sync signal for the ADC filter is not generated based on the disabled channel. The sync signal for the filter
corresponds to the beginning of the earlier of the two channels. If the first channel is disabled, the filter sync is
generated at the beginning of the second channel, if enabled. If both channels are disabled, there is no output to
the serial bus, and the filter sync corresponds to the beginning of the frame.
By default, when the word clocks and bit clocks are generated by the TLV320ADC3100, these clocks are active
only when the ADC is powered up within the device. This internal clock gating is done to save power. However,
the internal clock gating architecture also supports a feature wherein both the word clocks and bit clocks can be
active even when the codec in the device is powered down. This feature is useful when using the TDM mode
with multiple codecs on the same bus or when word clocks or bit clocks are used in the same system as general-
purpose clocks.
14
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Feature Description (接下页)
8.3.5.1 Right-Justified Mode
In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling
edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding
the rising edge of the word clock. 图 12 shows the right-justified mode timing.
1 / fs
WCLK
BCLK
Left Channel
n-2 n-3
Right Channel
DIN/
DOUT
n-2 n-3
0
n-1
2
1
0
n-1
2
1
0
MSB
LSB
MSB
LSB
图 12. Right-Justified Mode Timing Diagram
For right-justified mode, the number of bit clocks per frame must be greater than twice the programmed word-
length of the data.
注
The time-slot-based mode is not available in the right-justified mode.
8.3.5.2 Left-Justified Mode
In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling
edge of the word clock. Similarly, the MSB of the left channel is valid on the rising edge of the bit clock following
the rising edge of the word clock. 图 13 shows the standard timing of the left-justified mode.
Left Channel
Right Channel
WORD
CLOCK
BIT
CLOCK
n-1n-2 n-3
n-1n-2n-3
3
2
1
0
n-1n-2n-3
3
2
1
0
DATA
RD(n)
LD(n)
LD(n+1)
LD(n) = nth Sample of Left-Channel Data
RD(n) = nth Sample of Left-Channel Data
图 13. Left-Justified Mode (Standard Timing)
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Feature Description (接下页)
图 14 shows the left-justified mode with Ch_Offset_1 = 1.
Left Channel
Right Channel
WORD
CLOCK
BIT
CLOCK
n-1n-2 n-3
1
n-1n-2n-3
3
2
0
n-1n-2n-3
3
2
1
0
DATA
RD(n)
LD(n)
LD(n+1)
Ch_Offset_1 = 1
LD(n) = nth Sample of Left-Channel Data
Ch_Offset_1 = 1
RD(n) = nth Sample of Left-Channel Data
图 14. Left-Justified Mode With Ch_Offset_1 = 1
图 15 shows the left-justified mode with Ch_Offset_1 = 0 and bit clock inverted.
Left Channel
Right Channel
WORD
CLOCK
BIT
CLOCK
n-1n-2 n-3
n-1n-2n-3
3
2
1
0
n-1n-2n-3
3
2
1
DATA
3
LD(n)
RD(n)
LD(n+1)
Ch_Offset_1 = 0
LD(n) = nth Sample of Left-Channel Data
Ch_Offset_1 = 0
RD(n) = nth Sample of Left-Channel Data
图 15. Left-Justified Mode With Ch_Offset_1 = 0, Bit Clock Inverted
For left-justified mode, the number of bit clocks per frame must be greater than twice the programmed word
length of the data. Also, the programmed offset value must be less than the number of bit clocks per frame by at
least the programmed word length of the data.
When the time-slot-based channel assignment is disabled (page 0, register 38, bit 0 = 0), the left and right
channels have the same offset Ch_Offset_1 (page 0, register 28), and each edge of the word clock starts data
transfer for one of the two channels, depending on whether or not channel swapping is enabled. Data bits are
valid on the rising edges of the bit clock. With the time-slot-based channel assignment enabled (page 0, register
38, bit 0 = 1), the left and right channels have independent offsets (Ch_Offset_1 and Ch_Offset_2). The rising
edge of the word clock starts data transfer for the first channel after a delay of its programmed offset
(Ch_Offset_1) for this channel. Data transfer for the second channel starts after a delay of its programmed offset
(Ch_Offset_2) from the LSB of the first-channel data. The falling edge of the word clock is not used.
With no channel swapping, the MSB of the left channel is valid on the (Ch_Offset_1 + 1)th rising edge of the bit
clock following the rising edge of the word clock. Consequently, the MSB of the right channel is valid on the
(Ch_Offset_1 + 1)th rising edge of the bit clock following the falling edge of the word clock. The timing diagram of
图 14 illustrates the operation in this case, with an offset of 1. Because channel swapping is not enabled, the left-
channel data are before the right-channel data. With channel swapping enabled, the MSB of the right channel is
valid on the (Ch_Offset_1 + 1)th rising edge of the bit clock following the rising edge of the word clock. Thus, the
MSB of the left channel is valid on the (Ch_Offset_1 + 1)th rising edge of the bit clock following the falling edge
of the word clock. The timing diagram of 图 16 depicts the operation in this case, with an offset of 1. As shown in
the diagram, the right-channel data of a frame are before the left-channel data of that frame because of channel
swapping. Otherwise, the behavior is similar to the case where channel swapping is disabled. The MSB of the
right-channel data is valid on the second rising edge of the bit clock after the rising edge of the word clock, as a
result of an offset of 1. Similarly, the MSB of the left-channel data is valid on the second rising edge of the bit
clock after the falling edge of the word clock.
16
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Feature Description (接下页)
Right Channel
Left Channel
WORD
CLOCK
BIT
CLOCK
n-1n-2 n-3
RD(n+1)
n-1n-2n-3
3
2
1
0
n-1n-2n-3
3
2
1
0
DATA
RD(n)
LD(n)
Ch_Offset_1 = 1
Ch_Offset_1 = 1
图 16. Left-Justified Mode With Ch_Offset_1 = 1, Channel Swapping Enabled
When the time-based-slot mode is enabled with no channel swapping, the MSB of the left channel is valid on the
(Offset1 + 1)th rising edge of the bit clock following the rising edge of the word clock. Thus, the MSB of the right
channel is valid on the (Ch_Offset_2 + 1)th rising edge of the bit clock following the LSB of the left channel.
图 17 shows the operation with time-based-slot mode enabled, Ch_Offset_1 = 0, and Ch_Offset_2 = 1. The MSB
of the left channel is valid on the first rising edge of the bit clock after the rising edge of the word clock. Data
transfer for the right channel does not wait for the falling edge of the word clock, and the MSB of the right
channel is valid on the second rising edge of the bit clock after the LSB of the left channel.
WORD
CLOCK
BIT
CLOCK
n-1n-2n-3
n-1n-2n-3
3
2
1
0
n-1n-2n-3
3
2
1
0
DATA
LD(n)
Left Channel
RD(n)
Left Channel
LD(n+1)
Ch_Offset_1 = 0
Ch_Offset_2 = 1
图 17. Left-Justified Mode, Time-Based-Slot Mode Enabled, Ch_Offset_1 = 0, Ch_Offset_2 = 1
When the time-based-slot mode is enabled and channel swapping is enabled, the MSB of the right channel is
valid on the (Ch_Offset_1 + 1)th rising edge of the bit clock following the rising edge of the word clock. Thus, the
MSB of the left channel is valid on the (Ch_Offset_2 + 1)th rising edge of the bit clock following the LSB of the
right channel. 图 18 illustrates the operation in this mode with Ch_Offset_1 = 0 and Ch_Offset_2 = 1. The MSB
of the right channel is valid on the first rising edge of the bit clock after the rising edge of the word clock. Data
transfer for the left channel starts following the completion of data transfer for the right channel without waiting for
the falling edge of the word clock. The MSB of the left channel is valid on the second rising edge of the bit clock
after the LSB of the right channel.
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Feature Description (接下页)
WORD
CLOCK
BIT
CLOCK
n-1n-2n-3
n-1n-2n-3
3
2
1
0
n-1n-2n-3
3
2
1
0
DATA
RD(n)
Left Channel
LD(n)
Left Channel
RD(n+1)
Ch_Offset_1 = 0
Ch_Offset_2 = 1
图 18. Left-Justified Mode, Time-Based-Slot Mode Enabled, Ch_Offset_1 = 0, Ch_Offset_2 = 1,
Channel Swapping Enabled
8.3.5.3 I2S Mode
In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge
of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after
the rising edge of the word clock. 图 19 shows the standard I2S timing.
Left Channel
Right Channel
WORD
CLOCK
BIT
CLOCK
n-1n-2 n-3
n-1n-2n-3
3
2
1
0
n-1n-2n-3
3
2
1
DATA
3
LD(n)
RD(n)
LD(n+1)
Ch_Offset_1 = 0
LD(n) = nth Sample of Left-Channel Data
Ch_Offset_1 = 0
RD(n) = nth Sample of Left-Channel Data
图 19. I2S Mode (Standard Timing)
图 20 shows the I2S mode timing with Ch_Offset_1 = 2.
Left Channel
Right Channel
WORD
CLOCK
BIT
CLOCK
n-1
n-1n-2n-3
3
2
1
0
n-1
5
4
3
2
1
0
DATA
5
LD(n)
RD(n)
Ch_Offset_1 = 2
RD(n) = nth Sample of Left-Channel Data
LD(n+1)
Ch_Offset_1 = 0
LD(n) = nth Sample of Left-Channel Data
图 20. I2S Mode With Ch_Offset_1 = 2
18
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Feature Description (接下页)
图 21 shows the I2S mode timing with Ch_Offset_1 = 0 and the bit clock inverted.
Left Channel
Right Channel
WORD
CLOCK
BIT
CLOCK
n-1n-2 n-3
3
n-1n-2n-3
3
2
1
0
n-1n-2n-3
3
2
1
0
DATA
RD(n)
LD(n)
LD(n+1)
Ch_Offset_1 = 0
LD(n) = nth Sample of Left-Channel Data
Ch_Offset_1 = 0
RD(n) = nth Sample of Right-Channel Data
图 21. I2S Mode With Ch_Offset_1 = 0, Bit Clock Inverted
For the I2S mode, the number of bit clocks per channel must be greater than or equal to the programmed word
length of the data. Also, the programmed offset value must be less than the number of bit clocks per frame by at
least the programmed word length of the data.
8.3.5.4 DSP Mode
In DSP mode, the rising edge of the word clock starts the data transfer with the left-channel data first and is
immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock. 图 22
shows the standard timing for the DSP mode.
Left Channel
Right Channel
WORD
CLOCK
BIT
CLOCK
n-1n-2 n-3
n-1n-2 n-3
3
2
1
0
n-1n-2n-3
2 1
DATA
3
0
3
LD(n)
RD(n)
LD(n+1)
LD(n) = nth Sample of Left-Channel Data RD(n) = nth Sample of Right-Channel Data
图 22. DSP Mode (Standard Timing)
图 23 shows the DSP mode timing with Ch_Offset_1 = 1.
Left Channel
Right Channel
WORD
CLOCK
BIT
CLOCK
n-1n-2 n-3
n-1n-2 n-3
3
2
1
0 n-1n-2n-3
2
1
DATA
3
0
LD(n)
RD(n)
LD(n+1)
Ch_Offset_1 = 1
LD(n) = nth Sample of Left-Channel Data
RD(n) = nth Sample of Left-Channel Data
图 23. DSP Mode With Ch_Offset_1 = 1
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Feature Description (接下页)
图 24 shows the DSP mode timing with Ch_Offset_1 = 0 and the bit clock inverted.
Left Channel
Right Channel
WORD
CLOCK
BIT
CLOCK
n-1n-2 n-3
n-1n-2 n-3
3
2
1
0
n-1n-2n-3
2 1
DATA
3
0
3
LD(n)
RD(n)
LD(n+1)
Ch_Offset_1 = 0
图 24. DSP Mode With Ch_Offset_1 = 0, Bit Clock Inverted
For DSP mode, the number of bit clocks per frame must be greater than twice the programmed word length of
the data. Also, the programmed offset value must be less than the number of bit clocks per frame by at least the
programmed word length of the data.
图 25 shows the DSP time-slot-based mode without channel swapping, and with Ch_Offset_1 = 0 and
Ch_Offset_2 = 3. The MSB of the left channel data is valid on the first falling edge of the bit clock after the rising
edge of the word clock. Because the right channel has an offset of 3, the MSB of its data is valid on the third
falling edge of the bit clock after the LSB of the left-channel data. As in the case of other modes, the serial output
bus is put in the high-impedance state, if tri-stating of the output is enabled, during all extra bit-clock cycles in the
frame.
Right Channel
Left Channel
WORD
CLOCK
BIT
CLOCK
n-1n-2 n-3
n-1 n-2 n-3
3
2
1
0
n-1 n-2n-3
2
1
DATA
3
0
3
RD(n)
LD(n)
RD(n+1)
Ch_Offset_1 = 0
Ch_Offset_2 = 3
图 25. DSP Mode, Time-Slot-Based Mode Enabled, Ch_Offset_1 = 0, Ch_Offset_2 = 3
20
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Feature Description (接下页)
图 26 shows the timing diagram for the DSP mode with left and right channels swapped, Ch_Offset_1 = 0, and
Ch_Offset_2 = 3. The MSB of the right channel is valid on the first falling edge of the bit clock after the rising
edge of the word clock. Similarly, the MSB of the left channel is valid three bit-clock cycles after the LSB of right
channel because the offset for the left channel is 3.
Right Channel
Left Channel
WORD
CLOCK
BIT
CLOCK
n-1n-2 n-3
n-1 n-2 n-3
3
2
1
0
n-1 n-2n-3
2
1
DATA
3
0
3
RD(n)
LD(n)
RD(n+1)
Ch_Offset_1 = 0
Ch_Offset_2 = 3
图 26. DSP Mode, Time-Slot-Based Mode Enabled, Ch_Offset_1 = 0, Ch_Offset_2 = 3, Channel Swap
Enabled
8.3.6 Audio Clock Generation
The audio converters in the fully programmable filter mode of the TLV320ADC3100 require an internal audio
master clock at a frequency of ≥ N × fS, where N = IADC (page 0, register 21) when filter mode (page 0, register
61) equals zero; otherwise, N equals the instruction count from the ADC processing blocks (see 表 6). The
master clock is obtained from an external clock signal applied to the device.
The device can accept an MCLK input from 512 kHz to 50 MHz, which can then be passed through either a
programmable divider or a PLL to get the proper internal audio master clock required by the device. The BCLK
input can also be used to generate the internal audio master clock.
A primary concern is proper operation of the TLV320ADC3100 at various sample rates with the limited MCLK
frequencies available in the system. This device includes a programmable PLL to accommodate such situations.
The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with particular focus
paid to the standard MCLK rates already widely used.
When the PLL is enabled:
fS = (PLLCLK_IN × K × R) / (NADC × MADC × AOSR × P)
where
•
•
•
•
•
•
P = 1, 2, 3,…, 8
R = 1, 2, …, 16
K = J.D
J = 1, 2, 3, …, 63
D = 0000, 0001, 0002, 0003, …, 9998, 9999
PLLCLK_IN can be MCLK or BCLK, selected by page 0, register 4, bits 3:2
(1)
P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal
point), whereas D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits
of precision).
Examples:
If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004
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Feature Description (接下页)
When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified
performance:
512 kHz ≤ (PLLCLK_IN / P) ≤ 20 MHz
80 MHz ≤ (PLLCLK _IN × K × R / P) ≤ 110 MHz
4 ≤ J ≤ 55
When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied to meet specified
performance:
10 MHz ≤ PLLCLK _IN / P ≤ 20 MHz
80 MHz ≤ PLLCLK _IN × K × R / P ≤ 110 MHz
4 ≤ J ≤ 11
R = 1
Example:
For MCLK = 12 MHz, fS = 44.1 kHz, NADC = 8, MADC = 2, and AOSR = 128:
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264
Example:
For MCLK = 12 MHz, fS = 48 kHz , NADC = 8, MADC = 2, and AOSR = 128:
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920
表 1 lists several example cases of typical MCLK rates and how to program the PLL to achieve sample rates of
fS = 44.1 kHz or 48 kHz with NADC = 8, MADC = 2, and AOSR = 128.
表 1. Typical MCLK Rates
MCLK (MHz)
fS = 44.1 kHz
P
R
J
D
ACHIEVED fS
% ERROR
2.8224
5.6448
12.0
1
1
1
1
1
1
1
4
1
1
1
1
1
1
1
1
32
16
7
0
44,100.00
44,100.00
44,100.00
44,099.71
44,100.00
44,100.00
44,100.30
44,100.00
0.0000
0.0000
0.0000
–0.0007
0.0000
0.0000
0.0007
0.0000
0
5264
9474
6448
7040
5893
5264
13.0
6
16.0
5
19.2
4
19.68
48.0
4
7
fS = 48 kHz
2.048
3.072
4.096
6.144
8.192
12.0
1
1
1
1
1
1
1
1
1
1
4
1
1
1
1
1
1
1
1
1
1
1
48
32
24
16
12
8
0
48,000.00
48,000.00
48,000.00
48,000.00
48,000.00
48,000.00
47,999.71
48,000.00
48,000.00
47,999.79
48,000.00
0.0000
0.0000
0.0000
0.0000
0.0000
0.0000
–0.0006
0.0000
0.0000
–0.0004
0.0000
0
0
0
0
1920
5618
1440
1200
9951
1920
13.0
7
16.0
6
19.2
5
19.68
48.0
4
8
22
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图 27 shows a detailed diagram of the audio clock section of the TLV320ADC3100.
MCLK
50 MHzMAX
BCLK
13 MHzMAX
P0:0x04(4) [Clock-Gen Muxing] (0h)
PLL_CLK_IN REG
ADC_CLK
ADC_MOD_CLK
PLL_CLKIN
50 MHZMAX
P0:0x1D(29)
[ADC Interface Control 2]
(2h)
P0:0x05(5) [PLL P and R-VAL] (11h)
P0:0x06(6) [PLL J-VAL] (4h)
P0:0x07(7) [PLL D-VAL MSB] (0h)
P0:0x08(8) [PLL D-VAL LSB] (0h)
PLL
BDIV_CLKIN
26 MHZMAX
X(RxJ.D)/P
P0:0x1E(30)
[BDIV N_VAL] (1h)
PLL_CLKIN
100 MHZMAX
MCLK
50 MHzMAX
BCLK
13 MHzMAX
œ N
N = 1, 2, …, 127, 128
P0:0x04(4) [Clock-Gen Muxing] (0h)
CODEC_CLKIN REG
ADC_CLKIN
BCLK
P0:0x12(18)
BCLK is an output in master mode
[ADC NADC_VAL] (1h)]
P0:0x1B(27):[ADC Interface Control 1]
œ NADC
MCLK
BCLK PLL_CLK ADC_CLK ADC_MOD_CLK
NADC = 1, 2, …, 127, 128
50 MHZMAX 13 MHZMAX
ADC_CLK
33 MHZMAX
P0:0x19(25) [CLKOUT MUX] (0h)
P0:0x13(19)
[ADC NADC_VAL] (1h)]
œ MADC
CDIV_CLKIN
110 MHZMAX
MADC = 1, 2, …, 127, 128
ADC_MOD_CLK
6.5 MHZMAX
P0:0x1E(26)
[CLKOUT M_VAL] (1h)
œ M
P0:0x14(20)
[ADC AOSR_VAL] (80h)]
M = 1, 2, …, 127, 128
œ AOSR
AOSR = 1, 2, …, 255, 256
CLKOUT (DOUT,GPIO1)
P0:0x35(53)
[DOUT Control] (1Eh)
ADC_FS
100 kHZMAX
NOTE: MADC × AOSR ≥ IADC, where IADC is the number of instructions (instruction count) for the ADC MAC engine. IADC
is programmable from 2, 4,…, 510. The convention used in this figure is page number: register number (reset value).
图 27. Audio Clock Generation Processing
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8.3.7 Stereo Audio ADC
The TLV320ADC3100 includes a stereo audio ADC that uses a delta-sigma modulator with 128-times
oversampling in single-rate mode, followed by a digital decimation filter. The ADC supports sampling rates from
8 kHz to 48 kHz in single-rate mode, and up to 96 kHz in dual-rate mode. Whenever the ADC is in operation, the
device requires that an audio master clock be provided and appropriate audio clock generation be set up within
the device.
In order to provide optimal system power dissipation, the stereo ADC can be powered one channel at a time, to
support when only mono record capability is required. In addition, both channels can be fully or partially powered
down.
The integrated digital decimation filter removes high-frequency content and down-samples the audio data from
an initial sampling rate of 128 fS to the final output sampling rate of fS. The decimation filter provides a linear
phase output response with a group delay of 17 / fS. The –3-dB bandwidth of the decimation filter extends to
0.45 fS and scales with the sample rate (fS). The filter has a minimum 73-dB attenuation over the stop band from
0.55 fS to 64 fS. Independent digital high-pass filters are also included with each ADC channel, with a corner
frequency that can be set independently by programmable coefficients or can be disabled entirely.
Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering,
requirements for analog antialiasing filtering are relaxed. The TLV320ADC3100 integrates a second-order analog
antialiasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimation filter, provides
sufficient antialiasing filtering without requiring additional external components.
The ADC is preceded by a programmable gain amplifier (PGA) that allows analog gain control from 0 dB to
40 dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft-stepping algorithm that
only changes the actual volume level by one 0.5-dB step every one or two ADC output samples, depending on
the register programming (see register page 0, register 81). This soft-stepping specifies that volume control
changes occur smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and upon
power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the
gain applied by the PGA equals the desired value set by the register. The soft-stepping control can also be
disabled by programming a register bit.
8.3.8 Audio Analog Inputs
8.3.8.1 Digital Volume Control
The TLV320ADC3100 also has a digital volume-control block with a range from –12 dB to 20 dB (as shown in 表
2) in steps of 0.5 dB. This block is set by programming page 0, registers 83 and 84 for the left and right
channels, respectively.
表 2. Digital Volume Control for the ADC
DESIRED GAIN
(dB)
LEFT, RIGHT CHANNEL
PAGE 0, REGISTERS 83 AND 84, BITS 6:0
–12
–11.5
–11
...
110 1000
110 1001
110 1010
...
–0.5
0
111 1111
000 0000 (default)
000 0001
...
0.5
...
19.5
20
010 0111
010 1000
24
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During volume control changes, the soft-stepping feature is used to avoid audible artifacts. The soft-stepping rate
can be set to either 1 or 2 gain steps per sample. Soft-stepping can also be entirely disabled. This soft-stepping
is configured via page 0, register 81, bits 1:0, and is common to soft-stepping control for the analog PGA. During
power-down of an ADC channel, this volume control soft-steps down to –12 dB before powering down. Resulting
from the soft-stepping control, soon after changing the volume control setting or powering down the ADC
channel, the actual applied gain may be different from the one programmed through the control register. The
TLV320ADC3100 provides feedback through the read-only flags in page 0, register 36, bit 7 for the left channel
and page 0, register 36, bit 3 for the right channel.
8.3.8.2 Fine Digital Gain Adjustment
Additionally, the gain in each channel is finely adjustable in steps of 0.1 dB. This feature is useful when trying to
match the gain between channels. By programming page 0, register 82, the gain can be adjusted from 0 dB to
–0.4 dB in steps of 0.1 dB. This feature, in combination with the regular digital volume control, allows the gains
through the left and right channels be matched in the range of –0.5 dB to 0.5 dB with a resolution of 0.1 dB.
8.3.8.3 AGC
The TLV320ADC3100 includes automatic gain control (AGC) for ADC recording. AGC can be used to maintain a
nominally constant output level when recording speech. As opposed to manually setting the PGA gain, in the
AGC mode, the circuitry automatically adjusts the PGA gain as the input signal becomes overly loud or very
weak, such as when a person speaking into a microphone moves closer to or farther from the microphone. The
AGC algorithm has several programmable parameters (including target gain, attack and decay time constants,
noise threshold, and maximum PGA applicable) that allow the algorithm to be fine-tuned for any particular
application. The algorithm uses the absolute average of the signal (which is the average of the absolute value of
the signal) as a measure of the nominal amplitude of the output signal. Because the gain can be changed at the
sample interval time, the AGC algorithm operates at the ADC sample rate.
•
Target level represents the nominal output level at which the AGC attempts to hold the ADC output signal
level. The TLV320ADC3100 allows programming of eight different target levels that can be programmed from
–5.5 dB to –24 dB relative to a full-scale signal. Because the TLV320ADC3100 reacts to the signal absolute
average and not to peak levels, TI recommends that the target level be set with enough margin to avoid
clipping at the occurrence of loud sounds.
•
Attack time determines how quickly the AGC circuitry reduces the PGA gain when the output signal level
exceeds the target level resulting from an increase in input signal level. A wide range of attack-time
programmability is supported in terms of number of samples (that is, the number of ADC sample-frequency
clock cycles).
•
•
Decay time determines how quickly the PGA gain is increased when the output signal level falls below the
target level resulting from a reduction in input signal level. A wide range of decay-time programmability is
supported in terms of number of samples (that is, the number of ADC sample-frequency clock cycles).
Noise threshold. If the input signal level falls below the noise threshold, the AGC considers the duration that
the signal level remains below the threshold as silence, and thus brings down the gain to 0 dB in steps of
0.5 dB every sample period and sets the noise-threshold flag. The gain stays at 0 dB unless the input signal
average rises above the noise threshold setting, thus preventing noise from being amplified in the absence of
a signal. The noise threshold level in the AGC algorithm is programmable from –30 dB to –90 dB of full-scale.
When the AGC noise threshold is set to –70 dB, –80 db, or –90 dB, the maximum applicable microphone
input PGA setting must be greater than or equal to 11.5 dB, 21.5 dB, or 31.5 dB, respectively. This operation
includes hysteresis and debounce to prevent the AGC gain from cycling between high gain and 0 dB when
signals are near the noise threshold level. The noise (or silence) detection feature can also be entirely
disabled.
•
•
Maximum applicable PGA allows the maximum gain applied by the AGC to be restricted. This restriction can
be used for limiting PGA gain in situations where environmental noise is greater than the programmed noise
threshold. Microphone input maximum PGA can be programmed from 0 dB to 40 dB in steps of 0.5 dB.
Hysteresis, as the name suggests, determines a window around the noise threshold that must be exceeded
to detect if the recorded signal is indeed either noise or signal. If the energy of the recorded signal is initially
greater than the noise threshold, then the AGC recognizes the signal as noise only when the energy of the
recorded signal falls below the noise threshold by a value given by hysteresis. Similarly, after the recorded
signal is recognized as noise, for the AGC to recognize the sound as a signal, its energy must exceed the
noise threshold by a value given by the hysteresis setting. In order to prevent the AGC from jumping between
noise and signal states (which can happen when the energy of the recorded signal is very close to the noise
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threshold), a non-zero hysteresis value must be chosen. The hysteresis feature can also be disabled.
•
Debounce time (noise and signal) determines the hysteresis in time domain for noise detection. The AGC
continuously calculates the energy of the recorded signal. If the calculated energy is less than the set noise
threshold, then the AGC does not increase the input gain to achieve the target level. However, to handle
audible artifacts that can occur when the energy of the input signal is very close to the noise threshold, the
AGC checks if the energy of the recorded signal is less than the noise threshold for a duration greater than
the noise debounce time. Similarly, the AGC starts increasing the input-signal gain to reach the target level
when the calculated energy of the input signal is greater than the noise threshold. Again, to avoid audible
artifacts when the input-signal energy is very close to noise threshold, the energy of the input signal must
continuously exceed the noise threshold value for the signal debounce time. If the debounce times are kept
very small, then audible artifacts can result by rapidly enabling and disabling the AGC function. At the same
time, if the debounce time is kept too large, then the AGC can take more time to respond to changes in input
signal levels with respect to the noise threshold. Both noise and signal debounce time can be disabled.
•
•
The AGC noise threshold flag is a read-only flag indicating that the input signal has levels lower than the
noise threshold, and thus is detected as noise (or silence). In such a condition, the AGC applies a gain of
0 dB.
Gain applied by the AGC is a read-only register setting that gives a real-time feedback to the system on the
gain applied by the AGC to the recorded signal. This setting, along with the target setting, can be used to
determine the input signal level. In a steady state situation:
Target level (dB ) = gain applied by AGC (dB) + input signal level (dB)
When the AGC noise threshold flag is set, then the status of the gain applied by the AGC is not valid.
•
The AGC saturation flag is a read-only flag indicating that the ADC output signal has not reached its target
level. However, the AGC is unable to increase the gain further because the required gain is higher than the
maximum allowed PGA gain. Such a situation can happen when the input signal has very low energy and the
noise threshold is also set very low. When the AGC noise threshold flag is set, the status of the AGC
saturation flag must be ignored.
•
•
The ADC saturation flag is a read-only flag indicating an overflow condition in the ADC channel. On
overflow, the signal is clipped and distortion results. This distortion typically happens when the AGC target
level is kept very high and the energy in the input signal increases faster than the attack time.
An AGC low-pass filter is used to help determine the average level of the input signal. This average level is
compared to the programmed detection levels in the AGC to provide the correct functionality. This low-pass
filter is in the form of a first-order IIR filter. Two 8-bit registers are used to form the 16-bit digital coefficient, as
shown in the Register Maps section. In this way, a total of six registers are programmed to form the three IIR
coefficients. 公式 2 shows how the transfer function of the filter is implemented for signal-level detection:
-1
N0 + N1z
215 - D1z
H(z) =
-1
where
•
•
•
•
Coefficient N0 can be programmed by writing into page 4, registers 2 and 3
Coefficient N1 can be programmed by writing into page 4, registers 4 and 5
Coefficient D1 can be programmed by writing into page 4, registers 6 and 7
N0, N1, and D1 are 16-bit, 2s-complement numbers, and their default values implement a low-pass filter with
cutoff at 0.002735 × ADC_fS
(2)
表 3 lists various AGC programming options. The AGC can be used only if the analog microphone input is
routed to the ADC channel.
图 28 illustrates the input and output signals along with the decay and attack times of the AGC.
26
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表 3. AGC Parameter Settings
CONTROL REGISTER
LEFT ADC
Page 0, register 86
CONTROL REGISTER
RIGHT ADC
Page 0, register 94
FUNCTION
BIT
AGC enable
7
Target level
Page 0, register 86
Page 0, register 87
Page 0, register 87
Page 0, register 88
Page 0, register 89
Page 0, register 90
Page 0, register 91
Page 0, register 92
Page 0, register 93
Page 0, register 94
Page 0, register 95
Page 0, register 95
Page 0, register 96
Page 0, register 97
Page 0, register 98
Page 0, register 99
Page 0, register 100
Page 0, register 101
6:4
Hysteresis
7:6
Noise threshold
5:1
Maximum applicable PGA
Time constants (attack time)
Time constants (decay time)
Debounce time (noise)
Debounce time (signal)
Gain applied by the AGC
6:0
7:0
7:0
4:0
3:0
7:0 (read-only)
Page 0, register 45 (sticky flag),
Page 0, register 47 (non-sticky
flag)
Page 0, register 45 (sticky flag),
Page 0, register 47 (non-sticky flag)
AGC noise-threshold flag
AGC saturation flag
ADC saturation flag
6:5 (read-only)
5, 1 (read-only)
3:2 (read-only)
Page 0, register 36 (sticky flag)
Page 0, register 36 (sticky flag)
Page 0, register 42 (sticky flag),
Page 0, register 43 (non-sticky
flag)
Page 0, register 42 (sticky flag),
Page 0, register 43 (non-sticky flag)
Input
Signal
Output
Signal
Target
Level
AGC
Gain
Decay Time
Attack
Time
图 28. AGC Characteristics
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The TLV320ADC3100 includes two analog audio input pins, which can be configured as one fully-differential pair
and one single-ended input, or as three single-ended audio inputs. These pins connect through series resistors
and switches to the virtual ground terminals of two fully differential operational amplifiers (one per ADC and PGA
channel). By selecting to turn on only one set of switches per operational amplifier at a time, the inputs can be
effectively multiplexed to each ADC PGA channel.
By selecting to turn on multiple sets of switches per operational amplifier at a time, mixing can also be achieved.
Mixing of multiple inputs can easily lead to PGA outputs that exceed the range of the internal operational
amplifiers, resulting in saturation and clipping of the mixed output signal. Whenever mixing is being implemented,
take adequate precautions to avoid such a saturation case from occurring. In general, the mixed signal must not
exceed 2 VPP (single-ended) or 4 VPP (differential).
In most mixing applications, there is also a general requirement to adjust the levels of the individual signals being
mixed. For example, if a soft signal and a large signal are to be mixed and played together, the soft signal
generally must be amplified to a level comparable to the large signal before mixing. In order to accommodate this
requirement, the TLV320ADC3100 includes an input level control on each of the individual inputs before they are
mixed or multiplexed into the ADC PGAs, with programmable attenuation at 0 dB, –6 dB, or off.
注
This input-level control is not intended to be a volume control, but instead used for coarse
level setting. Finer soft-stepping of the input level is implemented in this device by the
ADC PGA.
图 29 shows various available configurations for the audio input.
AGC
IN2L(P)
IN3L(M)
IN2L(P)
IN3L(M)
PGA
0/+40 dB
0.5 dB Steps
+
IN2L(P)
IN3L(M)
IN2R(P)
IN3R(M)
ADC
+
œ
All coarse stage attenuations are set to 0 dB, œ6
dB, or Off by register setting.
The default is all the switches are off at startup.
AGC
IN2R(P)
IN3R(M)
IN2R(P)
IN2R(P)
IN3R(M)
PGA
0/+40 dB
0.5 dB Steps
+
ADC
+
œ
IN3R(M)
IN2L(P)
IN3L(M)
图 29. TLV320ADC3100 Available Audio Input Path Configurations
表 4 lists the available routing configurations for the audio signals on the TLV320ADC3100.
表 4. TLV320ADC3100 Audio Signals
AUDIO SIGNALS AVAILABLE TO THE LEFT ADC
AUDIO SIGNALS AVAILABLE TO THE RIGHT ADC
SINGLE-ENDED INPUTS
IN2L(P)
DIFFERENTIAL INPUTS
IN2L(P), IN3L(M)
SINGLE-ENDED INPUTS
IN2R(P)
DIFFERENTIAL INPUTS
IN2R(P), IN3R(M)
IN3L(M)
IN2R(P), IN3R(M)
IN3R(M)
IN2L(P), IN3L(M)
28
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Inputs can be selected as single-ended instead of fully differential, and mixing or multiplexing into the ADC PGAs
is also possible in this mode. However, an input pair cannot be selected as fully differential for connection to one
ADC PGA and simultaneously selected as single-ended for connection to the other ADC PGA channel. However,
an input can be selected or mixed into both the left and right channel PGAs, as long as the PGA has the same
configuration for both channels (either both single-ended or both fully differential).
8.3.9 Input Impedance and VCM Control
The TLV320ADC3100 includes several programmable settings to control the analog input pins, particularly when
the pins are not selected for connection to an ADC PGA. The default option allows unselected inputs to be put
into a high-impedance state. However, the pins on the device do include protection diode circuits connected to
AVDD and AVSS. Thus, if any voltage is driven onto a pin approximately one diode drop (~0.6 V) above AVDD
or one diode drop below AVSS, these protection diodes begin conducting current, resulting in an effective
impedance that no longer appears as a high-impedance state.
Another programmable option for unselected analog inputs is to weakly hold those inputs at the common-mode
input voltage of the ADC PGA (determined by an internal band-gap voltage reference). This feature is useful to
keep the AC-coupling capacitors connected to the analog inputs biased up at a normal DC level, thus avoiding
the need for them to charge up suddenly when the input is changed from being unselected to selected for
connection to an ADC PGA. This option is controlled in page 1, register 52 through page 1, register 57. This
option must be disabled when an input is selected for connection to an ADC PGA or selected for the analog input
bypass path, because the input can corrupt the recorded input signal if left operational when an input is selected.
In most cases, the analog input pins on the TLV320ADC3100 must be AC-coupled to analog input sources, the
only exception generally being if an ADC is used for DC voltage measurement. The AC-coupling capacitor
causes a high-pass filter pole to be inserted into the analog signal path, so the size of the capacitor must be
chosen to move that filter pole sufficiently low in frequency to cause minimal effect on the processed analog
signal. The input impedance of the analog inputs, when selected for connection to an ADC PGA, varies with the
setting of the input-level control, starting at approximately 35 kΩ with an input-level control setting of 0 dB, and
62.5-kΩ when the input-level control is set at –6 dB. For example, using a 0.1-µF, AC-coupling capacitor at an
analog input results in a high-pass filter pole of 45.5 Hz when the 0-dB, input-level control setting is selected. 表
5 lists various mixer gains and microphone PGA ranges to set a high-pass corner for the application.
表 5. Single-Ended Input Impedance vs PGA Ranges(1)
MIXER GAIN (dB)
MICROPHONE PGA RANGE (dB)
INPUT IMPEDANCE (Ω)
35,000
0
0
0–5.5
6–11.5
12–17.5
18–23.5
24–29.5
30–35.5
36–40
38,889
0
42,000
0
44,074
0
45,294
0
45,960
0
46,308
–6
–6
–6
–6
–6
–6
–6
0–5.5
62,222
6–11.5
12–17.5
18–23.5
24–29.5
30–35.5
36–40
70,000
77,778
84,000
88,148
90,588
91,919
(1) Valid when only one input is enabled.
8.3.10 MICBIAS Generation
The TLV320ADC3100 includes a programmable microphone bias output (MICBIAS1) capable of providing output
voltages of 2 V or 2.5 V (both derived from the on-chip, band-gap voltage) with 4-mA, output-current drive
capability. In addition, the MICBIAS output can be programmed to switch to AVDD directly through an on-chip
switch, or powered down completely when not needed, for power savings. This function is controlled by register
programming in page 1, register 51.
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8.3.11 ADC Decimation Filtering and Signal Processing
The TLV320ADC3100 ADC channel includes a built-in digital decimation filter to process the oversampled data
from the delta-sigma modulator to generate digital data at the Nyquist sampling rate with high dynamic range.
The decimation filter can be chosen from three different types, depending on the required frequency response,
group delay, and sampling rate.
8.3.11.1 Processing Blocks
The TLV320ADC3100 offers a range of processing blocks that implement various signal processing capabilities
along with decimation filtering. These processing blocks provide a choice of how much and what type of signal
processing is used and which decimation filter is applied.
The signal processing blocks available are:
•
•
•
•
First-order IIR
Scalable number of biquad filters
Variable-tap FIR filter
AGC
The processing blocks are tuned for common cases and can achieve high antialias filtering or low group delay in
combination with various signal processing effects such as audio effects and frequency shaping. The available
first-order IIR, biquad, and FIR filters have fully user-programmable coefficients. The ADC processing blocks can
be selected by writing to page 0, register 61. The default (reset) processing block is PRB_R1. 表 6 lists the
available processing blocks for the ADC.
表 6. ADC Processing Blocks
FIRST-ORDER
DECIMATION
FILTER
NUMBER OF
BIQUADS
PROCESSING
BLOCKS
REQUIRED
AOSR VALUE
CHANNEL
FIR
INSTR CTR
IIR
AVAILABLE
PRB_R1
PRB_R2
PRB_R3
PRB_R4
PRB_R5
PRB_R6
PRB_R7
PRB_R8
PRB_R9
PRB_R10
PRB_R11
PRB_R12
PRB_R13
PRB_R14
PRB_R15
PRB_R16
PRB_R17
PRB_R18
Stereo
Stereo
Stereo
Right
A
A
A
A
A
A
B
B
B
B
B
B
C
C
C
C
C
C
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
0
5
0
0
5
0
0
3
0
0
3
0
0
5
0
0
5
0
No
No
128, 64
128, 64
128, 64
128, 64
128, 64
128, 64
64
188
240
236
96
25-tap
No
Right
No
120
120
88
Right
25-tap
No
Stereo
Stereo
Stereo
Right
No
64
120
128
46
20-tap
No
64
64
Right
No
64
60
Right
20-tap
No
64
64
Right
32
70
Stereo
Stereo
Right
No
32
124
120
36
25-tap
No
32
32
Right
No
32
64
Right
25-tap
32
62
30
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ZHCSHY2 –MARCH 2018
8.3.11.2 Processing Blocks: Details
图 30 shows the signal chain for a first-order IIR with AGC gain compensation, using filter A.
1st Order
AGC
To Audio
Interface
From Delta-Sigma
Modulator
Gain
Filter A
IIR
*
Compensation
AGC
From Digital Vol. Ctrl
To Analog PGA
图 30. Signal Chain for PRB_R1 and PRB_R4
图 31 shows the signal chain for a five-biquad, first-order IIR with AGC gain compensation, using filter A.
1st Order
AGC
To Audio
Interface
From Delta-Sigma
Modulator
Gain
Filter A
HA
HB
HC
HD
HE
IIR
*
Compensation
AGC
From Digital Vol. Ctrl
To Analog PGA
图 31. Signal Chain for PRB_R2 and PRB_R5
图 32 shows the signal chain for a 25-tap FIR, first-order IIR with AGC gain compensation, using filter A.
1st Order
AGC
To Audio
Interface
From Delta-Sigma
Modulator
Gain
Filter A
25-Tap FIR
IIR
*
Compensation
AGC
From Digital Vol. Ctrl
To Analog PGA
图 32. Signal Chain for PRB_R3 and PRB_R6
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图 33 shows the signal chain for a first-order IIR with AGC gain compensation, using filter B.
1st Order
AGC
To Audio
Interface
From Delta-Sigma
Modulator
Gain
Filter B
IIR
*
Compensation
AGC
From Digital Vol. Ctrl
To Analog PGA
图 33. Signal Chain for PRB_R7 and PRB_R10
图 34 shows the signal chain for a three-biquad, first-order IIR with AGC gain compensation, using filter B.
1st Order
AGC
To Audio
Interface
From Delta-Sigma
Modulator
Gain
Filter B
HA
HB
HC
IIR
*
Compensation
AGC
From Digital Vol. Ctrl
To Analog PGA
图 34. Signal Chain for PRB_R8 and PRB_R11
图 35 shows the signal chain for a 20-tap FIR, first-order IIR with AGC gain compensation, using filter B.
1st Order
AGC
To Audio
Interface
From Delta-Sigma
Modulator
Gain
Filter B
20-Tap FIR
IIR
*
Compensation
AGC
From Digital Vol. Ctrl
To Analog PGA
图 35. Signal Chain for PRB_R9 and PRB_R12
32
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图 36 shows the signal chain for a first-order IIR with AGC gain compensation, using filter C.
1st Order
AGC
To Audio
Interface
From Delta-Sigma
Modulator
Gain
Filter C
IIR
*
Compensation
AGC
From Digital Vol. Ctrl
To Analog PGA
图 36. Signal Chain for PRB_R13 and PRB_R16
图 37 shows the signal chain for a five-biquad, first-order IIR with AGC gain compensation, using filter C.
1st Order
AGC
To Audio
Interface
From Delta-Sigma
Modulator
Gain
Filter C
HA
HB
HC
HD
HE
IIR
*
Compensation
AGC
From Digital Vol. Ctrl
To Analog PGA
图 37. Signal Chain for PRB_R14 and PRB_R17
图 38 shows the signal chain for a 25-tap FIR, first-order IIR with AGC gain compensation, using filter C.
1st Order
AGC
To Audio
Interface
From Delta-Sigma
Modulator
Gain
Filter C
25-Tap FIR
IIR
*
Compensation
AGC
From Digital Vol. Ctrl
To Analog PGA
图 38. Signal for PRB_R15 and PRB_R18
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8.3.11.3 User-Programmable Filters
Depending on the selected processing block, different types and orders of digital filtering are available. A first-
order IIR filter is always available, and is useful to filter out possible DC components of the signal efficiently. Up
to five biquad sections, or alternatively up to 25-tap FIR filters, are available for specific processing blocks. The
coefficients of the available filters are arranged as sequentially indexed coefficients in two banks. If adaptive
filtering is chosen, the coefficient banks can be switched while the processor is running.
The coefficients of these filters, as shown in 表 7, are each 16 bits wide, in 2s-complement format, and occupy
two consecutive 8-bit registers in the register space. Specifically, the filter coefficients, shown in 图 39, are in
1.15 (one dot 15) format with a range from –1.0 (0x8000) to 0.999969482421875 (0x7FFF).
表 7. ADC First-Order IIR Filter Coefficients
FILTER
FILTER COEFFICIENT
ADC COEFFICIENT, LEFT CHANNEL
C4 (page 4, registers 8, 9)
ADC COEFFICIENT, RIGHT CHANNEL
C36 (page 4, registers 72, 73)
C37 (page 4, registers 74, 75)
C38 (page 4, registers 76, 77)
N0
N1
D1
First-order IIR
C5 (page 4, registers 10, 11)
C6 (page 4, registers 12, 13)
Largest Positive Number
= 0.1111 1111 1111 111
= 0.999969482421875 = 1.0 œ 1 LSB
2œ15 Bit
2œ4 Bit
Largest Negative Number
= 1.0000 0000 0000 000
= 0 x 8000 = œ1.0 (by definition)
2œ1 Bit
Fraction Point
Sign Bit
S . xxxx xxxx xxxx xxx
图 39. 2s-Complement Coefficient Format
8.3.11.3.1 First-Order IIR Section
公式 3 gives the transfer function for the first-order IIR filter.
-1
N0 + N1z
215 - D1z
H(z) =
-1
(3)
The frequency response for the first-order IIR section with default coefficients is flat at a gain of 0 dB.
34
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8.3.11.3.2 Biquad Section
公式 4 gives the transfer function of each biquad filter.
N0 + 2 × N1z-1 + N2z-2
215 - 2 ´ D1z-1 - D2z-2
H(z) =
(4)
The frequency response for each of the biquad sections with default coefficients is flat at a gain of 0 dB. 表 8 lists
the available coefficients for the five biquad filters.
表 8. ADC Biquad Filter Coefficients
FILTER
FILTER COEFFICIENT
ADC COEFFICIENT, LEFT CHANNEL
C7 (page 4, registers 14, 15)
C8 (page 4, registers 16, 17)
C9 (page 4, registers 18, 19)
C10 (page 4, registers 20, 21)
C11 (page 4, registers 22, 23)
C12 (page 4, registers 24, 25)
C13 (page 4, registers 26, 27)
C14 (page 4, registers 28, 29)
C15 (page 4, registers 30, 31)
C16 (page 4, registers 32, 33)
C17 (page 4, registers 34, 35)
C18 (page 4, registers 36, 37)
C19 (page 4, registers 38, 39)
C20 (page 4, registers 40, 41)
C21 (page 4, registers 42, 43)
C22 (page 4, registers 44, 45)
C23 (page 4, registers 46, 47)
C24 (page 4, registers 48, 49)
C25 (page 4, registers 50, 51)
C26 (page 4, registers 52, 53)
C27 (page 4, registers 54, 55)
C28 (page 4, registers 56, 57)
C29 (page 4, registers 58, 59)
C30 (page 4, registers 60, 61)
C31 (page 4, registers 62, 63)
ADC COEFFICIENT, RIGHT CHANNEL
C39 (page 4, registers 78, 79)
C40 (page 4, registers 80, 81)
C41 (page 4, registers 82, 83)
C42 (page 4, registers 84, 85)
C43 (page 4, registers 86, 87)
C44 (page 4, registers 88, 89)
C45 (page 4, registers 90, 91)
C46 (page 4, registers 92, 93)
C47 (page 4, registers 94, 95)
C48 (page 4, registers 96, 97)
C49 (page 4, registers 98, 99)
C50 (page 4, registers 100, 101)
C51 (page 4, registers 102, 103)
C52 (page 4, registers 104, 105)
C53 (page 4, registers 106, 107)
C54 (page 4, registers 108, 109)
C55 (page 4, registers 110, 111)
C56 (page 4, registers 112,113)
C57 (page 4, registers 114, 115)
C58 (page 4, registers 116, 117)
C59 (page 4, registers 118, 119)
C60 (page 4, registers 120, 121)
C61 (page 4, registers 122,123)
C62 (page 4, registers 124, 125)
C63 (page 4, registers 126, 127)
N0
N1
N2
D1
D2
N0
N1
N2
D1
D2
N0
N1
N2
D1
D2
N0
N1
N2
D1
D2
N0
N1
N2
D1
D2
BIQUAD A
BIQUAD B
BIQUAD C
BIQUAD D
BIQUAD E
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8.3.11.3.3 FIR Section
Six of the available ADC processing blocks offer FIR filters for signal processing. PRB_R9 and PRB_R12 feature
a 20-tap FIR filter, whereas the processing blocks PRB_R3, PRB_R6, PRB_R15, and PRB_R18 feature a 25-tap
FIR filter. 公式 5 gives the transfer function of the Mth order FIR filter that is reconfigurable based on the
processing block chosen.
M
H(z) =
FIRnz-n
å
n=0
M = 24 for PRB _R3, PRB _R6, PRB _R15, and PRB _R18
M = 19 for PRB _R9 and PRB _R12
(5)
The coefficients of the FIR filters correspond to the ADC coefficient space as listed in 表 9 and are 16-bit, 2s-
complement format. There is no default transfer function for the FIR filter. When the FIR filter is used, all
applicable coefficients must be programmed.
表 9. ADC FIR Filter Coefficients
FILTER COEFFICIENT
FIR0
ADC COEFFICIENT, LEFT CHANNEL
C7 (page 4, registers 14, 15)
C8 (page 4, registers 16, 17)
C9 (page 4, registers 18, 19)
C10 (page 4, registers 20, 21)
C11 (page 4, registers 22, 23)
C12 (page 4, registers 24, 25)
C13 (page 4, registers 26, 27)
C14 (page 4, registers 28, 29)
C15 (page 4, registers 30, 31)
C16 (page 4, registers 32, 33)
C17 (page 4, registers 34, 35)
C18 (page 4, registers 36, 37)
C19 (page 4, registers 38, 39)
C20 (page 4, registers 40, 41)
C21 (page 4, registers 42, 43)
C22 (page 4, registers 44, 45)
C23 (page 4, registers 46, 47)
C24 (page 4, registers 48, 49)
C25 (page 4, registers 50, 51)
C26 (page 4, registers 52, 53)
C27 (page 4, registers 54, 55)
C28 (page 4, registers 56, 57)
C29 (page 4, registers 58, 59)
C30 (page 4, registers 60, 61)
C31 (page 4, registers 62, 63)
ADC COEFFICIENT, RIGHT CHANNEL
C39 (page 4, registers 78, 79)
C40 (page 4, registers 80, 81)
C41 (page 4, registers 82, 83)
C42 (page 4, registers 84, 85)
C43 (page 4, registers 86, 87)
C44 (page 4, registers 88, 89)
C45 (page 4, registers 90, 91)
C46 (page 4, registers 92, 93)
C47 (page 4, registers 94, 95)
C48 (page 4, registers 96, 97)
C49 (page 4, registers 98, 99)
C50 (page 4, registers 100, 101)
C51 (page 4, registers 102, 103)
C52 (page 4, registers 104, 105)
C53 (page 4, registers 106, 107)
C54 (page 4, registers 108, 109)
C55 (page 4, registers 110, 111)
C56 (page 4, registers 112, 113)
C57 (page 4, registers 114, 115)
C58 (page 4, registers 116, 117)
C59 (page 4, registers 118, 119)
C60 (page 4, registers 120, 121)
C61 (page 4, registers 122, 123)
C62 (page 4, registers 124, 125)
C63 (page 4, registers 126, 127)
FIR1
FIR2
FIR3
FIR4
FIR5
FIR6
FIR7
FIR8
FIR9
FIR10
FIR11
FIR12
FIR13
FIR14
FIR15
FIR16
FIR17
FIR18
FIR19
FIR20
FIR21
FIR22
FIR23
FIR24
8.3.11.4 Decimation Filter
The TLV320ADC3100 offers three different types of decimation filters. The integrated digital decimation filter
removes high-frequency content and downsamples the audio data from an initial sampling rate of AOSR × fS to
the final output sampling rate of fS. Decimation filtering is achieved using a higher-order cascaded integrator-
comb (CIC) filter followed by linear-phase FIR filters. The decimation filter cannot be chosen by itself; this filter is
implicitly set through the chosen processing block.
This section describes the properties of the available filters A, B, and C.
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8.3.11.4.1 Decimation Filter A
This filter is intended for use at sampling rates up to 48 kHz. When configuring this filter, the oversampling ratio
of the ADC can either be 128 or 64. For highest performance, the oversampling ratio must be set to 128. Filter A
can also be used for 96 kHz at an AOSR of 64. 表 10 specifies the performance of filter A. 图 40 shows the
frequency response for filter A.
表 10. Specification for ADC Decimation Filter A
PARAMETER
CONDITION
VALUE (Typical)
UNIT
AOSR = 128
Filter gain pass band
Filter gain stop band
Filter group delay
0 fS–0.39 fS
0.062
–73
dB
dB
s
0.55 fS–64 fS
17 / fS
0.062
0.05
Pass-band ripple, 8 kSPS
Pass-band ripple, 44.18 kSPS
Pass-band ripple, 48 kSPS
AOSR = 64
0 fS–0.39 fS
0 fS–0.39 fS
0 fS–0.39 fS
dB
dB
dB
0.05
Filter gain pass band
0 fS–0.39 fS
0.062
–73
dB
dB
s
Filter gain stop band
0.55 fS–32 fS
Filter group delay
17 / fS
0.062
0.05
Pass-band ripple, 8 kSPS
Pass-band ripple, 44.18 kSPS
Pass-band ripple, 48 kSPS
Pass-band ripple, 96 kSPS
0 fS–0.39 fS
0 fS–0.39 fS
0 fS–0.39 fS
0 kHz–20 kHz
dB
dB
dB
dB
0.05
0.1
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Frequency Normalized With Respect to fS
ADC channel response for decimation filter A
(red line corresponds to –73 dB)
图 40. ADC Decimation Filter A, Frequency Response
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8.3.11.4.2 Decimation Filter B
Filter B is intended to support sampling rates up to 96 kHz at an oversampling ratio of 64. 表 11 specifies the
performance of filter B. 图 41 shows the frequency response for filter B.
表 11. Specification for ADC Decimation Filter B
PARAMETER
CONDITION
VALUE (Typical)
UNIT
AOSR = 64
Filter gain pass band
Filter gain stop band
Filter group delay
0 fS–0.39 fS
±0.077
–46
dB
dB
s
0.6 fS–32 fS
11 / fS
0.076
0.06
Pass-band ripple, 8 kSPS
Pass-band ripple, 44.18 kSPS
Pass-band ripple, 48 kSPS
Pass-band ripple, 96 kSPS
0 fS–0.39 fS
0 fS–0.39 fS
0 fS–0.39 fS
0 kHz–20 kHz
dB
dB
dB
dB
0.06
0.11
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Frequency Normalized With Respect to fS
ADC channel response for decimation filter B
(red line corresponds to –44 dB)
图 41. ADC Decimation Filter B, Frequency Response
38
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8.3.11.4.3 Decimation Filter C
Filter type C, along with an AOSR of 32, is specially designed for 192-kSPS operation of the ADC. The pass
band, which extends up to 0.11 × fS (corresponds to 21 kHz), is suited for audio applications. 表 12 specifies the
performance of filter C. 图 42 shows the frequency response for filter C.
表 12. Specifications for ADC Decimation Filter C
PARAMETER
Filter gain from 0 fS to 0.11 fS
CONDITION
0 fS–0.11 fS
VALUE (Typical)
±0.033
–60
UNIT
dB
dB
s
Filter gain from 0.28 fS to 16 fS
Filter group delay
0.28 fS–16 fS
11 / fS
Pass-band ripple, 8 kSPS
Pass-band ripple, 44.18 kSPS
Pass-band ripple, 48 kSPS
Pass-band ripple, 96 kSPS
Pass-band ripple, 192 kSPS
0 fS–0.11 fS
0 fS–0.11 fS
0 fS–0.11 fS
0 fS–0.11 fS
0 kHz–20 kHz
0.033
dB
dB
dB
dB
dB
0.033
0.032
0.032
0.086
0
–20
–40
–60
–80
–100
–120
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Frequency Normalized With Respect to fS
ADC channel response for decimation filter C
(red line corresponds to –60 dB)
图 42. ADC Decimation Filter C, Frequency Response
8.3.11.5 ADC Data Interface
The decimation filter and signal processing block in the ADC channel passes 32-bit data words to the audio
serial interface one time every frame (WCLK). During each frame (WCLK), a pair of data words (for the left and
right channels) is passed. The audio serial interface rounds the data to the required word length of the interface
before converting to serial data per the different modes for audio serial interface.
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8.3.12 TLV320ADC3100 Comparison
表 13 lists a comparison between the TLV320ADC3100, TLV320ADC3101, and TLV320ADC3001. The
TLV320ADC3100 is form-factor and software compatible with the TLV320ADC3101.
表 13. Device Comparison Table
FEATURES
Number of ADCs
TLV320ADC3101
TLV320ADC3001
TLV320ADC3100
2
2
2
Number of inputs/outputs
Resolution (bits)
6, digital I / f
3, digital I / f
4, digital I / f
24
24
24
Control interface
I2C
I2C
I2C
Digital audio interface
Digital microphone support
Number of GPIOs
LJ, RJ, I2S, DSP, TDM
LJ, RJ, I2S, DSP, TDM
LJ, RJ, I2S, DSP, TDM
Yes
No
0
No
2
1
Number of Microphone bias
Package
2
1
1
4-mm × 4-mm, 24-pin QFN
2.24-mm × 2.16-mm, 16-pin
DSBGA (WCSP)
4-mm × 4-mm, 24-pin QFN
8.4 Device Functional Modes
8.4.1 Recording Mode
The recording mode is activated when the ADC blocks are enabled. The record path operates from 8 kHz to
48 kHz in single-rate mode and up to 96 kHz in dual-rate mode. This mode contains programmable input channel
configurations supporting single-ended and differential setups. In order to provide optimal system power
management, the stereo recording path can be powered up one channel at time, to support when only mono
record capability is required. Digital signal processing blocks can remove audible noise that may be introduced
by mechanical coupling. The TLV320ADC3100 includes automatic gain control (AGC).
8.5 Programming
8.5.1 Digital Control Serial Interface
8.5.1.1 I2C Control Mode
The TLV320ADC3100 supports the I2C control protocol and is capable of both standard and fast modes.
Standard mode is up to 100 kHz and fast mode is up to 400 kHz. When in I2C control mode, the
TLV320ADC3100 can be configured for one of four different addresses, using the I2C_ADR1 and I2C_ADR0
pins, which control the two LSBs of the device address. The five MSBs of the device address are fixed as 0011 0
and cannot be changed, whereas the two LSBs are given by I2C_ADR1:I2C_ADR0. 表 14 lists the four possible
device addresses resulting from this configuration.
表 14. I2C Slave Device Addresses for I2C_ADR1, I2C_ADR0 Settings
I2C_ADR1
I2C_ADR0
DEVICE ADDRESS
0011 000
0
0
1
1
0
1
0
1
0011 001
0011 010
0011 011
I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the
I2C bus only drive the bus lines low by connecting them to ground; they never drive the bus lines high. Instead,
the bus wires are pulled high by pullup resistors, so the bus wires are high when no device is driving them low.
This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.
Communication on the I2C bus always takes place between two devices, one acting as the master and the other
acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of
the master. Some I2C devices can act as masters or slaves, but the TLV320ADC3100 can only act as a slave
device.
40
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An I2C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data are
transmitted across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven to the
appropriate level when SCL is low (a low on SDA indicates the bit is 0; a high indicates the bit is 1). When the
SDA line has settled, the SCL line is brought high, then low. This pulse on SCL clocks the SDA bit into the
receiver shift register.
The I2C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads
from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line.
Under normal circumstances, the master drives the clock line.
Most of the time the bus is idle, no communication is taking place, and both lines are high. When communication
is taking place, the bus is active. Only master devices can start a communication by causing a START condition
on the bus. Normally, the data line is only allowed to change state when the clock line is low. If the data line
changes state when the clock line is high, the state is either a START condition or its counterpart, a STOP
condition. A START condition is when the clock line is high and the data line goes from high to low. A STOP
condition is when the clock line is high and the data line goes from low to high.
After the master issues a START condition, the master sends a byte indicating the slave device to communicate
with. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address that is used to
respond with. (Slaves can also have 10-bit addresses; see the I2C specification for details.) The master sends an
address in the address byte, together with a bit that indicates whether the slave device is to be read from or
written to.
Every byte transmitted on the I2C bus, whether address or data, is acknowledged with an acknowledge bit. When
a master has finished sending a byte (eight data bits) to a slave, the master stops driving SDA and waits for the
slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA low. The master then sends a
clock pulse to clock the acknowledge bit. Similarly, when a master has finished reading a byte, the master pulls
SDA low to acknowledge this read to the slave. The master then sends a clock pulse to clock the bit.
A not-acknowledge is performed by leaving SDA high during an acknowledge cycle. If the master attempts to
address a device not present on the bus, then the master receives a not-acknowledge because no device is
present at that address to pull the line low.
When a master has finished communicating with a slave, the master may issue a STOP condition. When a
STOP condition is issued, the bus becomes idle again. A master may also issue another START condition. If a
START condition is issued when the bus is active, this condition is called a repeated START condition.
The TLV320ADC3100 also responds to and acknowledges a general call, which consists of the master issuing a
command with a slave address byte of 00h. 图 43 and 图 44 show timing diagrams for I2C write and read
operations, respectively.
SCL
D(0)
DA(0)
RA(7)
RA(0)
D(7)
DA(6)
SDA
8-bit Device Address
(M)
Start
(M)
7-bit Device Address
(M)
Write Slave
8-bit Register Address
(M)
Slave
Ack
(S)
Slave Stop
Ack (M)
(S)
(M)
Ack
(S)
(M) => SDA Controlled by Master
(S) => SDA Controlled by Slave
图 43. I2C Write
SCL
SDA
DA(0)
D(7)
D(0)
DA(0)
RA(7)
RA(0)
DA(6)
DA(6)
Start
(M)
7-bit Device Address Write
(M) (M)
Slave 8-bit Register Address
Slave
Ack
(S)
Repeat
Start
(M)
7-bit Device Address Read
(M) (M)
Slave 8-bit Register Data
Master
No Ack
(M)
Stop
(M)
Ack
(S)
(M)
Ack
(S)
(M)
(M) => SDA Controlled by Master
(S) => SDA Controlled by Slave
图 44. I2C Read
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In the case of an I2C register write, if the master does not issue a STOP condition, then the device enters auto-
increment mode. So in the next eight clocks, the data on SDA are treated as the data for the next incremental
register.
Similarly, after the device has transmitted the 8-bit data from the addressed register for an I2C register read, and
if the master issues an acknowledge, the slave then takes control of the SDA bus and transmits the next eight
clocks of data for the next incremental register.
8.6 Register Maps
8.6.1 Control Registers
This section describes the control registers for the TLV320ADC3100 in detail. All registers are eight bits in width,
with bit 7 referring to the most-significant bit of each register and bit 0 referring to the least-significant bit.
Pages 0, 1, 4, 5, and 32–47 are available. All other pages are reserved. Do not read from or write to reserved
pages.
The procedure for register access is:
•
•
•
•
•
Select page N (write data N to register 0 regardless of the current page number)
Read or write data from or to valid registers in page N
Select new page M (write data M to register 0 regardless of the current page number)
Read or write data from or to valid registers in page M
Repeat as needed
表 15. Page, Register Map
REGISTER NO.
REGISTER NAME
PAGE 0: (Clock Multipliers and Dividers, Serial Interfaces, Flags, GPIO Interrupts and Programming)
0
1
Page Control Register
S/W RESET
2
Reserved
3
Reserved
4
Clock-Gen Multiplexing
PLL P and R-VAL
PLL J-VAL
5
6
7
PLL D-VAL MSB
8
PLL D-VAL LSB
9–17
18
19
20
21
22
23–24
25
26
27
28
29
30
31
32
33
34
Reserved
ADC NADC
ADC MADC
ADC AOSR
ADC IADC
ADC Digital Engine Decimation
Reserved
CLKOUT MUX
CLKOUT M Divider
ADC Audio Interface Control 1
Data Slot Offset Programmability 1 (Ch_Offset_1)
ADC Interface Control 2
BCLK N Divider
Secondary Audio Interface Control 1
Secondary Audio Interface Control 2
Secondary Audio Interface Control 3
I2S Sync
42
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Register Maps (接下页)
表 15. Page, Register Map (接下页)
REGISTER NO.
REGISTER NAME
35
36
Reserved
ADC Flag Register
37
Data Slot Offset Programmability 2 (Ch_Offset_2)
I2S TDM Control Register
Reserved
38
39–41
42
Interrupt Flags (Overflow)
Interrupt Flags (Overflow)
Reserved
43
44
45
Interrupt Flags–ADC
Reserved
46
47
Interrupt Flags–ADC
INT1 Interrupt Control
INT2 Interrupt Control
Reserved
48
49
50
51
Reserved
52
GPIO1 Control
53
DOUT (Out Pin) Control
Reserved
54–56
57
ADC Sync Control 1
ADC Sync Control 2
ADC CIC Filter Gain Control
Reserved
58
59
60
61
ADC Processing Block Selection
Programmable Instruction Mode Control Bits
Reserved
62
63–79
80
Reserved
81
ADC Digital
82
ADC Fine Volume Control
Left ADC Volume Control
Right ADC Volume Control
ADC Phase Compensation
Left AGC Control 1
83
84
85
86
87
Left AGC Control 2
88
Left AGC Maximum Gain
Left AGC Attack Time
Left AGC Decay Time
Left AGC Noise Debounce
Left AGC Signal Debounce
Left AGC Gain
89
90
91
92
93
94
Right AGC Control 1
Right AGC Control 2
Right AGC Maximum Gain
Right AGC Attack Time
Right AGC Decay Time
Right AGC Noise Debounce
Right AGC Signal Debounce
95
96
97
98
99
100
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Register Maps (接下页)
表 15. Page, Register Map (接下页)
REGISTER NO.
101
REGISTER NAME
Right AGC Gain
Reserved
102–127
PAGE1: (ADC Routing, PGA, Power-Controls, and so forth)
0
1–25
26
Page Control Register
Reserved
Dither Control
27–50
51
Reserved
MICBIAS Control
52
Left ADC Input Selection for Left PGA
Reserved
53
54
Left ADC Input Selection for Left PGA
Right ADC Input Selection for Right PGA
Reserved
55
56
57
Right ADC Input Selection for Right PGA
Reserved
58
59
Left Analog PGA Setting
Right Analog PGA Setting
ADC Low-Current Modes
ADC Analog PGA Flags
Reserved
60
61
62
63–127
PAGE 2: Reserved. Do not read or write to this page.
PAGE 3: Reserved. Do not read or write to this page.
PAGE 4: ADC Programmable Coefficients RAM (1:63)
PAGE 5: ADC Programmable Coefficients RAM (65:127)
PAGES 6–31: Reserved. Do not read from or write to these pages.
PAGES 32-47: ADC DSP Instruction RAM (Inst_0–Inst_511)
Page 32 Instructions Inst_0–Inst_31
Page 33 Instructions Inst_32–Inst_63
Page 34 Instruction Inst_64–Inst_95 through Page 47 Instruction Inst_480–Inst_511
PAGES 48–255: Reserved. Do not read from or write to these pages.
表 16 lists the access codes for the TLV320ADC3100 registers.
表 16. TLV320ADC3100 Access Type Codes
Access Type
Code
R
Description
Read
R
R-W
W
R/W
W
Read or write
Write
-n
Value after reset or the default
value
44
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8.6.2 Control Registers, Page 0: Clock Multipliers and Dividers, Serial Interfaces, Flags, Interrupts and
Programming of GPIOs
注
Valid pages are 0, 1, 4, 5, 32-47. All other pages are reserved (do not access).
8.6.2.1 Register 0: Page Control Register (address = 0d) [reset = 0000 0000b], Page 0
图 45. Register 0: Page Control
7
6
5
4
3
2
1
0
PAGE SEL
R/W-0000 0000h
表 17. Register 0: Page Control Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
PAGE SEL
R/W
0h
0000 0000: Page 0 selected
0000 0001: Page 1 selected
...
1111 1110: Page 254 selected (reserved)
1111 1111: Page 255 selected (reserved)
8.6.2.2 Register 1: Software Reset (address = 01d) [reset = 00h], Page 0
图 46. Register 1: Software Reset
7
6
5
4
3
2
1
0
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
SW_RST
W-0h
表 18. Register 1: Software Reset Field Descriptions
Bit
7:1
0
Field
Type
R
Reset
0h
Description
Reserved
SW_RST
Reserved. Write only zeros to these bits.
W
0h
0: Don't care
1: Self-clearing software reset for control register
8.6.2.3 Register 2: Reserved (address = 02d) [reset = 00h], Page 0
图 47. Register 2: Reserved
7
6
5
4
3
2
1
0
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
表 19. Register 2: Reserved Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Do not write any value other than reset value.
7:0
R
0h
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8.6.2.4 Register 3: Reserved (address = 03d) [reset = XXh], Page 0
图 48. Register 3: Reserved
7
6
5
4
3
2
1
0
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
表 20. Register 3: Reserved Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Do not write to this register.
7:0
R
Xh
8.6.2.5 Register 4: Clock-Gen Multiplexing (address = 04d) [reset = 00h], Page 0
图 49. Register 4: Clock-Gen Multiplexing(1)
7
6
5
4
3
2
1
0
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
PLL_CLKIN
R/W-00h
CODEC_CLKIN
R/W-00h
(1) See 图 27 for more details on clock generation multiplexing and dividers.
表 21. Register 4: Clock-Gen Multiplexing Field Descriptions
Bit
7:4
3:2
Field
Type
R
Reset
0h
Description
Reserved
PLL_CLKIN
Reserved. Do not write any value other than reset value.
R/W
00h
00: PLL_CLKIN = MCLK (device pin)
01: PLL_CLKIN = BCLK (device pin)
10: Reserved. Do not use.
11: PLL_CLKIN = logic level 0
1:0
CODEC_CLKIN
R/W
00h
00: CODEC_CLKIN = MCLK (device pin)
01: CODEC_CLKIN = BCLK (device pin)
10: Reserved. Do not use.
11: CODEC_CLKIN = PLL_CLK (generated on-chip)
8.6.2.6 Register 5: PLL P and R-VAL (address = 05d) [reset = 11h], Page 0
图 50. Register 5: PLL P and R-VAL
7
6
5
4
3
2
1
0
PLL ON
R/W-0h
PLL DIV
R/W-001h
PLL MULT R
R/W-0001h
表 22. Register 5: PLL P and R-VAL Field Descriptions
Bit
Field
Type
Reset
Description
7
PLL ON
R/W
0h
0: PLL is powered down
1: PLL is powered up
6:4
PLL DIV
R/W
R/W
001h
000: PLL divider P = 8
001: PLL divider P = 1
010: PLL divider P = 2
...
110: PLL divider P = 6
111: PLL divider P = 7
3:0
PLL MULT R
0001h
0000: PLL multiplier R = 16
0001: PLL multiplier R = 1
0010: PLL multiplier R = 2
...
1110: PLL multiplier R = 14
1111: PLL multiplier R = 15
46
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8.6.2.7 Register 6: PLL J-VAL (address = 06d) [reset = 0000 0100b], Page 0
图 51. Register 6: PLL J-VAL
7
6
5
4
3
2
1
0
Reserved
R/W-0h
Reserved
R/W-0h
PLL J-VAL
R/W-00 0100h
表 23. Register 6: PLL J-VAL Field Descriptions
Bit
7:6
5:0
Field
Type
R/W
R/W
Reset
Description
Reserved. Write only zeros to these bits.
Reserved
0h
PLL J-VAL
00 0100h 00 0000: Do not use (reserved)
00 0001: PLL multiplier J = 1
00 0010: PLL multiplier J = 2
00 0011: PLL multiplier J = 3
00 0100: PLL multiplier J = 4 (default)
...
11 1110: PLL multiplier J = 62
11 1111: PLL multiplier J = 63
8.6.2.8 Register 7: PLL D-VAL MSB (address = 07d) [reset = 00h], Page 0
This register is updated when page 0, register 8 is written immediately after page 0, register 7 is written.
图 52. Register 7: PLL D-VAL MSB
7
6
5
4
3
2
1
0
Reserved
R/W-0h
Reserved
R/W-0h
PLL D-VAL MSB
R/W-00 0000h
表 24. Register 7: PLL D-VAL MSB Field Descriptions
Bit
7:6
5:0
Field
Type
R/W
R/W
Reset
Description
Reserved. Write only zeros to these bits.
Reserved
0h
PLL D-VAL MSB
00 0000h PLL fractional multiplier bits 13:8.
8.6.2.9 Register 8: PLL D-VAL LSB (address = 08d) [reset = 00h], Page 0
This register must be written immediately after writing to page 0, register 7.
图 53. Register 8: PLL D-VAL LSB
7
6
5
4
3
2
1
0
PLL D-VAL LSB
R/W-0000 0000h
表 25. Register 8: PLL D-VAL LSB Field Descriptions
Bit
Field
PLL D-VAL LSB
Type
Reset
Description
7:0
R/W
0h
PLL fractional multiplier bits 7:0.
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8.6.2.10 Registers 9–17: Reserved (addresses = 09d, 10d, 11d, 12d, 13d, 14d, 15d, 16d, 17d) [reset =
XXh], Page 0
图 54. Registers 9–17: Reserved
7
6
5
4
3
2
1
0
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
表 26. Registers 9–17: Reserved Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Do not write to these registers.
7:0
R
Xh
8.6.2.11 Register 18: ADC NADC Clock Divider (address = 18d) [reset = 0000 0001b], Page 0
图 55. Register 18: ADC NADC Clock Divider
7
6
5
4
3
2
1
0
NADC CLK PWR
R/W-0h
NADC CLK DIV
R/W-000 0001h
表 27. Register 18: ADC NADC Clock Divider Field Descriptions
Bit
Field
Type
Reset
Description
7
NADC CLK PWR
R/W
0h
NADC clock divider power control:
0: NADC clock divider is powered down
1: NADC clock divider is powered up
6:0
NADC CLK DIV
R/W
000
NADC value:
0001h
000 0000: NADC clock divider = 128
000 0001: NADC clock divider = 1
000 0010: NADC clock divider = 2
...
111 1110: NADC clock divider = 126
111 1111: NADC clock divider = 127
8.6.2.12 Register 19: ADC MADC Clock Divider (address = 19d) [reset = 0000 0001b], Page 0
图 56. Register 19: ADC MADC Clock Divider
7
6
5
4
3
2
1
0
MADC CLK PWR
R/W-0h
MADC CLK DIV
R/W-000 0001h
表 28. Register 19: ADC MADC Clock Divider Field Descriptions
Bit
Field
Type
Reset
Description
7
MADC CLK PWR
R/W
0h
0: ADC MADC clock divider is powered down
1: ADC MADC clock divider is powered up
6:0
MADC CLK DIV
R/W
000
0001h
000 0000: MADC clock divider = 128
000 0001: MADC clock divider = 1
000 0010: MADC clock divider = 2
...
111 1110: MADC clock divider = 126
111 1111: MADC clock divider = 127
48
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8.6.2.13 Register 20: ADC AOSR (address = 20d) [reset = 1000 0000b], Page 0
图 57. Register 20: ADC AOSR(1)
7
6
5
4
3
2
1
0
ADC AOSR
R/W-1000 0000h
(1) The AOSR must be an integral multiple of the ADC decimation factor.
表 29. Register 20: ADC AOSR Field Descriptions
Bit
Field
Type
Reset
Description
7:0
ADC AOSR
R/W
1000
0000h
ADC oversampling value (AOSR):
0000 0000: AOSR = 256
0000 0001: AOSR = 1
0000 0010: AOSR = 2
...
1111 1110: AOSR = 254
1111 1111: AOSR = 255
8.6.2.14 Register 21: ADC IADC (address = 21d) [reset = 1000 0000b], Page 0
图 58. Register 21: ADC IADC(1)
7
6
5
4
3
2
1
0
ADC IADC
R/W-1000 0000h
(1) The IADC must be an integral multiple of the ADC decimation factor.
表 30. Register 21: ADC IADC Field Descriptions
Bit
Field
Type
Reset
Description
7:0
ADC IADC
R/W
1000
0000 0000: Reserved. Do not use.
0000h
Number of instructions for the ADC digital filter engine (IADC):
0000 0001: IADC = 2
0000 0010: IADC = 4
...
1011 1111: IADC = 382
1100 0000: IADC = 384
1100 0001–1111 1111: IADC = Up to 510
8.6.2.15 Register 22: ADC Digital Filter Engine Decimation (address = 22d) [reset = 0000 0100b], Page 0
图 59. Register 22: ADC Digital Filter Engine Decimation
7
6
5
4
3
2
1
0
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
DEC RATIO
R/W- 01000h
表 31. Register 22: ADC Digital Filter Engine Decimation Field Descriptions
Bit
7:4
3:0
Field
Type
R
Reset
0h
Description
Reserved
DEC RATIO
Reserved. Do not write any value other than reset value.
R/W
0100h
0000: Decimation ratio in the ADC digital filter engine = 16
0001: Decimation ratio in the ADC digital filter engine = 1
0010: Decimation ratio in the ADC digital filter engine = 2
...
1101: Decimation ratio in the ADC digital filter engine = 13
1110: Decimation ratio in the ADC digital filter engine = 14
1111: Decimation ratio in the ADC digital filter engine = 15
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8.6.2.16 Registers 23–24 (addresses) = 23d, 24d) [reset = XXh], Page 0
图 60. Registers 23–24
7
6
5
4
3
2
1
0
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
表 32. Registers 23–24 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Do not write to these registers.
7:0
R
Xh
8.6.2.17 Register 25: CLKOUT MUX (address = 25d) [reset = 00h], Page 0
图 61. Register 25: CLKOUT MUX
7
6
5
4
3
2
1
0
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
CDIV_CLKIN
R/W-000h
表 33. Register 25: CLKOUT MUX Field Descriptions
Bit
7:3
Field
Type
R
Reset
0h
Description
Reserved
Reserved. Do not write any value other than reset value.
2: 0
CDIV_CLKIN
R/W
000h
000: CDIV_CLKIN = MCLK (device pin)
001: CDIV_CLKIN = BCLK (device pin)
010: Reserved. Do not use.
011: CDIV_CLKIN = PLL_CLK (generated on-chip)
100: Reserved. Do not use.
101: Reserved. Do not use.
110: CDIV_CLKIN = ADC_CLK (generated on-chip)
111: CDIV_CLKIN = ADC_MOD_CLK (generated on-chip)
8.6.2.18 Register 26: CLKOUT M Divider (address = 26d) [reset = 0000 0001b], Page 0
图 62. Register 26: CLKOUT M Divider
7
6
5
4
3
2
1
0
CLKOUT M DIV PWR
R/W-0h
CLKOUT M DIV
R/W-000 0001h
表 34. Register 26: CLKOUT M Divider Field Descriptions
Bit
Field
Type
Reset
Description
7
CLKOUT M DIV PWR
R/W
0h
0: CLKOUT M divider is powered down
1: CLKOUT M divider is powered up
6:0
CLKOUT M DIV
R/W
000
0001h
000 0000: CLKOUT divider M = 128
000 0001: CLKOUT divider M = 1
000 0010: CLKOUT divider M = 2
...
111 1110: CLKOUT divider M = 126
111 1111: CLKOUT divider M = 127
50
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8.6.2.19 Register 27: ADC Audio Interface Control 1 (address = 27d) [reset = 00h], Page 0
图 63. Register 27: ADC Audio Interface Control 1
7
6
5
4
3
2
1
0
ADC interface
R/W-00h
ADC interface word length
R/W-00h
BCLK
R/W-0h
WCLK
R/W-0h
Reserved
R-0h
Tri-State DOUT
R/W-0h
表 35. Register 27: ADC Audio Interface Control 1 Field Descriptions
Bit
Field
Type
Reset
Description
7:6
ADC interface
R/W
00h
00: ADC interface = I2S
01: ADC interface = DSP
10: ADC interface = RJF
11: ADC interface = LJF
5:4
ADC interface word length
R/W
00h
00: ADC interface word length = 16 bits
01: ADC interface word length = 20 bits
10: ADC interface word length = 24 bits
11: ADC interface word length = 32 bits
3
2
BCLK
R/W
R/W
0h
0h
0: BCLK is input
1: BCLK is output
WCLK
0: WCLK is input
1: WCLK is output
1
0
Reserved
R
0h
0h
Reserved. Do not write any value other than reset value.
Tri-State DOUT
R/W
0: Tri-stating of DOUT: disabled
1: Tri-stating of DOUT: enabled
8.6.2.20 Register 28: Data Slot Offset Programmability 1 (Ch_Offset_1) (address = 28d) [reset = 00h],
Page 0
图 64. Register 28: Data Slot Offset Programmability 1 (Ch_Offset_1)
7
6
5
4
3
2
1
0
CH_OFFSET_1
R/W-0000 0000h
表 36. Register 28: Data Slot Offset Programmability 1 (Ch_Offset_1) Field Descriptions
Bit
Field
Type
Reset
Description
7:0
CH_OFFSET_1
R/W
0h
0000 0000: Offset = 0 BCLKs. Offset is measured with respect
to WCLK rising edge in DSP mode.(1)
0000 0001: Offset = 1 BCLKs
0000 0010: Offset = 2 BCLKs
...
1111 1110: Offset = 254 BCLKs
1111 1111: Offset = 255 BCLKs
(1) Usage controlled by page 0, register 38, bit 0.
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8.6.2.21 Register 29: ADC Interface Control 2 (address = 29d) [reset = 0000 0010b], Page 0
图 65. Register 29: ADC Interface Control 2
7
6
5
4
3
2
1
0
BWCLK_PWR codec
inactive
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
BCLK_INVERT
R/W-0h
BDIV_CLKIN
R/W-10h
R/W-0h
表 37. Register 29: ADC Interface Control 2 Field Descriptions
Bit
7:4
3
Field
Type
R/W
R/W
Reset
0h
Description
Reserved
Reserved. Do not write any value other than reset value.
BCLK_INVERT
0h
0: BCLK is not inverted (valid for both primary and secondary
BCLK)
1: BCLK is inverted (valid for both primary and secondary BCLK)
2
BWCLK_PWR codec inactive
BDIV_CLKIN
R/W
R/W
0h
0: BCLK and WCLK are active even with the codec powered
down: disabled (valid for both primary and secondary BCLK)
1: BCLK and WCLK are active even with the codec powered
down: enabled (valid for both primary and secondary BCLK)
1:0
10h
00: Reserved. Do not use.
01: Reserved. Do not use.
10: BDIV_CLKIN = ADC_CLK (generated on-chip)
11: BDIV_CLKIN = ADC_MOD_CLK (generated on-chip)
8.6.2.22 Register 30: BCLK N Divider (address = 30d) [reset = 0000 0001b], Page 0
图 66. Register 30: BCLK N Divider
7
6
5
4
3
2
1
0
BCLK N PWR
R/W-0h
BCLK N DIV
R/W-000 0001h
表 38. Register 30: BCLK N Divider Field Descriptions
Bit
Field
Type
Reset
Description
7
BCLK N PWR
R/W
0h
0: BCLK N divider is powered down
1: BCLK N divider is powered up
6:0
BCLK N DIV
R/W
000
0001h
000 0000: CLKOUT divider N = 128
000 0001: CLKOUT divider N = 1
000 0010: CLKOUT divider N = 2
...
111 1110: CLKOUT divider N = 126
111 1111: CLKOUT divider N = 127
52
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ZHCSHY2 –MARCH 2018
8.6.2.23 Register 31: Secondary Audio Interface Control 1 (address = 31d) [reset = 00h], Page 0
图 67. Register 31: Secondary Audio Interface Control 1
7
6
5
4
3
2
1
0
Reserved
R-0h
Sec BCLK from GPIO1
R/W-00h
Sec BCLK from GPIO1
R/W-00h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R-0h
表 39. Register 31: Secondary Audio Interface Control 1 Field Descriptions
Bit
7
Field
Type
R
Reset
0h
Description
Reserved
Reserved. Do not write any value other than reset value.
6:5
Sec BCLK from GPIO1
R/W
00h
00: Secondary BCLK is obtained from the GPIO1 pin
01, 10, 11: Reserved. Do not use.
4:3
Sec WCLK from GPIO1
R/W
00h
00: Secondary WCLK is obtained from the GPIO1 pin
01, 10, 11: Reserved. Do not use.
2:1
0
Reserved
Reserved
R/W
R
0h
0h
Reserved. Do not use.
Reserved. Do not write any value other than reset value.
8.6.2.24 Register 32: Secondary Audio Interface Control 2 (address = 32d) [reset = 00h], Page 0
图 68. Register 32: Secondary Audio Interface Control 2
7
6
5
4
3
2
1
0
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Choice of BCLK
R/W-0h
Choice of WCLK
R/W-0h
Reserved
R-0h
Reserved
R-0h
表 40. Register 32: Secondary Audio Interface Control 2 Field Descriptions
Bit
7:4
3
Field
Type
R
Reset
0h
Description
Reserved
Choice of BCLK
Reserved. Do not write any value other than reset value.
R/W
0h
0: Primary BCLK is used for audio interface and clocking
1: Secondary BCLK is used for audio interface and clocking
2
Choice of WCLK
Reserved
R/W
R
0h
0h
0: Primary WCLK is used for audio interface and clocking
1: Secondary WCLK is used for audio interface and clocking
1:0
Reserved. Do not write any value other than reset value.
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8.6.2.25 Register 33: Secondary Audio Interface Control 3 (address = 33d) [reset = 0001 0000b], Page 0
图 69. Register 33: Secondary Audio Interface Control 3
7
6
5
4
3
2
1
0
Source of Secondary
BCLK
Source of Secondary
WCLK
Source of Primary BCLK
R/W-0h
Source of Primary WCLK
R/W-01h
Reserved
R-0h
Reserved
R-0h
R/W-0h
R/W-00h
表 41. Register 33: Secondary Audio Interface Control 3 Field Descriptions
Bit
Field
Type
Reset
Description
7
Source of Primary BCLK
R/W
0h
0: Primary BCLK output = internally generated BCLK clock
1: Primary BCLK output = secondary BCLK
6
Source of Secondary BCLK
Source of Primary WCLK
R/W
R/W
0h
0: Secondary BCLK output = primary BCLK
1: Secondary BCLK output = internally generated BCLK clock
5:4
01h
00: Reserved. Do not use.
01: Primary WCLK output = internally generated ADC_fS clock
(default)
10: Primary WCLK output = secondary WCLK
11: Reserved. Do not use.
3:2
1:0
Source of Secondary WCLK
R/W
R
00h
0h
00: Secondary WCLK output = primary WCLK
01: Reserved. Do not use.
10: Secondary WCLK output = internally generated ADC_fS
clock
11: Reserved. Do not use.
Reserved
Reserved. Do not write any value other than reset value.
8.6.2.26 Register 34: I2S Sync (address = 34d) [reset = 00h], Page 0
图 70. Register 34: I2S Sync
7
6
5
4
3
2
1
0
I2C hang detect
flag
I2C general-call
accept
Re-sync logic
disabled
Re-sync without soft-
muting
I2C hang detect
R/W-0h
Reserved Reserved Reserved
R-0h R-0h R-0h
R-0h
R/W-0h
R/W-0h
R/W-0h
表 42. Register 34: I2S Sync Field Descriptions
Bit
Field
Type
Reset
Description
7
I2C hang detect
R/W
0h
0: Internal logic is enabled to detect the I2C hang and react
accordingly
1: Internal logic is disabled to detect the I2C hang
6(1)
I2C hang detect flag
I2C general-call accept
R
0h
0h
0: I2C hang is not detected
1: I2C hang detected flag; when set, this bit is cleared only after
reading this register
5
R/W
0: I2C general-call address is ignored
1: Device accepts I2C general-call address
4:2
1
Reserved
R
0h
0h
Reserved. Do not write any value other than reset value.
Re-sync logic disabled
R/W
0: Re-sync logic is disabled for the ADC
1: Re-sync stereo ADC with codec interface if the group delay
changed by more than ±ADC_fS / 4
0
Re-sync without soft-muting
R/W
0h
0: Re-sync is done without soft-muting the channel for the ADC
1: Re-sync is done by internally soft-muting the channel for the
ADC
(1) Read-only bit. Writes to this bit are not used anywhere.
54
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8.6.2.27 Register 35: Reserved (address = 35d) [reset = XXh], Page 0
图 71. Register 35: Reserved
7
6
5
4
3
2
1
0
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
表 43. Register 35: Reserved Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Do not write to this register.
7:0
R
Xh
8.6.2.28 Register 36: ADC Flag Register (address = 36d) [reset = 00h], Page 0
图 72. Register 36: ADC Flag Register
7
6
5
4
3
2
1
0
L-ADC PGA
gain
L-ADC
powered up
L-AGC not
saturated
R-ADC PGA
gain
R-ADC
powered up
R-AGC not
saturated
Reserved
R-0h
Reserved
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
表 44. Register 36: ADC Flag Register Field Descriptions
Bit
Field
Type
Reset
Description
7(1)
L-ADC PGA gain
R
0h
0: Left ADC PGA, applied gain ≠ programmed gain
1: Left ADC PGA, applied gain = programmed gain
6(1)
5(1)
L-ADC powered up
L-AGC not saturated
R
R
0h
0h
0: Left ADC powered down
1: Left ADC powered up
0: Left AGC not saturated
1: Left AGC applied gain = maximum applicable gain by the left AGC
4
3(1)
Reserved
R
R
0h
0h
Reserved. Do not write any value other than reset value.
R-ADC PGA gain
0: Right ADC PGA, applied gain ≠ programmed gain
1: Right ADC PGA, applied gain = programmed gain
2(1)
1(1)
0
R-ADC powered up
R-AGC not saturated
Reserved
R
R
R
0h
0h
0h
0: Right ADC powered down
1: Right ADC powered up
0: Right AGC not saturated
1: Right AGC applied gain = maximum applicable gain by the right AGC
Reserved. Do not write any value other than reset value.
(1) Read-only bits. Writes to this bit are not used anywhere.
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8.6.2.29 Register 37: Data Slot Offset Programmability 2 (Ch_Offset_2) (address = 37d) [reset = 00h],
Page 0
图 73. Register 37: Data Slot Offset Programmability 2 (Ch_Offset_2)
7
6
5
4
3
2
1
0
CH OFFSET 2
R/W-0000 0000h
表 45. Register 37: Data Slot Offset Programmability 2 (Ch_Offset_2) Field Descriptions
Bit
Field
Type
Reset
Description
7:0
CH OFFSET 2
R/W
0h
0000 0000: Offset = 0 BCLKs. Offset is measured with respect
to the end of the first channel(1)
0000 0001: Offset = 1 BCLKs
0000 0010: Offset = 2 BCLKs
...
1111 1110: Offset = 254 BCLKs
1111 1111: Offset = 255 BCLKs
(1) Usage is controlled by page 0, register 38, bit 0, TIME_SLOT_MODE_ENABLE.
8.6.2.30 Register 38: I2S TDM Control Register (address = 38d) [reset = 0000 0010b], Page 0
图 74. Register 38: I2S TDM Control Register
7
6
5
4
3
2
1
0
Reserved Reserved Reserved
Channel swap disable
R/W-0h
Channel disable
R/W-00h
EARLY_3-STATE
R/W-1h
TIME_SLOT_MODE
R/W-0h
R-0h
R-0h
R-0h
表 46. Register 38: I2S TDM Control Register Field Descriptions
Bit
7:5
4
Field
Type
R
Reset
0h
Description
Reserved
Reserved. Do not write any value other than reset value.
Channel swap disable
R/W
0h
0: Channel swap disabled
1: Channel swap enabled
3:2
Channel disable
R/W
00h
00: Both left and right channels enabled
01: Left channel enabled
10: Right channel enabled
11: Both left and right channels disabled
1
0
EARLY_3-STATE
R/W
R/W
1h
0h
0: EARLY_3-STATE disabled
1: EARLY_3-STATE enabled
TIME_SLOT_MODE
0: TIME_SLOT_MODE disabled – both channel offsets
controlled by Ch_Offset_1 (page 0, register 28)
1: TIME_SLOT_MODE enabled – channel-1 offset controlled by
Ch_Offset_1 (page 0, register 28) and channel-2 offset
controlled by Ch_Offset_2 (page 0, register 37)
8.6.2.31 Registers 39–41 (addresses) = 39d, 40d, 41d) [reset = XXh], Page 0
图 75. Registers 39–41
7
6
5
4
3
2
1
0
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
表 47. Registers 39–41 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Do not write to these registers.
7:0
R
Xh
56
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8.6.2.32 Register 42: Interrupt Flags (Overflow) (address = 42d) [reset = 00h], Page 0
图 76. Register 42: Interrupt Flags (Overflow)
7
6
5
4
3
2
1
0
ADC barrel-shifter
overflow flag
Reserved Reserved Reserved Reserved Left ADC overflow flag Right ADC overflow flag
Reserved
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
表 48. Register 42: Interrupt Flags (Overflow) Field Descriptions
Bit
7:4
3(1)
2(1)
1(1)
0
Field
Type
R
Reset
0h
Description
Reserved
Reserved
Left ADC overflow flag
Right ADC overflow flag
ADC barrel-shifter overflow flag
Reserved
R
0h
Left ADC overflow flag
Right ADC overflow flag
ADC barrel-shifter output-overflow flag
Reserved
R
0h
R
0h
R
0h
(1) Sticky flag bits. These are read-only bits. These bits are automatically cleared when read and are set only if a new source trigger
occurs.
8.6.2.33 Register 43: Interrupt Flags (Overflow) (address = 43d) [reset = 00h], Page 0
图 77. Register 43: Interrupt Flags (Overflow)
7
6
5
4
3
2
1
0
ADC barrel-shifter
overflow flag
Reserved Reserved Reserved Reserved
L-ADC Overflow
R-0h
R-ADC Overflow
R-0h
Reserved
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
表 49. Register 43: Interrupt Flags (Overflow) Field Descriptions
Bit
7:4
3
Field
Type
R
Reset
0h
Description
Reserved
Reserved
L-ADC Overflow
R-ADC Overflow
ADC barrel-shifter overflow flag
Reserved
R
0h
Left ADC overflow flag
Right ADC overflow flag
ADC barrel-shifter output-overflow flag
Reserved
2
R
0h
1
R
0h
0
R
0h
8.6.2.34 Register 44: Reserved (address = 44d) [reset = XXh], Page 0
图 78. Register 44: Reserved
7
6
5
4
3
2
1
0
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
表 50. Register 44: Reserved Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Do not write to this register.
7:0
R
Xh
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8.6.2.35 Register 45: Interrupt Flags—ADC (address = 45d) [reset = 00h], Page 0
图 79. Register 45: Interrupt Flags—ADC
7
6
5
4
3
2
1
0
Left AGC
Noise
Right AGC
Noise
ADC digital filter
engine standard
ADC digital filter
engine auxiliary
interrupt-port output
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Threshold Flag Threshold Flag interrupt-port output
R-0h R-0h R-0h
R-0h
表 51. Register 45: Interrupt Flags—ADC Field Descriptions
Bit
7
Field
Type
R
Reset
0h
Description(1)
Reserved
Reserved
6
Left AGC Noise Threshold Flag
R
0h
0: Left ADC signal power is greater than the noise threshold for
the left AGC
1: Left ADC signal power is less than the noise threshold for the
left AGC
5
Right AGC Noise Threshold Flag
R
0h
0: Right ADC signal power is greater than the noise threshold for
the right AGC
1: Right ADC signal power is less than the noise threshold for
the right AGC
4
3
ADC digital filter engine standard
interrupt-port output
R
R
R
0h
0h
0h
ADC digital filter engine standard interrupt-port output
ADC digital filter engine auxiliary interrupt-port output
Reserved
ADC digital filter engine auxiliary
interrupt-port output
2:0
Reserved
(1) Sticky flag bits. These are read-only bits. These bits are automatically cleared when read and are set only if a new source trigger
occurs.
8.6.2.36 Register 46: Reserved (address = 46d) [reset = XXh], Page 0
图 80. Register 46: Reserved
7
6
5
4
3
2
1
0
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
表 52. Register 46: Reserved Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Do not write to this register.
7:0
R
Xh
58
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ZHCSHY2 –MARCH 2018
8.6.2.37 Register 47: Interrupt Flags—ADC (address = 47d) [reset = 00h], Page 0
图 81. Register 47: Interrupt Flags—ADC
7
6
5
4
3
2
1
0
L-ADC power
status
R-ADC power
status
ADC Filt Std-Out
Instantaneous Value
ADC Filt Aux-Out
Instantaneous Value
Reserved
R-0h
Reserved Reserved Reserved
R-0h R-0h R-0h
R-0h
R-0h
R-0h
R-0h
表 53. Register 47: Interrupt Flags—ADC Field Descriptions
Bit
7
Field
Type
R
Reset
0h
Description
Reserved
Reserved
6
L-ADC power status
R
0h
0: Left ADC signal power is greater than the noise threshold for
the left AGC
1: Left ADC signal power is less than the noise threshold for the
left AGC
5
R-ADC power status
R
0h
0: Right ADC signal power is greater than the noise threshold for
the right AGC
1: Right ADC signal power is less than the noise threshold for
the right AGC
4
3
ADC Filt Std-Out Instantaneous
Value
R
R
R
0h
0h
0h
ADC digital filter engine standard interrupt-port output. This bit
indicates the instantaneous value of the interrupt port at the time
of reading the register.
ADC Filt Aux-Out Instantaneous
Value
ADC digital filter engine auxiliary interrupt-port output. This bit
indicates the instantaneous value of the interrupt port at the time
of reading the register.
2:0
Reserved
Reserved
8.6.2.38 Register 48: INT1 Interrupt Control (address = 48d) [reset = 00h], Page 0
图 82. Register 48: INT1 Interrupt Control
7
6
5
4
3
2
1
0
INT1 uses ADC
AGC noise
INT1 uses
Engine interrupts
INT1 uses ADC data-
ready interrupts
No. of INT1
Pulses
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
表 54. Register 48: INT1 Interrupt Control Field Descriptions
Bit
7:5
4
Field
Type
R
Reset
0h
Description
Reserved
Reserved. Do not write any value other than reset value.
INT1 uses ADC AGC noise
R/W
0h
0: ADC AGC noise interrupt is not used in the generation of
INT1 interrupt
1: ADC AGC noise interrupt is used in the generation of INT1
interrupt
3
2
Reserved
R
0h
0h
Reserved. Do not write any value other than reset value.
INT1 uses Engine interrupts
R/W
0: Engine-generated interrupts and overflow flags are not used
in the generation of INT1 interrupt
1: Engine-generated interrupts and overflow flags are used in
the generation of INT1 interrupt
1
0
INT1 uses ADC data-ready
interrupts
R/W
R/W
0h
0h
0: ADC data-available interrupt is not used in the generation of
INT1 interrupt
1: ADC data-available interrupt is used in the generation of INT1
interrupt
No. of INT1 Pulses
0: INT1 is only one pulse (active high) of duration typical 2 ms
1: INT1 is multiple pulses (active high) of duration typical 2 ms
and period 4 ms, until flag register 42 or 45 is read
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8.6.2.39 Register 49: INT2 Interrupt Control (address = 49d) [reset = 00h], Page 0
图 83. Register 49: INT2 Interrupt Control
7
6
5
4
3
2
1
0
INT2 Uses ADC
AGC Noise
INT2 Uses
Engine Interrupts
INT2 Uses ADC Data-
Ready Interrupts
No. of INT2
Pulses
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
表 55. Register 49: INT2 Interrupt Control Field Descriptions
Bit
7:5
4
Field
Type
R
Reset
0h
Description
Reserved
Reserved. Do not write any value other than reset value.
INT2 Uses ADC AGC Noise
R/W
0h
0: ADC AGC noise interrupt is not used in the generation of
INT2 interrupt
1: ADC AGC noise interrupt is used in the generation of INT2
interrupt
3
2
Reserved
R
0h
0h
Reserved. Do not write any value other than reset value.
INT2 Uses Engine Interrupts
R/W
0: Engine-generated interrupts and overflow flags are not used
in the generation of INT2 interrupt
1: Engine-generated interrupts and overflow flags are used in
the generation of INT2 interrupt
1
0
INT2 Uses ADC Data-Ready
Interrupts
R/W
R/W
0h
0h
0: ADC data-available interrupt is not used in the generation of
INT2 interrupt
1: ADC data-available interrupt is used in the generation of INT2
interrupt
No. of INT2 Pulses
0: INT2 is only one pulse (active high) of duration typical 2 ms
1: INT2 is multiple pulses (active high) of duration typical 2 ms
and period 4 ms, until flag register 42 or 45 is read
8.6.2.40 Register 50: Reserved (address = 50d) [reset = XXh], Page 0
图 84. Register 50: Reserved
7
6
5
4
3
2
1
0
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
表 56. Register 50: Reserved Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Do not write to this register.
7:0
R
Xh
8.6.2.41 Register 51: Reserved (address = 51d) [reset = 00h], Page 0
图 85. Register 51: Reserved
7
6
5
4
3
2
1
0
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
表 57. Register 51: Reserved
Bit
Field
Reserved
Type
Reset
Description
7:0
R/W
0h
Reserved. Do not write any value other than reset value.
60
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8.6.2.42 Register 52: GPIO1 Control (address = 52d) [reset = 00h], Page 0
图 86. Register 52: GPIO1 Control
7
6
5
4
3
2
1
0
Reserved
R-0h
Reserved
R-0h
GPIO1 SEL
R/W-0000h
GPIO1 IN BUF VAL
R-0h
GPIO1 VAL
R/W-0h
表 58. Register 52: GPIO1 Control Field Descriptions
Bit
7:6
5:2
Field
Type
R
Reset
0h
Description
Reserved
Reserved. Do not write any value other than reset value.
GPIO1 SEL
R/W
0000h
0000: GPIO1 disabled (input and output buffers powered down)
0001: GPIO1 is in input mode (can be used as secondary BCLK
input, secondary WCLK input, or in ClockGen block)
0010: GPIO1 is used as general-purpose input (GPI)
0011: GPIO1 output = general-purpose output
0100: GPIO1 output = CLKOUT output (source determined by
CDIV_CLKIN_REG; page 0, register 25)
0101: GPIO1 output = INT1 output
0110: GPIO1 output = INT2 output
0111: Reserved. Do not use.
1000: GPIO1 output = secondary BCLK output for codec
interface
1001: GPIO1 output = secondary WCLK output for codec
interface
1010: DMDIN output = ADC_MOD_CLK output for the digital
microphone
1011–1111: Reserved. Do not use.
1
0
GPIO1 IN BUF VAL
GPIO1 VAL
R
0h
0h
GPIO1 input buffer value
R/W
0: GPIO1 value = 0 when bits 5:2 are programmed to 0011
(general-purpose output)
1: GPIO1 value = 1 when bits 5:2 are programmed to 0011
(general-purpose output)
8.6.2.43 Register 53: DOUT (OUT Pin) Control (address = 53d) [reset = 0001 0010b], Page 0
图 87. Register 53: DOUT (OUT Pin) Control
7
6
5
4
3
2
1
0
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
DOUT bus-keeper EN
R/W-1h
DOUT FUNC SEL
R/W-001h
DOUT VAL
R/W-0h
表 59. Register 53: DOUT (OUT Pin) Control Field Descriptions
Bit
7:5
4
Field
Type
R
Reset
0h
Description
Reserved
Reserved. Do not write any value other than reset value.
DOUT bus-keeper EN
R/W
1h
0: DOUT bus keeper enabled
1: DOUT bus keeper disabled
3:1
DOUT FUNC SEL
R/W
001h
000: DOUT disabled (output buffer powered down)
001 DOUT = primary DOUT output for codec interface
010: DOUT = general-purpose output
011: DOUT = CLKOUT output
100: DOUT = INT1 output
101: DOUT = INT2 output
110: DOUT = secondary BCLK output for codec interface
111: DOUT = secondary WCLK output for codec interface
0
DOUT VAL
R/W
0h
DOUT value = 0 when bits 3:1 are programmed to 010 (general-
purpose output)
DOUT value = 1 when bits 3:1 are programmed to 010 (general-
purpose output)
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8.6.2.44 Registers 54–56 (addresses) = 54d, 55d, 56d) [reset = XXh], Page 0
图 88. Registers 54–56
7
6
5
4
3
2
1
0
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
表 60. Registers 54–56 Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Do not write to this register.
7:0
R
Xh
8.6.2.45 Register 57: ADC Sync Control 1 (address = 57d) [reset = 00h], Page 0
图 89. Register 57: ADC Sync Control 1
7
6
5
4
3
2
1
0
SYNC SEL
R/W-0h
CUSTOM SYNC SETTING
R/W-000 0000h
表 61. Register 57: ADC Sync Control 1 Field Descriptions
Bit
Field
SYNC1 SEL
Type
Reset
Description
7
R/W
0h
0: Default synchronization
1: Custom synchronization
6:0
CUSTOM SYNC1 SETTING
R/W
000 0000h 000 0000: Custom synchronization window size = 0 instructions
000 0001: Custom synchronization window size = 2 instructions
(±1 instruction)
000 0010: Custom synchronization window size = 4 instructions
(±2 instructions)
...
111 1111: Custom synchronization window size = 254
instructions (±127 instructions)
8.6.2.46 Register 58: ADC Sync Control 2 (address = 58d) [reset = 00h], Page 0
图 90. Register 58: ADC Sync Control 2
7
6
5
4
3
2
1
0
CUSTOM SYNC2 TARGET
R/W-0000 0000h
表 62. Register 58: ADC Sync Control 2 Field Descriptions
Bit
Field
CUSTOM SYNC2 TARGET
Type
Reset
Description
7:0
R/W
0h
0000 0000: Custom synchronization target = instruction 0
0000 0001: Custom synchronization target = instruction 2
0000 0010: Custom synchronization target = instruction 4
...
1111 1111: Custom synchronization target = instruction 510
62
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8.6.2.47 Register 59: ADC CIC Filter Gain Control (address = 59d) [reset = 0100 0100h], Page 0
图 91. Register 59: ADC CIC Filter Gain Control
7
6
5
4
3
2
1
0
L-CIC FILT GAIN
R/W-0100h
R-CIC FILT GAIN
R/W-0100h
表 63. Register 59: ADC CIC Filter Gain Control Field Descriptions
Bit
7:4
3:0
Field
Type
R/W
R/W
Reset
0100h
0100h
Description
L-CIC FILT GAIN
R-CIC FILT GAIN
Left CIC filter gain(1)
Right CIC filter gain(1)
(1) For proper operation, the CIC gain must be ≤ 1.
If AOSR (page 0, register 20) = 64 and [1 ≤ Filter Mode (page 0, register 61) ≤ 6], then the reset value of 4 results in CIC gain = 1.
Otherwise, the CIC gain = [AOSR / (64 × Digital Filter Engine Decimation)]4 × 2 (CIC Filter Gain Control) for 0 ≤ CIC Filter Gain Control ≤ 12,
and if CIC Filter Gain Control = 15, CIC gain is automatically set such that for 7 ≤ (AOSR / Digital Filter Engine Decimation) ≤ 64,
0.5 < CIC gain ≤ 1.
8.6.2.48 Register 60: Reserved (address = 60d) [reset = 00h], Page 0
图 92. Register 60: Reserved
7
6
5
4
3
2
1
0
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
表 64. Register 60: Reserved Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Do not write to this register.
7:0
R/W
0h
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8.6.2.49 Register 61: ADC Processing Block Selection (address = 61d) [reset = 0000 0001h], Page 0
图 93. Register 61: ADC Processing Block Selection
7
6
5
4
3
2
1
0
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
PRB SEL
R/W-0 0001h
表 65. Register 61: ADC Processing Block Selection Field Descriptions
Bit
7:5
4:0
Field
Type
R/W
R/W
Reset
0h
Description
Reserved
PRB SEL
Reserved. Do not write any value other than reset value.
0 0001h
0 0000: Reserved. Do not use.
0 0001: Select ADC signal processing block PRB_R1
0 0010: Select ADC signal processing block PRB_R2
0 0011: Select ADC signal processing block PRB_R3
0 0100: Select ADC signal processing block PRB_R4
0 0101: Select ADC signal processing block PRB_R5
0 0110: Select ADC signal processing block PRB_R6
0 0111: Select ADC signal processing block PRB_R7
0 1000: Select ADC signal processing block PRB_R8
0 1001: Select ADC signal processing block PRB_R9
0 1010: Select ADC signal processing block PRB_R10
0 1011: Select ADC signal processing block PRB_R11
0 1100: Select ADC signal processing block PRB_R12
0 1101: Select ADC signal processing block PRB_R13
0 1110: Select ADC signal processing block PRB_R14
0 1111: Select ADC signal processing block PRB_R15
1 0000: Select ADC signal processing block PRB_R16
1 0001: Select ADC signal processing block PRB_R17
1 0010: Select ADC signal processing block PRB_R18
1 0011–1 1111: Reserved. Do not use.
8.6.2.50 Register 62: Programmable Instruction-Mode Control Bits (address = 62d) [reset = 00h], Page 0
图 94. Register 62: Reserved
7
6
5
4
3
2
1
0
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
表 66. Register 62: Reserved
Bit
Field
Reserved
Type
Reset
Description
Reserved. Do not write any value other than reset value.
7:0
R/W
0h
8.6.2.51 Registers 63–79: Reserved (address = 63d - 79d) [reset = XXh], Page 0
图 95. Registers 63–79: Reserved
7
6
5
4
3
2
1
0
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
表 67. Registers 63–79: Reserved Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Do not write to these registers.
7:0
R
Xh
64
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ZHCSHY2 –MARCH 2018
8.6.2.52 Register 80: Reserved (address = 80d) [reset = 00h], Page 0
图 96. Register 80: Reserved
7
6
5
4
3
2
1
0
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
表 68. Register 80: Reserved
Bit
Field
Reserved
Type
Reset
Description
Reserved. Do not write any value other than reset value.
7:0
R/W
0h
8.6.2.53 Register 81: ADC Digital (address = 81d) [reset = 00h], Page 0
图 97. Register 81: ADC Digital
7
6
5
4
3
2
1
0
L-ADC PWR EN
R/W-0h
R-ADC PWR EN
R/W-0h
Reserved
ADC SOFT-STEP
R/W-00h
R/W-0000h
表 69. Register 81: ADC Digital Field Descriptions
Bit
Field
Type
Reset
Description
7
L-ADC PWR EN
R/W
0h
0: Left-channel ADC is powered down
1: Left-channel ADC is powered up
6
R-ADC PWR EN
R/W
0h
0: Right-channel ADC is powered down
1: Right-channel ADC is powered up
5:2
1:0
Reserved
R/W
R/W
0000h
00h
Reserved. Do not write any value other than reset value.
ADC SOFT-STEP
00: ADC channel volume control soft-stepping is enabled for one
step / fS
01: ADC channel volume control soft-stepping is enabled for one
step / 2 fS
10: ADC channel volume control soft-stepping is disabled
11: Reserved. Do not use.
8.6.2.54 Register 82: ADC Fine Volume Control (address = 82d) [reset = 1000 1000h], Page 0
图 98. Register 82: ADC Fine Volume Control
7
6
5
4
3
2
1
0
L-ADC MUTE
R/W-1h
L-ADC FINE GAIN
R/W-000h
R-ADC MUTE
R/W-1h
R-ADC FINE GAIN
R/W-000h
表 70. Register 82: ADC Fine Volume Control Field Descriptions
Bit
Field
Type
Reset
Description
7
L-ADC MUTE
R/W
1h
0: Left ADC channel not muted
1: Left ADC channel muted
6:4
L-ADC FINE GAIN
R/W
000h
000: Left ADC channel fine gain = 0 dB
001: Left ADC channel fine gain = –0.1 dB
010: Left ADC channel fine gain = –0.2 dB
011: Left ADC channel fine gain = –0.3 dB
100: Left ADC channel fine gain = –0.4 dB
101–111: Reserved. Do not use.
3
R-ADC MUTE
R/W
R/W
1h
0: Right ADC channel not muted
1: Right ADC channel muted
2:0
R-ADC FINE GAIN
000h
000: Right ADC channel fine gain = 0 dB
001: Right ADC channel fine gain = –0.1 dB
010: Right ADC channel fine gain = –0.2 dB
011: Right ADC channel fine gain = –0.3 dB
100: Right ADC channel fine gain = –0.4 dB
101–111: Reserved. Do not use.
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8.6.2.55 Register 83: Left ADC Volume Control (address = 83d) [reset = 00h], Page 0
图 99. Register 83: Left ADC Volume Control
7
6
5
4
3
2
1
0
Reserved
R-0h
L-ADC CH VOL
R/W-000 0000h
表 71. Register 83: Left ADC Volume Control Field Descriptions
Bit
7
Field
Type
R
Reset(1)
Description
Reserved. Do not write any value other than reset value.
Reserved
0h
6:0
L-ADC CH VOL
R/W
000 0000h 100 0000 – 110 1000: Left ADC channel volume = 0 dB
110 1000: Left ADC channel volume = –12 dB
110 1001: Left ADC channel volume = –11.5 dB
110 1010: Left ADC channel volume = –11.0 dB
...
111 1111: Left ADC channel volume = –0.5 dB
000 0000: Left ADC channel volume = –0.0 dB
000 0001: Left ADC channel volume = 0.5 dB
...
010 0110: Left ADC channel volume = 19.0 dB
010 0111: Left ADC channel volume = 19.5 dB
010 1000: Left ADC channel volume = 20 dB
010 1001– 011 1111 : Reserved. Do not use.
(1) Values in 2s-complement decimal format.
8.6.2.56 Register 84: Right ADC Volume Control (address = 84d) [reset = 00h], Page 0
图 100. Register 84: Right ADC Volume Control
7
6
5
4
3
2
1
0
Reserved
R-0h
R-ADC CH VOL
R/W-000 0000h
表 72. Register 84: Right ADC Volume Control Field Descriptions
Bit
7
Field
Type
R
Reset(1)
Description
Reserved. Do not write any value other than reset value.
Reserved
0h
6:0
R-ADC CH VOL
R/W
000 0000h 100 0000 – 110 1000: Right ADC channel volume = 0 dB
110 1000: Right ADC channel volume = –12 dB
110 1001: Right ADC channel volume = –11.5 dB
110 1010: Right ADC channel volume = –11.0 dB
...
111 1111: Right ADC channel volume = –0.5 dB
000 0000: Right ADC channel volume = –0.0 dB
000 0001: Right ADC channel volume = 0.5 dB
...
010 0110: Right ADC channel volume = 19.0 dB
010 0111: Right ADC channel volume = 19.5 dB
010 1000: Right ADC channel volume = 20 dB
010 1001– 011 1111 : Reserved. Do not use.
(1) Values in 2s-complement decimal format.
66
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8.6.2.57 Register 85: Left ADC Phase Compensation (address = 85d) [reset = 00h], Page 0
图 101. Register 85: Left ADC Phase Compensation
7
6
5
4
3
2
1
0
L-ADC PHASE COMP
R/W-0000 0000h
表 73. Register 85: Left ADC Phase Compensation Field Descriptions
Bit
Field
Type
Reset
Description
7:0
L-ADC PHASE COMP
R/W
0h
1000 0000: Left ADC has a phase shift of –128 ADC_MOD_CLK
cycles with respect to right ADC
1000 0001: Left ADC has a phase shift of –127 ADC_MOD_CLK
cycles with respect to right ADC
...
1111 1110: Left ADC has a phase shift of –2 ADC_MOD_CLK
cycles with respect to right ADC
1111 1111: Left ADC has a phase shift of –1 ADC_MOD_CLK
cycles with respect to right ADC
0000 0000: No phase shift between stereo ADC channels
0000 0001: Left ADC has a phase shift of 1 ADC_MOD_CLK
cycles with respect to right ADC
0000 0010: Left ADC has a phase shift of 2 ADC_MOD_CLK
cycles with respect to right ADC
...
0111 1110: Left ADC has a phase shift of 126 ADC_MOD_CLK
cycles with respect to right ADC
0111 1111: Left ADC has a phase shift of 127 ADC_MOD_CLK
cycles with respect to right ADC
8.6.2.58 Register 86: Left AGC Control 1 (address = 86d) [reset = 00h], Page 0
图 102. Register 86: Left AGC Control 1
7
6
5
4
3
2
1
0
L-AGC EN
R/W-0h
L-AGC TARGET
R/W-000h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R-0h
表 74. Register 86: Left AGC Control 1 Field Descriptions
Bit
Field
L-AGC EN
Type
Reset
Description
7
R/W
0h
0: Left AGC disabled
1: Left AGC enabled
6:4
3:0
L-AGC TARGET
R/W
000h
000: Left AGC target level = –5.5 dB
001: Left AGC target level = –8 dB
010: Left AGC target level = –10 dB
011: Left AGC target level = –12 dB
100: Left AGC target level = –14 dB
101: Left AGC target level = –17 dB
110: Left AGC target level = –20 dB
111: Left AGC target level = –24 dB
Reserved
R
0h
Reserved. Do not write any value other than reset value.
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8.6.2.59 Register 87: Left AGC Control 2 (address = 87d) [reset = 00h], Page 0
图 103. Register 87: Left AGC Control 2
7
6
5
4
3
2
1
0
L-AGC HYST
R/W-00h
L-AGC NOISE THRESHOLD
R/W- 0 0000h
AGC CLIP STEPPING EN
R/W-0h
表 75. Register 87: Left AGC Control 2 Field Descriptions
Bit
Field
Type
Reset
Description
7:6
L-AGC HYST
R/W
0h
00: Left AGC hysteresis setting of 1 dB
01: Left AGC hysteresis setting of 2 dB
10: Left AGC hysteresis setting of 4 dB
11: Left AGC hysteresis disabled
5:1
L-AGC NOISE THRESHOLD
R/W
R/W
0 0000h
00 000: Left AGC noise or silence detection is disabled
00 001: Left AGC noise threshold = –30 dB
00 010: Left AGC noise threshold = –32 dB
00 011: Left AGC noise threshold = –34 dB
...
11 101: Left AGC noise threshold = –86 dB
11 110: Left AGC noise threshold = –88 dB
11 111: Left AGC noise threshold = –90 dB
0
L-AGC CLIP STEPPING EN
0h
0: Disable clip stepping for AGC
1: Enable clip stepping for AGC
8.6.2.60 Register 88: Left AGC Maximum Gain (address = 88d) [reset = 0111 1111b], Page 0
图 104. Register 88: Left AGC Maximum Gain
7
6
5
4
3
2
1
0
Reserved
R-0h
L-AGC MAX GAIN
R/W-111 1111h
表 76. Register 88: Left AGC Maximum Gain Field Descriptions
Bit
7
Field
Type
R
Reset
Description
Reserved
0h
Reserved. Do not write any value other than reset value.
6:0
L-AGC MAX GAIN
R/W
111
1111h
000 0000: Left AGC maximum gain = 0 dB
000 0001: Left AGC maximum gain = 0.5 dB
000 0010: Left AGC maximum gain = 1 dB
...
101 0000: Left AGC maximum gain = 40 dB
101 0001 – 111 1111: Reserved. Do not use.
68
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8.6.2.61 Register 89: Left AGC Attack Time (address = 89d) [reset = 00h], Page 0
图 105. Register 89: Left AGC Attack Time
7
6
5
4
3
2
1
0
L-AGC ATTACK TIME
R/W-0000 0h
L-AGC ATTACK TIME MULT
R/W-000h
表 77. Register 89: Left AGC Attack Time Field Descriptions
Bit
Field
Type
Reset
Description
7:3
L-AGC ATTACK TIME
R/W
0000 0h
0000 0: Left AGC attack time = 1 × (32 / fS)
0000 1: Left AGC attack time = 3 × (32 / fS)
0001 0: Left AGC attack time = 5 × (32 / fS)
0001 1: Left AGC attack time = 7 × (32 / fS)
0010 0: Left AGC attack time = 9 × (32 / fS)
...
1111 0: Left AGC attack time = 61 × (32 / fS)
1111 1: Left AGC attack time = 63 × (32 / fS)
2:0
L-AGC ATTACK TIME MULT
R/W
000h
000: Multiply factor for the programmed left AGC attack time = 1
001: Multiply factor for the programmed left AGC attack time = 2
010: Multiply factor for the programmed left AGC attack time = 4
...
111: Multiply factor for the programmed left AGC attack time =
128
8.6.2.62 Register 90: Left AGC Decay Time (address = 90d) [reset = 00h], Page 0
图 106. Register 90: Left AGC Decay Time
7
6
5
4
3
2
1
0
L-AGC DECAY TIME
R/W-0000 0h
L-AGC DECAY TIME MULT
R/W-000h
表 78. Register 90: Left AGC Decay Time Field Descriptions
Bit
Field
Type
Reset
Description
7:3
L-AGC DECAY TIME
R/W
0000 0h
0000 0: Left AGC decay time = 1 × (512 / fS)
0000 1: Left AGC decay time = 3 × (512 / fS)
0001 0: Left AGC decay time = 5 × (512 / fS)
0001 1: Left AGC decay time = 7 × (512 / fS)
0010 0: Left AGC decay time = 9 × (512 / fS)
...
1111 0: Left AGC decay time = 61 × (512 / fS)
1111 1: Left AGC decay time = 63 × (512 / fS)
2:0
L-AGC DECAY TIME MULT
R/W
000h
000: Multiply factor for the programmed left AGC decay time = 1
001: Multiply factor for the programmed left AGC decay time = 2
010: Multiply factor for the programmed left AGC decay time = 4
...
111: Multiply factor for the programmed left AGC decay time =
128
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8.6.2.63 Register 91: Left AGC Noise Debounce (address = 91d) [reset = 00h], Page 0
图 107. Register 91: Left AGC Noise Debounce
7
6
5
4
3
2
1
0
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
L-AGC NOISE DEBOUNCE
R/W-0 0000h
表 79. Register 91: Left AGC Noise Debounce Field Descriptions
Bit
7:5
4:0
Field
Type
R
Reset
0h
Description
Reserved
Reserved. Do not write any value other than reset value.
L-AGC NOISE DEBOUNCE
R/W
0 0000h
0 0000: Left AGC noise debounce = 0 / fS
0 0001: Left AGC noise debounce = 4 / fS
0 0010: Left AGC noise debounce = 8 / fS
0 0011: Left AGC noise debounce = 16 / fS
0 0100: Left AGC noise debounce = 32 / fS
0 0101: Left AGC noise debounce = 64 / fS
0 0110: Left AGC noise debounce = 128 / fS
0 0111: Left AGC noise debounce = 256 / fS
0 1000: Left AGC noise debounce = 512 / fS
0 1001: Left AGC noise debounce = 1024 / fS
0 1010: Left AGC noise debounce = 2048 / fS
0 1011: Left AGC noise debounce = 4096 / fS
0 1100: Left AGC noise debounce = 2 × 4096 / fS
0 1101: Left AGC noise debounce = 3 × 4096 / fS
0 1110: Left AGC noise debounce = 4 × 4096 / fS
...
1 1110: Left AGC noise debounce = 20 × 4096 / fS
1 1111: Left AGC noise debounce = 21 × 4096 / fS
8.6.2.64 Register 92: Left AGC Signal Debounce (address = 92d) [reset = 00h], Page 0
图 108. Register 92: Left AGC Signal Debounce
7
6
5
4
3
2
1
0
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
L-AGC SIGNAL DEBOUNCE
R/W-0000h
表 80. Register 92: Left AGC Signal Debounce Field Descriptions
Bit
7:4
3:0
Field
Type
R
Reset
0h
Description
Reserved
Reserved. Do not write any value other than reset value.
L-AGC SIGNAL DEBOUNCE
R/W
0000h
0000: Left AGC signal debounce = 0 / fS
0001: Left AGC signal debounce = 4 / fS
0010: Left AGC signal debounce = 8 / fS
0011: Left AGC signal debounce = 16 / fS
0100: Left AGC signal debounce = 32 / fS
0101: Left AGC signal debounce = 64 / fS
0110: Left AGC signal debounce = 128 / fS
0111: Left AGC signal debounce = 256 / fS
1000: Left AGC signal debounce = 512 / fS
1001: Left AGC signal debounce = 1024 / fS
1010: Left AGC signal debounce = 2048 / fS
1011: Left AGC signal debounce = 2 × 2048 / fS
1100: Left AGC signal debounce = 3 × 2048 / fS
1101: Left AGC signal debounce = 4 × 2048 / fS
1110: Left AGC signal debounce = 5 × 2048 / fS
1111: Left AGC signal debounce = 6 × 2048 / fS
70
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ZHCSHY2 –MARCH 2018
8.6.2.65 Register 93: Left AGC Gain Applied (address = 93d) [reset = 00h], Page 0
图 109. Register 93: Left AGC Gain Applied
7
6
5
4
3
2
1
0
L-AGC GAIN APPL
R-0000 0000h
表 81. Register 93: Left AGC Gain Applied Field Descriptions
Bit
7:0(1)
Field
L-AGC GAIN APPL
Type
Reset
Description
R
0h
Left AGC Gain Value Status:
1110 1000: Gain applied by left AGC = –12 dB
1110 1001: Gain applied by left AGC = –11.5 dB
...
1111 1111: Gain applied by left AGC = –0.5 dB
0000 0000: Gain applied by left AGC = 0 dB
0000 0001: Gain applied by left AGC = 0.5 dB
...
0100 1111: Gain applied by left AGC = 39.5 dB
0101 0000: Gain applied by left AGC = 40 dB
0101 0001 – 1111 1111: Reserved. Do not use.
(1) These bits are read-only.
8.6.2.66 Register 94: Right AGC Control 1 (address = 94d) [reset = 00h], Page 0
图 110. Register 94: Right AGC Control 1
7
6
5
4
3
2
1
0
R-AGC EN
R/W-0h
R-AGC TARGET
R/W-000h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
表 82. Register 94: Right AGC Control 1 Field Descriptions
Bit
Field
R-AGC EN
Type
Reset
Description
7
R/W
0h
0: Right AGC disabled
1: Right AGC enabled
6:4
3:0
R-AGC TARGET
R/W
000h
000: Right AGC target level = –5.5 dB
000: Right AGC target level = –8 dB
001: Right AGC target level = –10 dB
010: Right AGC target level = –12 dB
011: Right AGC target level = –14 dB
100: Right AGC target level = –17 dB
101: Right AGC target level = –20 dB
111: Right AGC target level = –24 dB
Reserved
R
0h
Reserved. Do not write any value other than reset value.
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8.6.2.67 Register 95: Right AGC Control 2 (address = 95d) [reset = 00h], Page 0
图 111. Register 95: Right AGC Control 2
7
6
5
4
3
2
1
0
R-AGC HYST
R/W-00h
R-AGC NOISE THRESHOLD
R/W-00 000h
R-AGC CLIP STEPPING
R/W-0h
表 83. Register 95: Right AGC Control 2 Field Descriptions
Bit
Field
Type
Reset(1)
Description
7:6
R-AGC HYST
R/W
00h
00: Right AGC hysteresis setting of 1 dB
01: Right AGC hysteresis setting of 2 dB
10: Right AGC hysteresis setting of 4 dB
11: Right AGC hysteresis disabled.
5:1
R-AGC NOISE THRESHOLD
R/W
R/W
00 000h
00 000: Right AGC noise or silence detection is disabled
00 001: Right AGC noise threshold = –30 dB
00 010: Right AGC noise threshold = –32 dB
00 011: Right AGC noise threshold = –34 dB
...
11 101: Right AGC noise threshold = –86 dB
11 110: Right AGC noise threshold = –88 dB
11 111: Right AGC noise threshold = –90 dB
0
R-AGC CLIP STEPPING
0h
0: Disable clip stepping for right AGC
1: Enable clip stepping for right AGC
(1) Values in 2s-complement decimal format.
8.6.2.68 Register 96: Right AGC Maximum Gain (address = 96d) [reset = 0111 1111b], Page 0
图 112. Register 96: Right AGC Maximum Gain
7
6
5
4
3
2
1
0
Reserved
R-0h
R-AGC MAX GAIN
R/W-111 1111h
表 84. Register 96: Right AGC Maximum Gain Field Descriptions
Bit
7
Field
Type
R
Reset
Description
Reserved. Do not write any value other than reset value.
Reserved
0h
6:0
R-AGC MAX GAIN
R/W
111 1111h 000 0000: Right AGC maximum gain = 0 dB
000 0001: Right AGC maximum gain = 0.5 dB
000 0010: Right AGC maximum gain = 1 dB
...
101 0000: Right AGC maximum gain = 40 dB
101 0001–111 1111: Not used.
72
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ZHCSHY2 –MARCH 2018
8.6.2.69 Register 97: Right AGC Attack Time (address = 97d) [reset = 00h], Page 0
图 113. Register 97: Right AGC Attack Time
7
6
5
4
3
2
1
0
R-AGC ATTACK TIME
R/W-0000 0h
R-AGC ATTACK TIME MULT
R/W-000h
表 85. Register 97: Right AGC Attack Time Field Descriptions
Bit
Field
Type
Reset
Description
7:3
R-AGC ATTACK TIME
R/W
0000 0h
0000 0: Right AGC attack time = 1 × (32 / fS)
0000 1: Right AGC attack time = 3 × (32 / fS)
0001 0: Right AGC attack time = 5 × (32 / fS)
0001 1: Right AGC attack time = 7 × (32 / fS)
0010 0: Right AGC attack time = 9 × (32 / fS)
...
1111 0: Right AGC attack time = 61 × (32 / fS)
1111 1: Right AGC attack time = 63 × (32 / fS)
2:0
R-AGC ATTACK TIME MULT
R/W
000h
000: Multiply factor for the programmed right AGC attack time =
1
001: Multiply factor for the programmed right AGC attack time =
2
010: Multiply factor for the programmed right AGC attack time =
4
...
111: Multiply factor for the programmed right AGC attack time =
128
8.6.2.70 Register 98: Right AGC Decay Time (address = 98d) [reset = 00h], Page 0
图 114. Register 98: Right AGC Decay Time
7
6
5
4
3
2
1
0
R-AGC DECAY TIME
R/W-0000 0h
R-AGC DECAY TIME MULT
R/W-000h
表 86. Register 98: Right AGC Decay Time Field Descriptions
Bit
Field
Type
Reset
Description
7:3
R-AGC DECAY TIME
R/W
0000 0h
0000 0: Right AGC decay time = 1 × (512 / fS)
0000 1: Right AGC decay time = 3 × (512 / fS)
0001 0: Right AGC decay time = 5 × (512 / fS)
0001 1: Right AGC decay time = 7 × (512 / fS)
0010 0: Right AGC decay time = 9 × (512 / fS)
...
1111 0: Right AGC decay time = 61 × (512 / fS)
1111 1: Right AGC decay time = 63 × (512 / fS)
2:0
R-AGC DECAY TIME MULT
R/W
000h
000: Multiply factor for the programmed right AGC decay time =
1
001: Multiply factor for the programmed right AGC decay time =
2
010: Multiply factor for the programmed right AGC decay time =
4
111: Multiply factor for the programmed right AGC decay time =
128
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8.6.2.71 Register 99: Right AGC Noise Debounce (address = 99d) [reset = 00h], Page 0
图 115. Register 99: Right AGC Noise Debounce
7
6
5
4
3
2
1
0
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
R-AGC NOISE DEBOUNCE
R/W-0 0000h
表 87. Register 99: Right AGC Noise Debounce Field Descriptions
Bit
7:5
4:0
Field
Type
R
Reset
0h
Description
Reserved
Reserved. Do not write any value other than reset value.
R-AGC NOISE DEBOUNCE
R/W
0 0000h
0 0000: Right AGC noise debounce = 0 / fS
0 0001: Right AGC noise debounce = 4 / fS
0 0010: Right AGC noise debounce = 8 / fS
0 0011: Right AGC noise debounce = 16 / fS
0 0100: Right AGC noise debounce = 32 / fS
0 0101: Right AGC noise debounce = 64 / fS
0 0110: Right AGC noise debounce = 128 / fS
0 0111: Right AGC noise debounce = 256 / fS
0 1000: Right AGC noise debounce = 512 / fS
0 1001: Right AGC noise debounce = 1024 / fS
0 1010: Right AGC noise debounce = 2048 / fS
0 1011: Right AGC noise debounce = 4096 / fS
0 1100: Right AGC noise debounce = 2 × 4096 / fS
0 1101: Right AGC noise debounce = 3 × 4096 / fS
0 1110: Right AGC noise debounce = 4 × 4096 / fS
...
1 1110: Right AGC noise debounce = 20 × 4096 / fS
1 1111: Right AGC noise debounce = 21 × 4096 / fS, right AGC
noise debounce = 0 / fS
8.6.2.72 Register 100: Right AGC Signal Debounce (address = 100d) [reset = 00h], Page 0
图 116. Register 100: Right AGC Signal Debounce
7
6
5
4
3
2
1
0
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
R-AGC SIGNAL DEBOUNCE
R/W-0000h
表 88. Register 100: Right AGC Signal Debounce Field Descriptions
Bit
7:4
3:0
Field
Type
R
Reset
0h
Description
Reserved
Reserved. Do not write any value other than reset value.
R-AGC SIGNAL DEBOUNCE
R/W
0000h
0000: Right AGC signal debounce = 0 / fS
0001: Right AGC signal debounce = 4 / fS
0010: Right AGC signal debounce = 8 / fS
0011: Right AGC signal debounce = 16 / fS
0100: Right AGC signal debounce = 32 / fS
0101: Right AGC signal debounce = 64 / fS
0110: Right AGC signal debounce = 128 / fS
0111: Right AGC signal debounce = 256 / fS
1000: Right AGC signal debounce = 512 / fS
1001: Right AGC signal debounce = 1024 / fS
1010: Right AGC signal debounce = 2048 / fS
1011: Right AGC signal debounce = 2 × 2048 / fS
1100: Right AGC signal debounce = 3 × 2048 / fS
1101: Right AGC signal debounce = 4 × 2048 / fS
1110: Right AGC signal debounce = 5 × 2048 / fS
1111: Right AGC signal debounce = 6 × 2048 / fS, right AGC
signal debounce = 0 / fS
74
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ZHCSHY2 –MARCH 2018
8.6.2.73 Register 101: Right AGC Gain Applied (address = 101d) [reset = 00h], Page 0
图 117. Register 101: Right AGC Gain Applied
7
6
5
4
3
2
1
0
R-AGC GAIN APPL
R-0000 0000h
表 89. Register 101: Right AGC Gain Applied Field Descriptions
Bit
Field
R-AGC GAIN APPL
Type(1)
Reset
Description
7:0
R
0h
Right AGC gain value status:
1110 1000: Gain applied by right AGC = –12 dB
1110 1001: Gain applied by right AGC = –11.5 dB
...
1111 1111: Gain applied by right AGC = –0.5 dB
0000 0000: Gain applied by right AGC = 0 dB
0000 0001: Gain applied by right AGC = 0.5 dB
...
0100 1111: Gain applied by right AGC = 39.5 dB
0101 0000: Gain applied by right AGC = 40 dB
0101 0001 – 1111 1111: Reserved. Do not use.
(1) These bits are read-only.
8.6.2.74 Register 102–127: Reserved (addresses) = 102d–127d) [reset = XXh], Page 0
图 118. Register 102–127: Reserved
7
6
5
4
3
2
1
0
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
表 90. Register 102–127: Reserved Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Do not write to these registers.
7:0
R
Xh
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8.6.3 Control Registers, Page 1: ADC Routing, PGA, Power Controls, and So Forth
注
Valid pages are 0, 1, 4, 5, 32-47. All other pages are reserved (do not access).
8.6.3.1 Register 0: Page Control Register (address = 0d) [reset = 00h], Page 1
图 119. Register 0: Page Control Register
7
6
5
4
3
2
1
0
PAGE 0 CTRL
R/W-0000 0000h
表 91. Register 0: Page Control Register Field Descriptions
Bit
Field
PAGE 0 CTRL
Type
Reset
Description
7:0
R/W
0h
0000 0000: Page 0 selected
0000 0001: Page 1 selected
...
1111 1110: Page 254 selected (reserved)
1111 1111: Page 255 selected (reserved)
8.6.3.2 Register 1–25: Reserved (addresses) = 01d–25d) [reset = XXh], Page 1
图 120. Register 1–25: Reserved
7
6
5
4
3
2
1
0
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
表 92. Register 1–25: Reserved Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Do not write to these registers.
7:0
R
Xh
76
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8.6.3.3 Register 26: Dither Control (address = 26d) [reset = 00h], Page 1
图 121. Register 26: Dither Control
7
6
5
4
3
2
1
0
L-ADC DITHER OFFSET
R/W-0000h
R-ADC DITHER OFFSET
R/W-0000h
表 93. Register 26: Dither Control Field Descriptions
Bit
Field
Type
Reset
Description
7:4
L-ADC DITHER OFFSET
R/W
0000h
DC offset into input of left ADC; signed magnitude number in
±15-mV steps.
1111: –105 mV
...
1011: –45 mV
1010: –30 mV
1001: –15 mV
0000: 0 mV
0001: 15 mV
0010: 30 mV
0011: 45 mV
...
0111: 105 mV
3:0
R-ADC DITHER OFFSET
R/W
0000h
DC offset into input of right ADC; signed magnitude number in
±15-mV steps.
1111: –105 mV
...
1011: –45 mV
1010: –30 mV
1001: –15 mV
0000: 0 mV
0001: 15 mV
0010: 30 mV
0011: 45 mV
...
0111: 105 mV
8.6.3.4 Register 27–50: Reserved (addresses) = 27d–50d) [reset = XXh], Page 1
图 122. Register 27–50: Reserved
7
6
5
4
3
2
1
0
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
表 94. Register 27–50: Reserved Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Do not write to these registers.
7:0
R
Xh
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8.6.3.5 Register 51: MICBIAS Control (address = 51d) [reset = 00h], Page 1
图 123. Register 51: MICBIAS Control
7
6
5
4
3
2
1
0
Reserved
R-0h
MICBIAS VALUE
R/W-00h
Reserved
R/W-0h
Reserved
R/W-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
表 95. Register 51: MICBIAS Control Field Descriptions
Bit
7
Field
Type
R
Reset
0h
Description
Reserved
Reserved. Do not write any value other than reset value.
6:5
MICBIAS VALUE
R/W
00h
00: MICBIAS1 is powered down
01: MICBIAS1 is powered to 2 V
10: MICBIAS1 is powered to 2.5 V
11: MICBIAS1 is connected to AVDD
4:3
2:0
Reserved
Reserved
R/W
R
0h
0h
Reserved. Do not write any value other than reset value.
Reserved. Do not write any value other than reset value.
8.6.3.6 Register 52: Left ADC Input Selection for Left PGA (address = 52d) [reset = 0101 0111b], Page 1
图 124. Register 52: Left ADC Input Selection for Left PGA
7
6
5
4
3
2
1
0
LCH_SEL4
R/W-01h
LCH_SEL3
R/W-01h
LCH_SEL2
R/W-01h
Reserved
R/W-1h
Reserved
R/W-1h
表 96. Register 52: Left ADC Input Selection for Left PGA Field Descriptions
Bit
Field
Type
Reset
Description(1)
7:6
LCH_SEL4
R/W
01h
Differential pair using the IN2L(P) as plus and IN3L(M) as minus
inputs.
00: 0-dB setting is chosen
01: –6-dB setting is chosen
10: Is not connected to the left ADC PGA
11: Is not connected to the left ADC PGA
5:4
3:2
1:0
LCH_SEL3
LCH_SEL2
Reserved
R/W
R/W
R/W
01h
01h
1h
Used for the IN3L(M) pin, which is single-ended.
00: 0-dB setting is chosen
01: –6-dB setting is chosen
10: Is not connected to the left ADC PGA
11: Is not connected to the left ADC PGA
Used for the IN2L(P) pin, which is single-ended.
00: 0-dB setting is chosen
01: –6-dB setting is chosen
10: Is not connected to the left ADC PGA
11: Is not connected to the left ADC PGA
Reserved. Do not write any value other than reset value.
(1) To maintain the same PGA output level for both single-ended and differential pairs, the single-ended inputs have a 2× gain applied.
8.6.3.7 Register 53: Reserved (address = 53d) [reset = XXh], Page 1
图 125. Register 53: Reserved
7
6
5
4
3
2
1
0
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
表 97. Register 53: Reserved Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Do not write to this register.
7:0
R
Xh
78
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8.6.3.8 Register 54: Left ADC Input Selection for Left PGA (address = 54d) [reset = 0011 1111h], Page 1
图 126. Register 54: Left ADC Input Selection for Left PGA
7
6
5
4
3
2
1
0
L PGA BYPASS
R/W-0h
LCH_SELCM
R/W-0h
LCH_SEL3X
R/W-01h
LCH_SEL2X
R/W-01h
Reserved
R/W-1h
Reserved
R/W-1h
表 98. Register 54: Left ADC Input Selection for Left PGA Field Descriptions
Bit
Field
Type
Reset
Description(1)
7
L PGA BYPASS
R/W
0h
0: Do not bypass left PGA
1: Bypass left PGA, unbuffered differential pair using the IN2L(P)
as plus and IN3L(M) as minus inputs
6
LCH_SELCM
LCH_SEL3X
R/W
R/W
0h
0: Left ADC channel unselected inputs are not biased weakly to
the ADC common-mode voltage
1: Left ADC channel unselected inputs are biased weakly to the
ADC common-mode voltage
5:4
01h
Differential pair using the IN2L(P) as plus and IN2R(M) as minus
inputs.
00: 0-dB setting is chosen
01: –6-dB setting is chosen
10–11: Not connected to the left ADC PGA
3:2
1:0
LCH_SEL2X
Reserved
R/W
R/W
01h
1h
Differential pair using the IN2R(P) as plus and IN3R(M) as
minus inputs.
00: 0-dB setting is chosen
01: –6-dB setting is chosen
10–11: Is not connected to the left ADC PGA
Reserved. Do not write any value other than reset value.
(1) To maintain the same PGA output level for both single-ended and differential pairs, the single-ended inputs have a 2× gain applied.
8.6.3.9 Register 55: Right ADC Input Selection for Right PGA (address = 55d) [reset = 0101 0111b],
Page 1
图 127. Register 55: Right ADC Input Selection for Right PGA
7
6
5
4
3
2
1
0
RCH_SEL4
R/W-01h
RCH_SEL3
R/W-01h
RCH_SEL2
R/W-01h
Reserved
R/W-1h
Reserved
R/W-1h
表 99. Register 55: Right ADC Input Selection for Right PGA Field Descriptions
Bit
Field
Type
Reset
Description(1)
7:6
RCH_SEL4
R/W
01h
Differential pair using the IN2R(P) as plus and IN3R(M) as
minus inputs.
00: 0-dB setting is chosen
01: –6-dB setting is chosen
10–11: Not connected to the right ADC PGA
5:4
3:2
1:0
RCH_SEL3
RCH_SEL2
Reserved
R/W
R/W
R/W
01h
01h
1h
Used for the IN3R(M) pin, which is single-ended.
00: 0-dB setting is chosen
01: –6-dB setting is chosen
10–11: Not connected to the right ADC PGA
Used for the IN2R(P) pin, which is single-ended.
00: 0-dB setting is chosen
01: –6-dB setting is chosen
10–11: Not connected to the right ADC PGA
Reserved. Do not write any value other than reset value.
(1) To maintain the same PGA output level for both single-ended and differential pairs, the single-ended inputs have a 2× gain applied.
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8.6.3.10 Register 56: Reserved (address = 56d) [reset = XXh], Page 1
图 128. Register 56: Reserved
7
6
5
4
3
2
1
0
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
表 100. Register 56: Reserved Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Do not write to this register.
7:0
R
Xh
8.6.3.11 Register 57: Right ADC Input Selection for Right PGA (address = 57d) [reset = 0001 0111b],
Page 1
图 129. Register 57: Right ADC Input Selection for Right PGA
7
6
5
4
3
2
1
0
R PGA BYPASS
R/W-0h
RCH_SELCM
R/W-0h
RCH_SEL3X
R/W-01h
RCH_SEL2X
R/W-01h
Reserved
R/W-1h
Reserved
R/W-1h
表 101. Register 57: Right ADC Input Selection for Right PGA Field Descriptions
Bit
Field
Type
Reset
Description(1)
7
R PGA BYPASS
R/W
0h
0: Do not bypass right PGA
1: Bypass right PGA, unbuffered differential pair using the
IN2R(P) as plus and IN3R(M) as minus inputs
6
RCH_SELCM
RCH_SEL3X
R/W
R/W
0h
0: Right ADC channel unselected inputs are not biased weakly
to the ADC common-mode voltage
1: Right ADC channel unselected inputs are biased weakly to
the ADC common-mode voltage
5:4
01h
Differential pair using the IN2L(P) as plus and IN2R(M) as minus
inputs.
00: 0-dB setting is chosen
01: –6 dB setting is chosen
10–11: Not connected to the right ADC PGA
3:2
1:0
RCH_SEL2X
Reserved
R/W
R/W
01h
1h
Differential pair using the IN2L(P) as plus and IN3L(M) as minus
inputs.
00: 0-dB setting is chosen
01: –6-dB setting is chosen
10, 11: Not connected to the right ADC PGA
Reserved. Do not write any value other than reset value.
(1) To maintain the same PGA output level for both single-ended and differential pairs, the single-ended inputs have a 2× gain applied.
8.6.3.12 Register 58: Reserved (address = 58d) [reset = XXh], Page 1
图 130. Register 58: Reserved
7
6
5
4
3
2
1
0
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
表 102. Register 58: Reserved Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Do not write to this register.
7:0
R
Xh
80
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8.6.3.13 Register 59: Left Analog PGA Settings (address = 59d) [reset = 1000 0000h], Page 1
图 131. Register 59: Left Analog PGA Settings
7
6
5
4
3
2
1
0
L PGA MUTE
R/W-1h
L-PGA GAIN
R/W-000 0000h
表 103. Register 59: Left Analog PGA Settings Field Descriptions
Bit
Field
Type
Reset
Description
7
L PGA MUTE
R/W
1h
0: Left PGA is not muted
1: Left PGA is muted
6:0
L-PGA GAIN
R/W
000 0000h 000 0000: Left PGA gain = 0 dB
000 0001: Left PGA gain = 0.5 dB
000 0010: Left PGA gain = 1 dB
...
101 0000: Left PGA gain = 40 dB
101 0001–111 1111: Reserved. Do not use.
8.6.3.14 Register 60: Right Analog PGA Settings (address = 60d) [reset = 1000 0000h], Page 1
图 132. Register 60: Right Analog PGA Settings
7
6
5
4
3
2
1
0
R-PGA MUTE
R/W-1h
R-PGA GAIN
R/W-000 0000h
表 104. Register 60: Right Analog PGA Settings Field Descriptions
Bit
Field
Type
Reset
Description
7
R PGA MUTE
R/W
1h
0: Right PGA is not muted
1: Right PGA is muted
6:0
R-PGA GAIN
R/W
000 0000h 000 0000: Right PGA gain = 0 dB
000 0001: Right PGA gain = 0.5 dB
000 010: Right PGA gain = 1 dB
...
101 0000: Right PGA gain = 40 dB
101 0001–111 1111: Reserved. Do not use.
8.6.3.15 Register 61: ADC Low Current Modes (address = 61d) [reset = 00h], Page 1
图 133. Register 61: ADC Low Current Modes
7
6
5
4
3
2
1
0
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
MODULATOR CURRENT
R/W-0h
表 105. Register 61: ADC Low Current Modes Field Descriptions
Bit
7:1
0
Field
Type
R
Reset
0h
Description
Reserved
Reserved. Write only zeros to these bits.
MODULATOR CURRENT
R/W
0h
0: 1× ADC modulator current used
1: 0.5× ADC modulator current used
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8.6.3.16 Register 62: ADC Analog PGA Flags (address = 62d) [reset = 00h], Page 1
图 134. Register 62: ADC Analog PGA Flags
7
6
5
4
3
2
1
0
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
Reserved
R-0h
L ADC PGA FLAG
R-0h
R ADC PGA FLAG
R-0h
表 106. Register 62: ADC Analog PGA Flags Field Descriptions
Bit
7:2
1
Field
Type
R
Reset
0h
Description
Reserved
Reserved. Do not write any value other than reset value
L ADC PGA FLAG
R
0h
0: Left ADC PGA , applied gain ≠ programmed gain
1: Left ADC PGA , applied gain = programmed gain
0
R ADC PGA FLAG
R
0h
0: Right ADC PGA , applied gain ≠ programmed gain
1: Right ADC PGA , applied gain = programmed gain
8.6.3.17 Register 63–127: Reserved (addresses) = 63d–127d) [reset = XXh], Page 1
图 135. Register 63–127: Reserved
7
6
5
4
3
2
1
0
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
Reserved
R-Xh
表 107. Register 63–127: Reserved Field Descriptions
Bit
Field
Reserved
Type
Reset
Description
Reserved. Do not write to these registers.
7:0
R
Xh
82
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8.6.4 Control Registers, Page 4: ADC Digital Filter Coefficients
Default values shown for this page only become valid 100 µs following a hardware or software reset.
注
Valid pages are 0, 1, 4, 5, 32-47. All other pages are reserved (do not access).
8.6.4.1 Register 0: Page Control (address = 00d) [reset = 00h], Page 4
图 136. Register 0: Page Control
7
6
5
4
3
2
1
0
PAGE SELECT
R/W-0000 0000h
表 108. Register 0: Page Control Field Descriptions
Bit
Field
PAGE SELECT
Type
Reset
Description
7:0
R/W
0h
0000 0000: Page 0 selected
0000 0001: Page 1 selected
...
1111 1110: Page 254 selected (reserved)
1111 1111: Page 255 selected (reserved)
The remaining page 4 registers are either reserved registers or are used for setting coefficients for the various
filters in the processing blocks. Reserved registers must not be written to.
The filter coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit
coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient are
interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. When
programming any coefficient value for a filter, the MSB register must always be written first, immediately followed
by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both registers must be
written in this sequence. 表 109 is a list of the page 4 registers, excluding the previously described register 0.
表 109. Page 4 Registers
REGISTER
NUMBER
RESET VALUE
REGISTER NAME
1
2
XXXX XXXX
0000 0001
0001 0111
0000 0001
0001 0111
0111 1101
1101 0011
0111 1111
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
0111 1111
1111 1111
0000 0000
0000 0000
0000 0000
Reserved. Do not write to this register.
Coefficient N0(15:8) for AGC LPF (first-order IIR) used as averager to detect level(1)
Coefficient N0(7:0) for AGC LPF (first-order IIR) used as averager to detect level
Coefficient N1(15:8) for AGC LPF (first-order IIR) used as averager to detect level
Coefficient N1(7:0) for AGC LPF (first-order IIR) used as averager to detect level
Coefficient D1(15:8) for AGC LPF (first-order IIR) used as averager to detect level
Coefficient D1(7:0) for AGC LPF (first-order IIR) used as averager to detect level
Coefficient N0(15:8) for Left ADC programmable first-order IIR
3
4
5
6
7
8
9
Coefficient N0(7:0) for Left ADC programmable first-order IIR
10
11
12
13
14
15
16
17
18
Coefficient N1(15:8) for Left ADC programmable first-order IIR
Coefficient N1(7:0) for Left ADC programmable first-order IIR
Coefficient D1(15:8) for Left ADC programmable first-order IIR
Coefficient D1(7:0) for Left ADC programmable first-order IIR
Coefficient N0(15:8) for Left ADC Biquad A or Coefficient FIR0(15:8) for ADC FIR Filter
Coefficient N0(7:0) for Left ADC Biquad A or Coefficient FIR0(7:0) for ADC FIR Filter
Coefficient N1(15:8) for Left ADC Biquad A or Coefficient FIR1(15:8) for ADC FIR Filter
Coefficient N1(7:0) for Left ADC Biquad A or Coefficient FIR1(7:0) for ADC FIR Filter
Coefficient N2(15:8) for Left ADC Biquad A or Coefficient FIR2(15:8) for ADC FIR Filter
(1) Rows belonging to the same coefficient are shaded in this table for easier readability.
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表 109. Page 4 Registers (接下页)
REGISTER
RESET VALUE
REGISTER NAME
NUMBER
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0111 1111
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0111 1111
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0111 1111
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0111 1111
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
Coefficient N2(7:0) for Left ADC Biquad A or Coefficient FIR2(7:0) for ADC FIR Filter
Coefficient D1(15:8) for Left ADC Biquad A or Coefficient FIR3(15:8) for ADC FIR Filter
Coefficient D1(7:0) for Left ADC Biquad A or Coefficient FIR3(7:0) for ADC FIR Filter
Coefficient D2(15:8) for Left ADC Biquad A or Coefficient FIR4(15:8) for ADC FIR Filter
Coefficient D2(7:0) for Left ADC Biquad A or Coefficient FIR4(7:0) for ADC FIR Filter
Coefficient N0(15:8) for Left ADC Biquad B or Coefficient FIR5(15:8) for ADC FIR Filter
Coefficient N0(7:0) for Left ADC Biquad B or Coefficient FIR5(7:0) for ADC FIR Filter
Coefficient N1(15:8) for Left ADC Biquad B or Coefficient FIR6(15:8) for ADC FIR Filter
Coefficient N1(7:0) for Left ADC Biquad B or Coefficient FIR6(7:0) for ADC FIR Filter
Coefficient N2(15:8) for Left ADC Biquad B or Coefficient FIR7(15:8) for ADC FIR Filter
Coefficient N2(7:0) for Left ADC Biquad B or Coefficient FIR7(7:0) for ADC FIR Filter
Coefficient D1(15:8) for Left ADC Biquad B or Coefficient FIR8(15:8) for ADC FIR Filter
Coefficient D1(7:0) for Left ADC Biquad B or Coefficient FIR8(7:0) for ADC FIR Filter
Coefficient D2(15:8) for Left ADC Biquad B or Coefficient FIR9(15:8) for ADC FIR Filter
Coefficient D2(7:0) for Left ADC Biquad B or Coefficient FIR9(7:0) for ADC FIR Filter
Coefficient N0(15:8) for Left ADC Biquad C or Coefficient FIR10(15:8) for ADC FIR Filter
Coefficient N0(7:0) for Left ADC Biquad C or Coefficient FIR10(7:0) for ADC FIR Filter
Coefficient N1(15:8) for Left ADC Biquad C or Coefficient FIR11(15:8) for ADC FIR Filter
Coefficient N1(7:0) for Left ADC Biquad C or Coefficient FIR11(7:0) for ADC FIR Filter
Coefficient N2(15:8) for Left ADC Biquad C or Coefficient FIR12(15:8) for ADC FIR Filter
Coefficient N2(7:0) for Left ADC Biquad C or Coefficient FIR12(7:0) for ADC FIR Filter
Coefficient D1(15:8) for Left ADC Biquad C or Coefficient FIR13(15:8) for ADC FIR Filter
Coefficient D1(7:0) for Left ADC Biquad C or Coefficient FIR13(7:0) for ADC FIR Filter
Coefficient D2(15:8) for Left ADC Biquad C or Coefficient FIR14(15:8) for ADC FIR Filter
Coefficient D2(7:0) for Left ADC Biquad C or Coefficient FIR14(7:0) for ADC FIR Filter
Coefficient N0(15:8) for Left ADC Biquad D or Coefficient FIR15(15:8) for ADC FIR Filter
Coefficient N0(7:0) for Left ADC Biquad D or Coefficient FIR15(7:0) for ADC FIR Filter
Coefficient N1(15:8) for Left ADC Biquad D or Coefficient FIR16(15:8) for ADC FIR Filter
Coefficient N1(7:0) for Left ADC Biquad D or Coefficient FIR16(7:0) for ADC FIR Filter
Coefficient N2(15:8) for Left ADC Biquad D or Coefficient FIR17(15:8) for ADC FIR Filter
Coefficient N2(7:0) for Left ADC Biquad D or Coefficient FIR17(7:0) for ADC FIR Filter
Coefficient D1(15:8) for Left ADC Biquad D or Coefficient FIR18(15:8) for ADC FIR Filter
Coefficient D1(7:0) for Left ADC Biquad D or Coefficient FIR18(7:0) for ADC FIR Filter
Coefficient D2(15:8) for Left ADC Biquad D or Coefficient FIR19(15:8) for ADC FIR Filter
Coefficient D2(7:0) for Left ADC Biquad D or Coefficient FIR19(7:0) for ADC FIR Filter
Coefficient N0(15:8) for Left ADC Biquad E or Coefficient FIR20(15:8) for ADC FIR Filter
Coefficient N0(7:0) for Left ADC Biquad E or Coefficient FIR20(7:0) for ADC FIR Filter
Coefficient N1(15:8) for Left ADC Biquad E or Coefficient FIR21(15:8) for ADC FIR Filter
Coefficient N1(7:0) for Left ADC Biquad E or Coefficient FIR21(7:0) for ADC FIR Filter
Coefficient N2(15:8) for Left ADC Biquad E or Coefficient FIR22(15:8) for ADC FIR Filter
Coefficient N2(7:0) for Left ADC Biquad E or Coefficient FIR22(7:0) for ADC FIR Filter
Coefficient D1(15:8) for Left ADC Biquad E or Coefficient FIR23(15:8) for ADC FIR Filter
Coefficient D1(7:0) for Left ADC Biquad E or Coefficient FIR23(7:0) for ADC FIR Filter
Coefficient D2(15:8) for Left ADC Biquad E or Coefficient FIR24(15:8) for ADC FIR Filter
Coefficient D2(7:0) for Left ADC Biquad E or Coefficient FIR24(7:0) for ADC FIR Filter
Reserved
Reserved
84
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表 109. Page 4 Registers (接下页)
REGISTER
NUMBER
RESET VALUE
REGISTER NAME
66
67
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
68
69
70
71
72
Coefficient N0(15:8) for Right ADC programmable first-order IIR
Coefficient N0(7:0) for Right ADC programmable first-order IIR
Coefficient N1(15:8) for Right ADC programmable first-order IIR
Coefficient N1(7:0) for Right ADC programmable first-order IIR
Coefficient D1(15:8) for Right ADC programmable first-order IIR
Coefficient D1(7:0) for Right ADC programmable first-order IIR
73
74
75
76
77
78
Coefficient N0(15:8) for Right ADC Biquad A or Coefficient FIR0(15:8) for ADC FIR Filter
Coefficient N0(7:0) for Right ADC Biquad A or Coefficient FIR0(7:0) for ADC FIR Filter
Coefficient N1(15:8) for Right ADC Biquad A or Coefficient FIR1(15:8) for ADC FIR Filter
Coefficient N1(7:0) for Right ADC Biquad A or Coefficient FIR1(7:0) for ADC FIR Filter
Coefficient N2(15:8) for Right ADC Biquad A or Coefficient FIR2(15:8) for ADC FIR Filter
Coefficient N2(7:0) for Right ADC Biquad A or Coefficient FIR2(7:0) for ADC FIR Filter
Coefficient D1(15:8) for Right ADC Biquad A or Coefficient FIR3(15:8) for ADC FIR Filter
Coefficient D1(7:0) for Right ADC Biquad A or Coefficient FIR3(7:0) for ADC FIR Filter
Coefficient D2(15:8) for Right ADC Biquad A or Coefficient FIR4(15:8) for ADC FIR Filter
Coefficient D2(7:0) for Right ADC Biquad A or Coefficient FIR4(7:0) for ADC FIR Filter
Coefficient N0(15:8) for Right ADC Biquad B or Coefficient FIR5(15:8) for ADC FIR Filter
Coefficient N0(7:0) for Right ADC Biquad B or Coefficient FIR5(7:0) for ADC FIR Filter
Coefficient N1(15:8) for Right ADC Biquad B or Coefficient FIR6(15:8) for ADC FIR Filter
Coefficient N1(7:0) for Right ADC Biquad B or Coefficient FIR6(7:0) for ADC FIR Filter
Coefficient N2(15:8) for Right ADC Biquad B or Coefficient FIR7(15:8) for ADC FIR Filter
Coefficient N2(7:0) for Right ADC Biquad B or Coefficient FIR7(7:0) for ADC FIR Filter
Coefficient D1(15:8) for Right ADC Biquad B or Coefficient FIR8(15:8) for ADC FIR Filter
Coefficient D1(7:0) for Right ADC Biquad B or Coefficient FIR8(7:0) for ADC FIR Filter
Coefficient D2(15:8) for Right ADC Biquad B or Coefficient FIR9(15:8) for ADC FIR Filter
Coefficient D2(7:0) for Right ADC Biquad B or Coefficient FIR9(7:0) for ADC FIR Filter
Coefficient N0(15:8) for Right ADC Biquad C or Coefficient FIR10(15:8) for ADC FIR Filter
Coefficient N0(7:0) for Right ADC Biquad C or Coefficient FIR10(7:0) for ADC FIR Filter
Coefficient N1(15:8) for Right ADC Biquad C or Coefficient FIR11(15:8) for ADC FIR Filter
Coefficient N1(7:0) for Right ADC Biquad C or Coefficient FIR11(7:0) for ADC FIR Filter
Coefficient N2(15:8) for Right ADC Biquad C or Coefficient FIR12(15:8) for ADC FIR Filter
Coefficient N2(7:0) for Right ADC Biquad C or Coefficient FIR12(7:0) for ADC FIR Filter
Coefficient D1(15:8) for Right ADC Biquad C or Coefficient FIR13(15:8) for ADC FIR Filter
Coefficient D1(7:0) for Right ADC Biquad C or Coefficient FIR13(7:0) for ADC FIR Filter
Coefficient D2(15:8) for Right ADC Biquad C or Coefficient FIR14(15:8) for ADC FIR Filter
Coefficient D2(7:0) for Right ADC Biquad C or Coefficient FIR14(7:0) for ADC FIR Filter
Coefficient N0(15:8) for Right ADC Biquad D or Coefficient FIR15(15:8) for ADC FIR Filter
Coefficient N0(7:0) for Right ADC Biquad D or Coefficient FIR15(7:0) for ADC FIR Filter
Coefficient N1(15:8) for Right ADC Biquad D or Coefficient FIR16(15:8) for ADC FIR Filter
Coefficient N1(7:0) for Right ADC Biquad D or Coefficient FIR16(7:0) for ADC FIR Filter
Coefficient N2(15:8) for Right ADC Biquad D or Coefficient FIR17(15:8) for ADC FIR Filter
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
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表 109. Page 4 Registers (接下页)
REGISTER
NUMBER
RESET VALUE
REGISTER NAME
113
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
Coefficient N2(7:0) for Right ADC Biquad D or Coefficient FIR17(7:0) for ADC FIR Filter
Coefficient D1(15:8) for Right ADC Biquad D or Coefficient FIR18(15:8) for ADC FIR Filter
Coefficient D1(7:0) for Right ADC Biquad D or Coefficient FIR18(7:0) for ADC FIR Filter
Coefficient D2(15:8) for Right ADC Biquad D or Coefficient FIR19(15:8) for ADC FIR Filter
Coefficient D2(7:0) for Right ADC Biquad D or Coefficient FIR19(7:0) for ADC FIR Filter
Coefficient N0(15:8) for Right ADC Biquad E or Coefficient FIR20(15:8) for ADC FIR Filter
Coefficient N0(7:0) for Right ADC Biquad E or Coefficient FIR20(7:0) for ADC FIR Filter
Coefficient N1(15:8) for Right ADC Biquad E or Coefficient FIR21(15:8) for ADC FIR Filter
Coefficient N1(7:0) for Right ADC Biquad E or Coefficient FIR21(7:0) for ADC FIR Filter
Coefficient N2(15:8) for Right ADC Biquad E or Coefficient FIR22(15:8) for ADC FIR Filter
Coefficient N2(7:0) for Right ADC Biquad E or Coefficient FIR22(7:0) for ADC FIR Filter
Coefficient D1(15:8) for Right ADC Biquad E or Coefficient FIR23(15:8) for ADC FIR Filter
Coefficient D1(7:0) for Right ADC Biquad E or Coefficient FIR23(7:0) for ADC FIR Filter
Coefficient D2(15:8) for Right ADC Biquad E or Coefficient FIR24(15:8) for ADC FIR Filter
Coefficient D2(7:0) for Right ADC Biquad E or Coefficient FIR24(7:0) for ADC FIR Filter
114
115
116
117
118
119
120
121
122
123
124
125
126
127
86
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
图 137 shows the required external components and system level connections for proper operation of the device
in several popular use cases.
IOVDD
DBB
RP
RP
AVDD
(2.7 V œ 3.6 V)
AVDD
1 µF
0.1 µF
A
1 µF
1 µF
AVSS
IN2R(P)
IN3R(M)
Mic 1
1 µF
A
IOVDD
(1.1 V œ 3.3 V)
2 kΩ
IOVDD
DVDD
TLV320ADC3100
1.65 Vœ1.95 V
MICBIAS1
0.1 µF
1 µF
1 µF
0.1 µF
2 kΩ
1 µF
A
1 µF
1 µF
DVSS
IN2L(P)
IN3L(M)
Mic 2
I2C
ADDRESS
D
I2C_ADR0
I2C_ADR1
图 137. Typical Connections
Each of these configurations can be realized using the evaluation modules (EVMs) for the device. As previously
discussed in the Recording Mode section, the TLV320ADC3100 is form-factor and software compatible with the
TLV320ADC3101. Therefore, both the TLV320ADC3101 and the TLV320ADC3100 use the same EVM, the
TLV320ADC3101-K. These flexible modules allow full evaluation of the device in the most common modes of
operation. Any design variation can be supported by TI through schematic and layout reviews. Visit
http://e2e.ti.com for design assistance and join the audio amplifier discussion forum for additional information.
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9.2 Typical Application
A
1 µF
1 µF
IN2R(P)
IN3R(M)
Mic 1
1 µF
TLV320ADC3100
2 kΩ
MICBIAS1
2 kΩ
1 µF
A
1 µF
1 µF
IN2L(P)
IN3L(M)
Mic 2
图 138. Application With Two Analog Microphones Using a Shared MICBIAS
9.2.1 Design Requirements
表 110 lists the design parameters for this application.
表 110. Design Parameters
KEY PARAMETER
SPECIFICATION
AVDD
3.3 V
> 6 mA (PLL on, AGC off, digital filter engine off,
stereo record, fS = 48 kHz)
AVDD supply current
DVDD
1.8 V
> 4 mA (PLL on, AGC off, digital filter engine off,
stereo record, fS = 48 kHz)
DVDD supply current
IOVDD
1.8 V
Maximum MICBIAS current
4 mA (MICBIAS voltage 2.5 V)
9.2.2 Detailed Design Procedure
This section describes the necessary steps to configure the TLV320ADC3100.
9.2.2.1 Step 1
The system clock source (master clock) and the targeted ADC sampling frequency must be identified.
Depending on the targeted performance, the decimation filter type (A, B, or C) and AOSR value can be
determined:
•
•
•
Filter A must be used for 48-kHz high-performance operation; AOSR must be a multiple of 8
Filter B must be used for up to 96-kHz operations; AOSR must be a multiple of 4
Filter C must be used for up to 192-kHz operations; AOSR must be a multiple of 2
In all cases, 公式 6 limits the AOSR range:
2.8 MHz < AOSR × ADC_fs < 6.2 MHz
(6)
Based on the identified filter type and the required signal-processing capabilities, the appropriate processing
block can be determined from the list of available processing blocks (PRB_R1 to PRB_R18).
Based on the available master clock, the chosen AOSR and the targeted sampling rate, the clock divider values
NADC and MADC can be determined. If necessary, the internal PLL can add a large degree of flexibility.
88
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公式 7 describes that, in summary, ADC_CLKIN (derived directly from the system clock source or from the
internal PLL) divided by MADC, NADC, and AOSR must be equal to the ADC sampling rate ADC_fs. The
ADC_CLKIN clock signal is shared with the DAC clock-generation block.
ADC_CLKIN = NADC × MADC × AOSR x ADC_fs
(7)
To a large degree, NADC and MADC can be chosen independently in the range of 1 to 128. In general, as long
as 公式 8 is met, NADC must be as large as possible:
MADC × AOSR ≥ INSTR_CTR
(8)
RC is a function of the chosen processing block and is listed in 表 6.
The common-mode voltage setting of the device is determined by the available analog power supply.
At this point, the PRB_Rx, AOSR, NADC, MADC, and input and output common-mode values device-specific
parameters are known. If the PLL is used, the PLL parameters P, J, D, and R are determined as well.
9.2.2.2 Step 2
Setting up the device via register programming:
The following list gives a sequence of items that must be executed in the time between powering the device up
and reading data from the device:
1. Define starting point:
a. Power up applicable external hardware power supplies
b. Set register page to 0
c. Initiate SW reset
2. Program clock settings:
a. Program PLL clock dividers P, J, D, and R (if PLL is used)
b. Power up PLL (if PLL is used)
c. Program and power up NADC
d. Program and power up MADC
e. Program OSR value
f. Program I2S word length if required (for example, 20 bits)
g. Program the processing block to be used
3. Program analog blocks:
a. Set register page to 1
b. Program MICBIAS, if applicable
c. Program MICPGA
d. Program routing of inputs and common mode to ADC input
e. Unmute analog PGAs and set analog gain
4. Program ADC:
a. Set register page to 0
b. Power up ADC channel
c. Unmute digital volume control and set gain
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9.2.2.3 Example Register Setup to Record Analog Data Through ADC to Digital Out
A typical EVM I2C register control script follows to show how to set up the TLV320ADC3100 in record mode with
fS = 44.1 kHz and MCLK = 11.2896 MHz.
# Key: w 30 XX YY ==> write to I2C address 0x30, to register 0xXX, data 0xYY
#
#
# ==> comment delimiter
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are
# other valid sequences depending on which features are used.
#
# ADC3101EVM Key Jumper Settings and Audio Connections:
# 1. Remove Jumpers W12 and W13
# 2. Insert Jumpers W4 and W5
# 3. Insert a 3.5mm stereo audio plug into J9 for
#
#
single-ended input IN1L(P) - left channel and
single-ended input IN1R(M) - right channel
################################################################
# 1. Define starting point:
#
#
#
(a) Power up appicable external hardware power supplies
(b) Set register page to 0
w 30 00 00
#
(c) Initiate SW Reset
#
w 30 01 01
#
# 2. Program Clock Settings
#
#
(a) Program PLL clock dividers P,J,D,R (if PLL is necessary)
# In EVM, the ADC3001 receives: MCLK = 11.2896 MHz,
# BCLK = 2.8224 MHz, WCLK = 44.1 kHz
#
# Sinve the sample rate is a multiple of the input MCLK then
# no PLL is needed thereby saving power. Use Default (Reset) Settings:
# ADC_CLKIN = MCLK, P=1, R=1, J=4, D=0000
w 30 04 00
w 30 05 11
w 30 06 04
w 30 07 00
w 30 08 00
#
#
(b) Power up PLL (if PLL is necessary) - Not Used in this Example
w 30 05 11
#
(c) Program and power up NADC
#
# NADC = 1, divider powered on
w 30 12 81
#
#
#
(d) Program and power up MADC
# MADC = 2, divider powered on
w 30 13 82
#
#
#
(e) Program OSR value
# AOSR = 128 (default)
w 30 14 80
#
#
#
(f) Program I2S word length as required (16, 20, 24, 32 bits)
# mode is i2s, wordlength is 16, slave mode (default)
w 30 1B 00
#
#
#
(g) Program the processing block to be used
# PRB_P1
w 30 3d 01
#
# 3. Program Analog Blocks
#
#
(a) Set register Page to 1
90
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TLV320ADC3100
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ZHCSHY2 –MARCH 2018
w 30 00 01
#
#
(b) Program MICBIAS if applicable
#
# Not used (default)
w 30 33 00
#
#
#
(c) Program MICPGA
# Left Analog PGA Seeting = 0dB
w 30 3b 00
#
# Right Analog PGA Seeting = 0dB
w 30 3c 00
#
#
#
#
(d) Routing of inputs/common mode to ADC input
(e) Unmute analog PGAs and set analog gain
# Left ADC Input selection for Left PGA = IN1L(P) as Single-Ended
w 30 34 fc
#
# Right ADC Input selection for Right PGA = IN1R(M) as Single-Ended
w 30 37 fc
#
# 4. Program ADC
#
#
#
(a) Set register Page to 0
w 30 00 00
#
#
(b) Power up ADC channel
#
# Power-up Left ADC and Right ADC
w 30 51 c2
#
#
#
(c) Unmute digital volume control and set gain = 0 dB
# UNMUTE
w 30 52 00
#
9.2.2.4 MICBIAS
The TLV320ADC3100 has a built-in bias voltage output for the biasing of microphones. No intentional capacitors
must be connected directly to the MICBIAS output for filtering.
9.2.2.5 Decoupling Capacitors
The TLV320ADC3100 requires adequate power-supply decoupling to ensure that the noise and total harmonic
distortion (THD) are low. A good ceramic capacitor, typically 0.1 µF, placed as close as possible to the device
AVDD, IOVDD, and DVDD lead works best. Placing this decoupling capacitor close to the TLV320ADC3100 is
important for the performance of the converter. For filtering lower-frequency noise signals, a 1-µF or greater
capacitor placed near the device also helps.
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9.2.3 Application Curves
17
15
13
11
9
0
-20
Left Channel
Right Channel
-40
-60
-80
-100
-120
-140
7
5
0
2
4
6
8
10
12
14
16
18
20
0
5
10
15
20
25
30
35
40
Frequency (kHz)
D004
PGA Gain Setting (dB)
D005
图 139. Line Input to ADC FFT Plot
图 140. Input-Referred Noise vs PGA Gain
10 Power Supply Recommendations
The power supplies are designed to operate from 2.7 V to 3.6 V for AVDD, from 1.65 V to 1.95 V for DVDD and
from 1.1 V to 3.6 V for IOVDD. Any value out of these ranges must be avoided to ensure the correct behavior of
the device. The power supplies must be well regulated. Placing a decoupling capacitor close to the
TLV320ADC3100 improves the performance of the device. A low equivalent-series-resistance (ESR) ceramic
capacitor with a value of 0.1 µF is a typical choice. If the TLV320ADC3100 is used in highly noise-sensitive
circuits, TI recommends adding a small LC filter on the VDD connections.
92
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TLV320ADC3100
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ZHCSHY2 –MARCH 2018
11 Layout
11.1 Layout Guidelines
Each system design and PCB layout is unique. The layout must be carefully reviewed in the context of a specific
PCB design. However, the following guidelines can optimize the TLV320ADC3100 performance:
The decoupling capacitors for the power supplies must be placed close to the device terminals. 图 137 shows the
recommended decoupling capacitors for the TLV320ADC3100.
Route analog differential audio signals differentially on the PCB for better noise immunity. Avoid crossing digital
and analog signals to avoid undesirable crosstalk.
Analog and digital grounds must be separated to prevent possible digital noise from affecting the analog
performance of the board.
11.2 Layout Example
图 141. Layout Recommendation
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TLV320ADC3100
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12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
如需相关文档，请参阅：
•
•
•
《用于无线电话和便携式音频并具有嵌入式 miniDSP 的 TLV320ADC3101 低功耗立体声 ADC》
《用于无线电话和便携式音频并具有嵌入式 miniDSP 的 TLV320ADC3001 低功耗立体声 ADC》
《TLV320ADC3101EVM-K 用户指南》
12.2 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 上的器件产品文件夹。请单击右上角的提醒我 进行注册，即可每周
接收产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV320ADC3100IRGER
TLV320ADC3100IRGET
ACTIVE
VQFN
VQFN
RGE
24
24
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
ADC
3100
ACTIVE
RGE
NIPDAU
ADC
3100
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
RGE0024B
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
0.5
0.3
PIN 1 INDEX AREA
4.1
3.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 2.5
(0.2) TYP
2.45 0.1
7
12
EXPOSED
SEE TERMINAL
DETAIL
THERMAL PAD
13
6
2X
SYMM
25
2.5
18
1
0.3
24X
20X 0.5
0.2
19
24
0.1
C A B
SYMM
24X
PIN 1 ID
(OPTIONAL)
0.05
0.5
0.3
4219013/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.45)
SYMM
24
19
24X (0.6)
1
18
24X (0.25)
(R0.05)
TYP
25
SYMM
(3.8)
20X (0.5)
13
6
(
0.2) TYP
VIA
7
12
(0.975) TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219013/A 05/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGE0024B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.08)
(0.64) TYP
19
24
24X (0.6)
1
25
18
24X (0.25)
(R0.05) TYP
SYMM
(0.64)
TYP
(3.8)
20X (0.5)
13
6
METAL
TYP
7
12
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219013/A 05/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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