TLV320AIC1109 [TI]
PCM CODEC; PCM编解码器型号: | TLV320AIC1109 |
厂家: | TEXAS INSTRUMENTS |
描述: | PCM CODEC |
文件: | 总27页 (文件大小:354K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TLV320AIC1109
SLAS358 – DECEMBER 2001
PCM CODEC
FEATURES
DESCRIPTION
D
2.7-V Operation
The PCM codec is designed to perform the transmit
encoding analog/digital (A/D) conversion and receive
decoding digital/analog (D/A) conversion, together with
transmit and receive filtering, for voice-band
communications systems. The device operates in
either the 15-bit linear or 8-bit companded (µ-law or
A-Law) mode, which is selectable through the I C
interface. From a 2.048-MHz master clock input, the
PCM codec generates its own internal clocks.
D
Two Differential Microphone Inputs, One
Differential Earphone Output, and One
Single-Ended Earphone Output
D
Programmable Gain Amplifiers for Transmit,
Receive, Sidetone, and Volume Control
2
D
Earphone Mute and Microphone Mute
2
D
On-Chip I C-Bus, Which Provides a Simple,
Standard, Two-Wire Serial Interface With
Digital ICs
PBS PACKAGE
(TOP VIEW)
D
Programmable for 15-Bit Linear Data or 8-Bit
Companded (µ-Law or A-Law) Mode
D
32-Terminal TQFP Package
D
Designed for Analog and Digital Wireless
Handsets and Telecommunications
Applications
24 23 22 21 20 19 18 17
D
D
Dual-Tone Multifrequency (DTMF)
16
25
26
27
28
PLLV
PCMO
PCMI
DD
15
14
13
EARV
Pulse Density Modulated (PDM) Buzzer
Output
SS
EAR1ON
EARV
DV
SS
DV
DD
DD
12
EAR1OP
EARV
SCL
29
30
31
32
APPLICATIONS
11 SDA
10
9
SS
D
D
D
D
D
Digital Handset
Digital Headset
EAR2O
AV
NC
NC
DD
Cordless Phones
Digital PABX
1
2
3
4
5
6
7
8
Digital Voice Recording
NC – No internal connection
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either V
or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for
CC
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2001, Texas Instruments Incorporated
1
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PCMIN
PCMSYN
PCMCLK
PCMOUT
MIC1P
MIC1N
RX Vol
Control
g = 18 dB
to
PCM
Interface
EAR1OP
EAR1ON
Ear
Amp1
0 dB
MIC
Amplifier
2
g = 12 dB
or
RX Filter
and PGA
g = –6 dB
to
MIC
Amplifier
1
g =
TX Filter
and PGA
g = 10 dB
to
Digital
Modulator
and Filter
Analog
Modulator
23.5 dB
+6 dB
0 dB
0 dB
Sidetone
g = –24 db
to
Ear
Amp2
EAR2O
MIC2P
MIC2N
–12 dB
Control Bus
DTMF
Buzzer
Control
BUZZCON
Generator
REF
2
I
C
PLL
Power and RESET
I/F
TLV320AIC1109
SLAS358 – DECEMBER 2001
functional description
power-on/reset
The power for the various digital and analog circuits is separated to improve the noise performance of the
device. An external reset must be applied to the active low/RESET terminal to assure reset upon power on and
to bring the device to an operational state. After the initial power-on sequence the TLV320AIC1109 can be
2
functionally powered up and down by writing to the power control register through the I C interface. The device
has a pin selectable power-up in the default mode option. The hardwired pin-selectable PWRUPSEL function
allows the PCM codec to power up in the default mode and to be used without a microcontroller.
reference
A precision band gap reference voltage is generated internally and supplies all required voltage references to
operate the transmit and receive channels. The reference system also supplies bias voltage for use with an
electret microphone at terminal MBIAS. An external precision resistor is required for reference current setting
at terminal REXT.
control interface
2
2
The I C interface is a two-wire bidirectional serial interface. The I C interface controls the PCM codec by writing
data to six control registers: 1) power control, 2) mode control, 3) transmit PGA and sidetone control, 4) receive
PGA gain and volume control, 5) DTMF routing, and 6) tone selection control.
There are two power-up modes which may be selected at the PWRUPSEL terminal: 1) the PWRUPSEL state
2
(V
at terminal 20) causes the device to power-up in the default mode when power is applied. Without an I C
DD
interface or controlling device, the programmable functions will be fixed at he default gain levels and functions,
such as the sidetone and DTF, will not be accessible. 2) The PWRUPSEL state (ground at terminal 20) causes
2
the device to go to a power-down state when power is applied. In this mode an I C interface is required to power
up the device.
phase-locked loop
The internal digital filters and modulators require a 10.24-MHz clock that is generated by phase locking to the
2.048-MHz master clock input.
PCM interface
The PCM interface transmits and receives data at the PCMO and PCMI terminals respectively. The data is
transmitted or received at the PCMCLK speed once every PCMSYN cycle. The PCMCLK may be tied directly
to the 2.048-MHz master clock (MCLK). The PCMSYN can be driven by an external source or derived from the
master clock and used as an interrupt to the host controller.
microphone amplifiers
The microphone input is a switchable interface for two differential microphone inputs. The first stage is a low
noise differential amplifier that provides a gain of 23.5 dB. The second stage amplifier has a selectable gain of
0 dB or 12 dB.
analog modulator
The transmit channel modulator is a third-order sigma-delta design.
transmit filter and PGA
The transmit filter is a digital filter designed to meet CCITT G.714 requirements. The device operates in either
2
the 15-bit linear or 8-bit companded µ-law or A-law mode that is selectable through the I C interface. The
transmit PGA defaults to 0 dB.
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TLV320AIC1109
SLAS358 – DECEMBER 2001
functional description (continued)
sidetone
A portion of the transmitted audio is attenuated and fed back to the receive channel through the sidetone path.
The sidetone path defaults to the mute condition. The default gain of -12 dB is set in the sidetone control register.
The sidetone path can be enabled by writing to the power control register.
receive volume control
The receive volume control block acts as an attenuator with a range of –18 dB to 0 dB in 2 dB steps for control
of the receive channel volume. The receive volume control gain defaults to 0 dB.
receive filter and PGA
The receive filter is a digital filter that meets CCITT G.714 requirements with a high-pass filter that is selectable
2
through the I C interface. The device operates in either the 15-bit linear or 8-bit µ-law or A-law companded
2
mode, which is selectable through the I C interface. The gain defaults to –1 dB representing a 3 dBm0 level
for a 32 Ω to 110 Ω load impedance and the corresponding digital full scale PCMI code of –4 dB.
digital modulator and filter
Thesecond-orderdigitalmodulatorandfilterconvertthereceiveddigitalPCMdatatotheanalogoutputrequired
by the earphone interface.
earphone amplifiers
The analog signal can be routed to either of two earphone amplifiers, one with differential output (EAR1ON and
EAR1OP) and one with single-ended output (EAR2O). Clicks and pops are suppressed for EAR1 differential
output only.
tone generator
The tone generator provides generation of standard DTMF tones which are output to one of the following: 1)
the buzzer driver, as a pulse density modulation (PDM) signal, or 2) the receive path digital/analog converter
(D/A), for outputting through the earphone or as PCMO data. The integer value is loaded into one of two 8-bit
registers, the high tone register [04} or the low tone register {05}. The tone output is 2 dB higher when applied
to the high tone register {04}. The high DTMF tones must be applied to the high tone register, and the low DTMF
tones to the low tone register.
4
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TLV320AIC1109
SLAS358 – DECEMBER 2001
Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
NAME
TQFP
32
8
AV
AV
I
I
Analog positive power supply
Analog negative power supply
DD
SS
BUZZCON
19
13
14
27
29
31
28
30, 26
1
O
I
Buzzer output, a pulse-density modulated signal to apply to external buzzer driver
Digital positive power supply
DV
DV
DD
SS
I
Digital negative power supply
Earphone 1 amplifier output (–)
Earphone 1 amplifier output (+)
Earphone 2 amplifier output
EAR1ON
EAR1OP
EAR2O
O
O
O
I
EARV
EARV
Analog positive power supply for the earphone amplifiers
Analog negative power supply for the earphone amplifiers
Microphone bias supply output, no decoupling capacitors
Master system clock input (2.048 MHz) (digital)
MIC1 input (+)
DD
I
SS
MBIAS
MCLK
O
I
22
2
MIC1P
MIC1N
MIC2P
MIC2N
PCMI
I
3
I
MIC1 input (–)
4
I
MIC2 input (+)
5
I
MIC2 input (–)
15
16
18
17
24
25
20
6
I
Receive PCM input
PCMO
PCMSYN
PCMCLK
O
I
Transmit PCM output
PCM frame sync
I
PCM data clock
PLLV
PLLV
I
PLL negative power supply
SS
I
PLL digital power supply
DD
PWRUPSEL
REXT
I
Selects the power-up default mode
I/O Internal reference current setting terminal. This terminal uses a precision 100-kΩ resistor and no filtering
capacitors.
RESET
SCL
21
12
11
I
I
Active low reset
2
I C-bus serial clock. This input is used to synchronize the data transfer from and to the PCM codec.
2
SDA
I/O I C-bus serial address/data input/output. This is a bidirectional terminal used to transfer register control
addressesand data into and out of the codec. It is an open-drainterminalandthereforerequiresapullupresistor
to V
(typical 10 kΩ for 100 kHz).
DD
Ground return for bandgap internal reference
V
SS
23
I
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free air temperature range (industrial temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
5
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TLV320AIC1109
SLAS358 – DECEMBER 2001
DISSIPATION RATING TABLE
≤ 25°C DERATING FACTOR
T
A
T = 85°C
A
POWER RATING
PACKAGE
POWER RATING
ABOVE T = 25°C
A
PBS
702 mW
7.2 mW/°C
270 mW
recommended operating conditions (see Notes 1 and 2)
MIN
2.7
NOM
MAX
UNIT
V
Supply voltage, AV , DV , PLLV , EARV
DD
3.3
DD
DD
DD
High-level input voltage (V
)
0.7 × V
V
IHMIN
DD
Low-level input voltage (V
)
0.3 × V
V
ILMAX
DD
Load impedance between EAR1OP and EAR1ON-R
32 to 110
32
Ω
L
Load impedance for EAR2OP-R
Ω
L
Operating free-air temperature, T
–40
85
°C
A
NOTES: 1. To avoid possible damage and resulting reliability problems to these CMOS devices, the power-on initialization paragraph should
be followed, described in the Principles of Operations.
2. Voltages are with respect to AV , DV , PLLV
and EARV .
SS SS SS
SS
electrical characteristics over recommended ranges of supply voltage and free air temperature (unless
otherwise noted)
supply current
PARAMETER
TEST CONDITIONS
MIN
TYP
6
MAX
8
UNIT
mA
mA
µA
Operating, EAR1 selected, MicBias disabled
Operating, EAR2 selected, MicBias disabled
5.4
0.5
25
5
7
I
t
Supply current from V
DD
DD
Power down, Reg 2 bit 7 = 1, MCLK not present (see Note 3)
Power down, Reg 2 bit 7 = 0, MCLK not present (see Note 3)
35
75
10
µA
Power-up time from power down
ms
on(i)
NOTE 3: Measured while MIC1P and MIC1N are connected together. Less than 5 mV offset results in 0 value code on PCMOUT.
digital interface
PARAMETER
TEST CONDITIONS
MIN
= –0.25
DD
TYP
MAX
UNIT
V
V
V
High-level output voltage PCMO (BUZZCON)
Low-level output voltage PCMO
High-level input current, any digital input
Low-level input current, any digital input
Input capacitance
I
I
= –3.2 mA,
V
= 3 V DV
= 3 V
OH
OH
DD
DD
= 3.2 mA,
V
0.25
10
10
10
20
5
V
OL
OL
I
I
V = V
µA
µA
pF
pF
kΩ
IH
I
DD
SS
V = V
IL
I
C
C
R
I
Output capacitance
o
L
Load impedance (BUZZCON)
6
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TLV320AIC1109
SLAS358 – DECEMBER 2001
electrical characteristics over recommended ranges of supply voltage and free air temperature (unless
otherwise noted) (continued)
microphone interface
PARAMETER
TEST CONDITIONS
See Note 3
MIN
–5
TYP
MAX
5
UNIT
mV
nA
V
IO
Input offset voltage at MIC1N, MIC2N
Input bias current at MIC1N, MIC2N
Input capacitance at MIC1N, MIC2N
I
IB
–250
250
C
5
3
pF
i
Microphone input referred noise, psophometric weighted,
(C-message weighted is similar)
Micamp 1 gain = 23.5 dB
Micamp 2 gain = 0 dB
V
n
7.7 µV
rms
I
max
Output source current – MBIAS
Microphone bias supply voltage (see Note 4)
MICMUTE
1
2.4
–80
35
1.2
mA
O
V(
2.5
60
2.55
V
mbias)
dB
kΩ
Input impedance
Fully differential
100
NOTES: 3. Measured while MIC1P and MIC1N are connected together. Less than 5-mV offset results in 0 value code on PCMOUT.
4. Not a JEDEC symbol
speaker interface
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Fully differential, 110-Ω load,
3-dBm0 output, RGXPA = –4 dB
23.4
31.2
mW
Earphone AMP1 output power (See Note 5)
V
= 2.7 V, fully differential, 32-Ω load,
DD
3-dBm0 output, RGXPA = –4 dB
80.5 107.3
mW
V
= 2.7 V, single ended, 32-Ω load,
DD
Earphone AMP2 output power (See Note 5)
Output offset voltage at EAR1
10
12.5
mW
mV
3-dBm0 output
V
OO
Fully differential
±5
14.6
50.2
17.7
±30
19.4
66.9
22.1
3-dBm0 input, 110-Ω load
3-dBm0 input, 32-Ω load
3-dBm0 input
Maximum output current for EAR1(rms)
I
O
max
mA
dB
Maximum output current for EAR2 (rms)
EARMUTE
–80
NOTE 5: Maximum power is with a load impedance of –25%.
transmit gain and dynamic range, companded mode (µ-law or A-law) or linear mode selected, transmit slope
filter bypassed (see Notes 6 and 7)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Transmit reference-signal level (0dB)
Differential
175 mV
pp
Differential, normal mode
Differential, extended mode
248
63
1
Overload-signal level (3 dBm0)
Absolute gain error
mV
pp
0 dBm0 input signal, V
DD
±10%
–1
–0.5
–1
dB
MIC1N, MIC1P to PCMO at 3 dBm0 to –30 dBm0
MIC1N, MIC1P to PCMO at –31 dBm0 to –45 dBm0
MIC1N, MIC1P to PCMO at –46 dBm0 to –55 dBm0
0.5
1
Gain error with input level relative to gain at
–10 dBm0 MIC1N, MIC1P to PCMO
dB
–1.2
1.2
NOTES: 6. Unlessotherwisenoted,theanaloginputis0dB,1020-Hzsinewave,where0dBisdefinedasthezero-referencepointofthechannel
under test.
7. The reference signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 88-mV
.
rms
7
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TLV320AIC1109
SLAS358 – DECEMBER 2001
electrical characteristics over recommended ranges of supply voltage and free air temperature (unless
otherwise noted) (continued)
transmit gain and dynamic range, companded mode (µ-law or A-law) or linear mode selected, transmit slope
filter enabled (see Notes 6 and 7)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Transmit reference-signal level (0dB)
Differential
175 mV
pp
Differential, normal mode
Differential, extended mode
248
63
1
Overload-signal level (3 dBm0)
Absolute gain error
mV
pp
0 dBm0 input signal, V
DD
±10 %
–1
–0.5
–1
dB
MIC1N, MIC1P to PCMO at 3 dBm0 to –30 dBm0
MIC1N, MIC1P to PCMO at –31 dBm0 to –45 dBm0
MIC1N, MIC1P to PCMO at –46 dBm0 to –55 dBm0
0.5
1
Gain error with input level relative to gain at
–10 dBm0 MIC1N, MIC1P to PCMO
dB
–1.2
1.2
NOTES: 6. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the
channel under test.
7. The reference signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 88-mV
rms
.
transmit filter transfer, companded mode (µ-law or A-law) or linear mode selected, transmit slope filter
bypassed, external high-pass filter bypassed (MCLK = 2.048 MHz)
PARAMETER
TEST CONDITIONS
MIN
–0.5
–0.5
–0.5
–1.5
TYP
MAX
0.5
0.5
0.5
0
UNIT
f
f
f
f
f
f
f
f
f
or f
or f
or f
or f
or f
or f
or f
or f
or f
<100 Hz
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
= 200 Hz
= 300 Hz to 3 kHz
= 3.4 kHz
= 4 kHz
Gain relative to input signal gain at 1020 Hz, internal high-pass
filter disabled.
dB
–14
–35
–47
–15
–5
= 4.6 kHz
= 8 k Hz
<100 Hz
Gain relative to input signal gain at 1020 Hz, internal high-pass
filter enabled.
dB
= 200 Hz
8
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TLV320AIC1109
SLAS358 – DECEMBER 2001
electrical characteristics over recommended ranges of supply voltage and free air temperature (unless
otherwise noted) (continued)
transmit filter transfer, companded mode (µ-law or A-law) or linear mode selected, transmit slope filter
selected, transmit high-pass filter disabled (MCLK = 2.048 MHz) (see Note 8)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
–27
–8
UNIT
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
or f
=100 Hz
= 200 Hz
= 250 Hz
= 300 Hz
= 400 Hz
= 500 Hz
= 600 Hz
= 700 Hz
= 800 Hz
= 900 Hz
= 1000 Hz
= 1500 Hz
= 2000 Hz
= 2500 Hz
= 3000 Hz
= 3100 Hz
= 3300 Hz
= 3500 Hz
= 4000 Hz
= 4500 Hz
= 5000 Hz
= 8000 Hz
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC1
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
MIC2
–4
–1.8
–1.5
–1.3
–1.1
–0.8
–0.57
–0.25
0
Gain relative to input signal gain at 1.2 kHz, with slope filter selected
1.8
4
6.5
7.6
7.7
8
6.48
–13
–35
–45
–50
NOTE 8: The pass-band tolerance is ± 0.25 dB from 300 Hz to 3500 Hz.
transmit idle channel noise and distortion, companded mode (µ-law or A-law) selected, slope filter bypassed
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Transmit idle channel noise, psophometrically
weighted
TXPGA gain= 0 dB, micamp 1 gain = 23.5 dB,
micamp 2 gain = 0 dB
–86.6
–78 dBm0
p
MIC1N, MIC1P to PCMO at 3 dBm0
MIC1N, MIC1P to PCMO at 0 dBm0
MIC1N, MIC1P to PCMO at –5 dBm0
MIC1N, MIC1P to PCMO at –10 dBm0
MIC1N, MIC1P to PCMO at –20 dBm0
MIC1N, MIC1P to PCMO at –30 dBm0
MIC1N, MIC1P to PCMO at –40 dBm0
MIC1N, MIC1P to PCMO at –45 dBm0
CCITT G.712 (7.1), R2
27
30
33
36
35
26
24
19
49
51
Transmit signal-to-distortion ratio with
1020-Hz sine-wave input
dBm0
Intermodulation distortion, 2-tone CCITT method,
composite power level, –13 dBm0
dB
CCITT G.712 (7.2), R2
9
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TLV320AIC1109
SLAS358 – DECEMBER 2001
electrical characteristics over recommended ranges of supply voltage and free air temperature (unless
otherwise noted) (continued)
transmit idle channel noise and distortion, companded mode (µ-law or A-law) selected, slope filter enabled
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Transmit idle channel noise, psophometrically
weighted
TXPGA gain= 0 dB, micamp 1 gain = 23.5 dB,
micamp 2 gain = 0.0 dB
–86.6
–78 dBm0
p
MIC1N, MIC1P to PCMO at 3 dBm0
MIC1N, MIC1P to PCMO at 0 dBm0
MIC1N, MIC1P to PCMO at –5 dBm0
MIC1N, MIC1P to PCMO at –10 dBm0
MIC1N, MIC1P to PCMO at –20 dBm0
MIC1N, MIC1P to PCMO at –30 dBm0
MIC1N, MIC1P to PCMO at –40 dBm0
MIC1N, MIC1P to PCMO at –45 dBm0
CCITT G.712 (7.1), R2
27
30
33
36
35
26
24
19
49
51
Transmit signal-to-total distortion ratio with 1020-Hz
sine-wave input
dBm0
Intermodulation distortion, 2-tone CCITT method,
composite power level, –13 dBm0
dB
CCITT G.712 (7.2), R2
transmit idle channel noise and distortion, linear mode selected, slope filter bypassed
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TXPGA gain = 0 dB, micamp 1 gain = 23.5 dB,
micamp 2 gain = 0.0 dB
Transmit idle channel noise
–86.6
–78 dBm0
p
MIC1N, MIC1P to PCMO at 3 dBm0
MIC1N, MIC1P to PCMO at 0 dBm0
MIC1N, MIC1P to PCMO at –5 dBm0
MIC1N, MIC1P to PCMO at –10 dBm0
MIC1N, MIC1P to PCMO at –20 dBm0
MIC1N, MIC1P to PCMO at –30 dBm0
MIC1N, MIC1P to PCMO at –40 dBm0
MIC1N, MIC1P to PCMO at –45 dBm0
50
50
60
64
58
50
38
30
50
65
68
70
65
60
50
45
Transmit signal-to-total distortion ratio with 1020-Hz
sine-wave input
dB
transmit idle channel noise and distortion, linear mode selected, slope filter enabled
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TXPGA gain = 0 dB, micamp 1 gain = 23.5 dB,
micamp 2 gain = 0 dB
Transmit idle channel noise
–86.6
–78 dBm0
p
MIC1N, MIC1P to PCMO at 3 dBm0
MIC1N, MIC1P to PCMO at 0 dBm0
MIC1N, MIC1P to PCMO at –5 dBm0
MIC1N, MIC1P to PCMO at –10 dBm0
MIC1N, MIC1P to PCMO at –20 dBm0
MIC1N, MIC1P to PCMO at –30 dBm0
MIC1N, MIC1P to PCMO at –40 dBm0
MIC1N, MIC1P to PCMO at –45 dBm0
40
50
50
64
58
50
38
30
50
65
68
70
65
60
50
45
Transmit signal-to-total distortion ratio with 1020-Hz
sine-wave input
dB
10
www.ti.com
TLV320AIC1109
SLAS358 – DECEMBER 2001
electrical characteristics over recommended ranges of supply voltage and free air temperature (unless
otherwise noted) (continued)
receive gain and dynamic range, EAR1 selected, linear or companded (µ-law or A-law) mode selected (see
Note 9)
PARAMETER
TEST CONDITIONS
110 Ω load RXPGA = -4 dB
32 Ω load RXPGA = -4 dB
0 dBm0 input signal, V
MIN
TYP
4.54
4.54
MAX
UNIT
Overload-signal level (3.0 dB)
Absolute gain error
V
pp
ꢀ10 %
–1
1
dB
DD
PCMIN to EAR1ON, EAR1OP at 3 dBm0 to –40 dBm0
PCMIN to EAR1ON, EAR1OP at –41 dBm0 to –50 dBm0
PCMIN to EAR1ON, EAR1OP at –51 dBm0 to –55 dBm0
–0.5
–1
0.5
1
Gain error with output level relative to gain
at –10 dBm0
dB
–1.2
1.2
NOTE 9: RXPGA = –4 dB for 32 Ω or 110 Ω, RXVOL = 0 dB, 1020 Hz input signal at PCMI, output measured differentially between EAR1ON
and EAR1OP
receive gain and dynamic range, EAR2 selected, linear or companded (µ-law or A-law) mode selected (see
Note 10)
PARAMETER
Receive reference-signal level (0 dB)
Overload-signal level (3 dB)
Absolute gain error
TEST CONDITIONS
0 dBm0 PCM input signal
MIN
TYP
1.1
MAX
UNIT
V
V
pp
1.6
pp
0 dBm0 input signal, V
DD
ꢀ10 %
–1
–0.5
–1
1
0.5
1
dB
PCMIN to EAR2O at 3 dBm0 to –40 dBm0
PCMIN to EAR2O at –41 dBm0 to –50 dBm0
PCMIN to EAR2O at –51 dBm0 to –55 dBm0
Gain error with output level relative to gain at
–10 dBm0
dB
–1.2
1.2
NOTE 10: RXPGA = –1 dB, RXVOL = 0 dB
receive filter transfer, companded mode (µ-law or A-law) or linear mode selected (MCLK = 2.048 MHz) (see
Note 10)
PARAMETER
TEST CONDITIONS
MIN
–0.5
–0.5
–0.5
–1.5
TYP
MAX
0.5
0.5
0.5
0
UNIT
f
f
f
f
f
f
f
f
f
or f
or f
or f
or f
or f
or f
or f
or f
or f
<100 Hz
EAR1
EAR1
EAR1
EAR1
EAR1
EAR1
EAR1
EAR1
EAR1
EAR2
EAR2
EAR2
EAR2
EAR2
EAR2
EAR2
EAR2
EAR2
= 200 Hz
= 300 Hz to 3 kHz
= 3.4 kHz
= 4 kHz
Gain relative to input signal gain at 1020 Hz, internal
high-pass filter disabled
dB
–14
–35
–47
–15
–5
= 4.6 kHz
= 8 kHz
<100 Hz
Gain relative to input signal gain at 1020 Hz, internal
high-pass filter enabled
dB
= 200 Hz
NOTE 10. RXPGA = -1 dB, RXVOL = 0 dB
11
www.ti.com
TLV320AIC1109
SLAS358 – DECEMBER 2001
electrical characteristics over recommended ranges of supply voltage and free air temperature (unless
otherwise noted) (continued)
receive idle channel noise and distortion, EAR1 selected, companded mode (µ-law or A-law) selected (see
Note 9)
PARAMETER
Receive noise, psophometrically weighted
Receive noise, C-message weighted
TEST CONDITIONS
MIN
TYP
–89
36
MAX
UNIT
PCMIN = 11010101 (Α–law)
–86 dBm0
p
PCMIN = 11111111 (µ–law)
50 µV
rms
PCMIN to EAR1ON, EAR1OP at 3 dBm0
PCMIN to EAR1ON, EAR1OP at 0 dBm0
PCMIN to EAR1ON, EAR1OP at –5 dBm0
PCMIN to EAR1ON, EAR1OP at –10 dBm0
PCMIN to EAR1ON, EAR1OP at –20 dBm0
PCMIN to EAR1ON, EAR1OP at –30 dBm0
PCMIN to EAR1ON, EAR1OP at –40 dBm0
PCMIN to EAR1ON, EAR1OP at –45 dBm0
21
25
36
43
40
38
28
23
Receive signal-to-distortion ratio with 1020-Hz
sine-wave input
dB
NOTE 9: RXPGA = -4 dB for 32 Ω or 110 Ω, RXVOL = 0 dB, 1020-Hz input signal at PCMI, output measured differentially between EAR1ON and
EAR1OP.
receive idle channel noise and distortion, EAR1 selected, linear mode selected (see Note 9)
PARAMETER
TEST CONDITIONS
PCMIN = 0000000000000
MIN
TYP
–86
63
MAX
UNIT
Receive noise, (20-Hz to 20-kHz brickwall window)
–83 dBm0
PCMIN to EAR1ON, EAR1OP at 3 dBm0
PCMIN to EAR1ON, EAR1OP at 0 dBm0
PCMIN to EAR1ON, EAR1OP at –5 dBm0
PCMIN to EAR1ON, EAR1OP at –10 dBm0
PCMIN to EAR1ON, EAR1OP at –20 dBm0
PCMIN to EAR1ON, EAR1OP at –30 dBm0
PCMIN to EAR1ON, EAR1OP at –40 dBm0
PCMIN to EAR1ON, EAR1OP at –45 dBm0
CCITT G.712 (7.1), R2
50
53
53
50
48
46
36
30
50
54
65
63
60
Receive signal-to-distortion ratio with 1020 Hz
sine-wave input
dB
58
56
52
50
Intermodulation distortion, 2-tone CCITT method,
composite power level, –13 dBm0
dB
CCITT G.712 (7.2), R2
NOTE 9: RXPGA = –4 dB for 32 Ω or 110 Ω, RXVOL = 0 dB, 1020-Hz input signal at PCMI, output measured differentially between EAR1ON
and EAR1OP.
receive idle channel noise and distortio EAR2 selected, companded mode (µ-law or A-law) selected
(see Note 10)
PARAMETER
Receive noise, psophometrically weighted
Receive noise, C-message weighted
TEST CONDITIONS
PCMIN = 11010101 (Α–law)
PCMIN = 11111111 (µ–law)
MIN
TYP
–81
36
MAX
UNIT
–78 dBmo
p
50 µV
rms
PCMIN to EAR2O at 3 dBm0
PCMIN to EAR2O at 0 dBm0
PCMIN to EAR2O at –5 dBm0
PCMIN to EAR2O at –10 dBm0
PCMIN to EAR2O at –20 dBm0
PCMIN to EAR2O at –30 dBm0
PCMIN to EAR2O at –40 dBm0
PCMIN to EAR2O at –45 dBm0
21
25
36
43
40
38
28
23
Receive signal-to-distortion ratio with 1020-Hz
sine-wave input
dB
NOTE 10. RXPGA = –1 dB, RXVOL = 0 dB
12
www.ti.com
TLV320AIC1109
SLAS358 – DECEMBER 2001
electrical characteristics over recommended ranges of supply voltage and free air temperature (unless
otherwise noted) (continued)
receive idle channel noise and distortion, EAR2 selected, linear mode selected (see Note 10)
PARAMETER
TEST CONDITIONS
PCMIN = 0000000000000
MIN
TYP
–86
60
MAX
UNIT
Receive noise, (20-Hz to 20-kHz brickwall window)
–83
dBm0
PCMIN to EAR2O at 3 dBm0
PCMIN to EAR2O at 0 dBm0
PCMIN to EAR2O at –5 dBm0
PCMIN to EAR2O at –10 dBm0
PCMIN to EAR2O at –20 dBm0
PCMIN to EAR2O at –30 dBm0
PCMIN to EAR2O at –40 dBm0
PCMIN to EAR2O at –45 dBm0
CCITT G.712 (7.1), R2
45
60
58
55
53
52
50
45
50
54
65
62
Receive signal-to-noise + distortion ratio with 1020-Hz sine-wave
input
60
dB
dB
60
58
57
52
Intermodulation distortion, 2-tone CCITT method, composite
power level, –13 dBm0
CCITT G.712 (7.2), R2
NOTE 10: RXPGA = –1 dB, RXVOL = 0 dB
power supply rejection and crosstalk attenuation
PARAMETER
TEST CONDITIONS
MIC1N, MIC1P =0 V,
= 3 V + 100 mV
MIN
TYP
MAX
UNIT
Supply voltage rejection, transmit channel
–70
–45
dB
V
DD
, f = 0 to 50 kHz
, f = 0 to 50 kHz
peak to peak
dc
peak to peak
Supply voltage rejection, receive channel, PCM code = positive zero,
EAR1 selected (differential)
–70
–45
dB
dB
dB
V
DD
= 3 V + 100 mV
dc
Crosstalk attenuation, transmit-to-receive
(differential)
MIC1N, MIC1P = 0 dB, f = 300 to 3400 Hz measured
differentially between EAR1ON and EAR1OP
70
70
PCMIN = 0 dBm0, f = 300 to 3400 Hz measured at
PCMO, EAR1 amplifier
Crosstalk attenuation, receive-to-transmit
switching characteristics
clock timing requirements
PARAMETER
MIN
NOM
MAX
UNIT
ns
t
f
Transition time, MCLK
MCLK frequency
MCLK jitter
10
t
2.048
MHz
mclk
37%
256
512
68%
Number of PCMCLK clock cycles per PCMSYN frame
PCMCLK clock period
256
156
t
488
ns
c(PCMCLK)
Duty cycle, PCMCLK
45%
50%
transmit timing requirements (see Figure 5)
PARAMETER
MIN
20
MAX
UNIT
t
t
Setup time, PCMSYN high before falling edge of PCMCLK
Hold time, PCMSYN high after falling edge of PCMCLK
t
t
–20
–20
su(PCMSYN)
c(PCMCLK)
ns
20
h(PCMSYN)
c(PCMCLK)
13
www.ti.com
TLV320AIC1109
SLAS358 – DECEMBER 2001
switching characteristics (continued)
receive timing requirements (see Figure 6)
PARAMETER
MIN
20
MAX
UNIT
ns
t
t
t
t
Setup time, PCMSYN high before falling edge of PCMCLK
Hold time, PCMSYN high after falling edge of PCMCLK
Setup time, PCMI high or low before falling edge of PCMCLK
Hold time, PCMI high or low after falling edge of PCMCLK
t
t
–20
–20
su(PCSYN)
h(PCSYN)
su(PCMI)
h(PCMI)
c(PCMCLK)
20
ns
c(PCMCLK)
20
ns
20
ns
propagation delay times, C
= 10 pF (see Figure 5)
L(max)
PARAMETER
MIN
MAX
35
UNIT
ns
t
t
t
From PCMCLK bit 1 high to PCMO bit 1 valid
From PCMCLK high to PCMO valid, bit 2 to n
From PCMCLK bit n low to PCMO bit n Hi-Z
pd1
pd2
pd3
35
ns
30
ns
2
I C bus timing requirements (see Figure 7)
PARAMETER
MIN
MAX
UNIT
kHz
ns
SCL
Clock frequency
400
t
t
t
t
t
t
t
t
t
t
Clock high time
600
HIGH
LOW
r
Clock low time
1300
ns
SDA and SCL rise time
SDA and SCL fall time
300
300
ns
ns
f
Hold time (repeated) START condition. After this period the first clock pulse is generated.
600
600
0
ns
h(STA)
su(STA)
h(DAT)
su(DAT)
su(STO)
BUF
Setup time for repeated START condition
Data input hold time
ns
ns
Data input setup time
100
600
1300
ns
STOP condition setup time
Bus free time
ns
ns
DTMF generator characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DTMF high to low tone relative amplitude
(preemphasis)
1.5
2
2.5
dB
Tone frequency accuracy
Harmonic distortion
–1.5
1.5
%
Measured from lower tone group to highest parasitic
–20
dB
MICBIAS characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Load impedance (bias mode)
5
kΩ
14
www.ti.com
TLV320AIC1109
SLAS358 – DECEMBER 2001
PARAMETER MEASUREMENT INFORMATION
SCL
SDA
Start
A6
A5
A4
A0 R/W ACK
R7
R6
R5
R0 ACK
0
D7
D6
D5
D0 ACK
0
0
0
Stop
Slave Address
Register Address
Data
NOTE:SLAVE=VoiceCodec
2
Figure 1. I C-Bus Write to Voice Codec
SCL
A6
A5
A0 R/W ACK
R7 R6
R0 ACK
A6
A0 R/W ACK D7 D6
D0 ACK
SDA
Start
0
0
1
0
Stop
Slave Drives
The Data
Master
Drives
Slave Address
Register Address
Slave Address
Repeated
Start
ACK and Stop
NOTE: SLAVE = Voice Codec
2
Figure 2. I C Read From Voice Codec: Protocol A
SCL
SDA
R/W ACK
ACK
D0
A6 A5
A0 R/W ACK
R7 R6
R0 ACK
A6 A5
A0
D7
0
0
Start
Stop
Stop Start
Slave Drives
The Data
Master
Drives
Slave Address
Register Address
Slave Address
ACK and Stop
NOTE: SLAVE = Voice Codec
2
Figure 3. I C Read From Voice Codec: Protocol B
15
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TLV320AIC1109
SLAS358 – DECEMBER 2001
PRINCIPLES OF OPERATION
power-on initialization
An external reset with a minimum pulse width of 500 ns must be applied to the active low RESET terminal to
assure reset upon power on. All registers are set with default values upon external reset initialization.
The desired selection for all programmable functions can be initialized prior to a power-up command using the
2
I C interface.
Table 1. Power-Up and Power-Down Procedures (V
= 2.7 V, Earphone Amplifier Unloaded)
DD
MAXIMUM POWER
CONSUMPTION
DEVICE STATUS
Power up
PROCEDURE
Set bit 1 = 1 in power control register, EAR1 enabled
Set bit 1 = 0 in power control register, EAR2 enabled
Set bit 7 = 1 in TXPGA control register and bit 0 = 0
Set bit 7 = 0 in TXPGA control register and bit 0 = 0
16.2 mW
14.6 mW
1.35 µW
67.5 µW
Power down
In addition to resetting the power-down bit in the power control register, loss of MCLK (no transition detected)
automatically enters the device into a power-down state with PCMO in the high impedance state. If during a
pulse code modulation (PCM) data transmit cycle an asynchronous power down occurs, the PCM interface
remains powered up until the PCM data is completely transferred.
An additional power-down mode overrides the MCLK detection function. This allows the device to enter the
power-down state without regard to MCLK. Setting bit 7 of the TXPGA sidetone register to logic high enables
this function.
conversion laws
The device can be programmed either for a 15-bit linear or 8-bit (µ-law or A-law) companding mode. The
companding operation approximates the CCITT G.711 recommendation. The linear mode operation uses a
15-bit twos-complement format.
transmit operation
microphone input
The microphone input stage is a low noise differential amplifier that provides a preamplifier gain of 23.5 dB. A
microphone can be capacitively connected to the MIC1N and MIC1P inputs, while the MIC2N and MIC2P inputs
can be used to capacitively connect a second microphone or an auxiliary audio circuit.
16
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TLV320AIC1109
SLAS358 – DECEMBER 2001
PRINCIPLES OF OPERATION
transmit operation (continued)
_
MBIAS
+
V
ref
R
R
mic
510 kΩ
C MIC1N
i
34 kΩ
34 kΩ
_
+
M
I
C
C MIC1P
i
510 kΩ
mic
Figure 4. Typical Microphone Interface
microphone mute function
Transmit channel muting provides 80-dB attenuation of input microphone signal. The MICMUTE function can
2
be selected by setting bit 6 of the power control register through the I C interface.
transmit channel gain control
The values in the transmit PGA control registers control control the gain in the transmit path. The total TX
channel gain can vary from 35.5 dB to 13.5 dB. The default total TX channel gain is 23.5 dB.
Table 2. Transmit Gain Control
GAIN
MODE
BIT NAME
TP2 TP1
MIC AMP1 MIC AMP2
TX PGA
TOTAL TX GAIN
TP3
0
TP0
0
GAIN
23.5
23.5
23.5
23.5
23.5
23.5
23.5
23.5
23.5
23.5
23.5
23.5
GAIN
12
12
12
12
12
12
0
GAIN
0
MIN
35.3
33.3
31.3
29.3
27.3
25.3
23.3
21.3
19.3
17.3
15.3
13.3
TYP
35.5
33.5
31.5
29.5
27.5
25.5
23.5
21.5
19.5
17.5
17.5
13.5
MAX
35.7
33.7
31.7
29.7
27.7
25.7
23.7
21.7
19.7
17.7
17.7
13.7
UNIT
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
Extended
Extended
Extended
Extended
Extended
Extended
Normal
0
1
–2
–4
–6
–8
–10
0
0
0
0
1
0
0
0
1
1
0
1
1
0
–2
–4
–6
–8
–10
Normal
1
0
0
Normal
1
1
0
Normal
1
0
0
Normal
1
1
0
Normal
17
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TLV320AIC1109
SLAS358 – DECEMBER 2001
PRINCIPLES OF OPERATION
receive operation
receive channel gain control
The values in the receive PGA control registers control the gain in the receive path. PGA gain is set from –6 dB
2
to 6 dB in 1 dB steps through the I C interface. The default receive channel gain is –1 dB.
Table 3. Receive PGA Gain Control
BIT NAME
RP2
RELATIVE GAIN
RP3
0
RP1
0
RP0
0
MIN
5.8
TYP
6
MAX
6.2
UNIT
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
4.8
5
5.2
0
1
0
3.8
4
4.2
0
1
1
2.8
3
3.2
0
0
0
1.8
2
2.2
0
0
1
0.8
1
1.2
0
1
0
–0.2
–1.2
–2.2
–3.2
–4.2
–5.2
–6.2
0
0.2
0
1
1
–1
–2
–3
–4
–5
–6
–0.8
–1.8
–2.8
–3.8
–4.8
–5.8
1
0
0
1
0
1
1
1
0
1
1
1
1
0
0
sidetone gain control
The values in the sidetone PGA control registers control the sidetone gain. Sidetone gain is set from –12 dB
2
to –24 dB in 2-dB steps through the I C interface. Sidetone can be muted by setting bit 7 of the power control
register. The default sidetone gain is –12 dB.
Table 4. Sidetone Gain Control
BIT NAME
RELATIVE GAIN
ST2
0
ST1
0
ST0
0
MIN
TYP
–12
–14
–16
–18
–20
–22
–24
MAX
UNIT
dB
–12.2
–14.2
–16.2
–18.2
–20.2
–22.2
–24.2
–11.8
–13.8
–15.8
–17.8
–19.8
–21.8
–23.8
0
0
1
dB
0
1
0
dB
0
1
1
dB
1
0
0
dB
1
0
1
dB
1
1
0
dB
18
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TLV320AIC1109
SLAS358 – DECEMBER 2001
PRINCIPLES OF OPERATION
receive operation (continued)
receive volume control
The values in the volume control PGA control registers provide volume control into the earphone. Volume
2
control gain is set from 0 dB to –18 dB in 2-dB steps through the I C interface. The default RX volume control
gain is 0 dB.
Table 5. RX Volume Control
BIT NAME
RV1
RELATIVE GAIN
RV3
0
RV2
0
RV0
0
MIN
–0.2
TYP
0
MAX
0.2
UNIT
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
0
0
1
1
0
0
1
1
0
0
0
0
1
–2.2
–2
–1.8
0
0
0
–4.2
–4
–3.8
–5.8
–7.8
0
0
1
–6.2
–6
0
1
0
–8.2
–8
0
1
1
–10.2
–12.2
–14.2
–16.2
–18.2
–10
–12
–14
–16
–18
–9.8
–11.8
–13.8
–15.8
–17.8
0
1
0
0
1
1
1
0
0
1
0
1
earphone amplifier
Theanalogsignalcanberoutedtoeitheroneoftwoearphoneamplifiers:onewithadifferentialoutput(EAR1ON
and EAR1OP) capable of driving a 32-Ω load, or one with a single-ended output (EAR2O) capable of driving
a 32-Ω load.
earphone mute function
2
Muting can be selected by setting bit 3 of the power control register through the I C interface.
receive PCM data format
D
D
Companded mode: 8 bits are received, the most significant (MSB) first.
Linear mode: 15 bits are received, MSB first.
19
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TLV320AIC1109
SLAS358 – DECEMBER 2001
PRINCIPLES OF OPERATION
receive operation (continued)
Table 6. Receive-Data Bit Definitions
BIT NO.
COMPANDED
MODE
LINEAR
MODE
1
2
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
–
LD14
LD13
LD12
LD11
LD10
LD9
LD8
LD7
LD6
LD5
LD4
LD3
LD2
LD1
LD0
––
3
4
5
6
7
8
9
10
11
12
13
14
15
16
–
–
–
–
–
–
–
Transmit channel gain control bits always follow the PCM data in time:
CD7–CD0 = data word in companded mode
LD14–LD0 = data word in linear mode
DTMF generator operation and interface
The dual-tone multifrequency generator (DTMF) circuit generates the summed DTMF tones for push button
dialing and provides the PDM output for the BUZZCON user-alert tone. The integer value is determined by the
following formula, round tone [Freq (Hz)/7.8125 (Hz)]. The integer value is loaded into either one of two 8-bit
registers, high-tone register (04) or low-tone register (05). The tone output is 2 dB higher when applied to the
high-tone register (04). When generating DTMF tones, the high-frequency value must be applied to the
high-tone register (04) and the low DTMF value to the low-tone register.
Table 7. Typical DTMF and Single Tone Control
INTEGER
VALUE
TONE
FUNCTION
DT7
DT6
DT5
DT4
DT3
DT2
DT1
DT0
TONE/HZ
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
0
1
1
1
0
1
1
0
1
0
0
1
1
0
1
1
1
0
1
1
1
1
1
0
0
0
1
0
0
0
1
0
0
1
0
0
1
1
0
0
1
1
1
0
1
1
1
1
89
DTMF Low
DTMF Low
DTMF Low
DTMF Low
DTMF HIgh
DTMF HIgh
DTMF HIgh
DTMF HIgh
697
770
99
109
120
155
171
189
209
852
941
1209
1336
1477
1633
20
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TLV320AIC1109
SLAS358 – DECEMBER 2001
PRINCIPLES OF OPERATION
DTMF generator operation and interface (continued)
Tones from the DTMF generator block are present at all outputs and are controlled by enabling or disabling the
individual output ports. The values that determine the tone frequency are loaded into the tone registers (high
and low) as two separate values.
The values loaded into the tone registers initiate an iterative table look-up function, placing a 6-bit or 7-bit in 2s
complement value into the the tone registers. There is a 2 dB difference in the resulting output of the two
registers, the high tone register having the greater result.
buzzer logic section
The single-ended output BUZZCON is a PDM signal intended to drive a buzzer through an external driver
transistor. The PDM begins as a selected DTMF tones, generated and passed through the receive D/A channel,
and fed back to the transmit channel analog modulator, where a PDM signal is generated and routed to the
BUZZCON output.
support section
The clock generator and control circuit use the master clock input (MCLK) to generate internal clocks to drive
internal counters, filters, and convertors. Register control data is written into and read back from the PCM codec
registers via the control interface.
2
I C–bus protocols
2
The PCM codec serial interface is designed to be I C-bus compatible and operates in the slave mode. This
interface consists of the following terminals:
2
SCL:
SDA:
I C-bus serial clock — This input synchronizes the control data transfer from and to the codec.
2
I C-bus serial address/data input/output — This is a bidirectional terminal that transfers register
control addresses and data into and out of the codec. It is an open drain terminal and therefore
requires a pullup resistor to V
(typical 10 kΩ for 100 kHz).
CC
TLV320AIC1109 has a fixed device select address of {E2}HEX for write mode and {E3}HEX for read mode.
For normal data transfer, SDA is allowed to change only when SCL is low. Changes when SCL is high are
reserved for indicating the start and stop conditions.
Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain
stable whenever the clock line is at high. Changes in the data line while the clock line is at high are interpreted
as a start or stop condition.
2
Table 8. I C-Bus Conditions
CONDITION
STATUS
DESCRIPTION
Both data and clock lines remain at high
A
Bus not busy
Ahigh-to-lowtransitionoftheSDAlinewhiletheclock(SCL)ishighdeterminesastartcondition.
All commands must proceed from a start condition.
B
C
D
Start data transfer
Stop data transfer
Data valid
Alow-to-hightransitionoftheSDAlinewhiletheclock(SCL)ishighdeterminesastopcondition.
All operations must end with a stop condition.
Thestateofthedatalinerepresentsvaliddatawhen, afterastartcondition, thedatalineisstable
for the duration of the high period of the clock signal.
21
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TLV320AIC1109
SLAS358 – DECEMBER 2001
PRINCIPLES OF OPERATION
2
I C bus protocols
The data on the line must be changed during the low period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data
bytes, transferred between the start and stop conditions, is determined by the master device (microprocessor).
When addressed, the PCM codec generates an acknowledge after the reception of each byte. The master
device must generate an extra clock pulse that is associated with this acknowledge bit.
ThePCMcodecmustpulldowntheSDAlineduringtheacknowledgeclockpulsesothattheSDAlineisatstable
low state during the high period of the acknowledge related clock pulse. Setup and hold times must be taken
intoaccount. Duringreadoperations, themasterdevicemustsignalanendofdatatotheslavebynotgenerating
an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave (PCM codec) must
leave the data line high to enable the master device to generate the stop condition.
clock frequencies and sample rates
A fixed PCMSYN rate of 8 kHz determines the sampling rate.
register map addressing
REG
07
06
05
04
03
02
01
00
EAROUT
Sel
Power control
Mode control
00
Sidetone En
TXEn
RXEn
MICSEL
BIASEn
RXEn
PWRUP
RXFLTR
En
TXFLTR
En
TXSLOPE
En
01
Comp Sel
TMEn
PCMLB
Comp En
BUZZEn
TXPGA
RXPGA
02
03
PD0
RP3
TP3
RP2
TP2
RP1
TP1
RP0
TP0
RV3
ST2
RV2
ST1
RV1
ST0
RV0
HIFREQ
Sel4
HIFREQ
Sel7
HIFREQ
Sel6
HIFREQ
Sel5
HIFREQ
Sel3
HIFREQ
Sel2
HIFREQ
Sel1
HIFREQ
Sel0
High DTMF
Low DTMF
04
05
LOFREQ
Sel4
LOFREQ
Sel7
LOFREQ
Sel6
LOFREQ
Sel5
LOFREQ
Sel3
LOFREQ
Sel2
LOFREQ
Sel1
LOFREQ
Sel0
register power-up defaults
REG
00
07
06
1
05
1
04
1
03
0
02
1
01
1
00
0
†
‡
Power control
Power control
Mode control
TXPGA
1
1
0
0
0
0
0
00
0
0
1
1
0
1
1
01
0
0
0
0
0
1
0
02
1
0
0
0
0
0
0
RXPGA
03
1
1
1
0
0
0
0
High DTMF
Low DTMF
04
0
0
0
0
0
0
0
05
0
0
0
0
0
0
0
†
‡
Value when PWRUPSEL = 0
Value when PWRUPSEL = 1
22
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TLV320AIC1109
SLAS358 – DECEMBER 2001
PRINCIPLES OF OPERATION
register map
Table 9. Power Control Register: Address {00} HEX
BIT NUMBER
DEFINITIONS
7
1
6
1
5
1
4
1
3
0
2
1
1
1
0
0
Default setting PWRUPSEL = 0
Default setting PWRUPSEL = 1
Reference system, power-down
Reference system, power-up
EAR AMP1 selected, EAR AMP2 power down
EAR AMP2 selected, EAR AMP1 power down
Receive channel enabled
Receive channel muted
1
0
0
1
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
0
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
1
0
1
X
X
X
X
0
0
X
X
X
X
X
X
X
X
X
X
1
1
1
Receive channel, power down
MIC1 selected
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
MIC2 selected
X
X
X
X
X
Transmit channel enabled
Transmit channel muted
1
1
1
Transmit channel power down
Sidetone enabled
X
X
X
X
1
Sidetone muted
Table 10. Mode Control Register: Address {01} HEX
BIT NUMBER
DEFINITIONS
7
0
6
0
5
0
4
0
3
0
2
0
1
1
0
0
Default setting
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
0
X
X
X
X
0
0
0
TX channel high-pass filter enabled and slope filter enabled
0
1
TX channel high-pass filter enabled and slope filter disabled
TX channel high-pass filter disabled and slope filter enabled
TX channel high-pass filter disabled and slope filter disabled
RX channel high-pass filter disabled (low pass only)
RX channel high-pass filter enabled
BUZZCON disabled
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
1
BUZZCON enabled
X
X
X
X
X
X
X
Linear mode selected
1
A-law companding mode selected
µ-law companding mode selected
TX and RX channels normal mode
PCM loopback mode
0
1
X
X
X
X
X
X
X
X
1
X
X
Tone mode disabled
1
Tone mode enabled
23
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TLV320AIC1109
SLAS358 – DECEMBER 2001
PRINCIPLES OF OPERATION
register map (continued)
Transmit PGA and sidetone control register: Address {02}HEX
Bit definitions :
7
PDO
0
6
TP3
1
5
TP2
0
4
TP1
0
3
TP0
0
2
ST2
0
1
ST1
0
0
ST0
0
DEFINITION
See Table 2 and Table 4
Default setting
Receive volume control register: Address {03}HEX
Bit definitions :
7
RP3
0
6
RP2
1
5
RP1
1
4
RP0
1
3
RV3
0
2
RV2
0
1
RV1
0
0
RV0
0
DEFINITION
See Table 3 and Table 5
Default setting
High tone selection control register: Address {04}HEX
Bit definitions :
7
X
0
6
X
0
5
X
0
4
X
0
3
X
0
2
X
0
1
X
0
0
X
0
DEFINITION
DTMF (see Table 7)
Default setting
Low tone selection control register: Address {05}HEX
Bit definitions :
7
X
0
6
X
0
5
X
0
4
X
0
3
X
0
2
X
0
1
X
0
0
X
0
DEFINITION
DTMF (see Table 7)
Default setting
24
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TLV320AIC1109
SLAS358 – DECEMBER 2001
PRINCIPLES OF OPERATION
register map (continued)
Transmit Time Slot
0
1
2
3
4
N–2
N–1
N
N+1
80%
80%
PCMCLK
20%
20%
t
su(PCMSYN)
t
h(PCMSYN)
PCMSYN
See Note B
t
See Note A
PCMO
pd2
t
pd3
1
2
3
4
N–2
N–1
N
See Note C
t
pd1
t
See Note D
su(PCMO)
NOTES: A. This window is allowed for PCMSYN high.
B. This window is allowed for PCMSYN low (t
C. Transitions are measured at 50%.
max determined by data collision considerations).
h(PCMSYN)
D. Bit 1 = MSB, Bit N = LSB
Figure 5. Transmit Timing Diagram
Receive Time Slot
0
1
2
3
4
N –2
N –1
N
N +1
80%
80%
PCMCLK
t
20%
20%
t
su(PCMSYN)
h(PCMSYN)
PCMSYN
See Note B
See Note D
2
See Note A
t
h(PCMI)
1
3
4
N –2
N –1
N
PCMI
See Note C
t
su(PCMI)
NOTES: A. This window is allowed for PCMSYN high.
B. This window is allowed for PCMSYN low.
C. Transitions are measured at 50%.
D. Bit 1 = MSB, Bit N = LSB
Figure 6. Receive Timing Diagram
SDA
t
BUF
t
t
t
r
h(STA)
t
f
LOW
SCL
t
t
h(STA)
HIGH
t
t
su(STO)
su(STA)
t
t
h(DAT)
su(DAT)
STO
STA
STA
STO
2
Figure 7. I C-Bus Timing Diagram
25
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TLV320AIC1109
SLAS358 – DECEMBER 2001
MECHANICAL DATA
PBS (S-PQFP-G32)
PLASTIC QUAD FLATPACK
0,23
M
0,50
0,08
0,17
17
24
25
32
16
9
0,13 NOM
1
8
3,50 TYP
Gage Plane
5,05
SQ
4,95
0,25
7,10
SQ
0,10 MIN
6,90
0°–ā7°
0,70
0,40
1,05
0,95
Seating Plane
0,08
1,20 MAX
4087735/A 11/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
26
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Copyright 2001, Texas Instruments Incorporated
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