TLV320AIC33IZXH [TI]
具有 10 个输入、7 个输出、耳机/扬声器放大器和增强数字效果的低功耗立体声编解码器 | ZXH | 80 | -40 to 85;
| 型号： | TLV320AIC33IZXH |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 10 个输入、7 个输出、耳机/扬声器放大器和增强数字效果的低功耗立体声编解码器 | ZXH | 80 | -40 to 85 放大器 消费电路 商用集成电路 编解码器 |
| 文件： | 总13页 (文件大小：485K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV320AIC33
SLAS480 -- MAY 24, 2005
PRELIMINARY INFORMATION REV.17
Low Power Stereo Audio Codec for Portable Audio/Telephony
FEATURES
DESCRIPTION
• STEREO AUDIO DAC
The TLV320AIC33 is a low power stereo audio codec with
stereo headphone amplifier, as well as multiple inputs and
outputs programmable in single-ended or fully-differential
configurations. Extensive register-based power control is
included, enabling stereo 48-kHz DAC playback as low as
15mW(TBD) from a 3.3V analog supply, making it ideal for
portable battery-powered audio and telephony applications.
•
•
•
•
103dB-A SIGNAL-TO-NOISE RATIO
16/20/24/32-BIT DATA
SUPPORTS RATES FROM 8-kHz to 96-kHz
3D/BASS/TREBLE/EQ/DE-EMPHASIS EFFECTS
• STEREO AUDIO ADC
•
•
92dB-A SIGNAL-TO-NOISE RATIO
SUPPORTS RATES FROM 8-kHz TO 96-kHz
The record path of the TLV320AIC33 contains integrated
microphone bias, digitally controlled stereo microphone pre-
amp, and automatic gain control (AGC), with mix/mux
capability among the multiple analog inputs. The playback
path includes mix/mux capability from the stereo DAC and
selected inputs, through programmable volume controls, to
the various outputs.
• TEN AUDIO INPUT PINS
•
PROGRAMMABLE IN SINGLE-ENDED OR FULLY
DIFFERENTIAL CONFIGURATIONS
TRI-STATE CAPABILITY FOR FLOATING INPUT
CONFIGURATIONS
•
• SEVEN AUDIO OUTPUT DRIVERS
•
STEREO 8-OHM 325mW/CHANNEL SPEAKER
DRIVE CAPABILITY
The TLV320AIC33 contains four high-power output drivers as
well as three fully differential output drivers. The high-power
output drivers are capable of driving a variety of load
configurations, including up to four channels of single-ended
16-Ω headphones using ac-coupling capacitors, or stereo 16-
Ω headphones in a cap-less output configuration. In addition,
pairs of drivers can be used to drive 8-Ω speakers in a BTL
configuration at 325mW per channel.
•
STEREO FULLY-DIFFERENTIAL OR SINGLE-
ENDED HEADPHONE DRIVERS
•
•
FULLY DIFFERENTIAL STEREO LINE OUTPUTS
FULLY DIFFERENTIAL MONO OUTPUT
• LOW POWER: 14mW STEREO 48-kHz PLAYBACK
WITH 3.3V ANALOG SUPPLY
• PROGRAMMABLE INPUT/OUTPUT ANALOG GAINS
• AUTOMATIC GAIN CONTROL (AGC) FOR RECORD
• PROGRAMMABLE MICROPHONE BIAS LEVEL
The stereo audio DAC supports sampling rates from 8-kHz to
96-kHz and includes programmable digital filtering in the DAC
path for 3D, bass, treble, midrange effects, speaker
equalization, and de-emphasis for 32-kHz, 44.1-kHz, and 48-
kHz rates. The stereo audio ADC supports sampling rates
from 8-kHz to 96-kHz and is preceded by programmable gain
amplifiers providing up to +59.5-dB analog gain for low-level
microphone inputs.
• PROGRAMMABLE PLL FOR FLEXIBLE CLOCK
GENERATION
• CONTROL BUS SELECTABLE SPI OR I2C
• AUDIO SERIAL DATA BUS SUPPORTS I2S,
LEFT/RIGHT-JUSTIFIED, DSP, AND TDM MODES
• ALTERNATE SERIAL PCM/I2S DATA BUS FOR EASY
CONNECTION TO BLUETOOTH MODULE
The serial control bus supports SPI or I2C protocols, while the
serial audio data bus is programmable for I2S, left/right-
justified, DSP, or TDM modes. A highly programmable PLL is
included for flexible clock generation and support for all
standard audio rates from a wide range of available MCLKs,
varying from 2-MHz to 50-MHz, with special attention paid to
the most popular cases of 12-MHz, 13-MHz, 16-MHz, 19.2-
MHz, and 19.68-MHz system clocks.
• DIGITAL MICROPHONE INPUT SUPPORT
• EXTENSIVE MODULAR POWER CONTROL
• POWER SUPPLIES:
•
•
•
ANALOG: 2.7V – 3.6V
DIGITAL CORE: 1.525V – 1.95V
DIGITAL I/O: 1.1V – 3.6V
The TLV320AIC33 operates from an analog supply of
2.7V – 3.6V, a digital core supply of 1.525V – 1.95V, and a
digital I/O supply of 1.1V – 3.6V. The device is available in
5x5mm 80-ball u*jr BGA and 7x7mm 48-lead QFN.
• PACKAGES: 5X5MM 80-BGA
7X7MM 48-QFN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appear at the end of this data sheet.
Copyright © 2005, Texas Instruments Incorporated
The product described herein is a prototype product.
TI makes no warranty, either expressed, implied, or
statutory, including any implied warranty or
merchantability or fitness for a specific purpose, as to
this product.
The information contined here concerns products in the
formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change
or discontinue these products without notice.
www.ti.com
1
TLV320AIC33
MAY 24, 2005
PRELIMINARY INFORMATION REV.17
SIMPLIFIED BLOCK DIAGRAM
Audio Serial
Bus
Voltage Supplies
+
HPL+
MIC2/LINE2L+
MIC2/LINE2L-
MIC3/LINE3L
HPL-/HPLCOM
VCM
VCM
+
PGA
0/+59.5dB
0.5dB
MIC1/LINE1L+
MIC1/LINE1L-
Volume Ctl
& Effects
DAC
L
ADC
ADC
+
+
steps
+
PGA
0/+59.5dB
0.5dB
HPR-/HPRCOM/
SPKFC
MIC1/LINE1R+
MIC1/LINE1R-
Volume Ctl
& Effects
DAC
R
steps
MIC3/LINE3R
HPR+
+
MIC2/LINE2R+
MIC2/LINE2R-
+
LINE_OUT_L+
Bias/
Reference
Audio Clock
Generation
SPI / I2C Serial Control
Bus
LINE_OUT_L-
+
LINE_OUT_R+
LINE_OUT_R-
MONO_OUT+
+
MONO_OUT-
Figure 1. Simplified codec block diagram
Copyright © 2004, Texas Instruments Incorporated
The product described herein is a prototype product.
TI makes no warranty, either expressed, implied, or
statutory, including any implied warranty or
merchantability or fitness for a specific purpose, as to
this product.
The information contined here concerns products in the
formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change
or discontinue these products without notice.
www.ti.com
2
TLV320AIC33
MAY 24, 2005
PRELIMINARY INFORMATION REV.17
PACKAGE/ORDERING INFORMATION
OPERATING
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE
TLV320AIC33IZQE
Trays??, xx
BGA-80
QFN-48
ZQE
RGZ
TLV320AIC33IZQER Tape and Reel, 2000
TLV320AIC33IRGZ Rails, 52
TLV320AIC33IRGZR Tape and Reel, 2000
TLV320AIC33
-40C to 85C
PIN ASSIGNMENTS
12
1
J
13
48
H
G
F
E
D
C
B
A
37
24
1 2 3 4 5 6 7 8 9
25
36
48-lead QFN Package (Bottom view)
5x5mm 80-Ball BGA Package (Bottom View)
(Not to scale)
(Note: Shaded balls on BGA package are not connected to the die, but are electrically connected to
each other.)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appear at the end of this data sheet.
Copyright © 2004, Texas Instruments Incorporated
The product described herein is a prototype product.
TI makes no warranty, either expressed, implied, or
statutory, including any implied warranty or
merchantability or fitness for a specific purpose, as to
this product.
The information contined here concerns products in the
formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change
or discontinue these products without notice.
www.ti.com
3
TLV320AIC33
MAY 24, 2005
PRELIMINARY INFORMATION REV.17
PIN DESCRIPTION
BGA
BALL
A2
QFN PIN
NUMBER
13
PIN NAME
MICBIAS
DESCRIPTION
Microphone Bias Voltage Output
A1
14
MIC3R
MIC3 Input (Right or Multifunction)
C2,D2
B1,C1
15
16,17
AVSS_ADC
VDDA1
Analog ADC Ground Supply, 0V
ADC Analog and Output Driver Voltage Supply, 2.7V – 3.6V
D1
E1
E2,F2
18
19
20,21
HPLOUT
HPLCOM
DRVSS
High Power Output Driver (Left Plus)
High Power Output Driver (Left Minus or Multifunctional)
Analog Output Driver Ground Supply, 0V
F1
G1
H1
J1
G2,H2
J2
J3
J4
J5
J6
22
23
24
25
26
27
28
29
30
31
32
33
HPRCOM
HPROUT
VDDA1
High Power Output Driver (Right Minus or Multifunctional)
High Power Output Driver (Right Plus)
ADC Analog and Output Driver Voltage Supply, 2.7V – 3.6V
Analog DAC Voltage Supply, 2.7V – 3.6V
Analog DAC Ground Supply, 0V
Mono Line Output (Plus)
Mono Line Output (Minus)
Left Line Output (Plus)
Left Line Output (Minus)
AVDDA2
AVSS_DAC
MONO_LOP
MONO_LOM
LEFT_LOP
LEFT_LOM
RIGHT_LOP
RIGHT_LOM
/RESET
Right Line Output (Plus)
Right Line Output (Minus)
Reset
J7
H8
General Purpose Input/Output #2 (Input/Output) / Digital Microphone
Data Input / PLL Clock Input / Audio Serial Data Bus Bit Clock
Input/Output
J8
34
GPIO2
General Purpose Input/Output #1 (Input/Output) / PLL/Clock Mux Output
/ Short Circuit Interrupt / AGC Noise Flag / Digital Microphone Clock /
Audio Serial Data Bus Word Clock Input/Output
Digital Core Voltage Supply, 1.525V – 1.95V
Master Clock Input
Audio Serial Data Bus Bit Clock (Input/Output)
Audio Serial Data Bus Word Clock (Input/Output)
Audio Serial Data Bus Data Input (Input)
Audio Serial Data Bus Data Output (Output)
Digital Core / I/O Ground Supply, 0V
J9
H9
G8
G9
F9
E9
F8
D9
E8
C9
B8
B9
A8
35
36
37
38
39
40
41
42
43
44
45
46
47
GPIO1
DVDD
MCLK
BCLK
WCLK
DIN
DOUT
DVSS
SELECT
IOVDD
MFP0
MFP1
MFP2
Select Pin (SPI vs I2C Control Mode)
I/O Voltage Supply, 1.1V – 3.6V
Multifunction pin #0 - SPI Chip Select / GPI / I2C Address Pin #0
Multifunction pin #1 - SPI Serial Clock / GPI / I2C Address Pin #1
Multifunction pin #2 - SPI MISO Slave Serial Data Output / GPO
Multifunction pin #3 - SPI MOSI Slave Serial Data Input / GPI / Audio
Serial Data Bus Data Input
I2C Serial Clock / GPIO
I2C Serial Data Input/Output / GPIO
No Connect
A9
C8
D8
A7
A6
48
1
2
MFP3
SCL
SDA
NC
LINE1LP
3
MIC1 or Line1 Analog Input (Left Plus or Multifunction)
The product described herein is a prototype product.
TI makes no warranty, either expressed, implied, or
statutory, including any implied warranty or
merchantability or fitness for a specific purpose, as to
this product.
The information contined here concerns products in the
formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change
or discontinue these products without notice.
4
www.ti.com
TLV320AIC33
MAY 6, 2005
PRELIMINARY INFORMATION REV.17
A5
B7
B6
A4
B5
B4
A3
B3
B2
4
5
6
7
8
LINE1LM
LINE1RP
LINE1RM
LINE2LP
LINE2LM
LINE2RP
LINE2RM
MIC3L
MIC1 or Line1 Analog Input (Left Minus or Multifunction)
MIC1 or Line1 Analog Input (Right Plus or Multifunction)
MIC1 or Line1 Analog Input (Right Minus or Multifunction)
MIC2 or Line2 Analog Input (Left Plus or Multifunction)
MIC2 or Line2 Analog Input (Left Minus or Multifunction)
MIC2 or Line2 Analog Input (Right Plus or Multifunction)
MIC2 or Line2 Analog Input (Right Minus or Multifunction)
MIC3 Input (Left or Multifunction)
9
10
11
12
MICDET
Microphone Detect
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range unless otherwise noted (1)
RATINGS
-0.3V to 3.9V
-0.3V to 3.9V
-0.3V to 3.9V
-0.3V to 2.5V
-0.1V to 0.1V
-0.3V to IOVDD+0.3V
-0.3V to AVDD+0.3V
-40°C to +85°C
-65°C to +105°C
+105°C
VDDA1 to VSS, VDDA2 to AVSS_DAC
VDDA1 to DRVSS
IOVDD to DVSS
DVDD to DVSS
VDDA2 to VDDA1
Digital Input Voltage to DVSS
Analog Input Voltage to AVSS
Operating temperature range
Storage temperature range
Junction temperature (TJ Max)
Power dissipation
(TJ Max – TA) / θJA
TBD
BGA package
θJA Thermal impedance
Soldering vapor phase (60 sec)
Infrared (15 sec)
TBD
TBD
Lead temperature
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under
“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods
may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
2.7
1.525
1.1
NOM
3.3
1.8
MAX
3.6
1.95
3.6
UNIT
V
V
Analog supply voltage VDDA2, VDDA1(2)
Digital core supply voltage DVDD(2)
Digital I/O supply voltage IOVDD(2)
1.8
V
Analog full-scale 0dB input voltage (VDDA2, VDDA1 = 3.3V)
Stereo line output load resistance
Stereo headphone output load resistance
Digital output load capacitance
0.707
VRMS
kΩ
Ω
10
TBD
16
10
pF
Operating free-air temperature, TA
(2) Analog voltage values are with respect to AVSS_ADC, AVSS_DAC, DRVSS; digital voltage values are with respect to
DVSS.
-40
+85
°C
The product described herein is a prototype product.
TI makes no warranty, either expressed, implied, or
statutory, including any implied warranty or
merchantability or fitness for a specific purpose, as to
this product.
The information contined here concerns products in the
formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change
or discontinue these products without notice.
5
www.ti.com
TLV320AIC33
MAY 24, 2005
PRELIMINARY INFORMATION REV.17
ELECTRICAL CHARACTERISTICS
At 25°C, VDDA1, VDDA2, IOVDD = 3.3V, DVDD = 1.8V, Fs=48-kHz, 24-bit audio data, unless otherwise noted
PARAMETER
AUDIO ADC
Input signal level (0-dB)
TEST CONDITIONS
MIN
NOM
0.707
92
MAX
UNITS
VRMS
dB
Single-ended input configuration
Fs=48-kHz, 0-dB PGA gain,
MIC1/LINE1 inputs selected and
AC-shorted together
Signal-to-noise ratio, A-
weighted(3)(4)
Fs=48-kHz, 1-kHz -60-dB full-scale
input applied at MIC1/LINE1
inputs, 0-dB PGA gain
Fs=48-kHz, 1-kHz -1-dB full-scale
input applied at MIC1/LINE1
inputs, 0-dB PGA gain
Dynamic range, A-weighted(3)(4)
Total harmonic distortion
92
dB
dB
-80
1-kHz, 100mVpp on AVDD,
DRVDD
1-kHz, -1-dB
Power supply rejection ratio
ADC channel separation
TBD
TBD
dB
dB
ADC programmable gain amplifier
maximum gain
ADC programmable gain amplifier
step size
1-kHz input tone, RSOURCE<50Ω
+59.5
0.5
dB
dB
MIC1/LINE1 inputs,
Input Mix Attenuation = 0-dB
MIC1/LINE1 inputs
Input resistance
20
10
0
kΩ
pF
dB
dB
Input capacitance
Input level control minimum
attenuation setting
Input level control maximum
attenuation setting
12
Input level control attenuation
step size
1.5
dB
ADC DIGITAL DECIMATION
FILTER
Fs=48kHz
FILTER GAIN FROM 0 TO
0.39FS
dB
±0.1
Filter gain at 0.4125Fs
Filter gain at 0.45Fs
Filter gain at 0.5Fs
Filter gain from 0.55Fs to 64Fs
FILTER GROUP DELAY
MICROPHONE BIAS 1
-0.25
-3
-17.5
-75
dB
dB
dB
dB
Sec
17/Fs
2.0
2.5
Bias voltage
Programmable settings
V
VDDA1
Current sourcing
Output noise voltage
AUDIO DAC
2.5V setting
2.5V setting
Line output, Load = 10kΩ, 50pF
4
mA
nV/√Hz
TBD
The product described herein is a prototype product.
TI makes no warranty, either expressed, implied, or
statutory, including any implied warranty or
merchantability or fitness for a specific purpose, as to
this product.
The information contined here concerns products in the
formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change
or discontinue these products without notice.
6
www.ti.com
TLV320AIC33
MAY 6, 2005
PRELIMINARY INFORMATION REV.17
0-dB gain to line outputs. DAC
output common-mode setting =
1.35V, output level control gain =
0-dB
1.414
0-dB full-scale output voltage
VRMS
Fs=48-kHz, 0-dB gain to line
outputs, zero signal applied,
referenced to full-scale input level
Fs=48-kHz, 0-dB gain to line
outputs, 1-kHz -60-dB signal
applied
Signal-to-noise ratio, A-
weighted(5)
103
103
dB
dB
Dynamic range, A-weighted
Fs=48-kHz, 1-kHz -1-dB full-scale
signal applied
1-kHz, 100mVpp on AVDD_DAC,
AVDD_ADC, DRVDD1/2
1-kHz, 0-dB
Total harmonic distortion
-80
dB
dB
dB
Power supply rejection ratio
TBD
TBD
DAC channel separation (left to
right)
DAC Digital Interpolation Filter Fs = 48-kHz
Passband
High-pass filter disabled
High-pass filter disabled
0.45*Fs
Hz
dB
Hz
Passband ripple
Transition band
Stopband
TBD
0.45*Fs
0.55*Fs
0.55*Fs
7.5*Fs
Hz
Stopband attenuation
Group delay
65
21/Fs
dB
Sec
Stereo Headphone Driver
Pseudo-differential output
configuration (5)
0-dB full-scale output voltage
0-dB gain to high power outputs.
Output common-mode voltage
setting = 1.35V
0.707
1.35
VRMS
Programmable Output Common
Mode Voltage
First option
V
Second option
Third option
Fourth option
1.50
1.65
1.8
V
V
V
Maximum Programmable Output
Level Control Gain
Programmable Output Level
Control Gain Step Size
9
1
dB
dB
15
30
RL = 32Ω
RL = 16Ω
Maximum output power, PO
mW
dB
Signal-to-noise ratio, A-
weighted(6)
95
1-kHz output, PO = 10mW
1-kHz output, PO = 20mW
1-kHz, 100mVpp on AVDD_ADC,
AVDD_DAC, DRVDD1/2
1-kHz output
TBD
TBD
Total harmonic distortion
dB
Power supply rejection ratio
TBD
TBD
dB
dB
Mute attenuation
Digital I/O
The product described herein is a prototype product.
TI makes no warranty, either expressed, implied, or
statutory, including any implied warranty or
merchantability or fitness for a specific purpose, as to
this product.
The information contined here concerns products in the
formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change
or discontinue these products without notice.
7
www.ti.com
TLV320AIC33
MAY 24, 2005
PRELIMINARY INFORMATION REV.17
0.3 x
IOVDD
VIL Input low level
VIH Input high level
VOL Output low level
IIL = +5-uA
-0.3
V
V
V
V
0.7 x
IOVDD
IIH = +5-uA
0.1 x
IOVDD
IIH = 2 TTL loads
IOH = 2 TTL loads
0.8 x
IOVDD
VOH Output high level
Supply Current
Fs = 48-kHz
VDDA1
VDDA2
DVDD
VDDA1
VDDA2
DVDD
VDDA1
VDDA2
DVDD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Fs=48-kHz, PLL off,
headphone drivers off
Stereo line playback
Mono record
Stereo record
PLL
Fs=48-kHz, PLL and
AGC off
Fs=48-kHz, PLL and
AGC off
VDDA1 Additional power
VDDA2 consumed when PLL is
DVDD
VDDA1 LINE2LP/RP only routed
VDDA2 to single-ended
mA
powered
Headphone amplifier
Power down
headphones, DAC and
PLL off, no signal applied
VDDA1 All supply voltages
VDDA2 applied, all blocks
DVDD
TBD
TBD
TBD
programmed in lowest
power state
DVDD
TBD
(3) Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short
circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(4) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter.
Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than
shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although
not audible, may affect dynamic specification values.
(5) Unless otherwise noted, all measurements use output common-mode voltage setting of 1.35V, 0-dB
output level control gain, 16-ohm single-ended load.
(6) Ratio of output level with a 1-kHz full-scale input, to the output level playing an all-zero signal, measured
A-weighted over a 20-Hz to 20-kHz bandwidth.
The product described herein is a prototype product.
TI makes no warranty, either expressed, implied, or
statutory, including any implied warranty or
merchantability or fitness for a specific purpose, as to
this product.
The information contined here concerns products in the
formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change
or discontinue these products without notice.
8
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
VFBGA
VFBGA
QFN
Drawing
GQE
GQE
RGZ
TLV320AIC33IGQE
TLV320AIC33IGQER
TLV320AIC33IRGZ
TLV320AIC33IRGZR
TLV320AIC33IZQE
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
80
80
48
48
80
360
2500
250
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
QFN
RGZ
2000
360
BGA MI
CROSTA
R JUNI
OR
ZQE
TLV320AIC33IZQER
PREVIEW
BGA MI
CROSTA
R JUNI
OR
ZQE
80
2500
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
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retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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相关型号：
TLV320ALC23
Evaluation Platform for the TLV320ALC23 Stereo Audio CODEC and TLV230DAC23 Stereo DAC
TI
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