TLV320DAC3101IRHBT_技术文档

TLV320DAC3101

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Low-Power Stereo Audio DAC With Audio Processing

and Stereo Class-D Speaker Amplifier

Check for Samples: TLV320DAC3101

1 INTRODUCTION

1.1 Features

Playback Volume-Control Settings

• Programmable PLL for Flexible Clock

Generation

123

• Stereo Audio DAC With 95-dB SNR

• I²S, Left-Justified, Right-Justified, DSP, and

TDM Audio Interfaces

• Supports 8-kHz to 192-kHz Sample Rates

• Stereo 1.29-W Class-D BTL 8-Ω Speaker Driver

• I²C Control With Register Auto-Increment

• Full Power-Down Control

• Power Supplies:

With Direct Battery Connection

• 25 Built-In Processing Blocks (PRB_P1 –

PRB_P25) Providing Biquad Filters, DRC, and

3D

• Digital Sine-Wave Generator for Beeps and

Key-Clicks (PRB_P25)

• User-Programmable Biquad and FIR Filters

• Two Single-Ended Inputs With Mixing and

Output Level Control

– Analog: 2.7 V–3.6 V

– Digital Core: 1.65 V–1.95 V

– Digital I/O: 1.1 V–3.6 V

– Class-D: 2.7 V–5.5 V (SPLVDD and SPRVDD

≥ AVDD)

• 5-mm × 5-mm 32-QFN Package

• Stereo Headphone/Lineout and Class-D

Speaker Outputs Available

1.2 Applications

• Microphone Bias

• Headphone Detection

• Digital Mixing Capability

• Pin Control or Register Control for Digital-

•

Portable Audio Devices

Mobile Internet Devices

e-Books

1.3 Description

The TLV320DAC3101 is a low-power, highly integrated, high-performance DAC with selectable digital

audio processing blocks and 24-bit stereo playback.

The device integrates headphone drivers and speaker drivers. The TLV320DAC3101 has a suite of built-in

processing blocks for digital audio processing. The digital audio data format is programmable to work with

popular audio standard protocols (I²S, left/right-justified) in master, slave, DSP, and TDM modes. Bass

boost, treble, or EQ can be supported by the programmable digital signal-processing block. An on-chip

PLL provides the high-speed clock needed by the digital signal-processing block. The volume level can be

controlled by either pin control or by register control. The audio functions are controlled using the I²C serial

bus.

The TLV320DAC3101 has a programmable digital sine-wave generator and is available in a 32-pin QFN

package.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

MATLAB is a trademark of The MathWorks, Inc.

2

3

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

TLV320DAC3101

SLAS666A –JANUARY 2010–REVISED MAY 2012

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

AVSS

AVDD

HPVSS

HPVDD

SPLVSS

SPRVSS

SPRVDD

SPLVDD

P0/R116

7-Bit

Vol

ADC

VOL/MICDET

Audio Output Stage

Power Management

Left and Right

Volume-Control Register

P0/R117

P1/R33–R34

GPIO1

GPIO

I²C

De-Pop

and

Soft Start

SDA

SCL

RC CLK

AIN1

AIN2

Analog

Class-D Speaker

Driver

Note: Normally,

Attenuation

0 dB to –78 dB

and Mute

MCLK is PLL input;

however, BCLK or

GPIO1 can also be

6 dB to 24 dB

(6-dB steps)

(0.5-dB steps)

P0/R63/D5–D4

PLL input.

Left DAC

DAC

P1/R38

P1/R42

AIN1

L Data

R Data

(L+R)/2 Data

SPLP

SPLM

S

MCLK

PLL

Analog

Class A/B

Attenuation Headphone/Lineout

Driver

0 dB to 9 dB

(1-dB steps)

0 dB to –78 dB

and Mute

(0.5-dB steps)

WCLK

SDIN

P1/R40

P1/R36

BCLK

Serial

Interface

and

Process- Digital Vol

24 dB to

Mute

AIN2

HPL

ing

Blocks

MIXER

P1/R35

P1/R30–R31

Clocks

RESET

Analog

Class-D Speaker

Driver

Attenuation

0 dB to –78 dB

and Mute

6 dB to 24 dB

(6-dB steps)

(0.5-dB steps)

P0/R63/D3–D2

Right DAC

DAC

P1/R39

P1/R43

L Data

R Data

(L+R)/2 Data

SPRP

SPRM

S

P0/R64–R66

Analog

Class A/B

Attenuation Headphone/Lineout

Driver

0 dB to 9 dB

(1-dB steps)

0 dB to –78 dB

and Mute

(0.5-dB steps)

P1/R46

2 V/2.5 V/AVDD

MICBIAS

P1/R41

P1/R37

HPR

P1/R30–R31

IOVDD

DVSS

DVDD

IOVSS

B0360-02

Figure 1-1. Functional Block Diagram

2

INTRODUCTION

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NOTE

This data manual is designed using PDF document-viewing features that allow quick access

to information. For example, performing a global search on "page 0 / register 27" produces

all references to this page and register in a list. This makes it easy to traverse the list and

find all information related to a page and register. Note that the search string must be of the

indicated format. Also, this document includes document hyperlinks to allow the user to

quickly find a document reference. To come back to the original page, click the green left

arrow near the PDF page number at the bottom of the file. The hot-key for this function is alt-

left arrow on the keyboard. Another way to find information quickly is to use the PDF

bookmarks.

INTRODUCTION

3

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2 PACKAGE AND SIGNAL DESCRIPTIONS

2.1 Package/Ordering Information

OPERATING

TEMPERATURE

RANGE

TRANSPORT MEDIA,

QUANTITY

PACKAGE

DESIGNATOR

PRODUCT

PACKAGE

ORDERING NUMBER

TLV320DAC3101IRHBT

TLV320DAC3101IRHBR

Tape and reel, 250

Tape and reel, 3000

TLV320DAC3101

QFN-32

RHB

–40°C to 85°C

2.2 Device Information

RHB Package

(Top View)

24 23 22 21 20 19 18 17

25

16

15

14

13

12

11

10

9

SPRVSS

AVSS

NC

26

27

28

29

30

31

32

SPRP

HPL

AIN2

HPVDD

HPVSS

HPR

AIN1

TLV320DAC3101

MICBIAS

VOL/MICDET

SCL

RESET

GPIO1

SDA

1

2

3

4

5

6

7

8

P0048-14

Table 2-1. TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

AIN1

NO.

13

14

17

16

7

I

Analog input #1 routed to output mixer

Analog input #2 routed to output mixer

Analog power supply

AIN2

AVDD

AVSS

BCLK

DIN

–

Analog ground

I/O

I

Audio serial bit clock

5

Audio serial data input

DVDD

DVSS

GPIO1

HPL

3

–

Digital power – digital core

Digital ground

18

32

27

30

28

29

2

–

I/O

O

–

General-purpose input/output and multifunction pin

Left-channel headphone/line driver output

Right-channel headphone/line driver output

Headphone/line driver and PLL power

Headphone/line driver and PLL ground

Interface power

HPR

HPVDD

HPVSS

IOVDD

IOVSS

MCLK

–

1

–

Interface ground

8

I

Exterrnal master clock

4

PACKAGE AND SIGNAL DESCRIPTIONS

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Table 2-1. TERMINAL FUNCTIONS (continued)

TERMINAL

I/O

DESCRIPTION

NAME

MICBIAS

NC

NO.

12

4,15

31

10

9

–

I

Microphone bias for external microphone

No connecton

RESET

SCL

I

Device reset

I/O

O

–

I²C control bus clock input

I²C control bus data input

SDA

SPLM

19

22

21

20

23

26

24

25

Left-channel class-D speaker-driver inverting output

Left-channel class-D speaker-driver noninverting output

Left-channel class-D speaker-driver power supply

Left-channel class-D speaker-driver power supply ground

Right-channel class-D speaker-driver inverting output

Right-channel class-D speaker-driver noninverting output

Right-channel class-D speaker-driver power supply

Right-channel class-D speaker-driver power-supply ground

SPLP

SPLVDD

SPLVSS

SPRM

SPRP

–

O

–

SPRVDD

SPRVSS

–

Volume control or headphone detection. Note that microphone detection is also available on

devices that have an ADC.

VOL/MICDET

WCLK

11

6

I

I/O

Audio serial word clock

3 ELECTRICAL SPECIFICATIONS

3.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE

–0.3 to 3.9

UNIT

V

AVDD to AVSS

DVDD to DVSS

–0.3 to 2.5

V

HPVDD to HPVSS

–0.3 to 3.9

V

SPLVDD to SPLVSS

SPRVDD to SPRVSS

IOVDD to IOVSS

–0.3 to 6

V

–0.3 to 6

V

–0.3 to 3.9

V

Digital input voltage

Analog input voltage

Operating temperature range

Storage temperature range

Junction temperature (T_JMax)

Power dissipation

IOVSS – 0.3 to IOVDD + 0.3

AVSS – 0.3 to AVDD + 0.3

–40 to 85

V

°C

W

°C/W

–55 to 150

105

(T_JMax – T_A)/R_θJA

35

R_θJAthermal impedance (with thermal pad soldered to board)

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Table 3-1. System Thermal Characteristics⁽¹⁾

Power Rating at 25°C

Derating Factor

Power Rating at 70°C

Power Rating at 85°C

2.3 W

28.57 mW/°C

1 W

0.6 W

(1) This data was taken using 2-oz. (0.071-mm thick) trace and copper pad that is soldered to a JEDEC high-K, standard 4-layer 3-in. × 3-

in. (7.62-cm × 7.62-cm) PCB.

ELECTRICAL SPECIFICATIONS

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3.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2.7

NOM

3.3

MAX

3.6

UNIT

AVDD⁽¹⁾

DVDD

Referenced to AVSS⁽²⁾

Referenced to DVSS⁽²⁾

Referenced to HPVSS⁽²⁾

Referenced to SPLVSS⁽²⁾

Referenced to SPRVSS⁽²⁾

Referenced to IOVSS⁽²⁾

1.65

2.7

1.8

1.95

3.6

HPVDD

3.3

V

Power-supply voltage range

SPLVDD⁽¹⁾

SPRVDD⁽¹⁾

IOVDD

2.7

5.5

2.7

5.5

1.1

3.3

3.6

Resistance applied across class-D output pins

(BTL)

Speaker impedance

8

Ω

Headphone impedance

AC-coupled to R_L

16

Analog audio full-scale input

voltage

V_I

AVDD = 3.3 V, single-ended

0.707

10

V_RMS

Stereo line output load

impedance

AC coupled to R_L

IOVDD = 3.3 V

kΩ

MCLK⁽³⁾

f_SCL

Master clock frequency

SCL clock frequency

50

400

85

MHz

kHz

°C

T_A

Operating free-air temperature

–40

(1) To minimize battery-current leakage, the SPLVDD and SPRVDD voltage levels should not be below the AVDD voltage level.

(2) All grounds on board are tied together, so they should not differ in voltage by more than 0.2 V maximum for any combination of ground

signals. By use of a wide trace or ground plane, ensure a low-impedance connection between HPVSS and DVSS.

(3) The maximum input frequency should be 50 MHz for any digital pin used as a general-purpose clock.

3.3 Electrical Characteristics

At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPLVDD, SPRVDD = 3.6 V, DVDD = 1.8 V, f_S(audio) = 48 kHz, CODEC_CLKIN

= 256 × f_S, PLL = Off, VOL/MICDET pin disabled (unless otherwise noted)

PARAMETER

INTERNAL OSCILLATOR—RC_CLK

Oscillator frequency

TEST CONDITIONS

MIN

TYP

MAX UNIT

8.2

MHz

VOLUME CONTROL PIN (ADC); VOL/MICDET PIN ENABLED

VOL/MICDET pin configured as volume control

(page 0 / register 116, bit D7 = 1 and page 0 /

register 67, bit D7 = 0)

0.5 ×

V

Input voltage range

0

AVDD

Input capacitance

2

pF

Volume control steps

128

Steps

MICROPHONE BIAS

Page 1 / register 46, bits D1–D0 = 10

Page 1 / register 46, bits D1–D0 = 01

2.25

2.5

2

2.75

V

Voltage output

At 4-mA load current, page 1 / register 46, bits D1–D0

= 10 (MICBIAS = 2.5 V)

5

7

Voltage regulation

mV

At 4-mA load current, page 1 / register 46, bits D1–D0

= 01 (MICBIAS = 2 V)

6

ELECTRICAL SPECIFICATIONS

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Electrical Characteristics (continued)

At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPLVDD, SPRVDD = 3.6 V, DVDD = 1.8 V, f_S(audio) = 48 kHz, CODEC_CLKIN

= 256 × f_S, PLL = Off, VOL/MICDET pin disabled (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

AUDIO DAC

DAC Headphone Output, AC-Coupled Load = 16 Ω (Single-Ended),

Driver Gain = 0 dB, Parasitic Capacitance = 30 pF

Full-scale output voltage (0

dB)

Output common-mode setting = 1.65 V

0.707

Vrms

dB

SNR

THD

Signal-to-noise ratio

Total harmonic distortion

Measured as idle-channel noise, A-weighted^{(1) (2)}

0-dBFS input

80

95

–85

–65

–60

dB

Total harmonic distortion +

noise

THD+N

0-dBFS input

–82

dB

Mute attenuation

87

–62

20

dB

PSRR

P_O

Power-supply rejection ratio⁽³⁾Ripple on HPVDD (3.3 V) = 200 mVp-p at 1 kHz

R_L= 32 Ω, THD+N ≤ –60 dB

Maximum output power

mW

R_L= 16 Ω, THD+N ≤ –60 dB

60

DAC Lineout (HP Driver in Lineout Mode)

SNR

THD

Signal-to-noise ratio

Measured as idle-channel noise, A-weighted

0-dBFS input, 0-dB gain

95

dB

Total harmonic distortion

–86

Total harmonic distortion +

noise

THD+N

0-dBFS input, 0-dB gain

–82

dB

DAC Digital Interpolation Filter Characteristics

See Section 5.5.1.4 for DAC interpolation filter characteristics.

DAC Output to Class-D Speaker Output; Load = 8 Ω (Differential), 50 pF

SPLVDD = SPRVDD = 3.6 V, BTL measurement,

CM = 1.8 V, DAC input = 0 dBFS,

2.2

class-D gain = 6 dB, THD ≤ –16.5 dB

Output voltage

Vrms

SPLVDD = SPRVDD = 3.6 V, BTL measurement,

CM = 1.8 V, DAC input = –2 dBFS,

class-D gain = 6 dB, THD ≤ –20 dB

2.1

1.8

SPLVDD = SPRVDD = 3.6 V, BTL measurement,

DAC input = mute, CM = 1.8 V, class-D gain = 6 dB

Output, common-mode

Signal-to-noise ratio

V

SPLVDD = SPRVDD = 3.6 V, BTL measurement,

class-D gain = 6 dB, measured as idle-channel noise,

A-weighted (with respect to full-scale output value of

2.2 Vrms)^{(1) (2)}

SNR

87

dB

SPLVDD = SPRVDD = 3.6 V, BTL measurement,

CM = 1.8 V, class-D gain = 6 dB

THD

Total harmonic distortion

–67

–66

dB

Total harmonic distortion +

noise

SPLVDD = SPRVDD = 3.6 V, BTL measurement,

CM = 1.8 V, class-D gain = 6 dB

THD+N

PSRR

SPLVDD = SPRVDD = 3.6 V, BTL measurement,

ripple on SPLVDD/SPRVDD = 200 mVp-p at 1 kHz

Power-supply rejection ratio⁽⁴⁾

Mute attenuation

–44

110

540

dB

SPLVDD = SPRVDD = 3.6 V, BTL measurement,

CM = 1.8 V, class-D gain = 18 dB, THD = 10%

mW

SPLVDD = SPRVDD = 4.3 V, BTL measurement,

CM = 1.8 V, class-D gain = 18 dB, THD = 10%

P_O

Maximum output power

790

SPLVDD = SPRVDD = 5.5 V, BTL measurement,

CM = 1.8 V, class-D gain = 18 dB, THD = 10%

1.29

W

(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a

20-Hz to 20-kHz bandwidth using an audio analyzer.

(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may

result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter

removes out-of-band noise, which, although not audible, may affect dynamic specification values.

(3) DAC to headphone-out PSRR measurement is calculated as PSRR = 20 × log(ΔV_HPL/ ΔV_HPVDD).

(4) DAC to speaker-out PSRR measurement is calculated as PSRR = 20 × log(ΔV_{SPL(P + M)}/ ΔV_SPLVDD).

ELECTRICAL SPECIFICATIONS

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Electrical Characteristics (continued)

At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPLVDD, SPRVDD = 3.6 V, DVDD = 1.8 V, f_S(audio) = 48 kHz, CODEC_CLKIN

= 256 × f_S, PLL = Off, VOL/MICDET pin disabled (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DAC Output to Class-D Speaker Output; Load = 8 Ω (Differential), 50 pF (Continued)

Output-stage leakage current

for direct battery connection

SPLVDD = SPRVDD = 4.3 V, device is powered

down (power-up-reset condition)

80

nA

DAC Power Consumption

For DAC power consumption based per selected processing block, see Section 5.3.

DIGITAL INPUT/OUTPUT

Logic family

CMOS

0.7 ×

IOVDD

I_IH= 5 μA, IOVDD ≥ 1.6 V

V_IH

V

I_IH= 5 μA, IOVDD < 1.6 V

I_IL= 5 μA, IOVDD ≥ 1.6 V

IOVDD

0.3 ×

IOVDD

–0.3

V_IL

V

Logic level

I_IL= 5 μA, IOVDD < 1.6 V

0

0.8 ×

IOVDD

V_OH

V_OL

I_OH= 2 TTL loads

I_OL= 2 TTL loads

0.1 ×

IOVDD

V

Capacitive load

10

pF

8

ELECTRICAL SPECIFICATIONS

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3.4 Timing Characteristics

3.4.1 I²S/LJF/RJF Timing in Master Mode

All specifications at 25°C, DVDD = 1.8 V

Note: All timing specifications are measured at characterization only.

WCLK

t_d(WS)

t_r

BCLK

t_f

t_S(DI)

t_h(DI)

DIN

T0145-10

IOVDD = 1.1 V

IOVDD = 3.3 V

PARAMETER

UNIT

MIN

MAX

MIN

MAX

t_d(WS)

t_s(DI)

t_h(DI)

t_r

WCLK delay

DIN setup

DIN hold

45

20

ns

8

6

Rise time

Fall time

25

10

t_f

Figure 3-1. I²S/LJF/RJF Timing in Master Mode

ELECTRICAL SPECIFICATIONS

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3.4.2 I²S/LJF/RJF Timing in Slave Mode

All specifications at 25°C, DVDD = 1.8 V

Note: All timing specifications are measured at characterization only.

WCLK

t_h(WS)

t_r

t_H(BCLK)

t_S(WS)

BCLK

t_L(BCLK)

t_S(DI)

t_f

DIN

t_h(DI)

T0145-11

IOVDD = 1.1 V

IOVDD = 3.3 V

PARAMETER

UNIT

MIN

35

8

MAX

MIN

35

6

MAX

t_H(BCLK)

t_L(BCLK)

t_s(WS)

t_h(WS)

t_s(DI)

t_h(DI)

t_r

BCLK high period

BCLK low period

WCLK setup

WCLK hold

DIN setup

ns

8

6

8

6

DIN hold

8

6

Rise time

4

t_f

Fall time

Figure 3-2. I²S/LJF/RJF Timing in Slave Mode

10

ELECTRICAL SPECIFICATIONS

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3.4.3 DSP Timing in Master Mode

All specifications at 25°C, DVDD = 1.8 V

Note: All timing specifications are measured at characterization only.

WCLK

t_d(WS)

t_f

BCLK

t_S(DI)

t_r

DIN

t_h(DI)

T0146-09

IOVDD = 1.1 V

IOVDD = 3.3 V

PARAMETER

UNIT

MIN

MAX

MIN

MAX

t_d(WS)

t_s(DI)

t_h(DI)

t_r

WCLK delay

DIN setup

DIN hold

45

20

ns

8

Rise time

Fall time

25

10

t_f

Figure 3-3. DSP Timing in Master Mode

ELECTRICAL SPECIFICATIONS

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3.4.4 DSP Timing in Slave Mode

All specifications at 25°C, DVDD = 1.8 V

Note: All timing specifications are measured at characterization only.

WCLK

t_S(WS)

t_h(WS)

t_S(WS)

t_h(WS)

t_L(BCLK)

t_f

BCLK

t_H(BCLK)

t_S(DI)

t_r

DIN

t_h(DI)

T0146-10

IOVDD = 1.1 V

IOVDD = 3.3 V

PARAMETER

UNIT

MIN

35

8

MAX

MIN

35

8

MAX

t_H(BCLK)

t_L(BCLK)

t_s(WS)

t_h(WS)

t_s(DI)

t_h(DI)

t_r

BCLK high period

BCLK low period

WCLK setup

WCLK hold

DIN setup

ns

8

DIN hold

8

Rise time

4

t_f

Fall time

Figure 3-4. DSP Timing in Slave Mode

12

ELECTRICAL SPECIFICATIONS

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3.4.5 I²C Interface Timing

All specifications at 25°C, DVDD = 1.8 V

Note: All timing specifications are measured at characterization only.

SDA

t_BUF

t_LOW

t_r

t_HIGH

t_f

t_HD;STA

SCL

t_HD;STA

t_SU;DAT

t_HD;DAT

t_SU;STO

t_SU;STA

STO

STA

STO

T0295-02

Standard Mode

MIN TYP

Fast Mode

UNIT

PARAMETER

SCL clock frequency

MAX

MIN

TYP

MAX

f_SCL

0

100

0

400

kHz

Hold time, (repeated) START condition.

After this period, the first clock pulse is

generated.

t_HD;STA

4

0.8

μs

t_LOW

t_HIGH

LOW period of the SCL clock

HIGH period of the SCL clock

4.7

4

1.3

0.6

μs

Setup time for a repeated START

condition

Data hold time: for I²C bus devices

t_SU;STA

4.7

0

0.8

μs

t_HD;DAT

t_SU;DAT

t_r

3.45

0

100

0.9

μs

ns

μs

Data setup time

250

SDA and SCL rise time

SDA and SCL fall time

1000

300

20 + 0.1C_b

0.8

300

t_f

t_SU;STO

Set-up time for STOP condition

4

Bus free time between a STOP and

START condition

t_BUF

C_b

4.7

1.3

μs

Capacitive load for each bus line

400

pF

Figure 3-5. I²C Interface Timing

ELECTRICAL SPECIFICATIONS

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4 TYPICAL PERFORMANCE

4.1 DAC Performance

AMPLITUDE

vs

AMPLITUDE

vs

FREQUENCY

20

0

AVDD = HPVDD = 3.3 V

IOVDD = SPLVDD = 3.3 V

DVDD = 1.8 V

AVDD = HPVDD = 3.3 V

IOVDD = SPLVDD = 3.3 V

DVDD = 1.8 V

0

−20

−40

−60

−80

−100

−120

−140

−160

−40

−60

−80

−100

−120

−140

−160

0

5

10

15

20

0

5

10

15

20

f − Frequency − kHz

G023

G026

Figure 4-1. FFT – DAC to Line Output

Figure 4-2. FFT – DAC to Headphone Output

TOTAL HARMONIC DISTORTION + NOISE

vs

OUTPUT POWER

0

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

HPVDD = 2.7 V

CM = 1.35 V

HPVDD = 3 V

CM = 1.5 V

HPVDD = 3.3 V

CM = 1.65 V

HPVDD = 3.6 V

CM = 1.8 V

IOVDD = 3.3 V

DVDD = 1.8 V

Gain = 9 dB

R

L

= 16 Ω

0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14

P

O

− Output Power − W

G025

Figure 4-3. Headphone Output Power

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4.2 Class-D Speaker Driver Performance

TOTAL HARMONIC DISTORTION + NOISE

vs

TOTAL HARMONIC DISTORTION + NOISE

vs

OUTPUT POWER

0

−10

−20

−30

−40

−50

−60

−70

−80

AVDD = HPVDD = 3.3 V

IOVDD = 3.3 V

SPLVDD = 5.5 V

DVDD = 1.8 V

SPLVDD = 3.3 V

−10

−20

R

L

= 8 Ω

−30

−40

−50

−60

−70

−80

Driver Gain

= 24 dB

Driver Gain

= 12 dB

SPLVDD = 3.6 V

SPLVDD = 4.3 V

Driver Gain

= 18 dB

AVDD = 3.3 V

HPVDD = 3.3 V

IOVDD = 3.3 V

DVDD = 1.8 V

Gain = 18 dB

Driver Gain

= 6 dB

SPLVDD = 5.5 V

0.5

R

L

= 8 Ω

0.0

0.5

1.0

1.5

2.0

0.0

1.0

1.5

2.0

P

O

− Output Power − W

P − Output Power − W

O

G014

G015

Figure 4-4. Max Class-D Speaker-Driver Output

Power

Figure 4-5. Class-D Speaker-Driver Output Power

4.3 Analog Bypass Performance

AMPLITUDE

vs

AMPLITUDE

vs

FREQUENCY

20

AVDD = HPVDD = 3.3 V

0

−20

IOVDD = SPLVDD = 3.3 V

DVDD = 1.8 V

0

−20

IOVDD = SPLVDD = 3.3 V

DVDD = 1.8 V

−40

−60

−80

−100

−120

−140

−160

−100

−120

−140

−160

0

5

10

15

20

0

5

10

15

20

f − Frequency − kHz

G024

G027

Figure 4-6. FFT – Line-In Bypass to Line Output

Figure 4-7. FFT – Line-In Bypass to Headphone

Output

TYPICAL PERFORMANCE

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4.4 MICBIAS Performance

VOLTAGE

vs

CURRENT

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Micbias = AVDD (3.3 V)

Micbias = 2.5 V

Micbias = 2 V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

I − Current − mA

G016

Figure 4-8. MICBIAS

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5 APPLICATION INFORMATION

5.1 Typical Circuit Configuration

+3.3VA

SVDD

0.1 mF

22 mF

0.1 mF

22 mF

10 mF

SPKVDD SPKVDD

GPIO1

SPKVSS SPKVSS

HPVDD AVDD

AVSS HPVSS

SDA

SCL

8-W

Speaker

SPLP

SPLM

MCLK

WCLK

SDIN

8-W

Speaker

SPRP

SPRM

BCLK

TLV320DAC3101

RESET

To External

MIC Circuitry

MICBIAS

AIN1

Stereo

Headphone

Out

HPL

HPR

Analog In

AIN2

AVDD

34.8 kW

25 kW

VOL/MICDET

1 mF

9.76 kW

DVDD DVSS

IOVDD IOVSS

+1.8VD

0.1 mF

IOVDD

0.1 mF

AVSS

10 mF

S0400-05

Figure 5-1. Typical Circuit Configuration

5.2 Overview

The TLV320DAC3101 is a highly integrated stereo audio DAC for portable computing, communication,

and entertainment applications. A register-based architecture eases integration with microprocessor-based

systems through standard serial-interface buses. This device supports the two-wire I²C bus interface

which provides full register access. All peripheral functions are controlled through these registers and the

onboard state machines.

The TLV320DAC3101 consists of the following blocks:

•

Stereo Audio DAC

Dynamic Range Compressor (DRC)

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•

Digital sine-wave generator for clicks and beeps

Stereo headphone/lineout amplifier

Class-D stereo amplifier for 8-Ω speakers

Pin-controlled or register-controlled volume level

Power-down de-pop and power-up soft start

Analog inputs

I²C control interface

Power-down control block

Following a toggle of the RESET pin or a software reset, the device operates in the default mode. The I²C

interface is used to write to the control registers to configure the device.

The I²C address assigned to the TLV320DAC3101 is 001 1000. This device always operates in an I²C

slave mode. All registers are 8-bit, and all writable registers have read-back capability. The device auto-

increments to support sequential addressing and can be used with I²C fast mode. Once the device is

reset, all appropriate registers are updated by the host processor to configure the device as needed by the

user.

5.2.1 Device Initialization

5.2.1.1 Reset

The TLV320DAC3101 internal logic must be initialized to a known condition for proper device function. To

initialize the device to its default operating condition, the hardware reset pin (RESET) must be pulled low

for at least 10 ns. For this initialization to work, both the IOVDD and DVDD supplies must be powered up.

It is recommended that while the DVDD supply is being powered up, the RESET pin be pulled low.

The device can also be reset via software reset. Writing a 1 into page 0 / register 1, bit D0 resets the

device.

5.2.1.2 Device Start-Up Lockout Times

After the TLV320DAC3101 is initialized by hardware reset at power up or by software reset, the internal

memories are initialized to default values. This initialization takes place within 1 ms after pulling the

RESET signal high. During this initialization phase, no register-read or register-write operation should be

performed on DAC coefficient buffers. Also, no block within the codec should be powered up during the

initialization phase.

5.2.1.3 PLL Start-Up

Whenever the PLL is powered up, a start-up delay of approximately of 10 ms occurs after the power-up

command of the PLL and before the clocks are available to the codec. This delay is to ensure stable

operation of the PLL and clock-divider logic.

5.2.1.4 Power-Stage Reset

The power-stage-only reset is used to reset the device after an overcurrent latching shutdown has

occurred. Using this reset re-enables the output stage without resetting all of the registers in the device.

Each of the four power stages has its own dedicated reset bit. The headphone power-stage reset is

performed by setting page 1 / register 31, bit D7 for HPL and by setting page 1 / register 31, bit D6 for

HPR. The speaker power-stage reset is performed by setting page 1 / register 32, bit D7 for SPLP and

SPLM, and by setting page 1 / register 32, bit D6 for SPRP and SPRM.

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5.2.1.5 Software Power Down

By default, all circuit blocks are powered down following a reset condition. Hardware power up of each

circuit block can be controlled by writing to the appropriate control register. This approach allows the

lowest power-supply current for the functionality required. However, when a block is powered down, all of

the register settings are maintained as long as power is still being applied to the device.

5.2.2 Audio Analog I/O

The TLV320DAC3101 has a stereo audio DAC. It has a wide range of analog interfaces to support

different headsets and analog outputs. The TLV320DAC3101 has features to interface with output drivers

(8-Ω, 16-Ω, 32-Ω). A special circuit has also been included in the TLV320DAC3101 to insert a short key-

click sound into the stereo audio output. The key-click sound is used to provide feedback to the user when

a particular button is pressed or item is selected. The specific sound of the keyclick can be adjusted by

varying several register bits that control its frequency, duration, and amplitude. See Key-Click Functionality

With Digital Sine-Wave Generator (PRB_P25), Section 5.5.7.

5.3 Digital Processing Low-Power Modes

The TLV320DAC3101 device can be tuned to minimize power dissipation, to maximize performance, or to

an operating point between the two extremes to best fit the application. The choice of processing blocks,

PRB_P1 to PRB_P25 for stereo playback, also influences the power consumption. In fact, the numerous

processing blocks have been implemented to offer a choice among configurations having a different

balance of power optimization and signal-processing capabilities.

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5.3.1 DAC Playback on Headphones, Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V,

HPVDD = 3.3 V

DOSR = 128, Processing Block = PRB_P7 (Interpolation Filter B)

Power consumption = 24.28 mW

Table 5-1. PRB_P7 Alternative Processing Blocks, 24.28 mW

Processing Block

PRB_P1

Filter

A

Estimated Power Change (mW)

1.34

2.86

2.11

1.18

0.53

1.89

0.87

1.48

2.89

3.23

PRB_P2

A

PRB_P3

A

PRB_P8

B

PRB_P9

B

PRB_P10

PRB_P11

PRB_P23

PRB_P24

PRB_P25

B

A

DOSR = 64, Processing Block = PRB_P7 (Interpolation Filter B)

Power consumption = 24.5 mW

Table 5-2. PRB_P7 Alternative Processing Blocks, 24.5 mW

Processing Block

PRB_P1

Filter

A

Estimated Power Change (mW)

1.17

2.62

2

PRB_P2

A

PRB_P3

A

PRB_P8

B

0.99

0.5

PRB_P9

B

PRB_P10

PRB_P11

PRB_P23

PRB_P24

PRB_P25

B

1.46

0.66

1.43

2.69

2.92

B

A

5.3.2 DAC Playback on Headphones, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V,

HPVDD = 3.3 V

DOSR = 128, Processing Block = PRB_P12 (Interpolation Filter B)

Power consumption = 15.4 mW

Table 5-3. PRB_P12 Alternative Processing Blocks, 15.4 mW

Processing Block

PRB_P4

Filter

Estimated Power Change (mW)

A

B

0.57

1.48

1.08

0.56

0.27

0.89

0.31

PRB_P5

PRB_P6

PRB_P13

PRB_P14

PRB_P15

PRB_P16

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DOSR = 64, Processing Block = PRB_P12 (Interpolation Filter B)

Power consumption = 15.54 mW

Table 5-4. PRB_P12 Alternative Processing Blocks, 15.54 mW

Processing Block

PRB_P4

Filter

Estimated Power Change (mW)

A

B

0.37

1.23

1.15

0.43

0.13

0.85

0.21

PRB_P5

PRB_P6

PRB_P13

PRB_P14

PRB_P15

PRB_P16

5.3.3 DAC Playback on Headphones, Stereo, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V,

HPVDD = 3.3 V

DOSR = 768, Processing Block = PRB_P7 (Interpolation Filter B)

Power consumption = 22.44 mW

Table 5-5. PRB_P7 Alternative Processing Blocks, 22.44 mW

Processing Block

PRB_P1

Filter

A

Estimated Power Change (mW)

0.02

0.31

0.23

0.28

–0.03

0.14

0.05

0.29

0.26

0.47

PRB_P2

A

PRB_P3

A

PRB_P8

B

PRB_P9

B

PRB_P10

PRB_P11

PRB_P23

PRB_P24

PRB_P25

B

A

DOSR = 384, Processing Block = PRB_P7 (Interpolation Filter B)

Power consumption = 22.83 mW

Table 5-6. PRB_P7 Alternative Processing Blocks, 22.83 mW

Processing Block

Filter

A

Estimated Power Change (mW)

PRB_P1

PRB_P2

PRB_P3

PRB_P8

PRB_P9

PRB_P10

PRB_P11

PRB_P23

PRB_P24

PRB_P25

0.27

0.4

A

0.34

0.2

B

0.08

0.24

0.12

0.23

0.42

0.46

B

A

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5.3.4 DAC Playback on Headphones, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V,

HPVDD = 3.3 V

DOSR = 768, Processing Block = PRB_P12 (Interpolation Filter B)

Power consumption = 14.49 mW

Table 5-7. PRB_P12 Alternative Processing Blocks, 14.49 mW

Processing Block

PRB_P4

Filter

Estimated Power Change (mW)

A

B

–0.04

0.2

PRB_P5

PRB_P6

–0.01

0.1

PRB_P13

PRB_P14

PRB_P15

PRB_P16

0.05

–0.03

0.07

DOSR = 384, Processing Block = PRB_P12 (Interpolation Filter B)

Power consumption = 14.42 mW

Table 5-8. PRB_P12 Alternative Processing Blocks, 14.42 mW

Processing Block

PRB_P4

Filter

Estimated Power Change (mW)

A

B

0.16

0.3

PRB_P5

PRB_P6

0.2

PRB_P13

PRB_P14

PRB_P15

PRB_P16

0.15

0.07

0.18

0.09

5.3.5 DAC Playback on Headphones, Stereo, 192 kHz, DVDD = 1.8 V, AVDD = 3.3 V,

HPVDD = 3.3 V

DOSR = 32, Processing Block = PRB_P17 (Interpolation Filter C)

Power consumption = 27.05 mW

Table 5-9. PRB_P17 Alternative Processing Blocks, 27.05 mW

Processing Block

PRB_P18

Filter

C

Estimated Power Change (mW)

5.28

1.98

PRB_P19

C

5.3.6 DAC Playback on Line Out (10-kΩ load), Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3 V,

HPVDD = 3 V

DOSR = 64, Processing Block = PRB_P7 (Interpolation Filter B)

Power consumption = 12.85 mW

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5.4 Analog Signals

The TLV320DAC3101 analog signals consist of:

•

Microphone bias (MICBIAS)

Analog inputs AIN1 and AIN2

Analog outputs class-D speaker driver and headphone/lineout driver providing output capability for the

DAC, AIN1, AIN2 or a mix of the three

5.4.1 MICBIAS

The TLV320DAC3101 includes a microphone bias circuit which can source up to 4 mA of current and is

programmable to a 2-V, 2.5-V, or AVDD level. The level can be controlled by writing to page 1 /

register 46, bits D1–D0. This functionality is shown in Table 5-10.

Table 5-10. MICBIAS Settings

D1

0

D0

0

FUNCTIONALITY

MICBIAS output is powered down.

MICBIAS output is powered to 2 V.

MICBIAS output is powered to 2.5 V.

MICBIAS output is powered to AVDD.

0

1

0

1

During normal operation, MICBIAS can be set to 2.5 V for better performance. However, depending on the

model of microphone that is selected, optimal performance might be obtained at another setting, so the

performance at a given setting should be verified.

The lowest current consumption occurs when MICBIAS is powered down. The next-lowest current

consumption occurs when MICBIAS is set at AVDD.

5.4.2 Analog Inputs AIN1 and AIN2

AIN1 (pin 13) and AIN2 (pin 14) are inputs to the output mixer along with the DAC output. Page 1 /

register 35 provides control signals for determining the signals routed through the output mixer. The output

of the output mixer then can be attenuated or gained through the class-D and/or headphone/lineout

drivers.

5.5 Audio DAC and Audio Analog Outputs

Each channel of the stereo audio DAC consists of a digital audio processing block, a digital interpolation

filter, a digital delta-sigma modulator, and an analog reconstruction filter. This high oversampling ratio

(normally DOSR is between 32 and 128) exhibits good dynamic range by ensuring that the generated

quantization noise stays outside of the audio frequency band. Audio analog outputs include stereo

headphone/lineouts and stereo class-D speaker outputs.

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5.5.1 DAC

The TLV320DAC3101 stereo audio DAC supports data rates from 8 kHz to 192 kHz. Each channel of the

stereo audio DAC consists of a signal-processing engine with fixed processing blocks, a digital

interpolation filter, multibit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is

designed to provide enhanced performance at low sampling rates through increased oversampling and

image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal

images strongly suppressed within the audio band to beyond 20 kHz. To handle multiple input rates and

optimize power dissipation and performance, the TLV320DAC3101 allows the system designer to program

the oversampling rates over a wide range from 1 to 1024 by configuring page 0 / register 13 and page 0 /

register 14. The system designer can choose higher oversampling ratios for lower input data rates and

lower oversampling ratios for higher input data rates.

The TLV320DAC3101 DAC channel includes a built-in digital interpolation filter to generate oversampled

data for the delta-sigma modulator. The interpolation filter can be chosen from three different types,

depending on required frequency response, group delay, and sampling rate.

DAC power up is controlled by writing to page 0 / register 63, bit D7 for the left channel and bit D6 for the

right channel. The left-channel DAC clipping flag is provided as a read-only bit on page 0 / register 39,

bit D7. The right-channel DAC clipping flag is provided as a read-only bit on page 0 / register 39, bit D6.

5.5.1.1 DAC Processing Blocks

The TLV320DAC3101 implements signal-processing capabilities and interpolation filtering via processing

blocks. These fixed processing blocks give users the choice of how much and what type of signal

processing they use and which interpolation filter is applied.

The choices among these processing blocks allow the system designer to balance power conservation

and signal-processing flexibility. Table 5-11 gives an overview of all available processing blocks of the

DAC channel and their properties. The resource-class column gives an approximate indication of power

consumption for the digital (DVDD) supply; however, based on the out-of-band noise spectrum, the analog

power consumption of the drivers (HPVDD) may differ.

The signal processing blocks available are:

•

First-order IIR

Scalable number of biquad filters

3D effect

Digital sine-wave (beep) generator

The processing blocks are tuned for common cases and can achieve high image rejection or low group

delay in combination with various signal-processing effects such as audio effects and frequency shaping.

The available first-order IIR and biquad filters have fully user-programmable coefficients.

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Table 5-11. Overview – DAC Predefined Processing Blocks

Number

of

Biquads

Processing

Block No.

Interpolation

Filter

First-Order

IIR Available

Beep

Generator

Resource

Class

Channel

DRC

3D

PRB_P1

PRB_P2

PRB_P3

PRB_P4

PRB_P5

PRB_P6

PRB_P7

PRB_P8

PRB_P9

PRB_P10

PRB_P11

PRB_P12

PRB_P13

PRB_P14

PRB_P15

PRB_P16

PRB_P17

PRB_P18

PRB_P19

PRB_P20

PRB_P21

PRB_P22

PRB_P23

PRB_P24

PRB_P25

A

B

C

A

Stereo

Left

No

Yes

No

3

6

3

6

0

4

6

0

4

6

0

4

0

4

2

5

No

Yes

No

Yes

No

Yes

8

12

10

4

No

Left

Yes

No

Yes

No

6

Left

6

Stereo

Left

No

6

Yes

No

8

No

8

Yes

No

Yes

No

10

8

No

3

Left

Yes

No

4

Left

No

4

Left

Yes

No

Yes

No

6

Left

4

Stereo

Left

No

3

Yes

No

6

4

No

2

Left

Yes

No

3

Left

2

Stereo

No

8

Yes

12

5.5.1.2 DAC Processing Blocks – Signal Chain Details

5.5.1.2.1 Three Biquads, Filter A

BiQuad

A

from

Interface

BiQuad

B

BiQuad

C

Interp.

Filter A

´

to

Modulator

Digital

Volume

Ctrl

Figure 5-2. Signal Chain for PRB_P1 and PRB_P4

5.5.1.2.2 Six Biquads, First-Order IIR, DRC, Filter A or B

Interp.

Filter

A,B

BiQuad

A

BiQuad

B

BiQuad

C

BiQuad

D

BiQuad

E

BiQuad

F

´

IIR

to

Modulator

from

Interface

Digital

Volume

Ctrl

HPF

DRC

Figure 5-3. Signal Chain for PRB_P2, PRB_P5, PRB_P10, and PRB_P15

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5.5.1.2.3 Six Biquads, First-Order IIR, Filter A or B

Interp.

Filter

A,B

BiQuad

A

BiQuad

B

BiQuad

C

BiQuad

D

BiQuad

E

BiQuad

F

to

Modulator

´

IIR

from

Interface

Digital

Volume

Ctrl

Figure 5-4. Signal Chain for PRB_P3, PRB_P6, PRB_P11, and PRB_P16

5.5.1.2.4 IIR, Filter B or C

Interp.

Filter

B,C

´

to

Modulator

IIR

from

Interface

Digital

Volume

Ctrl

Figure 5-5. Signal Chain for PRB_P7, PRB_P12, PRB_P17, and PRB_P20

5.5.1.2.5 Four Biquads, DRC, Filter B

BiQuad

A

BiQuad

B

BiQuad

C

BiQuad

D

Interp.

Filter B

´

to

Modulator

from

Interface

Digital

Volume

Ctrl

HPF

DRC

Figure 5-6. Signal Chain for PRB_P8 and PRB_P13

5.5.1.2.6 Four Biquads, Filter B

BiQuad

A

from

Interface

BiQuad

B

BiQuad

C

BiQuad

D

Interp.

Filter B

´

to

Modulator

Digital

Volume

Ctrl

Figure 5-7. Signal Chain for PRB_P9 and PRB_P14

5.5.1.2.7 Four Biquads, First-Order IIR, DRC, Filter C

BiQuad

A

BiQuad

B

BiQuad

C

BiQuad

D

Interp.

Filter C

´

IIR

to

Modulator

from

Interface

Digital

Volume

Ctrl

HPF

DRC

Figure 5-8. Signal Chain for PRB_P18 and PRB_P21

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5.5.1.2.8 Four Biquads, First-Order IIR, Filter C

BiQuad

A

BiQuad

B

BiQuad

C

BiQuad

D

Interp.

Filter C

´

IIR

to

modulator

from

Interface

Digital

Volume

Ctrl

Figure 5-9. Signal Chain for PRB_P19 and PRB_P22

5.5.1.2.9 Two Biquads, 3D, Filter A

From

Left-

Channel

Interface

+

Biquad

B_L

Biquad

C_L

Interp.

Filter A

+

´

To

Modulator

+

Digital

Volume

Ctrl

+

Biquad

A_L

Biquad

A_R

3D

PGA

–

+

From

Right-

–

Biquad

B_R

Biquad

C_R

Interp.

Filter A

+

´

To

Modulator

Channel

Interface

Digital

Volume

Ctrl

NOTE: A_Lmeans biquad A of the left channel, and similarly, B_Rmeans biquad B of the right channel.

Figure 5-10. Signal Chain for PRB_P23

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5.5.1.2.10 Five Biquads, DRC, 3D, Filter A

IIR

Left

+

BiQuad

B

BiQuad

C

BiQuad

D

BiQuad

E

BiQuad

F

Interp.

Filter A

to

Modulator

´

+

from

Left

L

+

Channel

Interface

Digital

Volume

Ctrl

DRC

HPF

+

-

BiQuad

A

BiQuad

A

R

3D

PGA

+

L

-

IIR

Right

+

BiQuad

B

BiQuad

C

BiQuad

D

BiQuad

E

BiQuad

F

R

Interp.

Filter A

to

Modulator

´

+

R

from

Right

Channel

Interface

Digital

Volume

Ctrl

DRC

HPF

Figure 5-11. Signal Chain for PRB_P24

5.5.1.2.11 Five Biquads, DRC, 3D, Beep Generator, Filter A

From

+

Biquad

B_L

Biquad

C_L

Biquad

D_L

Biquad

E_L

Biquad

F_L

Left-

Channel

Interface

IIR

Left

Interp.

Filter A

+

´

To

Modulator

+

Digital

Volume

Ctrl

HPF

DRC

+

–

Biquad

A_L

Biquad

A_R

3D

PGA

+

Beep Volume Ctrl

´

Beep

Gen.

Beep Volume Ctrl

´

–

+

From

Right-

Channel

Interface

Biquad

B_R

Biquad

C_R

Biquad

D_R

Biquad

E_R

Biquad

F_R

IIR

Right

Interp.

Filter A

´

To

Modulator

+

Digital

Volume

Ctrl

DRC

HPF

Figure 5-12. Signal Chain for PRB_P25

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5.5.1.3 DAC User-Programmable Filters

Depending on the selected processing block, different types and orders of digital filtering are available. Up

to six biquad sections are available for specific processing blocks.

The coefficients of the available filters are arranged as sequentially-indexed coefficients in two banks. If

adaptive filtering is chosen, the coefficient banks can be switched in real time.

When the DAC is running, the user-programmable filter coefficients are locked and cannot be accessed

for either read or write.

However, the TLV320DAC3101 offers an adaptive filter mode as well. Setting page 8 / register 1,

bit D2 = 1 turns on double buffering of the coefficients. In this mode, filter coefficients can be updated

through the host and activated without stopping and restarting the DAC. This enables advanced adaptive

filtering applications.

In the double-buffering scheme, all coefficients are stored in two buffers (buffers A and B). When the DAC

is running and the adaptive filtering mode is turned on, setting page 8 / register 1, bit D0 = 1 switches the

coefficient buffers at the next start of a sampling period. This bit is set back to 0 after the switch occurs. At

the same time, page 8 / register 1, bit D1 toggles.

The flag in page 8 / register 1, bit D1 indicates which of the two buffers is actually in use.

Page 8 / register 1, bit D1 = 0: buffer A is in use by the DAC processing block; bit D1 = 1: buffer B is in

use.

While the device is running, coefficient updates are always made to the buffer not in use by the DAC,

regardless of the buffer to which the coefficients have been written.

Table 5-12. Adaptive-Mode Filter-Coefficient Buffer Switching

DAC Running? Page 8 / Register 1, Bit D1 Coefficient Buffer in Use

Writing to

Updates

No

0

1

None

Buffer A (Pages 8 and 9)

Buffer B (Pages 12 and 13)

Buffer A (Pages 8 and 9)

Buffer B (Pages 12 and 13)

Buffer A (Pages 8 and 9)

Buffer B (Pages 12 and 13)

Buffer A (Pages 8 and 9)

Buffer B (Pages 12 and 13)

Buffer A (Pages 8 and 9)

None

Yes

Buffer A

Buffer B

The user-programmable coefficients for the DAC processing blocks are defined on pages 8 and 9 for

buffer A and pages 12 and 13 for buffer B.

The coefficients of these filters are each 16-bit, 2s-complement format, occupying two consecutive 8-bit

registers in the register space. Specifically, the filter coefficients are in 1.15 (one dot 15) format with a

range from –1.0 (0x8000) to 0.999969482421875 (0x7FFF) as shown in Figure 5-13.

2^–15Bit

2^–4Bit

2^–1Bit

Largest Positive Number:

= 0.111111111111111111

= 0.999969482421875 = 1.0 – 1 LSB

Largest Negative Number:

= 1.000010000100001000

= 0x8000 = –1.0 (by definition)

Fraction

Point

Sign Bit

S...xxxxxxxxxxxxxxxxxx

Figure 5-13.

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5.5.1.3.1 First-Order IIR Section

The IIR is of first order and its transfer function is given by

N₀+ N₁z^-1

2¹⁵- D₁z^-1

H(z) =

(1)

The frequency response for the first-order IIR section with default coefficients is flat.

Table 5-13. DAC IIR Filter Coefficients

Default (Reset)

Filter

First-

order

IIR

Coefficient

Left DAC Channel

Right DAC Channel

Value

N0

Page 9 / register 2 and page 9 / register 3

Page 9 / register 8 and page 9 / register 9

0x7FFF (decimal

1.0 – LSB value)

N1

D1

Page 9 / register 4 and page 9 / register 5

Page 9 / register 6 and page 9 / register 7

Page 9 / register 10 and page 9 / register 11 0x0000

Page 9 / register 12 and page 9 / register 13 0x0000

5.5.1.3.2 Biquad Section

The transfer function of each of the biquad filters is given by

N₀+ 2´N₁z^-1+ N₂z^-2

2¹⁵- 2´D₁z^-1- D₂z^-2

H(z) =

(2)

Table 5-14. DAC Biquad Filter Coefficients

Default (Reset)

Value

Filter

Coefficient

Left DAC Channel

Right DAC Channel

Biquad

A

N0

Page 8 / register 2 and page 8 / register 3

Page 8 / register 66 and page 8 / register 67 0x7FFF (decimal

1.0 – LSB value)

N1

N2

D1

D2

N0

Page 8 / register 4 and page 8 / register 5

Page 8 / register 6 and page 8 / register 7

Page 8 / register 8 and page 8 / register 9

Page 8 / register 68 and page 8 / register 69 0x0000

Page 8 / register 70 and page 8 / register 71 0x0000

Page 8 / register 72 and page 8 / register 73 0x0000

Page 8 / register 10 and page 8 / register 11 Page 8 / register 74 and page 8 / register 75 0x0000

Biquad

B

Page 8 / register 12 and page 8 / register 13 Page 8 / register 76 and page 8 / register 77 0x7FFF (decimal

1.0 – LSB value)

N1

N2

D1

D2

N0

Page 8 / register 14 and page 8 / register 15 Page 8 / register 78 and page 8 / register 79 0x0000

Page 8 / register 16 and page 8 / register 17 Page 8 / register 80 and page 8 / register 81 0x0000

Page 8 / register 18 and page 8 / register 19 Page 8 / register 82 and page 8 / register 83 0x0000

Page 8 / register 20 and page 8 / register 21 Page 8 / register 84 and page 8 / register 85 0x0000

Biquad

C

Page 8 / register 22 and page 8 / register 23 Page 8 / register 86 and page 8 / register 87 0x7FFF (decimal

1.0 – LSB value)

N1

N2

D1

D2

N0

Page 8 / register 24 and page 8 / register 25 Page 8 / register 88 and page 8 / register 89 0x0000

Page 8 / register 26 and page 8 / register 27 Page 8 / register 90 and page 8 / register 91 0x0000

Page 8 / register 28 and page 8 / register 29 Page 8 / register 92 and page 8 / register 93 0x0000

Page 8 / register 30 and page 8 / register 31 Page 8 / register 94 and page 8 / register 95 0x0000

Biquad

D

Page 8 / register 32 and page 8 / register 33 Page 8 / register 96 and page 8 / register 97 0x7FFF (decimal

1.0 – LSB value)

N1

N2

Page 8 / register 34 and page 8 / register 35 Page 8 / register 98 and page 8 / register 99 0x0000

Page 8 / register 36 and page 8 / register 37 Page 8 / register 100 and page 8 / register

101

0x0000

D1

D2

Page 8 / register 38 and page 8 / register 39 Page 8 / register 102 and page 8 / register

103

Page 8 / register 40 and page 8 / register 41 Page 8 / register 104 and page 8 / register

105

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Table 5-14. DAC Biquad Filter Coefficients (continued)

Default (Reset)

Value

Coefficient

Left DAC Channel

Right DAC Channel

Biquad

E

N0

Page 8 / register 42 and page 8 / register 43 Page 8 / register 106 and page 8 / register

107

0x7FFF (decimal

1.0 – LSB value)

N1

N2

D1

D2

N0

N1

N2

D1

D2

Page 8 / register 44 and page 8 / register 45 Page 8 / register 108 and page 8 / register

109

0x0000

Page 8 / register 46 and page 8 / register 47 Page 8 / register 110 and page 8 / register

111

Page 8 / register 48 and page 8 / register 49 Page 8 / register 112 and page 8 / register

113

Page 8 / register 50 and page 8 / register 51 Page 8 / register 114 and page 8 / register

115

Biquad

F

Page 8 / register 52 and page 8 / register 53 Page 8 / register 116 and page 8 / register

117

0x7FFF (decimal

1.0 – LSB value)

Page 8 / register 54 and page 8 / register 55 Page 8 / register 118 and page 8 / register

119

0x0000

Page 8 / register 56 and page 8 / register 57 Page 8 / register 120 and page 8 / register

121

Page 8 / register 58 and page 8 / register 59 Page 8 / register 122 and page 8 / register

123

Page 8 / register 60 and page 8 / register 61 Page 8 / register 124 and page 8 / register

125

5.5.1.4 DAC Interpolation Filter Characteristics

5.5.1.4.1 Interpolation Filter A

Filter A is designed for an f_Sup to 48 ksps with a flat pass band of 0 kHz–20 kHz.

Table 5-15. Specification for DAC Interpolation Filter A

Parameter

Filter-gain pass band

Filter-gain stop band

Filter group delay

Condition

0 … 0.45 f_S

0.55 f_S… 7.455 f_S

Value (Typical)

Unit

dB

s

±0.015

–65

21/f_S

DAC Channel Response for Interpolation Filter A

(Red Line Corresponds to –65 dB)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

1

2

5

Frequency Normalized to f

6

3

4

7

S

Figure 5-14. Frequency Response of DAC Interpolation Filter A

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5.5.1.4.2 Interpolation Filter B

Filter B is specifically designed for an f_Sup to 96 ksps. Thus, the flat pass-band region easily covers the

required audio band of 0 kHz–20 kHz.

Table 5-16. Specification for DAC Interpolation Filter B

Parameter

Filter-gain pass band

Filter-gain stop band

Filter group delay

Condition

0 … 0.45 f_S

0.55 f_S… 3.45 f_S

Value (Typical)

Unit

dB

s

±0.015

–58

18/f_S

DAC Channel Response for Interpolation Filter B

(Red Line Corresponds to –58 dB)

0

–10

–20

–30

–40

–50

–60

–70

–80

0.5

1

1.5

2

2.5

Frequency Normalized to f

3

3.5

S

Figure 5-15. Frequency Response of Channel Interpolation Filter B

5.5.1.4.3 Interpolation Filter C

Filter C is specifically designed for the 192-ksps mode. The pass band extends up to 0.4 × f_S

(corresponds to 80 kHz), more than sufficient for audio applications.

Table 5-17. Specification for DAC Interpolation Filter C

Parameter

Filter-gain pass band

Filter-gain stop band

Filter group delay

Condition

0 … 0.35 f_S

0.6 f_S… 1.4 f_S

Value (Typical)

Unit

dB

s

±0.03

–43

13/f_S

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DAC Channel Response for Interpolation Filter C

(Red Line Corresponds to –43 dB)

0

–10

–20

–30

–40

–50

–60

–70

0

0.2

0.4

0.6

0.8

1

1.2

1.4

Frequency Normalized to f_S

Figure 5-16. Frequency Response of DAC Interpolation Filter C

5.5.2 DAC Digital-Volume Control

The DAC has a digital-volume control block which implements programmable gain. Each channel has an

independent volume control that can be varied from 24 dB to –63.5 dB in 0.5-dB steps. The left-channel

DAC volume can be controlled by writing to page 0 / register 65, bits D7–D0. The right-channel DAC

volume can be controlled by writing to page 0 / register 66, bits D7–D0. DAC muting and setting up a

master gain control to control both channels is done by writing to page 0 / register 64, bits D3–D0. The

gain is implemented with a soft-stepping algorithm, which only changes the actual volume by 0.125 dB per

input sample, either up or down, until the desired volume is reached. The rate of soft-stepping can be

slowed to one step per two input samples by writing to page 0 / register 63, bits D1–D0. Note that the

default source for volume-control level settings is controlled by register writes (page 0 / register 65 and

page 0 / register 66 to control volume). Use of the VOL/MICDET pin to control the DAC volume is ignored

until the volume control source selected has been changed to pin control (page 0 / register 116,

bit D7 = 1). This functionality is shown in Figure 1-1.

During soft-stepping, the host does not receive a signal when the DAC has been completely muted. This

may be important if the host must mute the DAC before making a significant change, such as changing

sample rates. In order to help with this situation, the device provides a flag back to the host via a read-

only register, page 0 / register 38, bit D4 for the left channel and bit D0 for the right channel. This

information alerts the host when the part has completed the soft-stepping and the actual volume has

reached the desired volume level. The soft-stepping feature can be disabled by writing to page 0 /

register 63, bits D1–D0.

If soft-stepping is enabled, the CODEC_CLKIN signal should be kept active until the DAC power-up flag is

cleared. When this flag is cleared, the internal DAC soft-stepping process is complete, and

CODEC_CLKIN can be stopped if desired. (The analog volume control can be ramped down using an

internal oscillator.)

5.5.3 Volume-Control Pin

The volume-control pin is not enabled by default but it can be enabled by writing 1 to page 0 /

register 116, bit D7. The default DAC volume control uses software control of the volume, which occurs if

page 0 / register 116, bit D7 = 0. Soft-stepping the volume level is set up by writing to page 0 / register 63,

bits D1–D0.

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When the volume-pin function is used, a 7-bit Vol ADC reads the voltage on the VOL/MICDET pin and

updates the digital volume control. (It overwrites the current value of the volume control.) The new volume

setting which has been applied due to a change of voltage on the volume control pin can be read on

page 0 / register 117, bits D6–D0. The 7-bit Vol ADC clock source can be selected on page 0 /

register 116, bit D6. The update rate can be programmed on page 0 / register 116, bits D2–D0 for this 7-

bit SAR ADC.

The VOL/MICDET pin gain mapping is shown in Table 5-18.

Table 5-18. VOL/MICDET Pin Gain Mapping

VOL/MICDET PIN SAR OUTPUT

DIGITAL GAIN APPLIED

0

1

18 dB

17.5 dB

17 dB

:

2

:

35

36

37

:

0.5 dB

0.0 dB

–0.5 dB

:

89

90

91

:

–26.5 dB

–27 dB

–28 dB

:

125

126

127

–62 dB

–63 dB

Mute

The VOL/MICDET pin connection and functionality are shown in Figure 5-17.

24 dB to Mute

Digital

DAC_L

D-S

DAC

Vol Processing

Blocks

Ctl

24 dB to Mute

Digital

AVDD

VREF

IN

DAC_R

AVDD

D-S

DAC

Vol Processing

Ctl

Blocks

R1

P1

R2

VOL/

MICDET

18 dB to Mute

7- Bit ADC

C_VOL

Tone Generator and Mixer Are

NOT Shown

24 dB to Mute

Volume Level

Register Controlled

AVSS

B0210-08

Figure 5-17. Digital Volume Controls for Beep Generator and DAC Play Data

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As shown in Table 5-18, the VOL/MICDET pin has a range of volume control from 18 dB down to –63 dB,

and mute. However, if less maximum gain is required, then a smaller range of voltage should be applied

to the VOL/MICDET pin. This can be done by increasing the value of R2 relative to the value of (P1 + R1),

so that more voltage is available at the bottom of P1. The circuit should also be designed such that for the

values of R1, R2, and P1 chosen, the maximum voltage (top of the potentiometer or VOL/MICDET pin)

does not exceed AVDD/2 (see Figure 5-17). The recommended values for R1, R2, and P1 for several

maximum gains are shown in Table 5-19.

Table 5-19. VOL/MICDET Pin Gain Scaling

ADC VOLTAGE

for AVDD = 3.3 V

(V)

R1

(kΩ)

P1

(kΩ)

R2

(kΩ)

DIGITAL GAIN RANGE

(dB)

25

33

25

0

0 V to 1.65 V

18 dB to –63 dB

3 dB to –63 dB

0 dB to –63 dB

7.68

9.76

0.386 V to 1.642 V

0.463 V to 1.649 V

34.8

5.5.4 Dynamic Range Compression

Typical music signals are characterized by crest factors, the ratio of peak signal power to average signal

power, of 12 dB or more. To avoid audible distortions due to clipping of peak signals, the gain of the DAC

channel must be adjusted so as not to cause hard clipping of peak signals. As a result, during nominal

periods, the applied gain is low, causing the perception that the signal is not loud enough. To overcome

this problem, dynamic range conpression (DRC) in the TLV320DAC3101 continuously monitors the output

of the DAC digital volume control to detect its power level relative to 0 dBFS. When the power level is low,

DRC increases the input signal gain to make it sound louder. At the same time, if a peaking signal is

detected, it autonomously reduces the applied gain to avoid hard clipping. This results in sounds more

pleasing to the ear as well as sounding louder during nominal periods.

The DRC functionality in the TLV320DAC3101 is implemented by a combination of processing blocks in

the DAC channel as described in Section 5.5.1.2.

DRC can be disabled by writing to page 0 / register 68, bits D6–D5.

DRC typically works on the filtered version of the input signal. The input signals have no audio information

at dc and extremely low frequencies; however, they can significantly influence the energy estimation

function in the dynamic range compressor (the DRC). Also, most of the information about signal energy is

concentrated in the low-frequency region of the input signal.

To estimate the energy of the input signal, the signal is first fed to the DRC high-pass filter and then to the

DRC low-pass filter. These filters are implemented as first-order IIR filters given by

N₀+ N₁z^-1

2¹⁵- D₁z^-1

H_HPF(z) =

(3)

N₀+ N₁z^-1

H_LPF(z) =

2¹⁵- D₁z^-1

(4)

The coefficients for these filters are 16 bits wide in 2s-complement format and are user-programmable

through register write as given in Table 5-20.

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Table 5-20. The DRC HPF and LPF Coefficients

Coefficient

Location

HPF N0

HPF N1

HPF D1

LPF N0

LPF N1

LPF D1

C71 page 9 / register 14 and page 9 / register 15

C72 page 9 / register 16 and page 9 / register 17

C73 page 9 / register 18 and page 9 / register 19

C74 page 9 / register 20 and page 9 / register 21

C75 page 9 / register 22 and page 9 / register 23

C76 page 9 / register 24 and page 9 / register 25

The default values of these coefficients implement a high-pass filter with a cutoff at 0.00166 × DAC_f_S,

and a low-pass filter with a cutoff at 0.00033 × DAC_f_S.

The output of the DRC high-pass filter is fed to the processing block selected for the DAC channel. The

absolute value of the DRC LPF filter is used for energy estimation within the DRC.

The gain in the DAC digital volume control is controlled by page 0 / register 65 and page 0 / register 66.

When the DRC is enabled, the applied gain is a function of the digital volume control register setting and

the output of the DRC.

The DRC parameters are described in sections that follow.

5.5.4.1 DRC Threshold

DRC threshold represents the level of the DAC playback signal at which the gain compression becomes

active. The output of the digital volume control in the DAC is compared with the set threshold. The

threshold value is programmable by writing to page 0 / register 68, bits D4–D2. The threshold value can

be adjusted between –3 dBFS and –24 dBFS in steps of 3 dB. Keeping the DRC threshold value too high

may not leave enough time for the DRC block to detect peaking signals, and can cause excessive

distortion at the outputs. Keeping the DRC threshold value too low can limit the perceived loudness of the

output signal.

The recommended DRC threshold value is –24 dB.

When the output signal exceeds the set DRC threshold, the interrupt flag bits at page 0 / register 44,

bits D3–D2 are updated. These flag bits are sticky in nature, and are reset only after they are read back

by the user. The non-sticky versions of the interrupt flags are also available at page 0 / register 46,

bits D3–D2.

5.5.4.2 DRC Hysteresis

DRC hysteresis is programmable by writing to page 0 / register 68, bits D1–D0. These bits can be

programmed to represent values between 0 dB and 3 dB in steps of 1 dB. It is a programmable window

around the programmed DRC threshold that must be exceeded for the disabled DRC to become enabled,

or the enabled DRC to become disabled. For example, if the DRC threshold is set to –12 dBFS and the

DRC hysteresis is set to 3 dB, then if the gain compression in the DRC is inactive, the output of the DAC

digital volume control must exceed –9 dBFS before gain compression due to the DRC is activated.

Similarly, when the gain compression in the DRC is active, the output of the DAC digital volume control

must fall below –15 dBFS for gain compression in the DRC to be deactivated. The DRC hysteresis feature

prevents the rapid activation and de-activation of gain compression in the DRC in cases when the output

of the DAC digital volume control rapidly fluctuates in a narrow region around the programmed DRC

threshold. By programming the DRC hysteresis as 0 dB, the hysteresis action is disabled.

The recommended value of DRC hysteresis is 3 dB.

5.5.4.3 DRC Hold Time

DRC hold time is intended to slow the start of decay for a specified period of time in response to a

decrease in energy level. To minimize audible artifacts, it is recommended to set the DRC hold time to 0

through programming page 0 / register 69, bits D6–D3 = 0000.

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5.5.4.4 DRC Attack Rate

When the output of the DAC digital volume control exceeds the programmed DRC threshold, the gain

applied in the DAC digital volume control is progressively reduced to avoid the signal from saturating the

channel. This process of reducing the applied gain is called attack. To avoid audible artifacts, the gain is

reduced slowly with a rate equaling the attack rate, programmable via page 0 / register 70, bits D7–D4.

Attack rates can be programmed from 4-dB gain change per sample period to 1.2207e–5-dB gain change

per sample period.

Attack rates should be programmed such that before the output of the DAC digital volume control can clip,

the input signal should be sufficiently attenuated. High attack rates can cause audible artifacts, and too-

slow attack rates may not be able to prevent the input signal from clipping.

The recommended DRC attack rate value is 1.9531e–4 dB per sample period.

5.5.4.5 DRC Decay Rate

When the DRC detects a reduction in output signal swing beyond the programmed DRC threshold, the

DRC enters a decay state, where the applied gain in the digital-volume control is gradually increased to

programmed values. To avoid audible artifacts, the gain is slowly increased with a rate equal to the decay

rate programmed through page 0 / register 70, bits D3–D0. The decay rates can be programmed from

1.5625e–3 dB per sample period to 4.7683e–7 dB per sample period. If the decay rates are programmed

too high, then sudden gain changes can cause audible artifacts. However, if it is programmed too slow,

then the output may be perceived as too low for a long time after the peak signal has passed.

The recommended value of DRC decay rate is 2.4414e–5 dB per sample period.

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5.5.4.6 Example Setup for DRC

•

Digital Vol gain = 12 dB

Threshold = –24 dB

Hysteresis = 3 dB

Hold time = 0 ms

Attack rate = 1.9531e–4 dB per sample period

Decay rate = 2.4414e–5 dB per sample period

Script

# Select Page 0

w 30 00 00

# DAC => 12 db gain left

w 30 41 18

# DAC => 12 db gain right

w 30 42 18

# DAC => DRC Enabled for both channels, Threshold = -24 db, Hysteresis = 3 dB

w 30 44 7F

# DRC Hold = 0 ms, Rate of Changes of Gain = 0.5 dB/Fs'

w 30 45 00

# Attack Rate = 1.9531e-4 dB/Frame , DRC Decay Rate =2.4414e-5 dB/Frame

w 30 46 B6

# Select Page 9

w 30 00 09

# DRC HPF

w 30 0E 7F AB 80 55 7F 56

# DRC LPF W 30 14 00 11 00 11 7F DE

5.5.5 Headphone Detection

The TLV320DAC3101 includes capability to monitor a headphone jack to determine if a plug has been

inserted into the jack. The device also includes the capability to detect a button press. Figure 5-18 shows

the circuit configuration to enable this feature.

HPR

HPL

VOL/MICDET

Micdet

Micbias

MICBIAS

Figure 5-18. Jack Connections for Headphone Detection

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Headphone detection is enabled by programming page 0 / register 67, bit D7. In order to avoid false

detections due to mechanical vibrations in headset jacks or microphone buttons, a debounce function is

provided for glitch rejection. For the case of headset insertion, a debounce function with a range of 32 ms

to 512 ms is provided. This can be programmed via page 0 / register 67, bits D4–D2. For improved button-

press detection, the debounce function has a range of 8 ms to 32 ms by programming page 0 / register

67, bits D1–D0.

The TLV320DAC3101 also provides feedback to the user through register-readable flags as well as an

interrupt on the I/O pins when a button press or a headset insertion/removal event is detected. The value

in page 0 / register 46, bits D5–D4 provides the instantaneous state of button press and headset insertion.

Page 0 / register 44, bit D5 is a sticky (latched) flag that is set when the button-press event is detected.

Page 0 / register 44, bit D4 is a sticky flag which is set when the headset insertion or removal event is

detected. These sticky flags are set by the event occurrence, and are reset only when read. This requires

polling page 0 / register 44. To avoid polling and the associated overhead, the TLV320DAC3101 also

provides an interrupt feature, whereby events can trigger the INT1 and/or INT2 interrupts. These interrupt

events can be routed to one of the digital output pins. See Section 5.5.6 for details.

The TLV320DAC3101 not only detects a headset insertion event, but also is able to distinguish between

the different headsets inserted, such as stereo headphones or cellular headphones. After the headset-

detection event, the user can read page 0 / register 67, bits D6–D5 to determine the type of headset

inserted.

Table 5-21. Headphone-Detection Block Registers

Register

Page 0 / register 67, bit D1

Page 0 / register 67, bits D4–D2

Page 0 / register 67, bits D1–D0

Page 0 / register 44, bit D5

Page 0 / register 44, bit D4

Page 0/ register 46, bit D5

Page 0 / register 46, bit D4

Page 0 / register 67, bits D6–D5

Description

Headset-detection enable/disable

Debounce programmability for headset detection

Debounce programmability for button press

Sticky flag for button-press event

Sticky flag for headset-insertion or -removal event

Status flag for button-press event

Status flag for headset insertion and removal

Flags for type of headset detected

The headset detection block requires AVDD to be powered. The headset detection feature in the

TLV320DAC3101 is achieved with very low power overhead, requiring less than 20 μA of additional

current from the AVDD supply.

5.5.6 Interrupts

Some specific events in the TLV320DAC3101 which may require host processor intervention, can be used

to trigger interrupts to the host processor. This avoids polling the status-flag registers continuously. The

TLV320DAC3101 has two defined interrupts, INT1 and INT2, that can be configured by programming

page 0 / register 48 and page 0 / register 49. A user can configure interrupts INT1 and INT2 to be

triggered by one or many events, such as:

•

Headset detection

Button press

DAC DRC signal exceeding threshold

Overcurrent condition in headphone drivers/speaker drivers

Data overflow in the DAC processing blocks and filters

Each of these INT1 and INT2 interrupts can be routed to pin GPIO1. These interrupt signals can either be

configured as a single pulse or a series of pulses by programming page 0 / register 48, bit D0 and

page 0 / register 49, bit D0. If the user configures the interrupts as a series of pulses, the events trigger

the start of pulses that stop when the flag registers in page 0 / register 44, page 0 / register 45, and

page 0 / register 50 are read by the user to determine the cause of the interrupt.

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5.5.7 Key-Click Functionality With Digital Sine-Wave Generator (PRB_P25)

A special algorithm has been included in the digital signal processing block PRB_P25 for generating a

digital sine-wave signal that is sent to the DAC. The digital sine-wave generator is also referred to as the

beep generator in this document.

This functionality is intended for generating key-click sounds or beeps for user feedback. The sine-wave

generator is very flexible (see Table 5-22) and is completely register programmable. Programming

page 0 / register 71 through page 0 / register 79 (8 bits each) completely controls the functionality of this

generator and allows for differentiating sounds.

The two registers used for programming the 16-bit sine-wave coefficient are page 0 / register 76 and

page 0 / register 77. The two registers used for programming the 16-bit cosine-wave coefficient are

page 0 / register 78 and page 0 / register 79. This coefficient resolution allows virtually any frequency of

sine wave in the audio band to be generated, up to f_S/2.

The three registers used to control the length of the sine-burst waveform are page 0 / register 73 through

page 0 / register 75. The resolution (bit) in the registers of the sine-burst length is one sample time, so this

allows great control on the overall time of the sine-burst waveform. This 24-bit length timer supports

16,777,215 sample times. (For example, if f_Sis set at 48 kHz, and the register value equals 96,000d

(01 7700h), then the sine burst lasts exactly 2 seconds.) The default settings for the tone generator, based

on using a sample rate of 48 kHz, are 1-kHz (approximately) sine wave, with a sine-burst length of five

cycles (5 ms).

Table 5-22. Beep Generator Register Locations (Page 0x00)

LEFT

BEEP

RIGHT

BEEP

BEEP LENGTH

SINE

COSINE

MSB

MID

LSB

MSB

LSB

MSB

LSB

CONTROL CONTROL

REGISTER

71 72

73

74

75

76

77

78

79

Table 5-23. Example Beep-Generator Settings for a 1000-Hz Tone

BEEP FREQUENCY

BEEP LENGTH

SINE

COSINE

SAMPLE RATE

MSB

(hex)

MID

(hex)

LSB

(hex)

MSB

(hex)

LSB

(hex)

MSB

(hex)

LSB

(hex)

Hz

1000⁽¹⁾

0

EE

10

D8

7E

E3

48,000

(1) These are the default settings.

Two registers are used to control the left sine-wave volume and the right sine-wave volume independently.

The 6-bit digital volume control used allows level control of 2 dB to –61 dB in 1-dB steps. The left-channel

volume is controlled by writing to page 0 / register 71, bits D5–D0. The right-channel volume is controlled

by writing to page 0, register 72, bits D5–D0. A master volume control that controls the left and right

channels of the beep generator can be set up by writing to page 0 / register 72, bits D7–D6. The default

volume control setting is 2 dB, which provides the maximum tone-generator output level.

For generating other tones, the three tone-generator coefficients can be found by running the following

script using MATLAB™ :

Sine = dec2hex(round(sin(2*pi*Fin/Fs)*2^15))

Cosine = dec2hex(round(cos(2*pi*Fin/Fs)*2^15))

Beep Length = dec2hex(floor(Fs*Cycle/Fin))

where,

f_in= Beep frequency desired

f_S= Sample rate

Cycle = Number of beep (sine wave) cycles that are needed

dec2hex = Decimal to hexadecimal conversion function

NOTES:

1. f_inshould be less than f_S/4.

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2. For the sine and cosine values, if the number of bits is less than the full 16-bit value, then the unused

MSBs must be written as 0s.

3. For the beep-length values, if number of bits is less than the full 24-bit value, then the unused MSBs

must be written as 0s.

Following the beep-volume control is a digital mixer that mixes in a playback data stream whose level has

already been set by the DAC volume control. Therefore, once the key-click volume level is set, the key-

click volume is not affected by the DAC volume control, which is the main control available to the end

user. This functionality is shown in Figure 1-1.

Following the DAC, the signal can be further scaled by the analog output volume control and power-

amplifier level control.

The beep generator is used for the key-click function. A single beep is generated by writing to page 0 /

register 71, bit D7. After the programmed beep length has finished, register 71, bit D7 is reset back to

zero.

5.5.8 Programming DAC Digital Filter Coefficients

The digital filter coefficients must be programmed through the I²C interface. All digital filtering for the DAC

signal path must be loaded into the RAM before the DAC is powered on. (Note that default ALLPASS filter

coefficients for programmable biquads are located in boot ROM. The boot ROM automatically loads the

default values into the RAM following a hardware reset (toggling the RESET pin) or after a software reset.

After resetting the device, loading boot ROM coefficients into the digital filters requires 100 μs of

programming time. During this time, reading or writing to page 8 through page 15 for updating DAC filter

coefficient values is not permitted. (The DAC should not be powered up until after all of the DAC

configurations have been done by the system microprocessor.)

5.5.9 Updating DAC Digital Filter Coefficients During PLAY

When it is required to update the DAC digital filter coefficients or beep generator during play, care must be

taken to avoid click and pop noise or even a possible oscillation noise. These artifacts can occur if the

DAC coefficients are updated without following the proper update sequence. The correct sequence is

shown in Figure 5-19. The values for times listed in Figure 5-19 are conservative and should be used for

software purposes.

There is also an adaptive mode, in which DAC coefficients can be updated while the DAC is on. For

details, see Section 5.5.1.3.

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Play - Paused

Volume Ramp Down

Soft Mute

DAC Volume Ramp Down WAIT Time (A)

Wait (A) ms

For f_S= 32 kHz ® Wait 25 ms (min)

For f_S= 48 kHz ® Wait 20 ms (min)

DAC Power Down

Update

Digital Filter

Coefficients

DAC Volume Ramp Up Time (B)

For f_S= 32 kHz ® 25 ms

For f_S= 48 kHz ® 20 ms

DAC Power UP

Wait 20 ms

Restore Previous

Volume Level (Ramp)

in (B) ms

Play - Continue

F0024-02

Figure 5-19. Example Flow For Updating DAC Digital Filter Coefficients During Play

5.5.10 Digital Mixing and Routing

The TLV320DAC3101 has four digital mixing blocks. Each mixer can provide either mixing or multiplexing

of the digital audio data. This arrangement of digital mixers allows independent volume control for both the

playback data and the key-click sound. The first set of mixers can be used to make monaural signals from

left and right audio data, or they can even be used to swap channels to the DAC. This function is

accomplished by selecting left audio data for the right DAC input, and right data for the left DAC input. The

second set of mixers provides mixing of the audio data stream and the key-click sound. The digital routing

can be configured by writing to page 0 / register 63, bits D5–D4 for the left channel and bits D3–D2 for the

right channel.

Because the key-click function uses the digital signal-processing block, the CODEC_CLKIN, DAC, analog

volume control, and output driver must be powered on for the key-click sound to occur.

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5.5.11 Analog Audio Routing

The TLV320DAC3101 has the capability to route the DAC output to either the headphone or the speaker

output. If desirable, both output drivers can be operated at the same time while playing at different volume

levels. The TLV320DAC3101 provides various digital routing capabilities, allowing digital mixing or even

channel swapping in the digital domain. All analog outputs other than the selected ones can be powered

down for optimal power consumption.

5.5.11.1 Analog Output Volume Control

The output volume control can be used to fine-tune the level of the mixer amplifier signal supplied to the

headphone driver or the speaker driver. This architecture supports separate and concurrent volume levels

for each of the four output drivers. This volume control can also be used as part of the output pop-noise

reduction scheme. This feature is available even if the DAC is powered down.

5.5.11.2 Headphone Analog Output Volume Control

For the headphone outputs, the analog volume control has a range from 0 dB to –78 dB in 0.5-dB steps

for most of the useful range plus mute, which is shown in Table 5-24. This volume control includes soft-

stepping logic. Routing the left-channel DAC output signal to the left-channel analog volume control is

done by writing to page 1 / register 35, bit D6. Routing the right-channel DAC output signal to the right-

channel analog volume control is done by writing to page 1 / register 35, bit D2.

Changing the left-channel analog volume for the headphone is controlled by writing to page 1 / register 36,

bits D6–D0. Changing the right-channel analog volume for the headphone is controlled by writing to

page 1 / register 37, bits D6–D0. Routing the signal from the output of the left-channel analog volume

control to the input of the left-channel headphone power amplifier is done by writing to page 1 /

register 36, bit D7. Routing the signal from the output of the right-channel analog volume control to the

input of the right-channel headphone power amplifier is done by writing to page 1 / register 37, bit D7.

The analog volume-control soft-stepping time is based on the setting in page 0 / register 63, bits D1–D0.

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Table 5-24. Analog Volume Control for Headphone and Speaker Outputs (for D7 = 1)⁽¹⁾

Register Value Analog Gain

(D6–D0)

(dB)

(D6–D0)

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

(dB)

(D6–D0)

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

(dB)

(D6–D0)

(dB)

0

0.0

–15.0

–15.5

–16.0

–16.5

–17.0

–17.5

–18.1

–18.6

–19.1

–19.6

–20.1

–20.6

–21.1

–21.6

–22.1

–22.6

–23.1

–23.6

–24.1

–24.6

–25.1

–25.6

–26.1

–26.6

–27.1

–27.6

–28.1

–28.6

–29.1

–29.6

–30.1

–30.6

–31.1

–31.6

–32.1

–32.6

–33.1

–33.6

–34.1

–34.6

–35.2

–35.7

–36.2

–36.7

–37.2

–37.7

–38.2

–38.7

–39.2

–39.7

–40.2

–40.7

–41.2

–41.7

–42.1

–42.7

–43.2

–43.8

–44.3

–44.8

90

–45.2

–45.8

–46.2

–46.7

–47.4

–47.9

–48.2

–48.7

–49.3

–50.0

–50.3

–51.0

–51.4

–51.8

–52.2

–52.7

–53.7

–54.2

–55.3

–56.7

–58.3

–60.2

–62.7

–64.3

–66.2

–68.7

–72.2

–78.3

1

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

–5.0

–5.5

–6.0

–6.5

–7.0

–7.5

–8.0

–8.5

–9.0

–9.5

–10.0

–10.5

–11.0

–11.5

–12.0

–12.5

–13.0

–13.5

–14.0

–14.5

91

2

92

3

93

4

94

5

95

6

96

7

97

8

98

9

99

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117–127

(1) Mute when D7 = 0 and D6–D0 = 127 (0x7F).

5.5.11.3 Class-D Speaker Analog Output Volume Control

For the speaker outputs, the analog volume control has a range from 0 dB to –78 dB in 0.5-dB steps for

most of the useful range plus mute, as seen in Table 5-24. The implementation includes soft-stepping

logic.

Routing the left-channel DAC output signal to the left-channel analog volume control is done by writing to

page 1 / register 35, bit D6. Routing the right-channel DAC output signal to the right-channel analog

volume control is done by writing to page 1 / register 35, bit D2. Changing the left-channel analog volume

for the speaker is controlled by writing to page 1 / register 38, bits D6–D0. Changing the right-channel

analog volume for the speaker is controlled by writing to page 1 / register 39, bits D6–D0.

Routing the signal from the output of the left-channel analog volume control to the input of the left-channel

speaker amplifier is done by writing to page 1 / register 38, bit D7. Routing the signal from the output of

the right-channel analog volume control to the input of the right-channel speaker amplifier is done by

writing to page 1 / register 39, bit D7.

The analog volume-control soft-stepping time is based on the setting in page 0 / register 63, bits D1–D0.

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5.5.12 Analog Outputs

Various analog routings are supported for playback. All the options can be conveniently viewed on the

functional block diagram, Figure 1-1.

5.5.12.1 Headphone Drivers

The TLV320DAC3101 features a stereo headphone driver (HPL and HPR) that can deliver up to 30 mW

per channel, at 3.3-V supply voltage, into a 16-Ω load. The headphones are used in a single-ended

configuration where an ac-coupling capacitor (dc-blocking) is connected between the device output pins

and the headphones. The headphone driver also supports 32-Ω and 10-kΩ loads without changing any

control register settings.

The headphone drivers can be configured to optimize the power consumption in the lineout-drive mode by

writing 11 to page 1 / register 44, bits D2–D1.

The output common mode of the headphone/lineout drivers can be programmed to 1.35 V, 1.5 V, 1.65 V,

or 1.8 V by setting page 1 / register 31, bits D4–D3. The common-mode voltage should be set ≤ AVDD/2.

The left headphone driver can be powered on by writing to page 1 / register 31, bit D7. The right

headphone driver can be powered on by writing to page 1 / register 31, bit D6. The left-output driver gain

can be controlled by writing to page 1 / register 40, bits D6–D3, and it can be muted by writing to page 1 /

register 40, bit D2. The right-output driver gain can be controlled by writing to page 1 / register 41,

bits D6–D3, and it can be muted by writing to page 1 / register 41, bit D2.

The TLV320DAC3101 has a short-circuit protection feature for the headphone drivers, which is always

enabled to provide protection. The output condition of the headphone driver during short circuit can be

programmed by writing to page 1 / register 31, bit D1. If D1 = 0 when a short circuit is detected, the device

limits the maximum current to the load. If D1 = 1 when a short circuit is detected, the device powers down

the output driver. The default condition for headphones is the current-limiting mode. In case of a short

circuit on either channel, the output is disabled and a status flag is provided as read-only bits on page 1 /

register 31, bit D0. If shutdown mode is enabled, then as soon as the short circuit is detected, page 1 /

register 31, bit D7 (for HPL) and/or page 1 / register 31, bit D6 (for HPR) clears automatically. Next, the

device requires a reset to re-enable the output stage. Resetting can be done in two ways. First, the device

master reset can be used, which requires either toggling the RESET pin or using the software reset. If

master reset is used, it resets all of the registers. Second, a dedicated headphone power-stage reset can

also be used to re-enable the output stage, and that keeps all of the other device settings. The headphone

power stage reset is done by setting page 1 / register 31, bit D7 for HPL and by setting page 1 /

register 31, bit D6 for HPR. If the fault condition has been removed, then the device returns to normal

operation. If the fault is still present, then another shutdown occurs. Repeated resetting (more than three

times) is not recommended, as this could lead to overheating.

5.5.12.2 Speaker Drivers

The TLV320DAC3101 has an integrated class-D stereo speaker driver (SPLP/SPLM and SPRP/SPRM)

capable of driving an 8-Ω differential load. The speaker driver can be powered directly from the battery

supply (2.7 V to 5.5 V) on the SPLVDD and SPRVDD pins; however, the voltage (including spike voltage)

must be limited below the absolute-maximum voltage of 6 V.

The speaker driver is capable of supplying 400 mW per channel with a 3.6-V power supply. Through the

use of digital mixing, the device can connect one or both digital audio playback data channels to either

speaker driver; this also allows digital channel swapping if needed.

The left class-D speaker driver can be powered on by writing to page 1 / register 32, bit D7. The right

class-D speaker driver can be powered on by writing to page 1 / register 32, bit D6. The left-output driver

gain can be controlled by writing to page 1 / register 42, bits D4–D3, and it can be muted by writing to

page 1 / register 42, bit D2. The right-output driver gain can be controlled by writing to page 1 /

register 43, bits D4–D3, and it can be muted by writing to page 1 / register 43, bit D2.

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The TLV320DAC3101 has a short-circuit protection feature for the speaker drivers that is always enabled

to provide protection. If the output is shorted, the output stage shuts down on the overcurrent condition.

(Current limiting is not an available option for the higher-current speaker-driver output stage.) In case of a

short circuit on either channel, the output is disabled and a status flag is provided as a read-only bit on

page 1 / register 32, bit D0.

If shutdown occurs due to an overcurrent condition, then the device requires a reset to re-enable the

output stage. Resetting can be done in two ways. First, the device master reset can be used, which

requires either toggling the RESET pin or using the software reset. If master reset is used, it resets all of

the registers. Second, a dedicated speaker power-stage reset can be used that keeps all of the other

device settings. The speaker power-stage reset is done by setting page 1 / register 32, bit D7 for SPLP

and SPLM and by setting page 1 / register 32, bit D6 for SPRP and SPRM. If the fault condition has been

removed, then the device returns to normal operation. If the fault is still present, then another shutdown

occurs. Repeated resetting (more than three times) is not recommended, as this could lead to

overheating.

To minimize battery current leakage, the SPLVDD and SPRVDD voltage levels should not be less

than the AVDD voltage level.

The TLV320DAC3101 has a thermal protection (OTP) feature for the speaker drivers which is always

enabled to provide protection. If the device is overheated, then the output stops switching. When the

device cools down, the device resumes switching. An overtemperature status flag is provided as a read-

only bit on page 0 / register 3, bit D1. The OTP feature is for self-protection of the device. If die

temperature can be controlled at the system/board level, then overtemperature does not occur.

5.5.13 Audio Output-Stage Power Configurations

After the device has been configured (following a RESET) and the circuitry has been powered up, the

audio output stage can be powered up and powered down by register control.

These functions soft-start automatically. By using these register controls, it is possible to control these four

output-stage configuratios independently.

See Table 5-25 for register control of audio output-stage power configurations.

Table 5-25. Audio-Output Stage-Power Configurations

Audio Output Pins

Desired Function

Power down HPL driver

Page 1 / Register, Bit Values

Page 1 / register 31, bit D7 = 0

Page 1 / register 31, bit D7 = 1

Page 1 / register 31, bit D6 = 0

Page 1 / register 31, bit D6 = 1

Page 1 / register 32, bit D7 = 0

Page 1 / register 32, bit D7 = 1

Page 1 / register 32, bit D6 = 0

Page 1 / register 32, bit D6 = 1

HPL

Power up HPL driver

Power down HPR driver

HPR

Power up HPR driver

Power down left class-D drivers

Power up left class-D drivers

Power down right class-D drivers

Power up right class-D drivers

SPLP / SPLM

SPRP / SPRM

5.5.14 DAC Setup

The following paragraphs are intended to guide a user through the steps necessary to configure the

TLV320DAC3101.

Step 1

The system clock source (master clock) and the targeted DAC sampling frequency must be identified.

Depending on the targeted performance, the decimation filter type (A, B, or C) and DOSR value can be

determined:

•

Filter A should be used for 48-kHz high-performance operation; DOSR must be a multiple of 8.

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•

Filter B should be used for up to 96-kHz operations; DOSR must be a multiple of 4.

Filter C should be used for up to 192-kHz operations; DOSR must be a multiple of 2.

In all cases, DOSR is limited in its range by the following condition:

2.8 MHz < DOSR × DAC_f_S< 6.2 MHz

Based on the identified filter type and the required signal processing capabilities, the appropriate

processing block can be determined from the list of available processing blocks (PRB_P1 to PRB_P25).

Based on the available master clock, the chosen DOSR and the targeted sampling rate, the clock divider

values NDAC and MDAC can be determined. If necessary, the internal PLL can add a large degree of

flexibility.

In summary, CODEC_CLKIN (derived directly from the system clock source or from the internal PLL)

divided by MDAC, NDAC, and DOSR must be equal to the DAC sampling rate DAC_f_S. The

CODEC_CLKIN clock signal is shared with the DAC clock generation block.

CODEC_CLKIN = NDAC × MDAC × DOSR × DAC_f_S

To a large degree, NDAC and MDAC can be chosen independently in the range of 1 to 128. In general,

NDAC should be as large as possible as long as the following condition can still be met:

MDAC × DOSR / 32 ≥ RC

RC is a function of the chosen processing block and is listed in Table 5-11.

The common-mode voltage setting of the device is determined by the available analog power supply.

At this point, the following device specific parameters are known: PRB_Rx, DOSR, NDAC, MDAC, input

and output common-mode values. If the PLL is used, the PLL parameters P, J, D and R are determined

as well.

Step 2

Setting up the device via register programming:

The following list gives an example sequence of items that must be executed in the time between

powering the device up and reading data from the device. Note that there are other valid sequences

depending on which features are used.

1. Define starting point:

(a) Power up applicable external power supplies

(b) Set register page to 0

(c) Initiate SW reset

2. Program clock settings

(a) Program PLL clock dividers P, J, D, R (if PLL is used)

(b) Power up PLL (if PLL is used)

(c) Program and power up NDAC

(d) Program and power up MDAC

(e) Program OSR value

(f) Program I²S word length if required (16, 20, 24, or 32 bits)

(g) Program the processing block to be used

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(h) Micellaneous page 0 controls

3. Program analog blocks

(a) Set register page to 1

(b) Program common-mode voltage

(c) Program headphone-specific depop settings (in case headphone driver is used)

(d) Program routing of DAC output to the output amplifier (headphone/lineout or speaker)

(e) Unmute and set gain of output drivers

(f) Power up output drivers

4. Apply waiting time determined by the de-pop settings and the soft-stepping settings of the driver gain

or poll page 1 / register 63

5. Power up DAC

(a) Set register page to 0

(b) Power up DAC channels and set digital gain

(c) Unmute digital volume control

A detailed example can be found in Section 5.5.15.

5.5.15 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker

Outputs

A typical EVM I²C register control script follows to show how to set up the TLV320DAC3101 in playback

mode with f_S= 44.1 kHz and MCLK = 11.2896 MHz.

# Key: w 30 XX YY ==> write to I2C address 0x30, to register 0xXX, data 0xYY

#

# ==> comment delimiter

# The following list gives an example sequence of items that must be executed in the time

# between powering the # device up and reading data from the device. Note that there are

# other valid sequences depending on which features are used.

# 1. Define starting point:

#

(a) Power up applicable external hardware power supplies

(b) Set register page to 0

w 30 00 00

#

(c) Initiate SW reset (PLL is powered off as part of reset)

#

w 30 01 01

#

# 2. Program clock settings

#

(a) Program PLL clock dividers P, J, D, R (if PLL is used)

# PLL_clkin = MCLK,codec_clkin = PLL_CLK

w 30 04 03

# J = 8

w 30 06 08

# D = 0000, D(13:8) = 0, D(7:0) = 0

w 30 07 00 00

#

(b) Power up PLL (if PLL is used)

# PLL Power up, P = 1, R = 1

#

w 30 05 91

#

(c) Program and power up NDAC

# NDAC is powered up and set to 8

w 30 0B 88

#

(d) Program and power up MDAC

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# MDAC is powered up and set to 2

w 30 0C 82

#

(e) Program OSR value

#

# DOSR = 128, DOSR(9:8) = 0, DOSR(7:0) = 128

w 30 0D 00 80

#

(f) Program I2S word length if required (16, 20, 24, 32 bits)

and master mode (BCLK and WCLK are outputs)

# mode is i2s, wordlength is 16, slave mode

w 30 1B 00

#

(g) Program the processing block to be used

#

# Select Processing Block PRB_P11

w 30 3C 0B

w 30 00 08

w 30 01 04

w 30 00 00

#

(h) Miscellaneous page 0 controls

# DAC => volume control thru pin disable

w 30 74 00

# 3. Program analog blocks

#

(a) Set register page to 1

w 30 00 01

#

(b) Program common-mode voltage (defalut = 1.35 V)

#

w 30 1F 04

#

(c) Program headphone-specific depop settings (in case headphone driver is used)

#

# De-pop, Power on = 800 ms, Step time = 4 ms

w 30 21 4E

#

(d) Program routing of DAC output to the output amplifier (headphone/lineout or speaker)

# LDAC routed to HPL out, RDAC routed to HPR out

w 30 23 44

#

(e) Unmute and set gain of output driver

# Unmute HPL, set gain = 0 db

w 30 28 06

# Unmute HPR, set gain = 0 dB

w 30 29 06

# Unmute Class-D Left, set gain = 18 dB

w 30 2A 1C

# Unmute Class-D Right, set gain = 18 dB

w 30 2B 1C

#

(f) Power up output drivers

# HPL and HPR powered up

w 30 1F C2

# Power-up Class-D drivers

w 30 20 C6

# Enable HPL output analog volume, set = -9 dB

w 30 24 92

# Enable HPR output analog volume, set = -9 dB

w 30 25 92

# Enable Class-D Left output analog volume, set = -9 dB

w 30 26 92

# Enable Class-D Right output analog volume, set = -9 dB

w 30 27 92

#

# 4. Apply waiting time determined by the de-pop settings and the soft-stepping settings

#

of the driver gain or poll page 1 / register 63

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#

# 5. Power up DAC

#

(a) Set register page to 0

w 30 00 00

#

(b) Power up DAC channels and set digital gain

#

# Powerup DAC left and right channels (soft step enabled)

w 30 3F D4

#

# DAC Left gain = -22 dB

w 30 41 D4

# DAC Right gain = -22 dB

w 30 42 D4

#

(c) Unmute digital volume control

# Unmute DAC left and right channels

w 30 40 00

5.6 Clock Generation and PLL

The TLV320DAC3101 supports a wide range of options for generating clocks for the DAC section as well

as interface and other control blocks as shown in Figure 5-20. The clocks for the DAC require a source

reference clock. This clock can be provided on variety of device pins, such as the MCLK, BCLK, or GPIO1

pins. The source reference clock for the codec can be chosen by programming the CODEC_CLKIN value

on page 0 / register 4, bits D1–D0. CODEC_CLKIN can then be routed through highly-flexible clock

dividers shown in Figure 5-20 to generate the various clocks required for the DAC. In the event that the

desired audio clocks cannot be generated from the reference clocks on MCLK, BCLK, or GPIO1, the

TLV320DAC3101 also provides the option of using the on-chip PLL which supports a wide range of

fractional multiplication values to generate the required clocks. Starting from CODEC_CLKIN, the

TLV320DAC3101 provides several programmable clock dividers to help achieve a variety of sampling

rates for the DAC.

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BCLK

DIN

MCLK

GPIO1

PLL_CLKIN

PLL

´ (R ´ J.D)/P

GPIO1

BCLK

MCLK

PLL_CLK

CODEC_CLKIN

NDAC = 1, 2, ..., 127, 128

¸ NDAC

To DAC MAC

DAC_CLK

MDAC = 1, 2, ..., 127, 128

¸ MDAC

DAC_MOD_CLK

DOSR = 1, 2, ..., 1023, 1024

¸ DOSR

DAC_f_S

B0357-04

Figure 5-20. Clock Distribution Tree

CODEC _ CLKIN

DAC _MOD _ CLK =

NDAC ´MDAC

CODEC _ CLKIN

DAC _ f_S=

NDAC ´MDAC ´DOSR

(5)

Table 5-26. CODEC CLKIN Clock Dividers

Divider

Bits

NDAC

MDAC

DOSR

Page 0 / register 11, bits D6–D0

Page 0 / register 12, bits D6–D0

Page 0 / register 13, bits D1–D0 and page 0 / register 14, bits D7–D0

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The DAC modulator is clocked by DAC_MOD_CLK. For proper power-up operation of the DAC channel,

DAC_MOD_CLK must be enabled by configuring the NDAC and MDAC clock dividers (page 0 /

register 11, bit D7 = 1 and page 0 / register 12, bit D7 = 1). When the DAC channel is powered down, the

device internally initiates a power-down sequence for proper shutdown. During this shutdown sequence,

the NDAC and MDAC dividers must not be powered down, or else a proper low-power shutdown may not

take place. The user can read back the power-status flag at page 0 / register 37, bit D7 and page 0 /

register 37, bit D3. When both the flags indicate power-down, the MDAC divider may be powered down,

followed by the NDAC divider.

In general, for proper operation, all the root clock dividers should be powered down only after the child

clock dividers have been powered down.

The TLV320DAC3101 also has options for routing some of the internal clocks to the GPIO1 pin to be used

as general-purpose clocks in the system. The feature is shown in Figure 5-22.

DAC_CLK DAC_MOD_CLK

BDIV_CLKIN

N = 1, 2, ..., 127, 128

÷N

BCLK

B0362-01

Figure 5-21. BCLK Output Options

In the mode when the TLV320DAC3101 is configured to drive the BCLK pin (page 0 / register 27,

bit D3 = 1), it can be driven as the divided value of BDIV_CLKIN. The division value can be programmed

in page 0 / register 30, bits D6–D0 from 1 to 128. BDIV_CLKIN can itself be configured to be one of

DAC_CLK (DAC processing clock), DAC_MOD_CLK by configuring the BDIV_CLKIN multiplexer in page

0 / register 29, bits D1–D0.

Additionally, a general-purpose clock can be driven out on GPIO1. This clock can be a divided-down

version of CDIV_CLKIN. The value of this clock divider can be programmed from 1 to 128 by writing to

page 0 / register 26, bits D6–D0. CDIV_CLKIN can itself be programmed as one of the clocks among the

list shown in Figure 5-22. This can be controlled by programming the multiplexer in page 0 / register 25,

bits D2–D0.

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PLL_CLK

DAC_MOD_CLK

DAC_CLK

MCLK

BCLK

DIN

CDIV_CLKIN

M = 1, 2, ..., 127, 128

÷ M

GPIO1 (CLKOUT)

B0363-01

Figure 5-22. General-Purpose Clock Output Options

Table 5-27. Maximum TLV320DAC3101 Clock Frequencies

Clock

DVDD ≥ 1.65 V

≤ 110 MHz

CODEC_CLKIN

DAC_CLK (DAC processing clock)

DAC_MOD_CLK

DAC_f_S

≤ 49.152 MHz

6.758 MHz

0.192 MHz

55 MHz

BDIV_CLKIN

CDIV_CLKIN

100 MHz when M is odd

110 MHz when M is even

5.6.1 PLL

For lower power consumption, it is best to derive the internal audio processing clocks using the simple

dividers. When the input MCLK or other source clock is not an integer multiple of the audio processing

clocks then it is necessary to use the on-board PLL. The TLV320DAC3101 fractional PLL can be used to

generate an internal master clock used to produce the processing clocks needed by the DAC. The

programmability of this PLL allows operation from a wide variety of clocks that may be available in the

system.

The PLL input supports clocks varying from 512 kHz to 20 MHz and is register-programmable to enable

generation of the required sampling rates with fine resolution. The PLL can be turned on by writing to

page 0 / register 5, bit D7. When the PLL is enabled, the PLL output clock, PLL_CLK, is given by the

following equation:

PLL_CLKIN´R ´ J.D

PLL_CLK =

P

(6)

where

R = 1, 2, 3, ..., 16 (page 0 / register 5, default value = 1)

J = 1, 2, 3, …, 63 (page 0 / register 6, default value = 4)

D = 0, 1, 2, …, 9999 (page 0 / register 7 and page 0 / register 8, default value = 0)

P = 1, 2, 3, …, 8 (page 0 / register 5, default value = 1)

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The PLL can be turned on via page 0 / register 5, bit D7. The variable P can be programmed via page 0 /

register 5, bits D6–D4. The variable R can be programmed via page 0 / register 5, bits D3–D0. The

variable J can be programmed via page 0 / register 6, bits D5–D0. The variable D is 14 bits and is

programmed into two registers. The MSB portion can be programmed via page 0 / register 7, bits D5–D0,

and the LSB portion is programmed via page 0 / register 8, bits D7–D0. For proper update of the D divider

value, page 0 / register 7 must be programmed first, followed immediately by page 0 / register 8. Unless

the write to page 0 / register 8 is completed, the new value of D does not take effect.

When the PLL is enabled, the following conditions must be satisfied:

•

When the PLL is enabled and D = 0, the following conditions must be satisfied for PLL_CLKIN:

PLL _CLKIN

512 kHz £

£ 20 MHz

P

80 MHz ≤ (PLL_CLKIN × J.D × R/P) ≤ 110 MHz

4 ≤ R × J ≤ 259

(7)

(8)

•

When the PLL is enabled and D ≠ 0, the following conditions must be satisfied for PLL_CLKIN:

PLL _CLKIN

10 MHz £

£ 20 MHz

P

80 MHz ≤ PLL_CLKIN × J.D × R/P ≤ 110 MHz

R = 1

The PLL can be powered up independently from the DAC block, and can also be used as a general-

purpose PLL by routing its output to the GPIO output. After powering up the PLL, PLL_CLK is available

typically after 10 ms.

The clocks for the codec and various signal processing blocks, CODEC_CLKIN, can be generated from

the MCLK input, BCLK input, GPIO input, or PLL_CLK (page 0 / register 4, bits D1–D0).

If CODEC_CLKIN is derived from the PLL, then the PLL must be powered up first and powered down last.

Table 5-28 lists several example cases of typical PLL_CLKIN rates and how to program the PLL to

achieve a sample rate, f_S, of either 44.1 kHz or 48 kHz.

Table 5-28. PLL Example Configurations

PLL_CLKIN (MHz)

PLLP

PLLR

PLLJ

PLLD

MDAC

NDAC

DOSR

f_S= 44.1 kHz

2.8224

5.6448

12

1

4

3

1

10

5

0

3

6

3

5

3

5

128

104

128

7

560

3504

2920

4100

560

13

6

16

5

19.2

4

48

7

f_S= 48 kHz

2.048

3.072

4.096

6.144

8.192

12

1

3

4

3

2

4

1

14

7

0

7

4

7

2

4

2

128

7

0

7

0

3

0

7

1680

3760

4800

16

5

19.2

4

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Table 5-28. PLL Example Configurations (continued)

PLL_CLKIN (MHz)

f_S= 44.1 kHz

48

PLLP

PLLR

PLLJ

PLLD

MDAC

NDAC

DOSR

4

1

7

1680

7

2

128

5.6.2 Timer

The internal clock runs nominally at 8.2 MHz. This is used for various internal timing intervals, de-bounce

logics and interrupts. The MCLK divider must be set such a way that the divider output is ~1 MHz for the

timers to be closer to the programmed value.

Powered on if

internal oscillator is

selected

Internal

Oscillator

÷8

0

Used for de-bounce time for

headset detection logic,

Interval timers

various power up timers and

for generation of interrupts

MCLK

Programmable

Divider

1

P3/R16, Bits D6-D0

P3/R16, Bit D7

Figure 5-23. Interval Timer Clock Selection

5.7 Digital Audio and Control Interface

5.7.1 Digital Audio Interface

Audio data is transferred between the host processor and the TLV320DAC3101 via the digital audio data

serial interface, or audio bus. The audio bus on this device is very flexible, including left- or right-justified

data options, support for I²S or DSP protocols, programmable data length options, a TDM mode for

multichannel operation, very flexible master/slave configurability for each bus-clock line, and the ability to

communicate with multiple devices within a system directly.

The audio bus of the TLV320DAC3101 can be configured for left- or right-justified, I²S, DSP, or TDM

modes of operation, where communication with standard telephony interfaces is supported within the TDM

mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by

configuring page 0 / register 27, bits D5–D4. In addition, the word clock and bit clock can be

independently configured in either master or slave mode for flexible connectivity to a wide variety of

processors. The word clock is used to define the beginning of a frame, and may be programmed as either

a pulse or a square-wave signal. The frequency of this clock corresponds to the DAC sampling frequency.

The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in master

mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider

in page 0 / register 30 (see Figure 5-20). The number of bit-clock pulses in a frame may need adjustment

to accommodate various word lengths as well as to support the case when multiple TLV320DAC3101s

may share the same audio bus.

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The TLV320DAC3101 also includes a feature to offset the position of start of data transfer with respect to

the word clock. This offset can be controlled in terms of number of bit clocks and can be programmed in

page 0 / register 28.

The TLV320DAC3101 also has the feature of inverting the polarity of the bit clock used for transferring the

audio data as compared to the default clock polarity used. This feature can be used independently of the

mode of audio interface chosen. This can be configured via page 0 / register 29, bit D3.

By default, when the word clocks and bit clocks are generated by the TLV320DAC3101, these clocks are

active only when the DAC is powered up within the device. This is done to save power. However, it also

supports a feature when both the word clocks and bit clocks can be active even when the codec in the

device is powered down. This is useful when using the TDM mode with multiple codecs on the same bus,

or when word clocks or bit clocks are used in the system as general-purpose clocks.

5.7.1.1 Right-Justified Mode

The audio interface of the TLV320DAC3101 can be put into the right-justified mode by programming

page 0 / register 27, bits D7–D6 = 10. In right-justified mode, the LSB of the left channel is valid on the

rising edge of the bit clock preceding the falling edge of the word clock. Similarly, the LSB of the right

channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock.

1/f_S

WCLK

BCLK

Right Channel

Left Channel

DIN

0

n–1 n–2 n–3

MSB

2

1

0

n–1 n–2 n–3

2

1

0

LSB

T0149-05

Figure 5-24. Timing Diagram for Right-Justified Mode

For the right-justified mode, the number of bit clocks per frame should be greater than or equal to twice

the programmed word length of the data.

5.7.1.2 Left-Justified Mode

The audio interface of the TLV320DAC3101 can be put into left-justified mode by programming page 0 /

register 27, bits D7–D6 = 11. In left-justified mode, the MSB of the right channel is valid on the rising edge

of the bit clock following the falling edge of the word clock. Similarly, the MSB of the left channel is valid

on the rising edge of the bit clock following the rising edge of the word clock.

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WORD

CLOCK

LEFT CHANNEL

RIGHT CHANNEL

BIT

CLOCK

N

-

N

-

N

-

N

-

N

-

N

-

N

-

N

-

N

-

3

2

1

0

3

2

1

0

DATA

1

2

3

1

2

3

1

2

3

LD(n)

RD(n)

LD(n+1)

LD(n) = n'th sample of left channel data

RD(n) = n'th sample of right channel data

Figure 5-25. Timing Diagram for Left-Justified Mode

WORD

CLOCK

LEFT CHANNEL

RIGHT CHANNEL

BIT

CLOCK

N

-

N

-

N

-

N

-

N

-

N

-

N

-

N

-

N

-

3

2

1

0

3

2

1

0

DATA

1

2

3

1

2

3

1

2

3

LD(n)

RD(n)

LD(n+1)

LD(n) = n'th sample of left channel data

RD(n) = n'th sample of right channel data

Figure 5-26. Timing Diagram for Left-Justified Mode With Offset = 1

WORD

CLOCK

LEFT CHANNEL

RIGHT CHANNEL

BIT

CLOCK

N

-

N

-

N

-

N

-

N

-

N

-

N

-

N

-

N

-

3

2

1

0

3

2

1

0

3

DATA

1

2

3

1

2

3

1

2

3

LD(n)

RD(n)

LD(n+1)

LD(n) = n'th sample of left channel data

RD(n) = n'th sample of right channel data

Figure 5-27. Timing Diagram for Left-Justified Mode With Offset = 0 and Inverted Bit Clock

For the left-justified mode, the number of bit clocks per frame should be greater than or equal to twice the

programmed word length of the data. Also, the programmed offset value should be less than the number

of bit clocks per frame by at least the programmed word length of the data.

5.7.1.3 I²S Mode

The audio interface of the TLV320DAC3101 can be put into I²S mode by programming page 0 /

register 27, bits D7–D6 = 00. In I²S mode, the MSB of the left channel is valid on the second rising edge

of the bit clock after the falling edge of the word clock. Similarly, the MSB of the right channel is valid on

the second rising edge of the bit clock after the rising edge of the word clock.

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WORD

CLOCK

LEFT CHANNEL

RIGHT CHANNEL

BIT

CLOCK

N

-

N

-

N

-

N

-

N

-

N

-

N

-

N

-

N

-

3

2

1

0

3

2

1

0

3

DATA

1

2

3

1

2

3

1

2

3

LD(n)

RD(n)

LD(n+1)

LD(n) = n'th sample of left channel data

RD(n) = n'th sample of right channel data

Figure 5-28. Timing Diagram for I²S Mode

WORD

CLOCK

LEFT CHANNEL

RIGHT CHANNEL

BIT

CLOCK

N

-

N

-

N

-

DATA

5

4

3

2

1

0

5

4

3

2

1

0

5

1

LD(n)

LD(n) = n'th sample of left channel data

RD(n)

RD(n) = n'th sample of right channel data

LD(n+1)

Figure 5-29. Timing Diagram for I²S Mode With Offset = 2

WORD

CLOCK

LEFT CHANNEL

RIGHT CHANNEL

BIT

CLOCK

N

-

N

-

N

-

N

-

N

-

N

-

N

-

N

-

N

-

3

2

1

0

3

2

1

0

3

DATA

1

2

3

1

2

3

1

2

3

LD(n)

RD(n)

LD(n+1)

LD(n) = n'th sample of left channel data

RD(n) = n'th sample of right channel data

Figure 5-30. Timing Diagram for I²S Mode With Offset = 0 and Bit Clock Inverted

For I²S mode, the number of bit clocks per channel should be greater than or equal to the programmed

word length of the data. Also, the programmed offset value should be less than the number of bit clocks

per frame by at least the programmed word length of the data.

5.7.1.4 DSP Mode

The audio interface of the TLV320DAC3101 can be put into DSP mode by programming page 0 /

register 27, bits D7–D6 = 01. In DSP mode, the falling edge of the word clock starts the data transfer with

the left-channel data first and immediately followed by the right-channel data. Each data bit is valid on the

falling edge of the bit clock.

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WORD

CLOCK

LEFT CHANNEL

RIGHT CHANNEL

BIT

CLOCK

N

-

N

-

N

-

N

-

N

-

N

-

N

-

N

-

N

-

3

2

1

0

3

2

1

0

3

DATA

1

2

3

1

2

3

1

2

3

LD(n)

RD(n)

LD(n+1)

LD(n) = n'th sample of left channel data

RD(n) = n'th sample of right channel data

Figure 5-31. Timing Diagram for DSP Mode

WORD

CLOCK

LEFT CHANNEL

RIGHT CHANNEL

BIT

CLOCK

N

-

N

-

N

-

N

-

N

-

N

-

N

-

N

-

N

-

3

2

1

0

3

2

1

0

DATA

1

2

3

1

2

3

1

2

3

LD(n)

RD(n)

LD(n+1)

LD(n) = n'th sample of left channel data

RD(n) = n'th sample of right channel data

Figure 5-32. Timing Diagram for DSP Mode With Offset = 1

WORD

CLOCK

LEFT CHANNEL

RIGHT CHANNEL

BIT

CLOCK

N

-

N

-

N

-

N

-

N

-

N

-

N

-

N

-

N

-

3

2

1

0

3

2

1

0

3

DATA

1

2

3

1

2

3

1

2

3

LD(n)

RD(n)

LD(n+1)

Figure 5-33. Timing Diagram for DSP Mode With Offset = 0 and Bit Clock Inverted

For the DSP mode, the number of bit clocks per frame should be greater than or equal to twice the

programmed word length of the data. Also, the programmed offset value should be less than the number

of bit clocks per frame by at least the programmed word length of the data.

5.7.2 Primary and Secondary Digital Audio Interface Selection

The audio serial interface on the TLV320DAC3101 has extensive I/O control to allow communication with

two independent processors for audio data. The processors can communicate with the device one at a

time. This feature is enabled by register programming of the various pin selections. Table 5-29 shows the

primary and secondary audio interface selection and registers. Figure 5-34 is a high-level diagram

showing the general signal flow and multiplexing for the primary and secondary audio interfaces.

Table 5-29. Primary and Secondary Audio Interface Selection

Desired Pin

Function

Possible

Pins

Page 0 Registers

Comment

R27/D2 = 1

R33/D5–D4

Primary WCLK is output from codec

Select source of primary WCLK (DAC_f_Sor secondary WCLK)

Primary WCLK

(OUT)

WCLK

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Table 5-29. Primary and Secondary Audio Interface Selection (continued)

Desired Pin

Function

Possible

Pins

Page 0 Registers

Comment

Primary WCLK (IN)

WCLK

R27/D2 = 0

Primary WCLK is input to codec

R27/D3 = 1

Primary BCLK is output from codec

Primary BCLK

(OUT)

BCLK

R33/D7

Select source of primary WCLK (internal BCLK or secondary BCLK)

Primary BCLK is input to codec

Primary BCLK (IN)

Primary DIN (IN)

BCLK

DIN

R27/D3 = 0

R32/D0

Select DIN to internal interface (0 = primary DIN; 1 = secondary DIN)

Secondary WCLK obtained from GPIO1 pin

GPIO1 = secondary WCLK output

R31/D4–D2 = 000

R51/D5–D2 = 1001

R33/D3–D2

Secondary WCLK

(OUT)

GPIO1

Select source of secondary WCLK (DAC_f_S, or primary WCLK)

Secondary WCLK obtained from GPIO1 pin

GPIO1 enabled as secondary input

R31/D4–D2 = 000

R51/D5–D2 = 0001

R31/D7–D5 = 000

R51/D5–D2 = 1000

R33/D6

Secondary WCLK

(IN)

Secondary BCLK obtained from GPIO1 pin

GPIO1 = secondary BCLK output

Secondary BCLK

(OUT)

Select source of secondary BCLK (primary BCLK or internal BCLK)

Secondary BCLK obtained from GPIO1 pin

GPIO1 enabled as secondary input

R31/D7–D5 = 000

R51/D5–D2 = 0001

R31/D1–D0 = 00

R51/D5–D2 = 0001

Secondary BCLK

(IN)

GPIO1

Secondary DIN obtained from GPIO1 pin

Secondary DIN (IN)

GPIO1 enabled as secondary input

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S_BCLK

BCLK

BCLK_OUT

BCLK_INT

S_BCLK

WCLK

S_WCLK

DAC_f_S

WCLK

Audio

DAC_WCLK_INT

Digital

Primary

Audio

Processor

Serial

Interface

S_WCLK

DOUT

DIN

DIN_INT

S_DIN

DIN

BCLK2

WCLK2

GPIO1

S_BCLK

S_WCLK

S_DIN

BCLK

BCLK_OUT

GPIO1

WCLK

BCLK_OUT

Clock

WCLK

DAC_f_S

Secondary

Audio

Processor

Generation

DAC_f_S

DOUT

DIN

B0375-01

Figure 5-34. Audio Serial Interface Multiplexing

5.7.3 Control Interface

The TLV320DAC3101 control interface supports the I²C communication protocol.

5.7.3.1 I²C Control Mode

The TLV320DAC3101 supports the I²C control protocol, and responds to the I²C address of 0011 000. I²C

is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on

the I²C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines

HIGH. Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no

device is driving them LOW. This way, two devices cannot conflict; if two devices drive the bus

simultaneously, there is no driver contention.

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Communication on the I²C bus always takes place between two devices, one acting as the master and the

other acting as the slave. Both masters and slaves can read and write, but slaves can only do so under

the direction of the master. Some I²C devices can act as masters or slaves, but the TLV320DAC3101 can

only act as a slave device.

An I²C bus consists of two lines, SDA and SCL. SDA carries data, and the SCL signal provides the clock.

All data is transmitted across the I²C bus in groups of eight bits. To send a bit on the I²C bus, the SDA line

is driven to the appropriate level while SCL is LOW (a LOW on SDA indicates the bit is zero, while a HIGH

indicates the bit is one).

Once the SDA line has settled, the SCL line is brought HIGH, then LOW. This pulse on the SCL line

clocks the SDA bit into the receiver shift register.

The I²C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master

reads from a slave, the slave drives the data line; when a master sends to a slave, the master drives the

data line.

Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When

communication is taking place, the bus is active. Only master devices can start communication on the bus.

Normally, the data line is only allowed to change state while the clock line is LOW. If the data line changes

state while the clock line is HIGH, it is either a START condition or its counterpart, a STOP condition. A

START condition is when the clock line is HIGH and the data line goes from HIGH to LOW. A STOP

condition is when the clock line is HIGH and the data line goes from LOW to HIGH.

After the master issues a START condition, it sends a byte that selects the slave device for

communication. This byte is called the address byte. Each device on an I²C bus has a unique 7-bit

address to which it responds. (Slaves can also have 10-bit addresses; see the I²C specification for

details.) The master sends an address in the address byte, together with a bit that indicates whether it is

to read from or write to the slave device.

Every byte transmitted on the I²C bus, whether it is address or data, is acknowledged with an

acknowledge bit. When a master has finished sending a byte (eight data bits) to a slave, it stops driving

SDA and waits for the slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA

LOW. The master then sends a clock pulse to clock the acknowledge bit. Similarly, when a master has

finished reading a byte, it pulls SDA LOW to acknowledge this to the slave. It then sends a clock pulse to

clock the bit. (Remember that the master always drives the clock line.)

A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is

not present on the bus, and the master attempts to address it, it receives a not-acknowledge because no

device is present at that address to pull the line LOW.

When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP

condition is issued, the bus becomes idle again. A master may also issue another START condition. When

a START condition is issued while the bus is active, it is called a repeated START condition.

The TLV320DAC3101 can also respond to and acknowledge a general call, which consists of the master

issuing a command with a slave address byte of 00h. This feature is disabled by default, but can be

enabled via page 0 / register 34, bit D5.

SCL

SDA

DA(6)

DA(0)

RA(7)

RA(0)

D(7)

D(0)

Slave

Ack

(S)

Slave

Ack

(S)

Slave

Ack

(S)

Start

(M)

7-bit Device Address

(M)

Write

(M)

8-bit Register Address

(M)

8-bit Register Data

(M)

Stop

(M)

(M) => SDA Controlled by Master

(S) => SDA Controlled by Slave

Figure 5-35. I²C Write

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SCL

SDA

DA(6)

DA(0)

D(7)

D(0)

DA(6)

DA(0)

RA(7)

RA(0)

Master

No Ack

(M)

Start

(M)

Stop

(M)

7-bit Device Address

(M)

Write

(M)

Slave

Ack

(S)

8-bit Register Address

(M)

Slave

Ack

(S)

Repeat

Start

(M)

7-bit Device Address

(M)

Read

(M)

Slave

Ack

(S)

8-bit Register Data

(S)

(M) => SDA Controlled by Master

(S) => SDA Controlled by Slave

Figure 5-36. I²C Read

In the case of an I²C register write, if the master does not issue a STOP condition, then the device enters

auto-increment mode. So in the next eight clocks, the data on SDA is treated as data for the next

incremental register.

Similarly, in the case of an I²C register read, after the device has sent out the 8-bit data from the

addressed register, if the master issues a ACKNOWLEDGE, the slave takes over control of the SDA bus

and transmits for the next eight clocks the data of the next incremental register.

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6 REGISTER MAP

6.1 TLV320DAC3101 Register Map

All features on this device are addressed using the I²C bus. All of the writable registers can be read back.

However, some registers contain status information or data, and are available for reading only.

The TLV320DAC3101 contains several pages of 8-bit registers, and each page can contain up to 128

registers. The register pages are divided up based on functional blocks for this device. The pages defined

for the TLV320DAC3101 are 0, 1, 3, 8–9, 12–13 (DAC coefficient pages). Page 0 is the default home

page after RESET. Page control is done by writing a new page value into register 0 of the current page.

The control registers for the TLV320DAC3101 are described in detail as follows. All registers are 8 bits in

width, with D7 referring to the most-significant bit of each register, and D0 referring to the least-significant

bit.

Pages 0, 1, 3, 8–9, and 12–13 are available for use; however, all other pages and registers are reserved.

Do not read from or write to reserved pages and registers. Also, do not write other than the reset values

for the reserved bits and read-only bits of non-reserved registers; otherwise, device functionality failure

can occur.

Note that the page and register numbers are shown in decimal format. For use in microcode these

decimal values may need to be converted to hexadecimal format. For convienience the register

numbers are shown in both formats whereas the page numbers are shown only in decimal format.

Table 6-1. Summary of Register Map

Page Number

Description

Page 0 is the default page on power up. Configuration for serial interface, digital I/O, etc.

Configuration for DAC, output drivers, volume controls, etc.

0

1

Register 16 controls the MCLK divider that controls the interrupt pulse duration, debounce timing, and detection-block

clock.

3

8–9

DAC filter and DRC coefficients (buffer A)

DAC filter and DRC coefficients (buffer B)

12–13

6.2 Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial

Interfaces, Flags, Interrupts, and GPIOs

Page 0 / Register 0 (0x00): Page Control Register

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R/W

0000 0000

0000 0000: Page 0 selected

0000 0001: Page 1 selected

...

1111 1110: Page 254 selected

1111 1111: Page 255 selected

Page 0 / Register 1 (0x01): Software Reset

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D1

D0

R/W

0000 000

0

Reserved. Write only zeros to these bits.

0: Don't care

1: Self-clearing software reset for control register

Page 0 / Register 2 (0x02): Reserved

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R

XXXX XXXX Reserved. Do not write to this register.

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Page 0 / Register 3 (0x03): OT FLAG

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D2

D1

R

XXXX XX

1

Reserved. Do not write to these bits.

0: Overtemperature protection flag (active-low). Valid only if speaker amplifier is powered up

1: Normal operation

D0

R/W

X

Reserved. Do not write to these bits.

Page 0 / Register 4 (0x04): Clock-Gen Muxing⁽¹⁾

DESCRIPTION

READ/

WRITE

RESET

VALUE

BIT

D7–D4

D3–D2

R/W

0000

00

Reserved. Write only zeros to these bits.

00: PLL_CLKIN = MCLK (device pin)

01: PLL_CLKIN = BCLK (device pin)

10: PLL_CLKIN = GPIO1 (device pin)

11: PLL_CLKIN = DIN (can be used for the system where DAC is not used)

D1–D0

R/W

00

00: CODEC_CLKIN = MCLK (device pin)

01: CODEC_CLKIN = BCLK (device pin)

10: CODEC_CLKIN = GPIO1 (device pin)

11: CODEC_CLKIN = PLL_CLK (generated on-chip)

(1) See Section 5.6 for more details on clock generation mutiplexing and dividers.

Page 0 / Register 5 (0x05): PLL P and R Values

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

0: PLL is powered down.

1: PLL is powered up.

D6–D4

R/W

001

000: PLL divider P = 8

001: PLL divider P = 1

010: PLL divider P = 2

...

110: PLL divider P = 6

111: PLL divider P = 7

D3–D0

R/W

0001

0000: PLL multiplier R = 16

0001: PLL multiplier R = 1

0010: PLL multiplier R = 2

...

1110: PLL multiplier R = 14

1111: PLL multiplier R = 15

Page 0 / Register 6 (0x06): PLL J Value

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D6

D5–D0

R/W

00

Reserved. Write only zeros to these bits.

00 0100

00 0000: Do not use (reserved)

00 0001: PLL multiplier J = 1

00 0010: PLL multiplier J = 2

...

11 1110: PLL multiplier J = 62

11 1111: PLL multiplier J = 63

Page 0 / Register 7 (0x07): PLL D-Value MSB⁽¹⁾

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D6

D5–D0

R/W

00

Reserved. Write only zeros to these bits.

00 0000

PLL fractional multiplier D-value MSBs D[13:8]

(1) Note that this register is updated only when page 0 / register 8 is written immediately after page 0 / register 7.

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Page 0 / Register 8 (0x08): PLL D-Value LSB⁽¹⁾

DESCRIPTION

READ/

WRITE

RESET

VALUE

BIT

D7–D0

R/W

0000 0000

PLL fractional multiplier D-value LSBs D[7:0]

(1) Note that page 0 / register 8 must be written immediately after page 0 / register 7.

Page 0 / Register 9 and Page 0 / Register 10: Reserved

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R/W

XXXX XXXX Reserved. Write only zeros to these bits.

Page 0 / Register 11 (0x0B): DAC NDAC_VAL

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

0: DAC NDAC divider is powered down.

1: DAC NDAC divider is powered up.

D6–D0

R/W

000 0001

000 0000: DAC NDAC divider = 128

000 0001: DAC NDAC divider = 1

000 0010: DAC NDAC divider = 2

...

111 1110: DAC NDAC divider = 126

111 1111: DAC NDAC divider = 127

Page 0 / Register 12 (0x0C): DAC MDAC_VAL

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

0: DAC MDAC divider is powered down.

1: DAC MDAC divider is powered up.

D6–D0

R/W

000 0001

000 0000: DAC MDAC divider = 128

000 0001: DAC MDAC divider = 1

000 0010: DAC MDAC divider = 2

...

111 1110: DAC MDAC divider = 126

111 1111: DAC MDAC divider = 127

Page 0 / Register 13 (0x0D): DAC DOSR_VAL MSB

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D2

D1–D0

R/W

0000 00

00

Reserved

DAC OSR value DOSR(9:8)

Page 0 / Register 14 (0x0E): DAC DOSR_VAL LSB^{(1) (2)}

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R/W

1000 0000

DAC OSR Value DOSR(7:0)

0000 0000: DAC OSR(7:0) = 1024 (MSB page 0 / register 13, bits D1–D0 = 00)

0000 0001: Reserved.

0000 0010: DAC OSR(7:0) = 2 (MSB page 0 / register 13, bits D1–D0 = 00)

...

1111 1110: DAC OSR(7:0) = 1022 (MSB page 0 / register 13, bits D1–D0 = 11)

1111 1111: DAC OSR(7:0) = Reserved. Do not use.

(1) DOSR must be a multiple of 2 when using filter type A, a multiple of 4 when using filter type B, and a multiple of 8 when using filter type

C.

(2) Note that page 0 / register 14 must be written to immediately after writing to page 0 / register 13.

Page 0 / Register 15–24: Reserved

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R/W

XXXX XXXX Reserved. Do not write to these registers.

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Page 0 / Register 25 (0x19): CLKOUT MUX

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D3

D2–D0

R/W

0000 0

000

Reserved

R/W

000: CDIV_CLKIN = MCLK (device pin)

001: CDIV_CLKIN = BCLK (device pin)

010: CDIV_CLKIN = DIN (can be used for the systems where DAC is not required)

011: CDIV_CLKIN = PLL_CLK (generated on-chip)

100: CDIV_CLKIN = DAC_CLK (generated on-chip)

101: CDIV_CLKIN = DAC_MOD_CLK (generated on-chip)

110: Reserved

111: Reserved

Page 0 / Register 26 (0x1A): CLKOUT M_VAL

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

0: CLKOUT M divider is powered down.

1: CLKOUT M divider is powered up.

D6–D0

R/W

000 0001

000 0000: CLKOUT divider M = 128

000 0001: CLKOUT divider M = 1

000 0010: CLKOUT divider M = 2

...

111 1110: CLKOUT divider M = 126

111 1111: CLKOUT divider M = 127

Page 0 / Register 27 (0x1B): Codec Interface Control 1

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D6

R/W

00

00: Codec interface = I²S

01: Codec Interface = DSP

10: Codec interface = RJF

11: Codec interface = LJF

D5–D4

R/W

00

00: Codec interface word length = 16 bits

01: Codec interface word length = 20 bits

10: Codec interface word length = 24 bits

11: Codec interface word length = 32 bits

D3

D2

R/W

0

0: BCLK is input.

1: BCLK is output.

0: WCLK is input.

1: WCLK is output.

D1–D0

00

Reserved

Page 0 / Register 28 (0x1C): Data-Slot Offset Programmability

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R/W

0000 0000

Offset (Measured With Respect to WCLK Rising Edge in DSP Mode)

0000 0000: Offset = 0 BCLKs

0000 0001: Offset = 1 BCLK

0000 0010: Offset = 2 BCLKs

...

1111 1110: Offset = 254 BCLKs

1111 1111: Offset = 255 BCLKs

REGISTER MAP

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Page 0 / Register 29 (0x1D): Codec Interface Control 2

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D4

D3

R/W

0000

0

Reserved

0: BCLK is not inverted (valid for both primary and secondary BCLK).

1: BCLK is inverted (valid for both primary and secondary BCLK).

D2

R/W

0

BCLK and WCLK Active Even With Codec Powered Down (Valid for Both Primary and Secondary

BCLK)

0: Disabled

1: Enabled

D1–D0

R/W

00

00: BDIV_CLKIN = DAC_CLK (generated on-chip)

01: BDIV_CLKIN = DAC_MOD_CLK (generated on-chip)

10: Reserved

11: Reserved

Page 0 / Register 30 (0x1E): BCLK N_VAL

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

0: BCLK N-divider is powered down.

1: BCLK N-divider is powered up.

D6–D0

R/W

000 0001

000 0000: BCLK divider N = 128

000 0001: BCLK divider N = 1

000 0010: BCLK divider N = 2

...

111 1110: BCLK divider N = 126

111 1111: BCLK divider N = 127

Page 0 / Register 31 (0x1F): Codec Secondary Interface Control 1

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D5

R/W

000

00

000: Secondary BCLK is obtained from the GPIO1 pin.

001: Secondary BCLK is not obtained from the GPIO1 pin.

010–111: Reserved

D4–D2

D1–D0

000: Secondary WCLK is obtained from the GPIO1 pin.

001: Secondary WCLK is not obtained from the GPIO1 pin.

010–111: Reserved

00: Secondary DIN is obtained from the GPIO1 pin.

01: Secondary DIN is not obtained from the GPIO1 pin.

10–11: Reserved

Page 0 / Register 32 (0x20): Codec Secondary Interface Control 2

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D4

D3

R/W

0000

0

Reserved

0: Primary BCLK is fed to codec serial-interface and ClockGen blocks.

1: Secondary BCLK is fed to codec serial-interface and ClockGen blocks.

D2

R/W

0

0: Primary WCLK is fed to codec serial-interface block.

1: Secondary WCLK is fed to codec serial-interface block.

D1

D0

R/W

0

Reserved

0: Primary DIN is fed to codec serial-interface block.

1: Secondary DIN is fed to codec serial-interface block.

68

REGISTER MAP

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Page 0 / Register 33 (0x21): Codec Secondary Interface Control 3

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

0: Primary BCLK output = internally generated BCLK clock

1: Primary BCLK output = secondary BCLK

D6

R/W

0

0: Secondary BCLK output = primary BCLK

1: Secondary BCLK output = internally generated BCLK clock

D5–D4

00

00: Primary WCLK output = internally generated DAC_f_S

01: Reserved

10: Primary WCLK output = secondary WCLK

11: Reserved

D3–D2

D1–D0

R/W

00

00: Secondary WCLK output = primary WCLK

01: Secondary WCLK output = internally generated DAC_f_Sclock

10: Reserved

11: Reserved

Reserved

Page 0 / Register 34 (0x22): I²C Bus Condition

DESCRIPTION

READ/

WRITE

RESET

VALUE

BIT

D7–D6

D5

R/W

00

0

Reserved. Write only the reset value to these bits.

0: I²C general-call address is ignored.

1: Device accepts I²C general-call address.

D4–D0

R/W

0 0000

Reserved. Write only zeros to these bits.

Page 0 / Register 35 (0x23) and Page 0 / Register 36 (0x24): Reserved

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R/W

XXXX XXXX Reserved. Write only zeros to these bits.

Page 0 / Register 37 (0x25): DAC Flag Register

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R

0

0: Left-channel DAC powered down

1: Left-channel DAC powered up

D6

D5

R/W

R

X

0

Reserved. Write only zero to this bit.

0: HPL driver powered down

1: HPL driver powered up

D4

D3

R

0

0: Left-channel class-D driver powered down

1: Left-channel class-D driver powered up

0: Right-channel DAC powered down

1: Right-channel DAC powered up

D2

D1

R/W

R

X

0

Reserved. Write only zero to this bit.

0: HPR driver powered down

1: HPR driver powered up

D0

R

0

0: Right-channel class-D driver powered down

1: Right-channel class-D driver powered up

Page 0 / Register 38 (0x26): DAC Flag Register

DESCRIPTION

READ/

WRITE

RESET

VALUE

BIT

D7–D5

D4

R/W

R

XXX

0

Reserved. Do not write to these bits.

0: Left-channel DAC PGA applied gain ≠ programmed gain

1: Left-channel DAC PGA applied gain = programmed gain

D3–D1

D0

R/W

R

XXX

0

Reserved. Write only zeros to these bits.

0: Right-channel DAC PGA applied gain ≠ programmed gain

1: Right-channel DAC PGA applied gain = programmed gain

REGISTER MAP

69

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Page 0 / Register 39 (0x27): Overflow Flags

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7⁽¹⁾

R

0

Left-Channel DAC Overflow Flag

0: Overflow has not occurred.

1: Overflow has occurred.

D6⁽¹⁾

D5⁽¹⁾

R

0

Right-Channel DAC Overflow Flag

0: Overflow has not occurred.

1: Overflow has occurred.

R

DAC Barrel Shifter Output Overflow Flag

0: Overflow has not occurred.

1: Overflow has occurred.

D4–D0

R/W

0 0000

Reserved

(1) Sticky flag bits. These are read-only bits. They are automatically cleared once they are read and are set only if the source trigger occurs

again.

Page 0 / Register 40 (0x28) Through Page 0 / Register 43 (0x2B): Reserved

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R/W

XXXX XXXX Reserved. Write only the reset value to these bits.

Page 0 / Register 44 (0x2C): DAC Interrupt Flags (Sticky Bits)

READ/

WRITE

RESET

BIT

DESCRIPTION

VALUE

D7⁽¹⁾

R

0

0: No short circuit is detected at HPL/left class-D driver.

1: Short circuit is detected at HPL/left class-D driver.

D6⁽¹⁾

D5⁽¹⁾

D4⁽¹⁾

D3⁽¹⁾

D2⁽¹⁾

D1–D0

0

0: No short circuit is detected at HPR/right class-D driver.

1: Short circuit is detected at HPR/right class-D driver.

X

0

0: No headset button pressed

1: Headset button pressed

0: No headset insertion/removal is detected.

1: Headset insertion/removal is detected.

0: Left DAC signal power is ≤ the signal threshold of DRC.

1: Left DAC signal power is > the signal threshold of DRC.

0

0: Right DAC signal power is ≤ the signal threshold of DRC.

1: Right DAC signal power is > the signal threshold of DRC.

00

Reserved

(1) Sticky flag bits. These are read-only bits. They are automatically cleared once they are read and are set only if the source trigger occurs

again.

Page 0 / Register 45 (0x2D): Reserved

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R/W

0000 0000 Reserved. Write only reset value to these bits.

70

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Page 0 / Register 46 (0x2E): DAC Interrupt Flags

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R

0

0: No short circuit detected at HPL/left class-D driver

1: Short circuit detected at HPL/left class-D driver

D6

D5

R

0

0: No short circuit detected at HPR/right class-D driver

1: Short circuit detected at HPR/right class-D driver

X

0

0: No headset button pressed

1: Headset button pressed

D4

0: Headset removal detected

1: Headset insertion detected

D3

0: Left DAC signal power is ≤ the signal threshold of the DRC.

1: Left DAC signal power is > the signal threshold of the DRC.

D2

0

0: Right DAC signal power is ≤ the signal threshold of the DRC.

1: Right DAC signal power is > the signal threshold of the DRC.

D1–D0

00

Reserved

Page 0 / Register 47 (0x2F): Reserved

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R/W

0000 0000 Reserved. Write only the reset value to these bits.

Page 0 / Register 48 (0x30): INT1 Control Register

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

0: Headset-insertion detect interrupt is not used in the generation of INT1 interrupt.

1: Headset-insertion detect interrupt is used in the generation of INT1 interrupt.

D6

D5

0: Button-press detect interrupt is not used in the generation of INT1 interrupt.

1: Button-press detect interrupt is used in the generation of INT1 interrupt.

0: DAC DRC signal-power interrupt is not used in the generation of INT1 interrupt.

1: DAC DRC signal-power interrupt is used in the generation of INT1 interrupt.

D4

D3

R/W

0

Reserved

0: Short-circuit interrupt is not used in the generation of INT1 interrupt.

1: Short-circuit interrupt is used in the generation of INT1 interrupt.

D2

R/W

0

0: DAC data overflow does not result in a. INT1 interrupt.

1: DAC data overflow results in an INT1 interrupt.

D1

D0

R/W

0

Reserved

0: INT1 is only one pulse (active-high) of typical 2-ms duration.

1: INT1 is multiple pulses (active-high) of typical 2-ms duration and 4-ms period, until page 0 / register

44 is read by the user.

Page 0 / Register 49 (0x31): INT2 Control Register

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

0: Headset-insertion detect interrupt is not used in the generation of INT2 interrupt.

1: Headset-insertion detect interrupt is used in the generation of INT2 interrupt.

D6

D5

0: Button-press detect interrupt is not used in the generation of INT2 interrupt.

1: Button-press detect interrupt is used in the generation of INT2 interrupt.

0: DAC DRC signal-power interrupt is not used in the generation of INT2 interrupt.

1: DAC DRC signal-power interrupt is used in the generation of INT2 interrupt.

D4

D3

R/W

0

Reserved

0: Short-circuit interrupt is not used in the generation of INT2 interrupt.

1: Short-circuit interrupt is used in the generation of INT2 interrupt.

D2

R/W

0

0: DAC data overflow does not result in an INT2 interrupt.

1: DAC data overflow results in an INT2 interrupt.

D1

D0

R/W

0

Reserved

0: INT2 is only one pulse (active-high) of typical 2-ms duration.

1: INT2 is multiple pulses (active-high) of typical 2-ms duration and 4-ms period, until page 0 / register

44 is read by the user.

REGISTER MAP

71

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Page 0 / Register 50 (0x32): Reserved

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7-D0

R/W

0000 0000 Reserved. Write only reset values.

Page 0 / Register 51 (0x33): GPIO1 In/Out Pin Control

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D6

D5–D2

R/W

XX

Reserved. Do not write any value other than reset value.

0000

0000: GPIO1 disabled (input and output buffers powered down)

0001: GPIO1 is in input mode (can be used as secondary BCLK input, secondary WCLK input,

secondary DIN input, or in ClockGen block).

0010: GPIO1 is used as general-purpose input (GPI).

0011: GPIO1 output = general-purpose output

0100: GPIO1 output = CLKOUT output

0101: GPIO1 output = INT1 output

0110: GPIO1 output = INT2 output

0111: Reserved

1000: GPIO1 output = secondary BCLK output for codec interface

1001: GPIO1 output = secondary WCLK output for codec interface

1010: Reserved

1011: Reserved

1100: Reserved

1101: Reserved

1110: Reserved

1111: Reserved

D1

D0

R

X

0

GPIO1 input buffer value

R/W

0: GPIO1 general-purpose output value = 0

1: GPIO1 general-purpose output value = 1

Page 0 / Register 52 (0x34): Reserved

DESCRIPTION

READ/

WRITE

RESET

VALUE

BIT

D7–D0

R/W

XX

Reserved. Do not write any value other than reset value.

Page 0 / Register 53 (0x35): Reserved

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R/W

0000 0000 Reserved

Page 0 / Register 54 (0x36): DIN (IN Pin) Control

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D3

D2–D1

R/W

0000 0

01

Reserved

00: DIN disabled (input buffer powered down)

01: DIN enabled (can be used as DIN for codec interface, Dig_Mic_In or in ClockGen block)

10: DIN is used as general-purpose input (GPI)

11: Reserved

D0

R

X

DIN input-buffer value

Page 0 / Register 55 (0x37) Through Page 0 / Register 59 (0x3B): Reserved

READ/

WRITE

RESET

BIT

DESCRIPTION

VALUE

D7–D0

R

XXXX XXXX Reserved. Do not write to these bits.

72

REGISTER MAP

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Page 0 / Register 60 (0x3C): DAC Processing Block Selection

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D5

D4–D0

R/W

000

Reserved. Write only default value.

0 0000: Reserved. Do not use.

R/W

00 0001

0 0001: DAC Signal Processing Block PRB_P1

0 0010: DAC Signal Processing Block PRB_P2

0 0011: DAC Signal Processing Block PRB_P3

0 0100: DAC Signal Processing Block PRB_P4

...

1 1000: DAC Signal Processing Block PRB_P24

1 1001: DAC Signal Processing Block PRB_P25

1 1010–1 1111: Reserved. Do not use.

Page 0 / Register 61–62: Reserved

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R

XXXX XXXX Reserved. Do not write.

Page 0 / Register 63 (0x3F): DAC Data-Path Setup

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

0: Left-channel DAC is powered down.

1: Left-channel DAC is powered up.

D6

0

0: Right-channel DAC is powered down.

1: Right-channel DAC is powered up.

D5–D4

01

00: Left-channel DAC data path = off

01: Left-channel DAC data path = left data

10: Left-channel DAC data path = right data

11: Left-channel DAC data path = left-channel and right-channel data ((L + R)/2)

D3–D2

D1–D0

R/W

01

00

00: Right-channel DAC data path = off

01: Right-channel DAC data path = right data

10: Right-channel DAC data path = left data

11: Right-channel DAC data path = left-channel and right-channel data ((L + R)/2)

00: DAC channel volume control soft-stepping is enabled for one step per sample period.

01: DAC channel volume control soft-stepping is enabled for one step per two sample periods.

10: DAC channel volume control soft-stepping is disabled.

11: Reserved. Do not write this sequence to these bits.

Page 0 / Register 64 (0x40): DAC VOLUME CONTROL

DESCRIPTION

READ/

WRITE

RESET

VALUE

BIT

D7–D4

D3

R/W

0000

1

Reserved. Write only zeros to these bits.

0: Left-channel DAC not muted

1: Left-channel DAC muted

D2

R/W

1

0: Right-channel DAC not muted

1: Right-channel DAC muted

D1–D0

00⁽¹⁾

00: Left and right channels have independent volume control.

01: Left-channel volume control Is the programmed value of right-channel volume control.

10: Right-channel volume control is the programmed value of left-channel volume control.

11: Same as 00

(1) When DRC is enabled, left and right channel volume controls are always independent. Program bits D1–D0 to 00.

REGISTER MAP

73

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Page 0 / Register 65 (0x41): DAC Left Volume Control

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R/W

0000 0000

Left DAC Channel Digital Volume Control Setting

0111 1111–0011 0001: Reserved. Do not use

0011 0000: Digital volume control = 24 dB

0010 1111: Digital volume control = 23.5 dB

0010 1110: Digital volume control = 23 dB

...

0000 0001: Digital volume control = 0.5 dB

0000 0000: Digital volume control = 0 dB

1111 1111: Digital volume control = –0.5 dB

...

1000 0010: Digital volume control = –63 dB

1000 0001: Digital volume control = –63.5 dB

1000 0000: Reserved

Page 0 / Register 66 (0x42): DAC Right Volume Control

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R/W

0000 0000

Right DAC Channel Digital Volume Control Setting

0111 1111–0011 0001: Reserved. Do not use

0011 0000: Digital volume control = 24 dB

0010 1111: Digital volume control = 23.5 dB

0010 1110: Digital volume control = 23 dB

...

0000 0001: Digital volume control = 0.5 dB

0000 0000: Digital volume control = 0 dB

1111 1111: Digital volume control = –0.5 dB

...

1000 0010: Digital volume control = –63 dB

1000 0001: Digital volume control = –63.5 dB

1000 0000: Reserved

Page 0 / Register 67 (0x43): Headset Detection

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

0: Headset detection disabled

1: Headset detection enabled

D6–D5

D4–D2

R

XX

00: No headset detected

01: Headset without microphone is detected

10: Reserved

11: Headset with microphone is detected

R/W

000

Debounce Programming for Glitch Rejection During Headset Detection⁽¹⁾

000: 16 ms (sampled with 2-ms clock)

001: 32 ms (sampled with 4-ms clock)

010: 64 ms (sampled with 8-ms clock)

011: 128 ms (sampled with 16-ms clock)

100: 256 ms (sampled with 32-ms clock)

101: 512 ms (sampled with 64-ms clock)

110: Reserved

111: Reserved

D1–D0

R/W

00

Debounce Programming for Glitch Rejection During Headset Button-Press Detection

00: 0 ms

01: 8 ms (sampled with 1-ms clock)

10: 16 ms (sampled with 2-ms clock)

11: 32 ms (sampled with 4-ms clock)

(1) Note that these times are generated using the 1 MHz reference clock which is defined in page 3 / register 16.

74

REGISTER MAP

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Page 0 / Register 68 (0x44): DRC Control 1

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

D6

R/W

0

Reserved. Write only the reset value to these bits.

R/W

0: DRC disabled for left channel

1: DRC enabled for left channel

D5

R/W

0

0: DRC disabled for right channel

1: DRC enabled for right channel

D4–D2

011

000: DRC threshold = –3 dB

001: DRC threshold = –6 dB

010: DRC threshold = –9 dB

011: DRC threshold = –12 dB

100: DRC threshold = –15 dB

101: DRC threshold = –18 dB

110: DRC threshold = –21 dB

111: DRC threshold = –24 dB

D1–D0

R/W

11

00: DRC hysteresis = 0 dB

01: DRC hysteresis = 1 dB

10: DRC hysteresis = 2 dB

11: DRC hysteresis = 3 dB

Page 0 / Register 69 (0x45): DRC Control 2

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D

R

0

Reserved. Write only the reset value to these bits.

D6–D3

R/W

0111

DRC Hold Programmability

0000: DRC hold disabled

0001:DRC hold time = 32 DAC word clocks

0010: DRC hold time = 64 DAC word clocks

0011: DRC hold time = 128 DAC word clocks

0100: DRC hold time = 256 DAC word clocks

0101: DRC hold time = 512 DAC word clocks

...

1110: DRC hold time = 4 × 32,768 DAC word clocks

1111: DRC hold time = 5 × 32,768 DAC word clocks

D2–D0

R

000

Reserved. Write only the reset value to these bits.

Page 0 / Register 70 (0x46): DRC Control 3

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D4

R/W

0000

0000: DRC attack rate = 4 dB per DAC word clock

0001: DRC attack rate = 2 dB per DAC word clock

0010: DRC attack rate = 1 dB per DAC word clock

...

1110: DRC attack rate = 2.4414e–5 dB per DAC word clock

1111: DRC attack rate = 1.2207e–5 dB per DAC word clock

D3–D0

R/W

0000

0000: DRC decay rate = 1.5625e–2 dB per DAC word clock

0001: DRC decay rate = 7.8125e–3 dB per DAC word clock

0010: DRC decay rate = 3.9062e–3 dB per DAC word clock

...

1110: DRC decay rate = 9.5367e–7 dB per DAC word clock

1111: DRC decay rate = 4.7683e–7 dB per DAC word clock

REGISTER MAP

75

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(1)

Page 0 / Register 71 (0x47): Left Beep Generator

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

0: Beep generator is disabled.

1: Beep generator is enabled (self-clearing based on beep duration).

D6

R/W

0

Reserved. Write only reset value.

D5–D0

00 0000

00 0000: Left-channel beep volume control = 2 dB

00 0001: Left-channel beep volume control = 1 dB

00 0010: Left-channel beep volume control = 0 dB

00 0011: Left-channel beep volume control = –1 dB

...

11 1110: Left-channel beep volume control = –60 dB

11 1111: Left-channel beep volume control = –61 dB

(1) The beep generator is only available in PRB_P25 DAC processing mode.

Page 0 / Register 72 (0x48): Right Beep Generator⁽¹⁾

DESCRIPTION

READ/

WRITE

RESET

VALUE

BIT

D7–D6

R/W

00

00: Left and right channels have independent beep volume control.

01: Left-channel beep volume control is the programmed value of right-channel beep volume control.

10: Right-channel beep volume control is the programmed value of left-channel beep volume control.

11: Same as 00

D5–D0

R/W

00 0000

00 0000: Right-channel beep volume control = 2 dB

00 0001: Right-channel beep volume control = 1 dB

00 0010: Right-channel beep volume control = 0 dB

00 0011: Right-channel beep volume control = –1 dB

...

11 1110: Right-channel beep volume control = –60 dB

11 1111: Right-channel beep volume control = –61 dB

(1) The beep generator is only available in PRB_P25 DAC processing mode.

Page 0 / Register 73 (0x49): Beep Length MSB

DESCRIPTION

READ/

WRITE

RESET

VALUE

BIT

D7–D0

R/W

0000 0000

8 MSBs out of 24 bits for the number of samples for which the beep must be generated.

Page 0 / Register 74 (0x4A): Beep Length Middle Bits

DESCRIPTION

READ/

WRITE

RESET

VALUE

BIT

D7–D0

R/W

0000 0000

8 middle bits out of 24 bits for the number of samples for which the beep must be generated.

Page 0 / Register 75 (0x4B): Beep Length LSB

DESCRIPTION

READ/

WRITE

RESET

VALUE

BIT

D7–D0

R/W

1110 1110

8 LSBs out of 24 bits for the number of samples for which beep need to be generated.

Page 0 / Register 76 (0x4C): Beep Sin(x) MSB

DESCRIPTION

READ/

WRITE

RESET

VALUE

BIT

D7–D0

R/W

0001 0000

8 MSBs out of 16 bits for sin(2π × f_in/f_S), where f_inis the beep frequency and f_Sis the DAC sample rate.

Page 0 / Register 77 (0x4D): Beep Sin(x) LSB

DESCRIPTION

READ/

WRITE

RESET

VALUE

BIT

D7–D0

R/W

1101 1000

8 LSBs out of 16 bits for sin(2π × f_in/f_S), where f_inis the beep frequency and f_Sis the DAC sample rate.

Page 0 / Register 78 (0x4E): Beep Cos(x) MSB

DESCRIPTION

READ/

WRITE

RESET

VALUE

BIT

D7–D0

R/W

0111 1110

8 MSBs out of 16 bits for cos(2π × f_in/f_S), where f_inis the beep frequency and f_Sis the DAC sample rate.

76

REGISTER MAP

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Page 0 / Register 79 (0x4F): Beep Cos(x) LSB

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R/W

1110 0011

8 LSBs out of 16 bits for cos(2π × f_in/f_S), where f_inis the beep frequency and f_Sis the DAC sample rate.

Page 0 / Register 80 (0x50) Through Page 0 / Register 115 (0x73): Reserved

READ/

WRITE

RESET

BIT

DESCRIPTION

VALUE

D7–D0

R/W

XXXX XXXX Reserved. Do not write to these registers.

Page 0 / Register 116 (0x74): VOL/MICDET-Pin SAR ADC – Volume Control

READ/

WRITE

RESET

BIT

DESCRIPTION

VALUE

D7

R/W

0

0: DAC volume control is controlled by control register. (7-bit Vol ADC is powered down)

1: DAC volume control is controlled by pin.

D6

0

0: Internal on-chip RC oscillator is used for the 7-bit Vol ADC for pin volume control.

1: MCLK is used for the 7-bit Vol ADC for pin volume control.

D5–D4

00

00: No hysteresis for volume control ADC output

01: Hysteresis of ±1 bit

10: Hysteresis of ±2 bits

11: Reserved. Do not write this sequence to these bits.

D3

R/W

0

Reserved. Write only reset value.

D2–D0

000

Throughput of the 7-bit Vol ADC for pin volume control, frequency based on MCLK or internal oscillator.

MCLK = 12 MHz

Internal Oscillator Source

000: Throughput =

001: Throughput =

010: Throughput =

011: Throughput =

100: Throughput =

101: Throughput =

110: Throughput =

111: Throughput =

15.625 Hz

31.25 Hz

62.5 Hz

125 Hz

250 Hz

500 Hz

1 kHz

10.68 Hz

21.35 Hz

42.71 Hz

8.2 Hz

170 Hz

340 Hz

680 Hz

1.37 kHz

2 kHz

Note: These values are based on a nominal oscillator

frequency of 8.2 MHz. The values scale according to

the actual oscillator frequency.

Page 0 / Register 117 (0x75): VOL/MICDET-Pin Gain

DESCRIPTION

READ/

WRITE

RESET

VALUE

BIT

D7

R

0

Reserved. Write only zero to this bit.

D6–D0

XXX XXXX 000 0000: Gain applied by pin volume control = 18 dB

000 0001: Gain applied by pin volume control = 17.5 dB

000 0010: Gain applied by pin volume control = 17 dB

...

010 0011: Gain applied by pin volume control = 0.5 dB

010 0100: Gain applied by pin volume control = 0 dB

010 0101: Gain applied by pin volume control = –0.5 dB

...

101 1001: Gain applied by pin volume control = –26.5 dB

101 1010: Gain applied by pin volume control = –27 dB

101 1011: Gain applied by pin volume control = –28 dB

...

111 1101: Gain applied by pin volume control = –62 dB

111 1110: Gain applied by pin volume control = –63 dB

111 1111: Reserved.

Page 0 / Register 118 (0x76) Through Page 0 / Register 127 (0x7F): Reserved

READ/

WRITE

RESET

BIT

DESCRIPTION

VALUE

D7–D0

R/W

XXXX XXXX Reserved. Do not write to these registers.

REGISTER MAP

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6.3 Control Registers, Page 1: DAC, Power-Controls and MISC Logic-Related

Programmabilities

Page 1 / Register 0 (0x00): Page Control Register

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R/W

0000 0000

0000 0000: Page 0 selected

0000 0001: Page 1 selected

...

1111 1110: Page 254 selected

1111 1111: Page 255 selected

Page 1 / Register 1 (0x01) Through Page 1 / Register 29 (0x1D): Reserved

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R/W

XXXX XXXX Reserved. Do not write to these registers.

Page 1 / Register 30 (0x1E): Headphone and Speaker Amplifier Error Control

READ/

WRITE

RESET

BIT

DESCRIPTION

VALUE

D7–D2

D1

R/W

0000 00

0

Reserved

0: Reset HPL and HPR power-up control bits on short-circuit detection if page 1 / register 31, D1 = 1.

1: HPL and HPR power-up control bits remain unchanged on short-circuit detection.

D0

R/W

0

0: Reset SPL and SPR power-up control bits on short-circuit detection.

1: SPL and SPR power-up control bits remain unchanged on short-circuit detection.

Page 1 / Register 31 (0x1F): Headphone Drivers

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

0: HPL output driver is powered down.

1: HPL output driver is powered up.

D6

R/W

0

0: HPR output driver is powered down.

1: HPR output driver is powered up.

D5

R/W

0

Reserved. Write only zero to this bit.

D4–D3

00: Output common-mode voltage = 1.35 V

01: Output common-mode voltage = 1.5 V

10: Output common-mode voltage = 1.65 V

11: Output common-mode voltage = 1.8 V

D2

D1

R/W

1

0

Reserved. Write only 1 to this bit.

0: If short-circuit protection is enabled for headphone driver and short circuit is detected, device limits

the

maximum current to the load.

1: If short-circuit protection is enabled for headphone driver and short circuit is detected, device powers

down the output driver.

D0

R

0

0: Short circuit is not detected on the headphone driver.

1: Short circuit is detected on the headphone driver.

Page 1 / Register 32 (0x20): Class-D Speaker Amplifier

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

0: Left-channel class-D output driver is powered down.

1: Left-channel class-D output driver is powered up.

D6

R/W

0

0: Right-channel class-D output driver is powered down.

1: Right-channel class-D output driver is powered up.

D5–D1

D0

R/W

R

00 011

0

Reserved. Write only the reset value to this bit.

0: Short circuit is not detected on the class-D driver. Valid only if class-D amplifier is powered up. For

short-circuit flag sticky bit, see page 0 / register 44.

1: Short circuit is detected on the class-D driver. Valid only if class-D amplifier is powered up. For short-

circuit flag sticky bit, see page 0 / register 44.

78

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Page 1 / Register 33 (0x21): HP Output Drivers POP Removal Settings

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

0: If power-down sequence is activated by device software, power down using page 1 / register 46, bit

D7, then power down the DAC simultaneously with the HP and SP amplifiers.

1: If power-down sequence is activated by device software, power down using page 1 / register 46, bit

D7, then power down DAC only after HP and SP amplifiers are completely powered down. This is to

optimize power-down POP.

D6–D3

R/W

0111

0000: Driver power-on time = 0 μs

0001: Driver power-on time = 15.3 μs

0010: Driver power-on time = 153 μs

0011: Driver power-on time = 1.53 ms

0100: Driver power-on time = 15.3 ms

0101: Driver power-on time = 76.2 ms

0110: Driver power-on time = 153 ms

0111: Driver power-on time = 304 ms

1000: Driver power-on time = 610 ms

1001: Driver power-on time = 1.22 s

1010: Driver power-on time = 3.04 s

1011: Driver power-on time = 6.1 s

1100–1111: Reserved. Do not write these sequences to these bits.

NOTE: These values are based on typical oscillator frequency of 8.2 MHz. Scale according to the actual

oscillator frequency.

D2–D1

R/W

11

0

00: Driver ramp-up step time = 0 ms

01: Driver ramp-up step time = 0.98 ms

10: Driver ramp-up step time = 1.95 ms

11: Driver ramp-up step time = 3.9 ms

NOTE: These values are based on typical oscillator frequency of 8.2 MHz. Scale according to the actual

oscillator frequency.

D0

0: Weakly driven output common-mode voltage is generated from resistor divider of the AVDD supply.

1: Reserved.

Page 1 / Register 34 (0x22): Output Driver PGA Ramp-Down Period Control

READ/

WRITE

RESET

BIT

DESCRIPTION

VALUE

D7

R/W

0

Reserved. Write only the reset value to this bit.

D6–D4

000

Speaker Power-Up Wait Time (Duration Based on Using Internal Oscillator)

000: Wait time = 0 ms

001: Wait time = 3.04 ms

010: Wait time = 7.62 ms

011: Wait time = 12.2 ms

100: Wait time = 15.3 ms

101: Wait time = 19.8 ms

110: Wait time = 24.4 ms

111: Wait time = 30.5 ms

NOTE: These values are based on typical oscillator frequency of 8.2 MHz. The values scale according

to the actual oscillator frequency.

D3–D0

R/W

0000

Reserved. Write only the reset value to these bits.

REGISTER MAP

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Page 1 / Register 35 (0x23): DAC_L and DAC_R Output Mixer Routing

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D6

R/W

00

00: DAC_L is not routed anywhere.

01: DAC_L is routed to the left-channel mixer amplifier.

10: DAC_L is routed directly to the HPL driver.

11: Reserved

D5

D4

R/W

0

0: AIN1 input is not routed to the left-channel mixer amplifier.

1: AIN1 input is routed to the left-channel mixer amplifier.

0: AIN2 input is not routed to the left-channel mixer amplifier.

1: AIN2 input is routed to the left-channel mixer amplifier.

D3–D2

R/W

00

00: DAC_R is not routed anywhere.

01: DAC_R is routed to the right-channel mixer amplifier.

10: DAC_R is routed directly to the HPR driver.

11: Reserved

D1

D0

R/W

0

0: AIN2 input is not routed to the right-channel mixer amplifier.

1: AIN2 input is routed to the right-channel mixer amplifier.

0: HPL driver output is not routed to the HPR driver.

1: HPL driver output is routed to the HPR driver input (used for differential output mode).

Page 1 / Register 36 (0x24): Left Analog Vol to HPL

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

0: Left-channel analog volume control is not routed to HPL output driver.

1: Left-channel analog volume control is routed to HPL output driver.

D6–D0

R/W

111 1111

Left-channel analog volume control gain (non-linear) for the HPL output driver, 0 dB to –78 dB. See

Table 5-24.

Page 1 / Register 37 (0x25): Right Analog Vol to HPR

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

0: Right-channel analog volume control is not routed to HPR output driver.

1: Right-channel analog volume control is routed to HPR output driver.

D6–D0

R/W

111 1111

Right-channel analog volume control gain (non-linear) for the HPR output driver, 0 dB to –78 dB. See

Table 5-24.

Page 1 / Register 38 (0x26): Left Analog Vol to SPL

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

0: Left-channel analog volume control output is not routed to left-channel class-D output driver.

1: Left-channel analog volume control output is routed to left-channel class-D output driver.

D6–D0

R/W

111 1111

Left-channel analog volume control output gain (non-linear) for the left-channel class-D output driver,

0 dB to –78 dB. See Table 5-24.

Page 1 / Register 39 (0x27): Right Analog Vol to SPR

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

0: Right-channel analog volume control output is not routed to right-channel class-D output driver.

1: Right-channel analog volume control output is routed to right-channel class-D output driver.

D6–D0

R/W

111 1111

Right-channel analog volume control output gain (non-linear) for the right-channel class-D output driver,

0 dB to –78 dB. See and Table 5-24.

80

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Page 1 / Register 40 (0x28): HPL Driver

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

Reserved. Write only zero to this bit.

D6–D3

R/W

0000

0000: HPL driver PGA = 0 dB

0001: HPL driver PGA = 1 dB

0010: HPL driver PGA = 2 dB

...

1000: HPL driver PGA = 8 dB

1001: HPL driver PGA = 9 dB

1010–1111: Reserved. Do not write these sequences to these bits.

D2

D1

D0

R/W

R

0

1

0

0: HPL driver is muted.

1: HPL driver is not muted.

0: HPL driver is weakly driven to a common mode during power down.⁽¹⁾

1: HPL driver is high-impedance during power down.

0: Not all programmed gains to HPL have been applied yet.

1: All programmed gains to HPL have been applied.

(1) If D1 is programmed as 0, Page 1 / Register 33 D0 must be set to 0.

Page 1 / Register 41 (0x29): HPR Driver

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

Reserved. Write only zero to this bit.

D6–D3

0000

0000: HPR driver PGA = 0 dB

0001: HPR driver PGA = 1 dB

0010: HPR driver PGA = 2 dB

...

1000: HPR driver PGA = 8 dB

1001: HPR driver PGA = 9 dB

1010–1111: Reserved. Do not write these sequences to these bits.

D2

D1

D0

R/W

R

0

1

0

0: HPR driver is muted.

1: HPR driver is not muted.

0: HPR driver is weakly driven to a common mode during power down.⁽¹⁾

1: HPR driver is high-impedance during power down.

0: Not all programmed gains to HPR have been applied yet.

1: All programmed gains to HPR have been applied.

(1) If D1 is programmed as 0, Page 1 / Register 33 D0 must be set to 0.

Page 1 / Register 42 (0x2A): SPL Driver

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D5

D4–D3

R/W

000

00

Reserved. Write only zeros to these bits.

00: Left-channel class-D driver output stage gain = 6 dB

01: Left-channel class-D driver output stage gain = 12 dB

10: Left-channel class-D driver output stage gain = 18 dB

11: Left-channel class-D driver output stage gain = 24 dB

D2

R/W

0

0: Left-channel class-D driver is muted.

1: Left-channel class-D driver is not muted.

D1

D0

R/W

R

0

Reserved. Write only zero to this bit.

0: Not all programmed gains to left-channel class-D driver have been applied yet.

1: All programmed gains to left-channel class-D driver have been applied.

REGISTER MAP

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Page 1 / Register 43 (0x2B): SPR Driver

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D5

D4–D3

R/W

000

00

Reserved. Write only zeros to these bits.

00: Right-channel class-D driver output stage gain = 6 dB

01: Right-channel class-D driver output stage gain = 12 dB

10: Right-channel class-D driver output stage gain = 18 dB

11: Right-channel class-D driver output stage gain = 24 dB

D2

R/W

0

0: Right-channel class-D driver is muted.

1: Right-channel class-D driver is not muted.

D1

D0

R/W

R

0

Reserved. Write only zero to this bit.

0: Not all programmed gains to right-channel class-D driver have been applied yet.

1: All programmed gains to right-channel class-D driver have been applied.

Page 1 / Register 44 (0x2C): HP Driver Control

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D5

R/W

000

Debounce Time for Headset Short-Circuit Detection

MCLK/DIV (Page 3 /

register 16) = 1-MHz Internal Oscillator Source

(1)

Source

000: Debounce time =

001: Debounce time =

010: Debounce time =

011: Debounce time =

100: Debounce time =

101: Debounce time =

110: Debounce time =

111: Debounce time =

0 μs

8 μs

0 μs

7.8 μs

16 μs

32 μs

64 μs

128 μs

256 μs

512 μs

15.6 μs

31.2 μs

62.4 μs

124.9 μs

250 μs

500 μs

Note: These values are based on a nominal oscillator

frequency of 8.2 MHz. The values scale according to

the actual oscillator frequency.

D4–D3

R/W

00

00: Default mode for the DAC

01: DAC performance increased by increasing the current

10: Reserved

11: DAC performance increased further by increasing the current again

D2

D1

D0

R/W

0

0: HPL output driver is programmed as headphone driver.

1: HPL output driver is programmed as lineout driver.

0: HPR output driver is programmed as headphone driver.

1: HPR output driver is programmed as lineout driver.

Reserved. Write only zero to this bit.

(1) The clock used for the debounce has a clock period = debounce duration/8.

Page 1 / Register 45 (0x2D): Reserved

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R/W

XXXX XXXX Reserved. Do not write to these registers.

Page 1 / Register 46 (0x2E): MICBIAS

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

0: Device software power down is not enabled.

1: Device software power down is enabled.

Reserved. Write only zeros to these bits.

D6–D4

D3

R/W

000

0

0: Programmed MICBIAS is not powered up if headset detection is enabled but headset is not inserted.

1: Programmed MICBIAS is powered up even if headset is not inserted.

D2

R/W

0

Reserved. Write only zero to this bit.

D1–D0

00

00: MICBIAS output is powered down.

01: MICBIAS output is powered to 2 V.

10: MICBIAS output is powered to 2.5 V.

11: MICBIAS output is powered to AVDD.

82

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Page 1 / Register 47 (0x2F) Through Page 1 / Register 49 (0x31): Reserved

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R

XXXX XXXX Reserved. Do not write to these bits.

Page 1 / Register 50 (0x32): Input CM Settings

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

0

0: AIN1 input is floating if it is not used for analog bypass.

1: AIN1 input is connected to CM internally if it is not used for analog bypass.

D6

0

0: AIN2 input is floating if it is not used for analog bypass.

1: AIN2 input is connected to CM internally if it is not used for analog bypass.

D5–D0

000000

Reserved. Write only zeros to these bits.

Page 1 / Register 51 (0x33) Through Page 1 / Register 127 (0x7F): Reserved

READ/

WRITE

RESET

BIT

DESCRIPTION

VALUE

D7–D0

R/W

XXXX XXXX Reserved. Write only the reset value to these bits.

6.4 Control Registers, Page 3: MCLK Divider for Programmable Delay Timer

Default values shown for this page only become valid 100 μs following a hardware or software reset.

Page 3 / Register 0 (0x00): Page Control Register

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R/W

0000 0000

0000 0000: Page 0 selected

0000 0001: Page 1 selected

...

1111 1110: Page 254 selected

1111 1111: Page 255 selected

The only register used in page 3 is register 16. The remaining page-3 registers are reserved and should

not be written to.

Page 3 / Register 16 (0x10): Timer Clock MCLK Divider

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7

R/W

1

0: Internal oscillator is used for programmable delay timer.

1: External MCLK⁽¹⁾is used for programmable delay timer.

D6–D0

R/W

0000 0001

MCLK Divider to Generate 1-MHz Clock for the Programmable Delay Timer

000 0000: MCLK divider = 128

000 0001: MCLK divider = 1

000 0010: MCLK divider = 2

...

111 1110: MCLK divider = 126

111 1111: MCLK divider = 127

(1) External clock is used only to control the delay programmed between the conversions and not used for doing the actual conversion. This

feature is provided in case a more accurate delay is desired, because the internal oscillator frequency varies from device to device.

6.5 Control Registers, Page 8: DAC Programmable Coefficients RAM Buffer A (1:63)

Default values shown for this page only become valid 100 μs following a hardware or software reset.

Page 8 / Register 0 (0x00): Page Control Register

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R/W

0000 0000

0000 0000: Page 0 selected

0000 0001: Page 1 selected

...

1111 1110: Page 254 selected

1111 1111: Page 255 selected

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Page 8 / Register 1 (0x01): DAC Coefficient RAM Control

DESCRIPTION

READ/

WRITE

RESET

VALUE

BIT

D7–D3

D2

R/W

0000 0

0

Reserved. Write only the reset value.

DAC Adaptive Filtering Control

0: Adaptive filtering disabled in DAC processing block

1: Adaptive filtering enabled in DAC processing block

D1

D0

R

0

DAC Adaptive Filter Buffer Control Flag

0: In adaptive filter mode, DAC processing block accesses DAC coefficient buffer A, and the external

control interface accesses DAC coefficient buffer B.

1: In adaptive filter mode, DAC processing block accesses DAC coefficient buffer B, and the external

control interface accesses DAC coefficient buffer A.

R/W

DAC Adaptive Filter Buffer Switch Control

0: DAC coefficient buffers are not switched at the next frame boundary.

1: DAC coefficient buffers are switched at the next frame boundary, if adaptive filtering mode is enabled.

This bit self-clears on switching.

The remaining page-8 registers are either reserved registers or are used for setting coefficients for the

various filters in the TLV320DAC3101. Reserved registers should not be written to.

The filter coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit

coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient is

interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. When

programming any coefficient value for a filter, the MSB register should always be written first, immediately

followed by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both

registers should be written in this sequence. Table 6-2 is a list of the page-8 registers, excepting the

previously described register 0.

Table 6-2. Page 8 DAC Buffer A Registers

REGISTER

NUMBER

RESET VALUE

REGISTER NAME

2 (0x02)

0111 1111

1111 1111

0000 0000

0111 1111

1111 1111

0000 0000

0111 1111

1111 1111

0000 0000

Coefficient N0(15:8) for left DAC-programmable biquad A

Coefficient N0(7:0) for left DAC-programmable biquad A

Coefficient N1(15:8) for left DAC-programmable biquad A

Coefficient N1(7:0) for left DAC-programmable biquad A

Coefficient N2(15:8) for left DAC-programmable biquad A

Coefficient N2(7:0) for left DAC-programmable biquad A

Coefficient D1(15:8) for left DAC-programmable biquad A

Coefficient D1(7:0) for left DAC-programmable biquad A

Coefficient D2(15:8) for left DAC-programmable biquad A

Coefficient D2(7:0) for left DAC-programmable biquad A

Coefficient N0(15:8) for left DAC-programmable biquad B

Coefficient N0(7:0) for left DAC-programmable biquad B

Coefficient N1(15:8) for left DAC-programmable biquad B

Coefficient N1(7:0) for left DAC-programmable biquad B

Coefficient N2(15:8) for left DAC-programmable biquad B

Coefficient N2(7:0) for left DAC-programmable biquad B

Coefficient D1(15:8) for left DAC-programmable biquad B

Coefficient D1(7:0) for left DAC-programmable biquad B

Coefficient D2(15:8) for left DAC-programmable biquad B

Coefficient D2(7:0) for left DAC-programmable biquad B

Coefficient N0(15:8) for left DAC-programmable biquad C

Coefficient N0(7:0) for left DAC-programmable biquad C

Coefficient N1(15:8) for left DAC-programmable biquad C

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

8 (0x08)

9 (0x09)

10 (0x0A)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

15 (0x0F)

16 (0x10)

17 (0x11)

18 (0x12)

19 (0x13)

20 (0x14)

21 (0x15)

22 (0x16)

23 (0x17)

24 (0x18)

84

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Table 6-2. Page 8 DAC Buffer A Registers (continued)

REGISTER

RESET VALUE

REGISTER NAME

NUMBER

25 (0x19)

26 (0x1A)

27 (0x1B)

28 (0x1C)

29 (0x1D)

30 (0x1E)

31 (0x1F)

32 (0x20)

33 (0x21)

34 (0x22)

35 (0x23)

36 (0x24)

37 (0x25)

38 (0x26)

39 (0x27)

40 (0x28)

41 (0x29)

42 (0x2A)

43 (0x2B)

44 (0x2C)

45 (0x2D)

46 (0x2E)

47 (0x2F)

48 (0x30)

49 (0x31)

50 (0x32)

51 (0x33)

52 (0x34)

53 (0x35)

54 (0x36)

55 (0x37)

56 (0x38)

57 (0x39)

58 (0x3A)

59 (0x3B)

60 (0x3C)

61 (0x3D)

62 (0x3E)

63 (0x3F)

64 (0x40)

65 (0x41)

66 (0x42)

67 (0x43)

68 (0x44)

69 (0x45)

70 (0x46)

71 (0x47)

0000 0000

0111 1111

1111 1111

0000 0000

0111 1111

1111 1111

0000 0000

0111 1111

1111 1111

0000 0000

0111 1111

1111 1111

0000 0000

Coefficient N1(7:0) for left DAC-programmable biquad C

Coefficient N2(15:8) for left DAC-programmable biquad C

Coefficient N2(7:0) for left DAC-programmable biquad C

Coefficient D1(15:8) for left DAC-programmable biquad C

Coefficient D1(7:0) for left DAC-programmable biquad C

Coefficient D2(15:8) for left DAC-programmable biquad C

Coefficient D2(7:0) for left DAC-programmable biquad C

Coefficient N0(15:8) for left DAC-programmable biquad D

Coefficient N0(7:0) for left DAC-programmable biquad D

Coefficient N1(15:8) for left DAC-programmable biquad D

Coefficient N1(7:0) for left DAC-programmable biquad D

Coefficient N2(15:8) for left DAC-programmable biquad D

Coefficient N2(7:0) for left DAC-programmable biquad D

Coefficient D1(15:8) for left DAC-programmable biquad D

Coefficient D1(7:0) for left DAC-programmable biquad D

Coefficient D2(15:8) for left DAC-programmable biquad D

Coefficient D2(7:0) for left DAC-programmable biquad D

Coefficient N0(15:8) for left DAC-programmable biquad E

Coefficient N0(7:0) for left DAC-programmable biquad E

Coefficient N1(15:8) for left DAC-programmable biquad E

Coefficient N1(7:0) for left DAC-programmable biquad E

Coefficient N2(15:8) for left DAC-programmable biquad E

Coefficient N2(7:0) for left DAC-programmable biquad E

Coefficient D1(15:8) for left DAC-programmable biquad E

Coefficient D1(7:0) for left DAC-programmable biquad E

Coefficient D2(15:8) for left DAC-programmable biquad E

Coefficient D2(7:0) for left DAC-programmable biquad E

Coefficient N0(15:8) for left DAC-programmable biquad F

Coefficient N0(7:0) for left DAC-programmable biquad F

Coefficient N1(15:8) for left DAC-programmable biquad F

Coefficient N1(7:0) for left DAC-programmable biquad F

Coefficient N2(15:8) for left DAC-programmable biquad F

Coefficient N2(7:0) for left DAC-programmable biquad F

Coefficient D1(15:8) for left DAC-programmable biquad F

Coefficient D1(7:0) for left DAC-programmable biquad F

Coefficient D2(15:8) for left DAC-programmable biquad F

Coefficient D2(7:0) for left DAC-programmable biquad F

Reserved

8 MSBs of 3D PGA gain for PRB_P23, PRB_P24 and PRB_P25

8 LSBs of 3D PGA gain for PRB_P23, PRB_P24 and PRB_P25

Coefficient N0(15:8) for right DAC-programmable biquad A

Coefficient N0(7:0) for right DAC-programmable biquad A

Coefficient N1(15:8) for right DAC-programmable biquad A

Coefficient N1(7:0) for right DAC-programmable biquad A

Coefficient N2(15:8) for right DAC-programmable biquad A

Coefficient N2(7:0) for right DAC-programmable biquad A

REGISTER MAP

85

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Table 6-2. Page 8 DAC Buffer A Registers (continued)

REGISTER

NUMBER

RESET VALUE

REGISTER NAME

72 (0x48)

73 (0x49)

74 (0x4A)

75 (0x4B)

76 (0x4C)

77 (0x4D)

78 (0x4E)

79 (0x4F)

80 (0x50)

81 (0x51)

82 (0x52)

83 (0x53)

84 (0x54)

85 (0x55)

86 (0x56)

87 (0x57)

88 (0x58)

89 (0x59)

90 (0x5A)

91 (0x5B)

92 (0x5C)

93 (0x5D)

94 (0x5E)

95 (0x5F)

96 (0x60)

97 (0x61)

98 (0x62)

99 (0x63)

100 (0x64)

101 (0x65)

102 (0x66)

103 (0x67)

104 (0x68)

105 (0x69)

106 (0x6A)

107 (0x6B)

108 (0x6C)

109 (0x6D)

110 (0x6E)

111 (0x6F)

112 (0x70)

113 (0x71)

114 (0x72)

115 (0x73)

116 (0x74)

117 (0x75)

118 (0x76)

0000 0000

0111 1111

1111 1111

0000 0000

0111 1111

1111 1111

0000 0000

0111 1111

1111 1111

0000 0000

0111 1111

1111 1111

0000 0000

0111 1111

1111 1111

0000 0000

Coefficient D1(15:8) for right DAC-programmable biquad A

Coefficient D1(7:0) for right DAC-programmable biquad A

Coefficient D2(15:8) for right DAC-programmable biquad A

Coefficient D2(7:0) for right DAC-programmable biquad A

Coefficient N0(15:8) for right DAC-programmable biquad B

Coefficient N0(7:0) for right DAC-programmable biquad B

Coefficient N1(15:8) for right DAC-programmable biquad B

Coefficient N1(7:0) for right DAC-programmable biquad B

Coefficient N2(15:8) for right DAC-programmable biquad B

Coefficient N2(7:0) for right DAC-programmable biquad B

Coefficient D1(15:8) for right DAC-programmable biquad B

Coefficient D1(7:0) for right DAC-programmable biquad B

Coefficient D2(15:8) for right DAC-programmable biquad B

Coefficient D2(7:0) for right DAC-programmable biquad B

Coefficient N0(15:8) for right DAC-programmable biquad C

Coefficient N0(7:0) for right DAC-programmable biquad C

Coefficient N1(15:8) for right DAC-programmable biquad C

Coefficient N1(7:0) for right DAC-programmable biquad C

Coefficient N2(15:8) for right DAC-programmable biquad C

Coefficient N2(7:0) for right DAC-programmable biquad C

Coefficient D1(15:8) for right DAC-programmable biquad C

Coefficient D1(7:0) for right DAC-programmable biquad C

Coefficient D2(15:8) for right DAC-programmable biquad C

Coefficient D2(7:0) for right DAC-programmable biquad C

Coefficient N0(15:8) for right DAC-programmable biquad D

Coefficient N0(7:0) for right DAC-programmable biquad D

Coefficient N1(15:8) for right DAC-programmable biquad D

Coefficient N1(7:0) for right DAC-programmable biquad D

Coefficient N2(15:8) for right DAC-programmable biquad D

Coefficient N2(7:0) for right DAC-programmable biquad D

Coefficient D1(15:8) for right DAC-programmable biquad D

Coefficient D1(7:0) for right DAC-programmable biquad D

Coefficient D2(15:8) for right DAC-programmable biquad D

Coefficient D2(7:0) for right DAC-programmable biquad D

Coefficient N0(15:8) for right DAC-programmable biquad E

Coefficient N0(7:0) for right DAC-programmable biquad E

Coefficient N1(15:8) for right DAC-programmable biquad E

Coefficient N1(7:0) for right DAC-programmable biquad E

Coefficient N2(15:8) for right DAC-programmable biquad E

Coefficient N2(7:0) for right DAC-programmable biquad E

Coefficient D1(15:8) for right DAC-programmable biquad E

Coefficient D1(7:0) for right DAC-programmable biquad E

Coefficient D2(15:8) for right DAC-programmable biquad E

Coefficient D2(7:0) for right DAC-programmable biquad E

Coefficient N0(15:8) for right DAC-programmable biquad F

Coefficient N0(7:0) for right DAC-programmable biquad F

Coefficient N1(15:8) for right DAC-programmable biquad F

86

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Table 6-2. Page 8 DAC Buffer A Registers (continued)

REGISTER

RESET VALUE

REGISTER NAME

NUMBER

119 (0x77)

120 (0x78)

121 (0x79)

122 (0x7A)

123 (0x7B)

124 (0x7C)

125 (0x7D)

126–127

0000 0000

Coefficient N1(7:0) for right DAC-programmable biquad F

Coefficient N2(15:8) for right DAC-programmable biquad F

Coefficient N2(7:0) for right DAC-programmable biquad F

Coefficient D1(15:8) for right DAC-programmable biquad F

Coefficient D1(7:0) for right DAC-programmable biquad F

Coefficient D2(15:8) for right DAC-programmable biquad F

Coefficient D2(7:0) for right DAC-programmable biquad F

Reserved

REGISTER MAP

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6.6 Control Registers, Page 9: DAC Programmable Coefficients RAM Buffer A (65:127)

Default values shown for this page only become valid 100 μs following a hardware or software reset.

Page 9 / Register 0 (0x00): Page Control Register

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R/W

0000 0000

0000 0000: Page 0 selected

0000 0001: Page 1 selected

...

1111 1110: Page 254 selected

1111 1111: Page 255 selected

The remaining page-9 registers are either reserved registers or are used for setting coefficients for the

various filters in the TLV320DAC3101. Reserved registers should not be written to.

The filter-coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit

coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient is

interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. When

programming any coefficient value for a filter, the MSB register should always be written first, immediately

followed by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both

registers should be written in this sequence. Table 6-3 is a list of the page-9 registers, excepting the

previously described register 0.

Table 6-3. Page 9 DAC Buffer A Registers

REGISTER

NUMBER

RESET VALUE

REGISTER NAME

Reserved. Do not write to this register.

1 (0x01)

XXXX XXXX

0111 1111

1111 1111

0000 0000

0111 1111

1111 1111

0000 0000

0111 1111

1111 0111

1000 0000

0000 1001

0111 1111

1110 1111

0000 0000

0001 0001

0000 0000

0001 0001

0111 1111

1101 1110

0000 0000

2 (0x02)

Coefficient N0(15:8) for left DAC-programmable first-order IIR

Coefficient N0(7:0) for left DAC-programmable first-order IIR

Coefficient N1(15:8) for left DAC-programmable first-order IIR

Coefficient N1(7:0) for left DAC-programmable first-order IIR

Coefficient D1(15:8) for left DAC-programmable first-order IIR

Coefficient D1(7:0) for left DAC-programmable first-order IIR

Coefficient N0(15:8) for right DAC-programmable first-order IIR

Coefficient N0(7:0) for right DAC-programmable first-order IIR

Coefficient N1(15:8) for right DAC-programmable first-order IIR

Coefficient N1(7:0) for right DAC-programmable first-order IIR

Coefficient D1(15:8) for right DAC-programmable first-order IIR

Coefficient D1(7:0) for right DAC-programmable first-order IIR

Coefficient N0(15:8) for DRC first-order high-pass filter

Coefficient N0(7:0) for DRC first-order high-pass filter

Coefficient N1(15:8) for DRC first-order high-pass filter

Coefficient N1(7:0) for DRC first-order high-pass filter

Coefficient D1(15:8) for DRC first-order high-pass filter

Coefficient D1(7:0) for DRC first-order high-pass filter

Coefficient N0(15:8) for DRC first-order low-pass filter

Coefficient N0(7:0) for DRC first-order low-pass filter

Coefficient N1(15:8) for DRC first-order low-pass filter

Coefficient N1(7:0) for DRC first-order low-pass filter

Coefficient D1(15:8) for DRC first-order low-pass filter

Coefficient D1(7:0) for DRC first-order low-pass filter

Reserved

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

8 (0x08)

9 (0x09)

10 (0x0A)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

15 (0x0F)

16 (0x10)

17 (0x11)

18 (0x12)

19 (0x13)

20 (0x14)

21 (0x15)

22 (0x16)

23 (0x17)

24 (0x18)

25 (0x19)

26–127

88

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6.7 Control Registers, Page 12: DAC Programmable Coefficients RAM Buffer B (1:63)

Table 6-4. Page 12 / Register 0 (0x00): Page Control Register

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R/W

0000 0000

0000 0000: Page 0 selected

0000 0001: Page 1 selected

...

1111 1110: Page 254 selected

1111 1111: Page 255 selected

The remaining page-13 registers are either reserved registers or are used for setting coefficients for the

various filters in the TLV320DAC3101. Reserved registers should not be written to.

The filter-coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit

coefficient for a single filter. The 16-bit integer contained in the MSB and LSB registers for a coefficient is

interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767. When

programming any coefficient value for a filter, the MSB register should always be written first, immediately

followed by the LSB register. Even if only the MSB or LSB portion of the coefficient changes, both

registers should be written in this sequence. Table 6-3 is a list of the page-13 registers, excepting the

previously described register 0.

Table 6-5. Page 12 DAC Buffer B Registers

REGISTER

NUMBER

RESET VALUE

REGISTER NAME

Reserved. Do not write to this register.

1 (0x01)

0000 0000

0111 1111

1111 1111

0000 0000

0111 1111

1111 1111

0000 0000

0111 1111

1111 1111

0000 0000

2 (0x02)

Coefficient NO(15:8) for left DAC-programmable biquad A

Coefficient NO(7:0) for left DAC-programmable biquad A

Coefficient N1(15:8) for left DAC-programmable biquad A

Coefficient N1(7:0) for left DAC-programmable biquad A

Coefficient N2(15:8) for left DAC-programmable biquad A

Coefficient N2(7:0) for left DAC-programmable biquad A

Coefficient D1(15:8) for left DAC-programmable biquad A

Coefficient D1(7:0) for left DAC-programmable biquad A

Coefficient D2(15:8) for left DAC-programmable biquad A

Coefficient D2(7:0) for left DAC-programmable biquad A

Coefficient NO(15:8) for left DAC-programmable biquad B

Coefficient NO(7:0) for left DAC-programmable biquad B

Coefficient N1(15:8) for left DAC-programmable biquad B

Coefficient N1(7:0) for left DAC-programmable biquad B

Coefficient N2(15:8) for left DAC-programmable biquad B

Coefficient N2(7:0) for left DAC-programmable biquad B

Coefficient D1(15:8) for left DAC-programmable biquad B

Coefficient D1(7:0) for left DAC-programmable biquad B

Coefficient D2(15:8) for left DAC-programmable biquad B

Coefficient D2(7:0) for left DAC-programmable biquad B

Coefficient NO(15:8) for left DAC-programmable biquad C

Coefficient NO(7:0) for left DAC-programmable biquad C

Coefficient N1(15:8) for left DAC-programmable biquad C

Coefficient N1(7:0) for left DAC-programmable biquad C

Coefficient N2(15:8) for left DAC-programmable biquad C

Coefficient N2(7:0) for left DAC-programmable biquad C

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

8 (0x08)

9 (0x09)

10 (0x0A)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

15 (0x0F)

16 (0x10)

17 (0x11)

18 (0x12)

19 (0x13)

20 (0x14)

21 (0x15)

22 (0x16)

23 (0x17)

24 (0x18)

25 (0x19)

26 (0x1A)

27 (0x1B)

REGISTER MAP

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Table 6-5. Page 12 DAC Buffer B Registers (continued)

REGISTER

NUMBER

RESET VALUE

REGISTER NAME

28 (0x1C)

29 (0x1D)

30 (0x1E)

31 (0x1F)

32 (0x20)

33 (0x21)

34 (0x22)

35 (0x23)

36 (0x24)

37 (0x25)

38 (0x26)

39 (0x27)

40 (0x28)

41 (0x29)

42 (0x2A)

43 (0x2B)

44 (0x2C)

45 (0x2D)

46 (0x2E)

47 (0x2F)

48 (0x30)

49 (0x31)

50 (0x32)

51 (0x33)

52 (0x34)

53 (0x35)

54 (0x36)

55 (0x37)

56 (0x38)

57 (0x39)

58 (0x3A)

59 (0x3B)

60 (0x3C)

61 (0x3D)

62 (0x3E)

63 (0x3F)

64 (0x40)

65 (0x41)

66 (0x42)

67 (0x43)

68 (0x44)

69 (0x45)

70 (0x46)

71 (0x47)

72 (0x48)

73 (0x49)

74 (0x4A)

0000 0000

0111 1111

1111 1111

0000 0000

0111 1111

1111 1111

0000 0000

0111 1111

1111 1111

0000 0000

0111 1111

1111 1111

0000 0000

Coefficient D1(15:8) for left DAC-programmable biquad C

Coefficient D1(7:0) for left DAC-programmable biquad C

Coefficient D2(15:8) for left DAC-programmable biquad C

Coefficient D2(7:0) for left DAC-programmable biquad C

Coefficient NO(15:8) for left DAC-programmable biquad D

Coefficient NO(7:0) for left DAC-programmable biquad D

Coefficient N1(15:8) for left DAC-programmable biquad D

Coefficient N1(7:0) for left DAC-programmable biquad D

Coefficient N2(15:8) for left DAC-programmable biquad D

Coefficient N2(7:0) for left DAC-programmable biquad D

Coefficient D1(15:8) for left DAC-programmable biquad D

Coefficient D1(7:0) for left DAC-programmable biquad D

Coefficient D2(15:8) for left DAC-programmable biquad D

Coefficient D2(17:0) for left DAC-programmable biquad D

Coefficient NO(15:8) for left DAC-programmable biquad E

Coefficient NO(7:0) for left DAC-programmable biquad E

Coefficient N1(15:8) for left DAC-programmable biquad E

Coefficient N1(7:0) for left DAC-programmable biquad E

Coefficient N2(15:8) for left DAC-programmable biquad E

Coefficient N2(7:0) for left DAC-programmable biquad E

Coefficient D1(15:8) for left DAC-programmable biquad E

Coefficient D1(7:0) for left DAC-programmable biquad E

Coefficient D2(15:8) for left DAC-programmable biquad E

Coefficient D2(7:0) for left DAC-programmable biquad E

Coefficient NO(15:8) for left DAC-programmable biquad F

Coefficient NO(7:0) for left DAC-programmable biquad F

Coefficient N1(15:8) for left DAC-programmable biquad F

Coefficient N1(7:0) for left DAC-programmable biquad F

Coefficient N2(15:8) for left DAC-programmable biquad F

Coefficient N2(7:0) for left DAC-programmable biquad F

Coefficient D1(15:8) for left DAC-programmable biquad F

Coefficient D1(7:0) for left DAC-programmable biquad F

Coefficient D2(15:8) for left DAC-programmable biquad F

Coefficient D2(7:0) for left DAC-programmable biquad F

Reserved

8 MSBs 3D PGA gain for PRB_P23, PRB_P24 and PRB_P25

8 LSBs 3D PGA gain for PRB_P23, PRB_P24 and PRB_P25

Coefficient NO(15:8) for right DAC-programmable biquad A

Coefficient NO(7:0) for right DAC-programmable biquad A

Coefficient N1(15:8) for right DAC-programmable biquad A

Coefficient N1(7:0) for right DAC-programmable biquad A

Coefficient N2(15:8) for right DAC-programmable biquad A

Coefficient N2(7:0) for right DAC-programmable biquad A

Coefficient D1(15:8) for right DAC-programmable biquad A

Coefficient D1(7:0) for right DAC-programmable biquad A

Coefficient D2(15:8) for right DAC-programmable biquad A

90

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Table 6-5. Page 12 DAC Buffer B Registers (continued)

REGISTER

RESET VALUE

REGISTER NAME

NUMBER

75 (0x4B)

76 (0x4C)

77 (0x4D)

78 (0x4E)

79 (0x4F)

80 (0x50)

81 (0x51)

82 (0x52)

83 (0x53)

84 (0x54)

85 (0x55)

86 (0x56)

87 (0x57)

88 (0x58)

89 (0x59)

90 (0x5A)

91 (0x5B)

92 (0x5C)

93 (0x5D)

94 (0x5E)

95 (0x5F)

96 (0x60)

97 (0x61)

98 (0x62)

99 (0x63)

100 (0x64)

101 (0x65)

102 (0x66)

103 (0x67)

104 (0x68)

105 (0x69)

106 (0x6A)

107 (0x6B)

108 (0x6C)

109 (0x6D)

110 (0x6E)

111 (0x6F)

112 (0x70)

113 (0x71)

114 (0x72)

115 (0x73)

116 (0x74)

117 (0x75)

118 (0x76)

119 (0x77)

120 (0x78)

121 (0x79)

0000 0000

0111 1111

1111 1111

0000 0000

0111 1111

1111 1111

0000 0000

0111 1111

1111 1111

0000 0000

0111 1111

1111 1111

0000 0000

0111 1111

1111 1111

0000 0000

Coefficient D2(7:0) for right DAC-programmable biquad A

Coefficient NO(15:8) for right DAC-programmable biquad B

Coefficient NO(7:0) for right DAC-programmable biquad B

Coefficient N1(15:8) for right DAC-programmable biquad B

Coefficient N1(7:0) for right DAC-programmable biquad B

Coefficient N2(15:8) for right DAC-programmable biquad B

Coefficient N2(7:0) for right DAC-programmable biquad B

Coefficient D1(15:8) for right DAC-programmable biquad B

Coefficient D1(7:0) for right DAC-programmable biquad B

Coefficient D2(15:8) for right DAC-programmable biquad B

Coefficient D2(7:0) for right DAC-programmable biquad B

Coefficient NO(15:8) for right DAC-programmable biquad C

Coefficient NO(7:0) for right DAC-programmable biquad C

Coefficient N1(15:8) for right DAC-programmable biquad C

Coefficient N1(7:0) for right DAC-programmable biquad C

Coefficient N2(15:8) for right DAC-programmable biquad C

Coefficient N2(7:0) for right DAC-programmable biquad C

Coefficient D1(15:8) for right DAC-programmable biquad C

Coefficient D1(7:0) for right DAC-programmable biquad C

Coefficient D2(15:8) for right DAC-programmable biquad C

Coefficient D2(7:0) for right DAC-programmable biquad C

Coefficient NO(15:8) for right DAC-programmable biquad D

Coefficient NO(7:0) for right DAC-programmable biquad D

Coefficient N1(15:8) for right DAC-programmable biquad D

Coefficient N1(7:0) for right DAC-programmable biquad D

Coefficient N2(15:8) for right DAC-programmable biquad D

Coefficient N2(7:0) for right DAC-programmable biquad D

Coefficient D1(15:8) for right DAC-programmable biquad D

Coefficient D1(7:0) for right DAC-programmable biquad D

Coefficient D2(15:8) for right DAC-programmable biquad D

Coefficient D2(7:0) for right DAC-programmable biquad D

Coefficient NO(15:8) for right DAC-programmable biquad E

Coefficient NO(7:0) for right DAC-programmable biquad E

Coefficient N1(15:8) for right DAC-programmable biquad E

Coefficient N1(7:0) for right DAC-programmable biquad E

Coefficient N2(15:8) for right DAC-programmable biquad E

Coefficient N2(7:0) for right DAC-programmable biquad E

Coefficient D1(15:8) for right DAC-programmable biquad E

Coefficient D1(7:0) for right DAC-programmable biquad E

Coefficient ND2(15:8) for right DAC-programmable biquad E

Coefficient ND2(7:0) for right DAC-programmable biquad E

Coefficient NO(15:8) for right DAC-programmable biquad F

Coefficient NO(7:0) for right DAC-programmable biquad F

Coefficient N1(15:8) for right DAC-programmable biquad F

Coefficient N1(7:0) for right DAC-programmable biquad F

Coefficient N2(15:8) for right DAC-programmable biquad F

Coefficient N2(7:0) for right DAC-programmable biquad F

REGISTER MAP

91

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TLV320DAC3101

SLAS666A –JANUARY 2010–REVISED MAY 2012

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Table 6-5. Page 12 DAC Buffer B Registers (continued)

REGISTER

NUMBER

RESET VALUE

REGISTER NAME

122 (0x7A)

123 (0x7B)

124 (0x7C)

125 (0x7D)

126–127

0000 0000

Coefficient D1(15:8) for right DAC-programmable biquad F

Coefficient D1(7:0) for right DAC-programmable biquad F

Coefficient D2(15:8) for right DAC-programmable biquad F

Coefficient D2(7:0) for right DAC-programmable biquad F

Reserved

6.8 Control Registers, Page 13: DAC Programmable Coefficients RAM Buffer B (65:127)

Table 6-6. Page 13 / Register 0 (0x00): Page Control Register

READ/

WRITE

RESET

VALUE

BIT

DESCRIPTION

D7–D0

R/W

0000 0000

0000 0000: Page 0 selected

0000 0001: Page 1 selected

...

1111 1110: Page 254 selected

1111 1111: Page 255 selected

Table 6-7. Page 13 DAC Buffer B Registers