TLV3544-Q1 [TI]
汽车类 250MHz 轨到轨 I/O CMOS 四路运算放大器;
| 型号： | TLV3544-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 250MHz 轨到轨 I/O CMOS 四路运算放大器 放大器 运算放大器 |
| 文件： | 总29页 (文件大小：1037K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV3544-Q1
ZHCSGU7 –OCTOBER 2017
TLV3544-Q1 250MHz，轨至轨输入输出，用于汽车的CMOS 运算放大器
1 特性
2 应用
1
•
•
符合汽车应用 要求
具有符合 AEC-Q100 标准的下列结果：
•
•
•
•
•
•
•
•
•
•
电流感应放大器
逆变器和电机控制
发动机管理
–
器件温度等级 1：环境工作温度范围 TA 为
–40°C 至 +125°C
电池管理
–
–
器件 HBM ESD 分类等级 1C
器件 CDM ESD 分类等级 C3
导航和雷达系统
浓度传感器
•
•
•
•
•
•
•
单位增益带宽：250MHz
高带宽：100MHz GBW
高压摆率：150V/µs
低噪声：7.5nV√Hz
轨至轨 I/O
盲点监测系统
短程到中程雷达
环视和倒车摄像头视频处理
用于送电传感器系统的汽车 SAR ADC 驱动器
3 说明
高输出电流：> 100mA
出色的视频性能：
TLV3544-Q1 系列高速电压反馈 CMOS 运算放大器专
为视频应用和其他需要宽带宽的 应用 而设计。这些器
件单位增益稳定，可以输出大电流。差分增益为
0.02%，而差分相位为 0.09°。静态电流仅为每通道
4.9mA。
–
–
差分增益：0.02%，差分相位：0.09°
0.1dB 增益平坦度：40MHz
•
•
•
•
低输入偏置电流：3pA
静态电流：5.2mA
热关断
TLV3544-Q1 四通道运算放大器针对低至 2.5V
(±1.25V) 和高达 5.5V (±2.75V) 的单电源或双电源供电
运行进行了优化。共模输入范围超出电源供电范围。电
源轨的输出摆幅在 100mV 以内，从而支持宽动态范
围。
电源范围：2.5V 至 5.5V
简化图
Out A
-In A
+In A
V+
Out D
-In D
+In D
V-
1
2
3
4
5
6
7
14
13
12
11
10
9
多通道版本具有完全独立的电路，可将串扰降到最低并
彻底消除相互干扰。所有器件的额定扩展工作温度范围
为 –40°C 至 +125°C。
A
D
器件信息(1)
+In B
-In B
Out B
+In C
-In C
Out C
B
C
器件型号
封装
封装尺寸（标称值）
薄型小外形尺寸封装
(TSSOP) (14)
TLV3544-Q1
5.00mm x 4.40mm
8
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS897
TLV3544-Q1
ZHCSGU7 –OCTOBER 2017
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 18
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application ................................................. 19
Power Supply Recommendations...................... 21
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information: TLV3544-Q1 ........................... 4
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 21
10.3 Power Dissipation ................................................. 21
11 器件和文档支持 ..................................................... 23
11.1 文档支持 ............................................................... 23
11.2 接收文档更新通知 ................................................. 23
11.3 社区资源................................................................ 23
11.4 商标....................................................................... 23
11.5 静电放电警告......................................................... 23
11.6 Glossary................................................................ 23
12 机械、封装和可订购信息....................................... 23
6.5 Electrical Characteristics: VS = 2.7 V to 5.5 V Single-
Supply ........................................................................ 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2017 年 10 月
*
初始发行版。
2
Copyright © 2017, Texas Instruments Incorporated
TLV3544-Q1
www.ti.com.cn
ZHCSGU7 –OCTOBER 2017
5 Pin Configuration and Functions
PW Package
14-Pin TSSOP
Top View
Out A
-In A
+In A
V+
Out D
-In D
+In D
V-
1
2
3
4
5
6
7
14
13
12
11
10
9
A
D
+In B
-In B
Out B
+In C
-In C
Out C
B
C
8
Pin Functions
PIN
I/O
DESCRIPTION
NAME
–In A
+In A
–In B
+In B
–In C
+In C
–In D
+In D
Out A
Out B
Out C
Out D
V–
NO.
2
I
I
Inverting input, channel A
3
Noninverting input, channel A
Inverting input, channel B
Noninverting input, channel B
Inverting input, channel C
Noninverting input, channel C
Inverting input, channel D
Noninverting input, channel D
Output, channel A
6
I
5
I
9
I
10
13
12
1
I
I
I
O
O
O
O
—
—
7
Output, channel B
8
Output, channel C
14
11
4
Output, channel D
Negative (lowest) supply
Positive (highest) supply
V+
Copyright © 2017, Texas Instruments Incorporated
3
TLV3544-Q1
ZHCSGU7 –OCTOBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
7.5
UNIT
V
Supply voltage, V+ to V−
Voltage
Signal input terminals(2)
(V−) − (0.5)
(V+) + 0.5
10
Signal input terminals(2)
Output short circuit(3)
–10
mA
Current
Continuous
Operating, TA
–55
–65
150
150
150
Temperature
Junction, TJ
Storage, Tstg
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.5
MAX
UNIT
V
VS
Supply voltage, V– to V+
Specified temperature
5.5
–40
125
°C
6.4 Thermal Information: TLV3544-Q1
TLV3544-Q1
PW (TSSOP)
14 PINS
92.6
THERMAL METRIC
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
27.5
33.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.9
ψJB
33.1
RθJC(bot)
—
4
Copyright © 2017, Texas Instruments Incorporated
TLV3544-Q1
www.ti.com.cn
ZHCSGU7 –OCTOBER 2017
6.5 Electrical Characteristics: VS = 2.7 V to 5.5 V Single-Supply
At TA = 25°C, RF = 0 Ω, RL = 1 kΩ, and connected to VS/2, unless otherwise noted.
PARAMETER
OFFSET VOLTAGE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOS
Input offset voltage
VS = 5 V, at TA = 25°C
±2
±10
mV
dVOS/dT
Input offset voltage vs temperature
VS = 5 V, at TA = −40°C to +125°C
±4.5
µV/°C
VS = 2.7 V to 5.5 V,
VCM = (VS/2) − 0.55 V
±200
±800
±900
PSRR
Input offset voltage vs power supply
µV/V
VS = 2.7 V to 5.5 V,
VCM = (VS/2) − 0.55 V,
at TA = −40°C to +125°C
INPUT BIAS CURRENT
IB
Input bias current
3
pA
pA
IOS
Input offset current
±1
NOISE
en
Input voltage noise density
Current noise density
f = 1 MHz
f = 1 MHz
7.5
50
nV/√Hz
fA/√Hz
in
INPUT VOLTAGE RANGE
VCM
Common-mode voltage
(V−) − 0.1
(V+) + 0.1
V
VS = 5.5 V, –0.1 V < VCM < 3.5 V,
at TA = 25°C
66
80
68
CMRR
Common-mode rejection ratio
dB
VS = 5.5 V, –0.1 V < VCM < 5.6 V,
at TA = 25°C
56
INPUT IMPEDANCE
Differential
Common-mode
OPEN-LOOP GAIN
1013 || 2
1013 || 2
Ω || pF
Ω || pF
VS = 5.5 V, 0.3 V < VO < 4.7 V,
at TA = 25°C
94
90
110
AOL
Open-loop gain
dB
VS = 5 V, 0.4 V < VO < 4.6 V,
at TA = –40°C to +125°C
FREQUENCY RESPONSE
At G = +1, VO = 100 mVPP
RF = 25 Ω
,
250
f−3dB
Small-signal bandwidth
MHz
At G = +2, VO = 100 mVPP
G = +10
90
100
40
GBW
f0.1dB
Gain-bandwidth product
MHz
MHz
Bandwidth for 0.1-dB gain flatness
At G = +2, VO = 100 mVPP
VS = 5 V, G = +1, 4-V step
VS = 5 V, G = +1, 2-V step
VS = 3 V, G = +1, 2-V step
150
130
110
SR
Slew rate
V/µs
ns
At G = +1, VO = 200 mVPP
,
2
11
30
10% to 90%
Rise-and-fall time
At G = +1, VO = 2 VPP, 10% to 90%
0.1%, VS = 5 V, G = +1,
2-V output step
Settling time
ns
ns
0.01%, VS = 5 V, G = +1,
2-V output step
60
5
Overload recovery time
VIN × Gain = VS
Copyright © 2017, Texas Instruments Incorporated
5
TLV3544-Q1
ZHCSGU7 –OCTOBER 2017
www.ti.com.cn
Electrical Characteristics: VS = 2.7 V to 5.5 V Single-Supply (continued)
At TA = 25°C, RF = 0 Ω, RL = 1 kΩ, and connected to VS/2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE, continued
Second
harmonic
At G = +1, f = 1 MHz, VO = 2 VPP
RL = 200 Ω, VCM = 1.5 V
,
–75
–83
Harmonic distortion
dBc
At G = +1, f = 1 MHz, VO = 2 VPP
,
Third harmonic
RL = 200 Ω, VCM = 1.5 V
Differential gain error
Differential phase error
NTSC, RL = 150 Ω
NTSC, RL = 150 Ω
0.02%
0.09
°
Channel-to-channel
crosstalk
TLV3544-Q1
f = 5 MHz
–84
dB
OUTPUT
VS = 5 V, RL = 1 kΩ, AOL > 94 dB,
at TA = 25°C
Voltage output swing from rail
Output current(1)(2)
0.1
0.3
V
IO
VS = 5 V
100
mA
mA
Ω
VS = 3 V
50
0.05
35
Closed-loop output impedance
Open-loop output resistance
f < 100 kHz
RO
Ω
POWER SUPPLY
Specified voltage
2.7
2.5
5
VS
IQ
V
Operating voltage
5.5
At TA = 25°C, VS = 5 V, enabled,
IO = 0
Quiescent current (per amplifier)
5.2
6.5
mA
THERMAL SHUTDOWN – JUNCTION TEMPERATURE
Shutdown
Reset from shutdown
THERMAL RANGE
Specified
160
140
°C
°C
–40
–55
–65
125
150
150
°C
°C
°C
Operating
Storage
(1) See typical characteristic curves, Output Voltage Swing vs Output Current (图 20 and 图 22).
(2) Specified by design.
6
版权 © 2017, Texas Instruments Incorporated
TLV3544-Q1
www.ti.com.cn
ZHCSGU7 –OCTOBER 2017
6.6 Typical Characteristics
At TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS/2, unless otherwise noted.
3
0
3
0
G = +1
RF = 25W
VO = 0.1VPP
VO = 0.1VPP, RF = 604W
G = +2, RF = 604W
G = +5, RF = 604W
G = +10, RF = 604W
-3
-3
G = -1
G = -2
-6
-6
G = -5
-9
-9
G = -10
-12
-12
-15
-15
100k
1M
10M
Frequency (Hz)
100M
1G
100k
1M
10M
100M
1G
Frequency (Hz)
图 1. Noninverting Small-Signal Frequency Response
图 2. Inverting Small-Signal Frequency Response
Time (20ns/div)
Time (20ns/div)
图 3. Noninverting Small-Signal Step Response
图 4. Noninverting Large-Signal Step Response
-50
0.5
VO = 0.1VPP
0.4
0.3
G = -1
f = 1MHz
RL = 200W
-60
-70
G = +1
RF = 25W
0.2
0.1
0
2nd Harmonic
3rd Harmonic
-80
-0.1
-0.2
-0.3
-0.4
-0.5
G = +2
RF = 604W
-90
-100
0
1
2
3
4
100k
1M
10M
100M
1G
Output Voltage (VPP
)
Frequency (Hz)
图 5. 0.1-dB Gain Flatness
图 6. Harmonic Distortion vs Output Voltage
版权 © 2017, Texas Instruments Incorporated
7
TLV3544-Q1
ZHCSGU7 –OCTOBER 2017
www.ti.com.cn
Typical Characteristics (接下页)
At TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS/2, unless otherwise noted.
-50
-50
VO = 2VPP
f = 1MHz
RL = 200W
VO = 2VPP
f = 1MHz
RL = 200W
-60
-60
-70
-70
2nd Harmonic
2nd Harmonic
-80
-80
3rd Harmonic
-90
-90
3rd Harmonic
-100
-100
1
10
1
10
Gain (V/V)
Gain (V/V)
图 7. Harmonic Distortion vs Noninverting Gain
图 8. Harmonic Distortion vs Inverting Gain
-50
-60
-50
-60
G = +1
G = +1
VO = 2VPP
f = 1MHz
VCM = 1.5V
VO = 2VPP
RL = 200W
VCM = 1.5V
-70
-70
2nd Harmonic
3rd Harmonic
2nd Harmonic
3rd Harmonic
-80
-80
-90
-90
-100
-100
100
1k
100k
1M
10M
RL (W)
Frequency (Hz)
图 9. Harmonic Distortion vs Frequency
图 10. Harmonic Distortion vs Load Resistance
RL = 10kW
3
0
10k
1k
G = +1
RF = 0W
-3
Current Noise
Voltage Noise
VO = 0.1VPP
RL = 1kW
CL = 0pF
-6
100
10
1
RL = 100W
RL = 50W
-9
-12
-15
100k
1M
10M
100M
1G
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
图 12. Frequency Response for Various RL
图 11. Input Voltage and Current Noise
Spectral Density vs Frequency
8
版权 © 2017, Texas Instruments Incorporated
TLV3544-Q1
www.ti.com.cn
ZHCSGU7 –OCTOBER 2017
Typical Characteristics (接下页)
At TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS/2, unless otherwise noted.
9
160
140
120
100
80
G = +1
For 0.1 dB
Flatness
VO = 0.1VPP
RS = 0W
6
CL = 100pF
3
0
-3
-6
-9
-12
-15
CL = 47pF
60
V
R
S
IN
V
O
TLV3544
40
C
1 kW
CL = 5.6pF
L
20
0
1
1k
100k
1M
10M
Frequency (Hz)
100M
1G
10
100
Capacitive Load (pF)
图 13. Frequency Response for Various CL
图 14. Recommended RS vs Capacitive Load
100
80
60
40
20
0
3
0
G = +1,
CL = 5.6 pF, RS = 0 W
VO = 0.1 VPP
CMRR
CL = 47 pF, RS = 140 W
-3
PSRR+
CL = 100 pF, RS = 120 W
-6
PSRR-
-9
V
R
S
IN
V
O
TLV3544
C
1 kW
L
-12
-15
100k
1G
1M
10M
100M
10k
100k
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
图 15. Frequency Response vs Capacitive Load
图 16. Common-Mode Rejection Ratio and
Power-Supply Rejection Ratio vs Frequency
180
0.8
160
140
120
100
80
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Phase
dP
60
40
Gain
20
0
-20
-40
dG
1
2
3
4
10
100
1k
10k 100k
1M
10M 100M 1G
Frequency (Hz)
Number of 150W Loads
图 18. Composite Video Differential Gain and Phase
图 17. Open-Loop Gain and Phase
版权 © 2017, Texas Instruments Incorporated
9
TLV3544-Q1
ZHCSGU7 –OCTOBER 2017
www.ti.com.cn
Typical Characteristics (接下页)
At TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS/2, unless otherwise noted.
10k
3
2
1
0
1k
100
10
1
+125°C
+25°C
-55°C
-55 -35 -15
5
25
45
65
85 105 125 135
0
20
40
60
80
100
120
Temperature (°C)
Output Current (mA)
图 19. Input Bias Current vs Temperature
图 20. Output Voltage Swing vs Output Current for
VS = 3 V
5
4
3
2
1
0
7
6
5
4
3
2
1
0
VS = 5V
+25°C
+125°C
-55°C
VS = 2.5V
-55 -35 -15
5
25
45
65
85 105 125 135
0
25
50
75
100
125
150
175
200
Temperature (°C)
Output Current (mA)
图 21. Supply Current vs Temperature
图 22. Output Voltage Swing vs Output Current for
VS = 5 V
6
5
4
3
2
1
0
100
10
VS = 5.5V
Maximum Output
Voltage without
Slew Rate-
Induced Distortion
1
VS = 2.7V
0.1
0.01
TLV3544
ZO
100k
1M
10M
100M
1G
1
10
100
Frequency (Hz)
Frequency (MHz)
图 23. Closed-Loop Output Impedance vs Frequency
图 24. Maximum Output Voltage vs Frequency
10
版权 © 2017, Texas Instruments Incorporated
TLV3544-Q1
www.ti.com.cn
ZHCSGU7 –OCTOBER 2017
Typical Characteristics (接下页)
At TA = 25°C, VS = 5 V, G = +1, RF = 0 Ω, RL = 1 kΩ, and connected to VS/2, unless otherwise noted.
120
110
100
90
0.5
0.4
RL = 1kW
VO = 2VPP
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
80
70
0
10
20 30
40
50
60
70
80
90 100
-55 -35 -15
5
25
45
65
85 105 125 135
Time (ns)
Temperature (°C)
图 25. Output Settling Time to 0.1%
图 26. Open-Loop Gain vs Temperature
100
90
80
70
60
50
Common-Mode Rejection Ratio
Power-Supply Rejection Ratio
-8 -7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7 8
-55 -35 -15
5
25
45
65
85 105 125 135
Offset Voltage (mV)
Temperature (°C)
图 27. Offset Voltage Production Distribution
图 28. Common-Mode Rejection Ratio and
Power-Supply Rejection Ratio vs Temperature
0
-20
-40
TLV3544
-60
-80
-100
-120
100k
1M
10M
Frequency (Hz)
100M
1G
图 29. Channel-to-Channel Crosstalk
版权 © 2017, Texas Instruments Incorporated
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TLV3544-Q1
ZHCSGU7 –OCTOBER 2017
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7 Detailed Description
7.1 Overview
The TLV3544-Q1 is a quad-channel CMOS, rail-to-rail I/O, high-speed, voltage-feedback operational amplifier
designed for video, high-speed, and other applications.
The amplifier features a 100-MHz gain bandwidth and 150-V/µs slew rate, but it is unity-gain stable and can be
operated as a +1-V/V voltage follower.
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VIN
-
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V-
(Ground)
Copyright © 2017, Texas Instruments Incorporated
12
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TLV3544-Q1
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ZHCSGU7 –OCTOBER 2017
7.3 Feature Description
7.3.1 TLV3544-Q1 Comparison
表 1 lists several members of the device family that includes the TLV3544-Q1.
表 1. Device Family Comparison
FEATURES
PRODUCT
OPAx357
OPAx355
OPAx356
Shutdown Version of TLV3544 Family
200-MHz GBW, Rail-to-Rail Output, CMOS, Shutdown
200-MHz GBW, Rail-to-Rail Output, CMOS
38-MHz GBW, Rail-to-Rail Input/Output, CMOS
75-MHz BW G = 2, Rail-to-Rail Output
OPAx350/OPAx353
OPA2631
150-MHz BW G = 2, Rail-to-Rail Output
OPA2634
100-MHz BW, Differential Input/Output, 3.3-V Supply
THS412x
7.3.2 Operating Voltage
The TLV3544-Q1 is specified over a power-supply range of 2.7 V to 5.5 V (±1.35 V to ±2.75 V). However, the
supply voltage may range from 2.5 V to 5.5 V (±1.25 V to ±2.75 V).
CAUTION
Supply voltages higher than 7.5 V (absolute maximum) can permanently damage the
amplifier.
Parameters that vary over supply voltage or temperature are shown in Typical Characteristics of this data sheet.
7.3.3 Rail-to-Rail Input
The specified input common-mode voltage range of the TLV3544-Q1 extends 100 mV beyond the supply rails.
This extended range is achieved with a complementary input stage—an N-channel input differential pair in
parallel with a P-channel differential pair, as shown in the Functional Block Diagram. The N-channel pair is active
for input voltages close to the positive rail, typically (V+) − 1.2 V to 100 mV above the positive supply, while the
P-channel pair is on for inputs from 100 mV below the negative supply to approximately (V+) − 1.2 V. There is a
small transition region, typically (V+) − 1.5 V to (V+) − 0.9 V, in which both pairs are on. This 600-mV transition
region can vary ±500 mV with process variation. Thus, the transition region (both input stages on) can range
from (V+) − 2 V to (V+) − 1.5 V on the low end, up to (V+) − 0.9 V to (V+) − 0.4 V on the high end.
A double-folded cascode adds the signal from the two input pairs and presents a differential signal to the class
AB output stage.
7.3.4 Rail-to-Rail Output
A class AB output stage with common-source transistors is used to achieve rail-to-rail output. For high-
impedance loads (> 200 Ω), the output voltage swing is typically 100 mV from the supply rails. With 10-Ω loads,
a useful output swing can be achieved while maintaining high open-loop gain. See the typical characteristic
curves, Output Voltage Swing vs Output Current (图 20 and 图 22).
7.3.5 Output Drive
The TLV3544-Q1 output stage can supply a continuous output current of ±100 mA and yet provide approximately
2.7 V of output swing on a 5-V supply, as shown in 图 30. For maximum reliability, TI does not recommend
running a continuous DC current in excess of ±100 mA. Refer to the typical characteristic curves, Output Voltage
Swing vs Output Current (图 20 and 图 22). For supplying continuous output currents greater than ±100 mA, the
TLV3544-Q1 may be operated in parallel, as shown in 图 31.
版权 © 2017, Texas Instruments Incorporated
13
TLV3544-Q1
ZHCSGU7 –OCTOBER 2017
www.ti.com.cn
R2
+
1 kW
V1
5 V
-
C1
50 pF
1 mF
R1
V+
10 kW
TLV3544
R3
V-
RSHUNT
10 kW
VIN
+
1 W
R4
1 kW
-
1V In = 100 mA
Out, as Shown
Laser Diode
Copyright © 2017, Texas Instruments Incorporated
图 30. Laser Diode Driver
The TLV3544-Q1 provides peak currents up to 200 mA, which corresponds to the typical short-circuit current.
Therefore, an on-chip thermal shutdown circuit is provided to protect the TLV3544-Q1 from dangerously high
junction temperatures. At 160°C, the protection circuit shuts down the amplifier. Normal operation resumes when
the junction temperature cools to below 140°C.
R2
10 kW
C1
200 pF
+5V
1 mF
R1
100 kW
R5
1 W
TLV3544-A
R3
100 kW
+
-
R6
RSHUNT
2 V In = 200 mA
Out, as Shown
1 W
1 W
TLV3544-B
R4
10 kW
Laser Diode
Copyright © 2017, Texas Instruments Incorporated
图 31. Parallel Operation
14
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7.3.6 Video
The TLV3544-Q1 output stage is capable of driving standard back-terminated 75-Ω video cables, as shown in 图
32. By back-terminating a transmission line, it does not exhibit a capacitive load to its driver. A properly back-
terminated 75-Ω cable does not appear as capacitance; it presents only a 150-Ω resistive load to the TLV3544-
Q1 output.
+5 V
Video
In
75 W
Video
Output
TLV3544
75 W
+2.5 V
604 W
604 W
+2.5 V
Copyright © 2017, Texas Instruments Incorporated
图 32. Single-Supply Video Line Driver
The TLV3544-Q1 can be used as an amplifier for RGB graphic signals, which have a voltage of zero at the video
black level, by offsetting and AC-coupling the signal. See 图 33.
版权 © 2017, Texas Instruments Incorporated
15
TLV3544-Q1
ZHCSGU7 –OCTOBER 2017
www.ti.com.cn
604W
1mF
+3 V
+
10 nF
V+
604W
75W
Red
75W
R1
R2
(1)
Red
TLV3544-A
V+
R1
R2
(1)
Green
75W
Green
75W
TLV3544-B
604W
604W
604W
V+
604W
75W
Blue
75W
R1
R2
Blue(1)
TLV3544-C
Copyright © 2017, Texas Instruments Incorporated
(1) Source video signal offset 300 mV above ground to accommodate op amp swing−to−ground capability.
图 33. RGB Cable Driver
16
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TLV3544-Q1
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ZHCSGU7 –OCTOBER 2017
7.3.7 Driving Analog-to-Digital converters
The TLV3544-Q1 series op amps offer 60 ns of settling time to 0.01%, making them a good choice for driving
high- and medium-speed sampling A/D converters and reference circuits. The TLV3544-Q1 provides an effective
means of buffering the A/D converter input capacitance and resulting charge injection while providing signal gain.
For applications requiring high DC accuracy, the OPA350 series is recommended.
图 34 illustrates the TLV3544-Q1 driving an A/D converter. With the TLV3544-Q1 in an inverting configuration, a
capacitor across the feedback resistor can be used to filter high-frequency noise in the signal.
+5 V
330 pF
5 kW
5 kW
VIN
VREF
V+
ADS7816, ADS7861,
+In
or ADS7864
TLV3544
12-Bit A/D Converter
+2.5 V
-In
GND
VIN = 0V to -5 V for 0 V to 5 V output.
NOTE: A/D converter input = 0 V to VREF
Copyright © 2017, Texas Instruments Incorporated
图 34. The TLV3544-Q1 in Inverting Configuration Driving the ADS7816
7.3.8 Capacitive Load and Stability
The TLV3544-Q1 series op amps can drive a wide range of capacitive loads. However, all op amps under certain
conditions may become unstable. Op amp configuration, gain, and load value are just a few of the factors to
consider when determining stability. An op amp in unity-gain configuration is most susceptible to the effects of
capacitive loading. The capacitive load reacts with the device output resistance, along with any additional load
resistance, to create a pole in the small-signal response that degrades the phase margin. Refer to the typical
characteristic curve, Frequency Response for Various CL (图 13) for details.
The TLV3544-Q1 topology enhances its ability to drive capacitive loads. In unity gain, these op amps perform
well with large capacitive loads. Refer to the typical characteristic curves, Recommended RS vs Capacitive Load
(图 14) and Frequency Response vs Capacitive Load (图 15) for details.
One method of improving capacitive load drive in the unity-gain configuration is to insert a 10-Ω to 20-Ω resistor
in series with the output, as shown in 图 35. This configuration significantly reduces ringing with large capacitive
loads—see the typical characteristic curve, Frequency Response vs Capacitive Load (图 15). However, if there is
a resistive load in parallel with the capacitive load, RS creates a voltage divider. This voltage division introduces a
DC error at the output and slightly reduces output swing. This error may be insignificant. For instance, with RL =
10 kΩ and RS = 20 Ω, there is approximately a 0.2% error at the output.
V+
RS
VOUT
TLV3544
VIN
RL
CL
Copyright © 2017, Texas Instruments Incorporated
图 35. Series Resistor in Unity-Gain Configuration Improves Capacitive Load Drive
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ZHCSGU7 –OCTOBER 2017
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7.3.9 Wideband Transimpedance Amplifier
Wide bandwidth, low input bias current, low input voltage, and current noise make the TLV3544-Q1 an ideal
wideband photodiode transimpedance amplifier for low-voltage single-supply applications. Low-voltage noise is
important because photodiode capacitance causes the effective noise gain of the circuit to increase at high
frequency.
The key elements to a transimpedance design, as shown in 图 36, are the expected diode capacitance [including
the parasitic input common-mode and differential-mode input capacitance (2 + 2) pF for the TLV3544-Q1], the
desired transimpedance gain (RF), and the Gain-Bandwidth Product (GBW) for the TLV3544-Q1 (100 MHz
typical). With these three variables set, the feedback capacitor value (CF) may be set to control the frequency
response.
CF
< 1 pF
(prevents gain peaking)
RF
10 MW
+V
l
CD
VOUT
TLV3544
Copyright © 2017, Texas Instruments Incorporated
图 36. Transimpedance Amplifier
To achieve a maximally flat, second-order, Butterworth frequency response, the feedback pole must be set as
shown in 公式 1:
1
GBP
4pRFCD
=
2pRFCF
(1)
Typical surface-mount resistors have a parasitic capacitance of approximately 0.2 pF that must be deducted from
the calculated feedback capacitance value. Bandwidth is calculated by 公式 2:
GBP
f
=
Hz
-3dB
2pRFCD
(2)
For even higher transimpedance bandwidth, the high-speed CMOS OPA355 (200-MHz GBW) or the OPA655
(400-MHz GBW) may be used.
7.4 Device Functional Modes
The TLV3544-Q1 is powered on when the supply is connected. The devices can be operated as single-supply
operational amplifiers or dual-supply amplifiers depending on the application. The devices can also be used with
asymmetrical supplies as long as the differential voltage (V– to V+) is at least 1.8 V and no greater than 5.5 V
(example: V– set to –3.5 V and V+ set to 1.5 V).
18
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV3544-Q1 is a CMOS, rail-to-rail I/O, high-speed, voltage-feedback operational amplifier designed for
video, high-speed, and other applications. The amplifier features a 100-MHz gain bandwidth, and 150-V/µs slew
rate, but it is unity-gain stable and can be operated as a 1-V/V voltage follower.
8.2 Typical Application
Wide gain bandwidth, low input bias current, low input voltage, and current noise make the TLV3544-Q1 an ideal
wideband photodiode transimpedance amplifier. Low-voltage noise is important because photodiode capacitance
causes the effective noise gain of the circuit to increase at high frequency. The key elements to a
transimpedance design, as shown in 图 37, are the expected diode capacitance, which include the parasitic input
common-mode and differential-mode input capacitance; the desired transimpedance gain; and the gain-
bandwidth (GBW) for the TLV3544-Q1 (20 MHz). With these three variables set, the feedback capacitor value
can be set to control the frequency response. Feedback capacitance includes the stray capacitance of, which is
0.2 pF for a typical surface-mount resistor.
C(F)
< 1 pF
R(F)
10 MW
V(V+)
I
C(D)
VO
TLV3544
V(V-)
Copyright © 2017, Texas Instruments Incorporated
图 37. Dual-Supply Transimpedance Amplifier
8.2.1 Design Requirements
For this design example, use the parameters listed in 表 2 as the input parameters.
表 2. Design Parameters
PARAMETER
EXAMPLE VALUE
2.5 V
Supply voltage, V(V+)
Supply voltage, V(V-)
–2.5 V
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ZHCSGU7 –OCTOBER 2017
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C(F) is optional to prevent gain peaking. C(F) includes the stray capacitance of R(F)
.
8.2.2 Detailed Design Procedure
To achieve a maximally-flat, second-order Butterworth frequency response, set the feedback pole using 公式 3.
(3)
Calculate the bandwidth using 公式 4.
(4)
8.2.2.1 Optimizing the Transimpedance Circuit
To achieve the best performance, components must be selected according to the following guidelines:
1. For lowest noise, select R(F) to create the total required gain. Using a lower value for R(F) and adding gain after
the transimpedance amplifier generally produces poorer noise performance. The noise produced by R(F)
increases with the square-root of R(F), whereas the signal increases linearly. Therefore, signal-to-noise ratio
improves when all the required gain is placed in the transimpedance stage.
2. Minimize photodiode capacitance and stray capacitance at the summing junction (inverting input). This
capacitance causes the voltage noise of the op amp to be amplified (increasing amplification at high frequency).
Using a low-noise voltage source to reverse-bias a photodiode can significantly reduce the capacitance. Smaller
photodiodes have lower capacitance. Use optics to concentrate light on a small photodiode.
3. Noise increases with increased bandwidth. Limit the circuit bandwidth to only that required. Use a capacitor
across the R(F) to limit bandwidth, even if not required for stability.
4. Circuit board leakage can degrade the performance of an otherwise well-designed amplifier. Clean the circuit
board carefully. A circuit board guard trace that encircles the summing junction and is driven at the same voltage
can help control leakage.
8.2.3 Application Curve
图 38. AC Transfer Function
20
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TLV3544-Q1
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ZHCSGU7 –OCTOBER 2017
9 Power Supply Recommendations
The TLV3544-Q1 is specified for operation from 2.5 V to 5.5 V (±1.25 to ±2.75 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are shown Typical Characteristics.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, see Layout
Guidelines.
10 Layout
10.1 Layout Guidelines
Good high-frequency printed-circuit board (PCB) layout techniques must be employed for the TLV3544-Q1.
Generous use of ground planes, short and direct signal traces, and a suitable bypass capacitor located at the V+
pin assure clean, stable operation. Large areas of copper also provides a means of dissipating heat that is
generated in normal operation.
TI does not recommend using sockets with any high-speed amplifier.
A 10-nF ceramic bypass capacitor is the minimum recommended value; adding a 1-µF or larger tantalum
capacitor in parallel can be beneficial when driving a low-resistance load. Providing adequate bypass
capacitance is essential to achieving very low harmonic and intermodulation distortion.
10.2 Layout Example
图 39. Operational Amplifier Board Layout for Noninverting Configuration
10.3 Power Dissipation
Power dissipation depends on power-supply voltage, signal and load conditions. With DC signals, power
dissipation is equal to the product of output current times the voltage across the conducting output transistor,
VS − VO. Power dissipation can be minimized by using the lowest possible power-supply voltage necessary to
assure the required output voltage swing.
For resistive loads, the maximum power dissipation occurs at a DC output voltage of one-half the power-supply
voltage. Dissipation with AC signals is lower. AB-039 Power Amplifier Stress and Power Handling Limitations
explains how to calculate or measure power dissipation with unusual signals and loads, and can be found at
www.ti.com.
版权 © 2017, Texas Instruments Incorporated
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TLV3544-Q1
ZHCSGU7 –OCTOBER 2017
www.ti.com.cn
Power Dissipation (接下页)
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature must be limited to 150°C, maximum. To estimate the
margin of safety in a complete design, increase the ambient temperature until the thermal protection is triggered
at 160°C. The thermal protection should trigger more than 35°C above the maximum expected ambient condition
of the application.
22
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ZHCSGU7 –OCTOBER 2017
11 器件和文档支持
11.1 文档支持
相关文档请参见以下部分：
•
•
•
•
•
•
•
•
•
•
《ADS8326 16 位、2.7V 至 5.5V 高速微功耗采样模数转换器》
《电路板布局布线技巧》
《用直观方式补偿跨阻放大器》
《FilterPro™ 用户指南》
《高速运算放大器噪声分析》
《OPA380 和 OPA2380 精密高速跨阻放大器》
《具有关闭功能的 OPA355、OPA2355 和 OPA3355 200MHz CMOS 运算放大器》
《OPA656 宽带单位增益稳定 FET 输入运算放大器》
《功率放大器应力和功率处理限制》
《PowerPAD 热增强型封装》
11.2 接收文档更新通知
要接收文档更新通知，请转至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品信
息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
版权 © 2017, Texas Instruments Incorporated
23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV3544QPWRQ1
ACTIVE
TSSOP
PW
14
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
3544Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV3544QPWRQ1
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 14
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
TLV3544QPWRQ1
2000
Pack Materials-Page 2
重要声明和免责声明
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