TLV365DBVR [TI]
50-MHz single-supply operational amplifier with rail-to-rail input and output | DBV | 5 | -40 to 125;
| 型号： | TLV365DBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 50-MHz single-supply operational amplifier with rail-to-rail input and output | DBV | 5 | -40 to 125 |
| 文件： | 总35页 (文件大小：2540K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV365, TLV2365
ZHCSPF9A –DECEMBER 2022 –REVISED JUNE 2023
TLVx365 50MHz、零交叉、高CMRR、RRIO 运算放大器
1 特性
3 说明
• 增益带宽：50MHz
• 零交叉失真拓扑：
TLV365 和 TLV2365 器件 (TLVx365) 是零交叉、轨到
轨输入和输出 CMOS 运算放大器系列，针对低电压和
成本敏感型应用进行了优化。得益于低噪声 (4.5nV/√
Hz) 和高速运行（50MHz 增益带宽）特性，此类器件
成为在低侧电流检测、音频、信号调节和传感器放大等
应用中驱动采样模数转换器(ADC) 的理想之选。
– CMRR：115dB（典型值）
– 轨至轨输入和输出
• 输入超出电源轨100mV
• 噪声：4.5nV/√Hz
• 压摆率：27 V/µs
• 快速稳定：0.2μs 至0.01%
• 精度:
特殊功能包括出色的共模抑制比(CMRR)、无输入级交
叉失真、高输入阻抗和轨到轨输入和输出摆幅。输入共
模范围同时包括正负电源。输出电压摆幅在电源轨的
10mV 以内。
– 温漂2μV/°C（最大值）
– 输入偏置电流：20pA（最大值）
• 工作电压：2.2V 至5.5V
TLVx365 的额定工作温度范围为−40°C 至+125°C。
器件信息
2 应用
封装(1)
器件型号
TLV365
TLV2365 (2)
通道数
DBV（SOT-23，5)
D（SOIC，8）
• 信号调节
• 数据采集
• 有源滤波器
• 测试设备
• 音频
单通道
双通道
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
(2) 预发布信息（非量产数据）。
• 宽带放大器
• 机架式服务器
Short-Circuit
Detection
R2
VTH
–
2 kΩ
LOAD
RF
TLV3201
C2
2.2 pF
+
VS+
VS+
RG
RG
−
V
ISH
–
−
REXT
V
U2
TLV365
SD1
RSH
TLV365
ADS7042
BAT17
U1
TLV365
+
VOUT
CEXT
RF
R1
7.5 Ω
+
V
VREF
C1
VIN
+
V
10 nF
TLVx365 用于电流检测
快速趋稳峰值检测器
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOSAA8
TLV365, TLV2365
ZHCSPF9A –DECEMBER 2022 –REVISED JUNE 2023
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................13
9 Application and Implementation..................................14
9.1 Application Information............................................. 14
9.2 Typical Applications.................................................. 16
9.3 Power Supply Recommendations.............................18
9.4 Layout....................................................................... 19
10 Device and Documentation Support..........................20
10.1 Device Support....................................................... 20
10.2 Documentation Support.......................................... 21
10.3 接收文档更新通知................................................... 21
10.4 支持资源..................................................................21
10.5 Trademarks.............................................................21
10.6 静电放电警告.......................................................... 21
10.7 术语表..................................................................... 21
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings ....................................... 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................6
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram.........................................10
8.3 Feature Description...................................................11
Information.................................................................... 21
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2022) to Revision A (June 2023)
Page
• 将OPA2365 的状态从“预发布”改为“预告信息”......................................................................................... 1
• Added Device Comparison Table ...................................................................................................................... 3
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English Data Sheet: SBOSAA8
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ZHCSPF9A –DECEMBER 2022 –REVISED JUNE 2023
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5 Device Comparison Table
OFFSET
VOLTAGE
NOISE
(nV/√Hz)
MINIMUM
GAIN STABLE
(V/V)
IQ/CHANNEL
TYPICAL
(mA)
GAIN
BANDWIDTH
(MHz)
DRIFT
TYPICAL
(µV/C)
SLEW RATE
(V/µs)
DEVICE
INPUT TYPE
TLVx365
OPAx607
OPAx365
CMOS
CMOS
CMOS
0.4
0.3
1
1
6
1
4.6
0.9
4.6
50
50
50
27
24
25
4.5
3.8
4.5
6 Pin Configuration and Functions
VOUT
1
2
3
5
4
V+
−
V
−
IN
+IN
图6-1. TLV365 DBV Package, 5-Pin SOT-23 (Top View)
表6-1. Pin Functions: TLV365
PIN
TYPE
DESCRIPTION
NAME
–IN
+IN
NO.
4
Input
Input
—
Negative (inverting) input
Positive (noninverting) input
Negative (lowest) power supply
Positive (highest) power supply
Output
3
2
V–
V+
5
—
VOUT
1
Output
V
OUTA
1
2
3
4
8
7
6
5
V+
VOUT
−
B
IN A
+IN A
−
IN B
+IN B
−
V
图6-2. TLV2365 D Package, 8-Pin SOIC (Top View)
Pin Functions: TLV2365
PIN
TYPE
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
V–
NO.
2
Input
Input
Input
Input
—
Negative (inverting) input signal, channel A
3
Positive (noninverting) input signal, channel A
Negative (inverting) input signal, channel B
Positive (noninverting) input signal, channel B
Negative (lowest) power supply
Positive (highest) power supply
Output, channel A
6
5
4
V+
8
—
VOUT
VOUT
A
B
1
Output
Output
7
Output, channel B
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English Data Sheet: SBOSAA8
TLV365, TLV2365
ZHCSPF9A –DECEMBER 2022 –REVISED JUNE 2023
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
VS
VI
6
(V+) + 0.5
±5
Supply voltage, VS = (V+) –(V–)
Input voltage
V
(V–) –0.5
VID
II
Differential input voltage
Continuous input current(2)
Output short-circuit(3)
Operating temperature
Junction temperature
Storage temperature
V
±10
mA
ISC
TA
TJ
Continuous
125
150
150
°C
°C
°C
–40
Tstg
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
(2) Input pins are diode-clamped to the power-supply rails. Limit the current of input signals that can swing more than 0.5 V beyond the
supply rails to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.2
NOM
MAX
5.5
UNIT
VS
TA
V
Supply voltage, VS = (V+) –(V–)
Specified temperature
25
125
°C
–40
7.4 Thermal Information
TLV365
TLV2365
THERMAL METRIC(1)
DBV (SOT-23)
D (SOIC)
8 PINS
140
UNIT
5 PINS
179
78
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
89
46
80
Junction-to-top characterization parameter
Junction-to-board characterization parameter
19
28
46
80
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
at VS = 2.2 V to 5.5 V, TA = 25°C, RL = 10 kΩ, VCM,VOUT = mid-supply, and gain = 1 V/V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
±0.4
±0.4
100
±1.9
mV
dVOS/dT
PSRR
Input offset voltage drift
Power-supply rejection ratio
±2 µV/°C
dB
TA = –40°C to +125°C
VS = 2.2 V to 5.5 V, TA = –40 to +125℃
INPUT BIAS CURRENT
±5
±20
IB
Input bias current
pA
TA = –40℃to +125℃
See 图7-5
NOISE
Input voltage noise (peak-to-peak)
Input voltage noise density
Input current noise density
f = 0.1 Hz to 10 Hz
f = 500 kHz
5.4
4.5
5.8
µVPP
eN
in
nV/√Hz
fA/√Hz
f = 1 kHz
INPUT VOLTAGE
VCM
Common-mode voltage
(V+) + 0.1
V
(V–) –0.1
115
110
(V–) –100 mV < VCM < (V+) + 100 mV
TA = –40℃to +125℃
CMRR
Common-mode rejection ratio
dB
INPUT IMPEDANCE
Differential
Common-mode
OPEN-LOOP GAIN
5
1
CIN
pF
RL = 10 kΩ, (V–) + 0.1 V < VOUT < (V+) –0.1
100
95
120
V
RL = 10 kΩ, TA = –40 to +125℃
AOL
Open-loop voltage gain
dB
°
RL = 600 Ω, (V–) + 0.2 V < VOUT < (V+) –0.2
100
94
120
56
V
RL = 600 Ω, TA = –40 to +125℃
Phase margin
FREQUENCY RESPONSE (VS = 5 V)
GBW
SR
Gain-bandwidth product
Slew rate
50
27
MHz
V/µs
0.1%, 4-V step
0.15
tS
Settling time
µs
0.01%, 4-V step
0.2
Overdrive recovery time
VIN+ × gain > VS
< 0.1
0.00025
µs
%
THD + N
Total harmonic distortion + noise(6)
VOUT = 4 VPP, f = 1 kHz, RL = 600 Ω
OUTPUT
10
12
Output voltage swing from supply rails
mV
mA
TA = –40°C to +125°C
ISC
Short-circuit current
±85
See 图7-16
40
Capacitive load drive
ZO
Open-loop output impedance
f = 1 MHz, IO = 0 mA
Ω
POWER SUPPLY
IO = 0 mA
4.6
5.8
6.3
IQ
Quiescent current per amplifier
mA
IO = 0 mA, TA = –40°C to +125°C
(1) Low-pass-filter bandwidth is 20 kHz for f = 1 kHz.
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ZHCSPF9A –DECEMBER 2022 –REVISED JUNE 2023
www.ti.com.cn
7.6 Typical Characteristics
at TA = 25°C, VS = 5 V, RL = 10 kΩ, and gain = 1 V/V (unless otherwise noted)
120
105
90
75
60
45
30
15
0
240
210
180
150
120
90
120
100
80
60
40
20
0
Gain (dB)
Phase Margin ()
60
30
0
PSRR
CMRR
-15
-30
-30
-60
10
100
1k
10k
100k
1M
10M 100M
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
图7-1. Open-Loop Gain and Phase vs Frequency
40k
图7-2. Power-Supply and Common-Mode Rejection Ratio
30
VS = 5.5 V
VS = 2.2 V
VS = 2.2 V
VS = 5.5 V
27
35k
30k
25k
20k
15k
10k
5k
24
21
18
15
12
9
6
3
0
Offset Voltage Drift (µV/°C)
40 units, μ= 0.06 μV/°C, σ= 0.4
μV/°C
Input Offset Voltage (µV)
70000 units, μ= 9.3 μV, σ= 320 μV.
图7-3. Offset Voltage Production Distribution
图7-4. Offset Voltage Drift Distribution
250
750
650
550
450
350
250
150
50
200
150
100
50
0
-50
-50
-50
-25
0
25
50
75
100
125
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Temmperature (C)
Common-Mode Voltage (V)
40 units
40 units
图7-5. Input Bias Current vs Temperature
图7-6. Input Bias Current vs Common-Mode Voltage
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ, and gain = 1 V/V (unless otherwise noted)
120
90
60
Source
30
0
-30
-60
-90
-120
Sink
-50
-25
0
25
50
75
100
125
Temperature (C)
VS = ±2.75 V
20 units
图7-7. Output Voltage vs Output Current
图7-8. Short-Circuit Current vs Temperature
3
0
3
0
-3
-3
-6
-6
VOUT = 200 mVPP
VOUT = 1 VPP
VOUT = 2 VPP
VOUT = 4 VPP
Gain = 1 V/V
Gain = −1 V/V
Gain = 10 V/V
Gain = 21 V/V
-9
-9
-12
-12
100k
1M
10M
100M
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
图7-9. Frequency Response vs Output Voltage
图7-10. Small-Signal Frequency Response vs Gain
6
0.01
Gain = 1 V/V, VRMS = 1.448 V
Gain = 1 V/V, VRMS = 1 V
Gain = 10 V/V, VRMS = 1.448 V
Gain = 10 V/V, VRMS = 1 V
3
0
0.001
-3
-6
-9
CL = 20 pF
CL = 10 pF
CL = 5 pF
0.0001
1M
10M
Frequency (Hz)
100M
100
1k
Frequency (Hz)
10k
RL = 600 Ω
图7-11. Small-Signal Response vs Capacitive Load
图7-12. Total Harmonic Distortion + Noise vs Frequency
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ, and gain = 1 V/V (unless otherwise noted)
4
3
100
10
1
2
1
0
-1
-2
-3
-4
0
1
2
3
4
5
6
7
8
9
10
10
100
1k
10k
100k
1M
Time (1s/div)
Frequency (Hz)
.
图7-13. 0.1-Hz to 10-Hz Input Voltage Noise
图7-14. Input Voltage Noise Spectral Density
10p
1p
80
70
60
50
40
30
20
10
0
Gain = 1 V/V
Gain = −1 V/V
Gain = 10 V/V
0.1p
10f
1f
0.1f
100m
1
10
100
1k
10k
100k
1M
10M
1p
10p
100p
1n
Frequency (Hz)
Capacitive Load (F)
For gain ≠1 V/V, RF = 1 kΩ. For gain = 1 V/V, RF = 0 Ω.
图7-16. Overshoot vs Capacitive Load
图7-15. Input Current Noise Spectral Density
3
2
VOUT
VIN
VOUT
VIN
1
0
-1
-2
-3
Time (50ns/div)
Time (200ns/div)
RL = 600 Ω
RL = 600 Ω
图7-17. Small-Signal Step Response
图7-18. Large-Signal Step Response
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RL = 10 kΩ, and gain = 1 V/V (unless otherwise noted)
10k
4
3
Ideal Output
Measured Ouput
2
1k
1
0
-1
-2
-3
-4
100
10
10
100
1k
10k
100k
1M
10M
100M
Time (100 ns/div)
Frequency (Hz)
VS = ±2.75 V
图7-19. Overdrive Recovery
图7-20. Open-Loop Output Impedance
120
100
80
60
40
20
0
100
90
80
70
60
50
40
30
20
-3 -2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
3
10M
100M
Frequency (Hz)
1G
10G
Output Voltage (V)
VS = ±2.75 V
图7-21. Open Loop Voltage Gain vs Output Voltage
图7-22. Electromagnetic Interference Rejection Ratio Referred
to Noninverting Input (EMIRR+) vs Frequency
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8 Detailed Description
8.1 Overview
The TLVx365 series of operational amplifiers feature rail-to-rail input and output, wide-bandwidth making these
devices an excellent choice for driving ADCs. Other typical applications include signal conditioning, low-side
current sensing, signal buffering and sensor amplification. The TLVx365 operates with either a single supply or
dual supplies.
Furthermore, the TLVx365 amplifier parameters are fully specified from 2.2 V to 5.5 V. Many of the specifications
apply from −40°C to +125°C.
8.2 Functional Block Diagram
V+
Low-Noise
Charge Pump
Bias Circuitry
+IN
−IN
OUT
Input Stage Load
Bias Circuitry
V−
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8.3 Feature Description
8.3.1 Rail-to-Rail Input
The TLVx365 product family features true rail-to-rail input operation, with supply voltages as low as ±1.1 V
(2.2 V). A unique zerø-crossover input topology eliminates the input offset transition region typical of many rail-
to-rail, complementary stage operational amplifiers. As shown in 图8-1, this topology also allows the TLVx365 to
provide excellent common-mode performance over the entire input range, which extends 100 mV beyond both
power-supply rails. When driving ADCs, the highly linear VCM range of the TLVx365 makes sure that the system
linearity performance is not compromised. For a simplified schematic illustrating the rail-to-rail input circuitry, see
节8.2.
200
VS
=
2.75 V
150
100
50
TLV365-Q1
0
−
50
−
100
Competitors
−
150
−
200
−
−
−
1
3
2
0
1
2
3
Common−Mode Voltage (V)
图8-1. TLVx365 Linear Offset Over the Entire Common-Mode Range
8.3.2 Input and ESD Protection
图 8-2 shows that the TLVx365 incorporates internal electrostatic discharge (ESD) protection circuits on all pins.
In the case of input and output pins, this protection primarily consists of current-steering diodes connected
between the input and power-supply pins. These ESD protection diodes also provide in-circuit, input overdrive
protection if the current is limited to 10 mA; see also 节 7.1. 图 8-3 shows how a series input resistor can be
added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier
input; the resistor must be kept to the minimum value in noise-sensitive applications.
V+
TVS
V+
IOVERLOAD
TLV365
10 mA max
TLV365
VOUT
VIN
5 kΩ
+IN
–
VOUT
图8-3. Input Current Protection
–IN
+
Power-Supply
ESD Cell
V–
图8-2. ESD Protection Scheme
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8.3.3 Driving Capacitive Loads
The TLVx365 can be used in applications where driving a capacitive load is required. An op amp in a unity-gain,
buffer configuration and driving a capacitive load exhibits a greater tendency to be unstable than an amplifier
operated at a higher gain. The capacitive load, in conjunction with the op-amp output impedance, creates a pole
within the feedback loop that degrades the phase margin. The degradation of the phase margin increases as the
capacitive loading increases.
图 8-4 shows one technique to increase the capacitive-load drive capability of the amplifier operating in unity
gain is to insert a small resistor, RISO, in series with the output. This resistor significantly reduces the overshoot
and ringing associated with capacitive loads.
RISO
TLV365
IN+
Gain = 1 V/V
RG
RF
RISO
TLV365
IN+
Gain 1 V/V
图8-4. Improving Capacitive Load Drive
A possible drawback of this technique is the voltage divider created with the added series resistor (RISO) and any
resistor (RL) connected in parallel with the capacitive load. The voltage divider introduces a gain error at the
output that also reduces the output swing. The error contributed by the voltage divider can be insignificant. For
instance, with a load resistance of RL = 10 kΩand RISO = 20 Ω, the gain error is only approximately 0.2%.
图 8-5 shows the recommended isolation resistor (RISO) to be connected at the output of TLVx365 for different
capacitive loads. The TLVx365 can drive higher capacitive loads without the need of isolation resistors at higher
gains.
For gain > 1 V/V, RF = 1 kΩ
For gain = 1 V/V, RF = 0 Ω
图8-5. Recommended Isolation Resistor vs Capacitive Load
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8.3.4 Active Filter
The TLVx365 is an excellent choice for active filter applications requiring a wide bandwidth, fast slew rate, low-
noise, single-supply operational amplifier. 图8-6 shows a 500-kHz, second-order, low-pass filter using a multiple-
feedback (MFB) topology. The components have been selected to provide a maximally-flat Butterworth
response. Beyond the cutoff frequency, rolloff is −40 dB/dec. The Butterworth response is designed for
applications requiring predictable gain characteristics, such as the antialiasing filter used ahead of an ADC.
R3
549Ω
C2
150 pF
V+
R1
R2
549 Ω
1.24 kΩ
VIN
TLV365
VOUT
C1
1 nF
−
V
图8-6. Second-Order Butterworth, 500-kHz Low-Pass Filter
When considering the MFB filter, the output is inverted, relative to the input. If this inversion is not desired, then a
noninverting output can be achieved through one of these options:
• add an inverting amplifier
• add an additional second-order MFB stage
• use a noninverting filter topology, such as the Sallen-Key
图8-7 shows the Sallen-Key topology.
C3
220 pF
R3
R1
R2
150 kΩ
1.8 kΩ
19.5 kΩ
VIN = 1VRMS
C1
3.3 nF
C2
TLV365
VOUT
47 pF
图8-7. Configured as a Three-Pole, 20-kHz, Sallen-Key Filter
8.4 Device Functional Modes
The device has one mode of operation that applies when operated within the recommended operating
conditions.
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TLVx365 offer outstanding dc and ac performance. These devices operate with up to a 5.5-V power supply,
offer an ultra-low input bias current and a 50-MHz bandwidth with true rail-to-rail input capability.
9.1.1 Overdrive Recovery Performance
The TLVx365 family exhibits excellent overdrive recovery when the output is driven well beyond the V+ or V–
supplies. When configured in a low-side current-sensing configuration (as in 图 9-1), the output of the op amp
(TLVx365) is often driven to or less than ground as a result of ground bounce at the power ground or the ≤ 0-A
current being measured across shunt resistance RSH. The TLVx365 has the ability to recover from an overdrive
event in < 100 ns. 图 9-2 shows the comparison of the overdrive recovery performance of TLVx365 and other
popular op amps in the same category.
300 V
3.3 V
Switching
Circuit
TLV3201
VTH
+
–
10 k
Interrupt
ISH
3.3 V
3.3 V
MCU
1 k
1 k
–
VOUT
RSH
Digital I/O
DUT
ADS7056
+
10 k
GND
图9-1. Low Side Current Sensing Application Circuit
5
OPA365
OPA836
OPA607
TLV365
4
3
2
1
0
-1
Time (200 ns/div)
Gain = 10 V/V. VOUT driven to (V–) –1 V
图9-2. TLVx365 Overdrive Recovery
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9.1.2 Achieving an Output Level of Zero Volts
Certain single-supply applications require the op‑amp output to swing from 0 V to a positive full-scale voltage
and have high accuracy. An example is an op amp employed to drive a single-supply ADC having an input range
from 0 V to 3.3 V. Rail-to-rail output amplifiers with very light output loading can achieve an output level within
few millivolts of 0 V (or V+ at the high end), but not true 0 V. Furthermore, the deviation from 0 V only becomes
greater as the required load current increases. This increased deviation is a result of limitations of the CMOS
output stage.
When a pulldown resistor is connected from the amplifier output to a negative voltage source, the TLVx365 can
achieve an output level of 0 V, and even a few millivolts below 0 V. 图9-3 shows a circuit using this technique.
V+ = +5 V
TLV365
VOUT
VIN
500 µA
RP =10 kΩ
Op Amps
Negative
Supply
−
−
V = 5 V
(Additional
Grounded
Negative Supply)
图9-3. Swing-to-Ground
A pulldown current of approximately 500 μA is required when TLVx365 is connected as a unity-gain buffer.
Pulldown resistor RL is calculated from RL = [(VO − VNEG) / (500 μA)].
图9-4 shows the offset voltage vs output swing.
20m
15m
10m
5m
0
−5m
−10m
−15m
−20m
-3 -2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
3
Output Voltage (V)
VS = ±2.75 V
图9-4. Offset Voltage vs Output Swing
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9.2 Typical Applications
9.2.1 Second-Order Low-Pass Filter
Low-pass filters are commonly employed in signal processing applications to reduce noise and prevent aliasing.
The TLVx365 is designed to construct high-speed, high-precision active filters. 图9-5 shows a second-order low-
pass filter commonly encountered in signal processing applications.
R4
2.94 kꢀ
C5
1 nF
œ
R1
590 ꢀ
R3
499 ꢀ
Output
+
Input
C2
39 nF
Copyright © 2016, Texas Instruments Incorporated
图9-5. Second-Order Low-Pass Filter
9.2.1.1 Design Requirements
Use the following parameters for this design example:
• Gain = 5 V/V (inverting gain)
• Low-pass cutoff frequency = 25 kHz
• Second-order, Chebyshev filter response with 3-dB gain peaking in the pass band
9.2.1.2 Detailed Design Procedure
图 9-5 shows the infinite-gain, multiple-feedback circuit for a low-pass network function. Use 方程式 1 to
calculate the voltage transfer function.
-1 R1R3C2C5
Output
Input
s =
( )
s2 + s C 1 R +1 R +1 R +1 R R C C
2
1
3
4
3 4 2 5
(1)
This circuit produces a signal inversion. For this circuit, use 方程式2 to calculate the gain at dc and the low-pass
cutoff frequency.
R4
Gain =
R1
1
fC
=
1 R R C C
(
3 4 2 5
)
2p
(2)
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9.2.1.3 Application Curve
20
0
-20
-40
-60
100
1k
10k
Frequency (Hz)
100k
1M
图9-6. TLVx365 Second-Order 25 kHz, Chebyshev, Low-Pass Filter
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9.2.2 ADC Driver and Reference Buffer
图 9-7 shows the use of a TLVx365 op amp as a SAR ADC input and reference pin driver. Sensors, which are
used for interfacing with the physical environment, exhibit high output impedance and cannot drive SAR ADC
inputs directly. The TLVx365 devices exhibit a very low-input bias current of 20 pA (maximum), and therefore do
not load these high-output impedance sensors. A wide-GBW amplifier connected to the output of these sensors
is needed to charge the switching capacitors at the SAR ADC input and to settle fast, to the required accuracy,
within the given acquisition time.
The ADC core draws transient current from the reference input during the conversion (digitization) phase, which
must be driven with a wide-GBW amplifier to offer fast settling and maintain a stable reference voltage for
excellent digitization performance. The TLVx365 reference buffer is used in a composite loop with the OPA378
precision amplifier because of limitations in precision performance of wide-GBW amplifiers. The precision
amplifier maintains low-offset output, whereas the TLVx365 provide the output drive and fast-settling
performance.
RF
RG
5 V
5 V
5 V
–
+
RS
AVDD
DVDD
Sensor
TLV365
ZOUT
ADS7945
14-bit
CCB
2 MSPS
VREF
5 V
5 V
5 V
–
OPA378
+
–
RFILT
Reference
TLV365
CFILT
+
图9-7. TLVx365 as a SAR ADC Driver
9.3 Power Supply Recommendations
The TLVx365 family is operational when the power-supply voltage is greater than 2.2 V (±1.1 V). The maximum
power supply voltage for the TLVx365 family is 5.5 V (±2.75 V). The TLVx365 operate on both single and dual
supplies. The maximum permissible voltage, VS, is 6 V.
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9.4 Layout
9.4.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including
the following guidelines:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole or through the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
– The TLVx365 is capable of peak output current (in excess of 50 mA). Applications with low impedance
loads or capacitive loads with fast transient signals demand large currents from the power supplies. Larger
bypass capacitors, such as 1-µF solid tantalum capacitors, can improve dynamic performance in these
applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed
to in parallel with the noisy trace.
• Place the external components as close to the device as possible. 图9-8 shows that keeping RF and RG
close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
9.4.2 Layout Example
VIN A
VIN B
+
+
VOUT A
VOUT B
RG
RG
RF
RF
(Schematic Representation)
Place components
close to device and to
each other to reduce
parasitic errors.
VOUT A
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
VS+
GND
OUT A
V+
RF
VOUT B
GND
-IN A
+IN A
V–
OUT B
-IN B
RF
RG
GND
VIN B
VIN A
RG
+IN B
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
GND
ceramic bypass
capacitor. Place as
close to the device
as possible.
VS–
Ground (GND) plane on another layer
as possible.
图9-8. Layout Recommendation for TLV2365 SOIC Package
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10 Device and Documentation Support
10.1 Device Support
10.1.1 Development Support
10.1.1.1 PSpice® for TI
PSpice® for TI 是可帮助评估模拟电路性能的设计和仿真环境。在进行布局和制造之前创建子系统设计和原型解决
方案，可降低开发成本并缩短上市时间。
10.1.1.2 TINA-TI™ 仿真软件（免费下载）
TINA-TI™ 仿真软件是一款简单易用、功能强大且基于 SPICE 引擎的电路仿真程序。TINA-TI 仿真软件是 TINA™
软件的一款免费全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI 仿
真软件提供所有传统的SPICE 直流、瞬态和频域分析，以及其他设计功能。
TINA-TI 仿真软件提供全面的后处理能力，便于用户以多种方式获得结果，用户可从设计工具和仿真网页免费下
载。虚拟仪器提供选择输入波形和探测电路节点、电压以及波形的能力，从而构建一个动态的快速启动工具。
备注
必须安装 TINA 软件或者 TINA-TI 软件后才能使用这些文件。请从 TINA-TI™ 软件文件夹中下载免费的
TINA-TI 仿真软件。
10.1.1.3 DIP-Adapter-EVM
借助 DIP-Adapter-EVM 加快运算放大器的原型设计和测试，该 EVM 有助于快速轻松地连接小型表面贴装器件并
且价格低廉。使用随附的 Samtec 端子板连接任何受支持的运算放大器，或者将这些端子板直接连接至现有电
路。DIP-Adapter-EVM 套件支持以下业界通用封装：D 或 U (SOIC-8)、PW (TSSOP-8)、DGK (VSSOP-8)、
DBV（SOT-23-6、SOT-23-5 和SOT-23-3）、DCK（SC70-6 和SC70-5）和DRL (SOT563-6)。
10.1.1.4 DIYAMP-EVM
DIYAMP-EVM 是一款独特的评估模块(EVM)，可提供真实的放大器电路，使用户能够快速评估设计概念并验证仿
真。此 EVM 采用 3 种业界通用封装选项（SC70、SOT23 和 SOIC）并提供 12 种流行的放大器配置，包括放大
器、滤波器、稳定性补偿以及同时适用于单电源和双电源的比较器配置。
10.1.1.5 TI 参考设计
TI 参考设计是由TI 的精密模拟应用专家创建的模拟解决方案。TI 参考设计提供了许多实用电路的工作原理、组件
选择、仿真、完整印刷电路板 (PCB) 电路原理图和布局布线、物料清单以及性能测量结果。TI 参考设计可在线获
取，网址为https://www.ti.com/reference-designs。
10.1.1.6 滤波器设计工具
滤波器设计工具是一款简单、功能强大且便于使用的有源滤波器设计程序。利用滤波设计器，用户可使用精选 TI
运算放大器和TI 供应商合作伙伴提供的无源器件来打造理想滤波器设计方案。
设计工具和仿真网页以基于网络的工具形式提供滤波设计工具。用户通过该工具可在短时间内完成多级有源滤波
器解决方案的设计、优化和仿真。
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10.2 Documentation Support
10.2.1 Related Documentation
The following documents are relevant to using the TLVx365, and recommended for reference. All are available
for download at www.ti.com unless otherwise noted.
• Texas Instruments, FilterPro™ software user's guide
• Texas Instruments, Low Power Input and Reference Driver Circuit for ADS8318 and ADS8319 application
report
• Texas Instruments, Op Amp Performance Analysis application bulletin
• Texas Instruments, Single-Supply Operation of Operational Amplifiers application bulletin
• Texas Instruments, The Best of Baker's Best –Amplifiers eBook reference book
10.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.5 Trademarks
TINA-TI™, FilterPro™, and TI E2E™ are trademarks of Texas Instruments.
TINA™ is a trademark of DesignSoft, Inc.
PSpice® is a registered trademark of Cadence Design Systems, Inc.
所有商标均为其各自所有者的财产。
10.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
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13-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV365DBVR
XTLV2365DR
ACTIVE
ACTIVE
SOT-23
SOIC
DBV
D
5
8
3000 RoHS & Green
3000 TBD
NIPDAU
Level-1-260C-UNLIM
Call TI
-40 to 125
-40 to 125
T365
Samples
Samples
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jul-2023
OTHER QUALIFIED VERSIONS OF TLV365 :
Automotive : TLV365-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV365DBVR
SOT-23
DBV
5
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-23 DBV
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
TLV365DBVR
5
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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