TLV4062DRYR [TI]
具有集成基准的双路比较器（推挽式） | DRY | 6 | -40 to 125;
| 型号： | TLV4062DRYR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成基准的双路比较器（推挽式） | DRY | 6 | -40 to 125 比较器 |
| 文件： | 总33页 (文件大小：2166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV4062, TLV4082
SBVS404A –APRIL 2020–REVISED JUNE 2020
TLV4062, TLV4082 Dual-Channel, Low-Power Comparator with Integrated Reference
1 Features
3 Description
The TLV4062 and TLV4082 are a family of high-
accuracy, dual-channel comparators featuring low
power and small solution size. The IN1 and IN2
inputs include hysteresis to reject brief glitches, thus
ensuring stable output operation without false
triggering.
1
•
Wide supply voltage range: 1.5 V to 5.5 V
Two-channel detectors in small packages
High threshold accuracy: 1% over temperature
Precision hysteresis: 60 mV
•
•
•
•
•
•
Low quiescent current: 2 µA (typ)
The TLV4062 and TLV4082 have adjustable INx
inputs that can be configured by an external resistor
divider pair. When the voltage at the IN1 or IN2 input
goes below the falling threshold, OUT1 or OUT2 is
driven low, respectively. When IN1 or IN2 rises above
the rising threshold, OUT1 or OUT2 goes high,
respectively.
Temperature range: –40°C to +125°C
Push-pull (TLV4062) and open-drain (TLV4082)
output options
•
Available in an SOT-23 and µSON package
2 Applications
•
•
•
•
Electricity meters
Thermostats
The comparators have a very low quiescent current
of 2 µA (typical) and provide a precise, space-
conscious solution for low-power, voltage monitoring.
The TLV4062 and TLV4082 operate from 1.5 V to 5.5
V, over the –40°C to +125°C temperature range.
Cordless power tools
Circuit breakers
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
2.90 mm × 1.60 mm
1.45 mm × 1.00 mm
TLV4062, TLV4082 SOT-23 (6)
TLV4062, TLV4082 µSON (6)
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Block Diagram for TLV4062
Block Diagram for TLV4082
V+
V+
VPU
Rpu1
IN1
IN1
OUT1
OUT1
VPU
IN2
Rpu2
IN2
OUT2
OUT2
VIT+
VIT+
V-
V-
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV4062, TLV4082
SBVS404A –APRIL 2020–REVISED JUNE 2020
www.ti.com
Table of Contents
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Applications ................................................ 13
Power Supply Recommendations...................... 18
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 6
6.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagrams ..................................... 10
8
9
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1 Documentation Support ........................................ 20
11.2 Receiving Notification of Documentation Updates 20
11.3 Related Links ........................................................ 20
11.4 Support Resources ............................................... 21
11.5 Trademarks........................................................... 21
11.6 Electrostatic Discharge Caution............................ 21
11.7 Glossary................................................................ 21
7
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (April 2020) to Revision A
Page
•
Deleted 1% hysteresis option ................................................................................................................................................ 1
2
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SBVS404A –APRIL 2020–REVISED JUNE 2020
5 Pin Configuration and Functions
DRY Package
1.45-mm x 1-mm µSON
Top View
IN1
1
6
V+
GND
IN2
2
5
4
OUT1
OUT2
3
DBV Package
6-Pin SOT-23
Top View
1
2
6
5
V+
IN1
OUT1
V-
OUT2
3
4
IN2
Pin Functions
NO.
NAME
GND
I/O
DESCRIPTION
DBV
DRY
5
2
—
Ground
OUT1 is the output for IN1. OUT1 is asserted (driven low) when the voltage at IN1 falls below VIT–
OUT1 is deasserted (goes high) after IN1 rises higher than VIT+
OUT1 is a push-pull output for the TLV4062 and an open-drain output for the TLV4082.
The open-drain device (TLV4082) can be pulled up to 5.5 V independent of V+; a pullup resistor is
required for this device.
.
.
OUT1
OUT2
2
3
5
4
O
O
OUT2 is the output for IN2. OUT2 is asserted (driven low) when the voltage at IN2 falls below VIT–
OUT2 is deasserted (goes high) after IN2 rises higher than VIT+
OUT2 is a push-pull output for the TLV4062 and an open-drain output for the TLV4082.
The open-drain device (TLV4082) can be pulled up to 5.5 V independent of V+; a pullup resistor is
required for this device.
.
.
This pin is connected to the voltage to be monitored with the use of an external resistor divider.
When the voltage at this pin drops below the threshold voltage (VIT–), OUT1 is asserted.
IN1
IN2
6
4
1
3
I
I
This pin is connected to the voltage to be monitored with the use of an external resistor divider.
When the voltage at this pin drops below the threshold voltage (VIT–), OUT2 is asserted.
Supply voltage input. Connect a 1.5-V to 5.5-V supply to V+ in order to power the device. Good
V+
1
6
I
analog design practice is to place a 0.1-µF ceramic capacitor close to this pin (required for V+ < 1.5
V).
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
VDD
7
OUT1, OUT2 (TLV4062 only)
VDD + 0.3
Voltage
V
OUT1, OUT2 (TLV4082 only)
7
IN1, IN2
7
IN1, IN2(2)
10
Current
mA
°C
OUT1, OUT2
±20
125
150
(3)
Operating junction, TJ
–40
–65
Temperature
Storage, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to GND. Input signals that can swing 0.3V below GND must be current-limited to 10mA or less.
(3) For low-power devices, the junction temperature rise above the ambient temperature is negligible; therefore, the junction temperature is
considered equal to the ambient temperature (TJ = TA).
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC
specification JESD22-C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP155 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
1.5
0
NOM
MAX
5.5
UNIT
Power-supply voltage
Input voltage
V
V
IN1, IN2
5.5
Output voltage (TLV4062 only)
Output voltage (TLV4082 only)
Pullup resistor (TLV4082 only)
Current
OUT1, OUT2
OUT1, OUT2
0
VDD + 0.3
5.5
V
0
V
RPU
1.5
–5
10,000
5
kΩ
mA
µF
°C
OUT1, OUT2
CIN
TJ
Input capacitor
0.1
25
Junction temperature
–40
125
4
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SBVS404A –APRIL 2020–REVISED JUNE 2020
6.4 Thermal Information
TLV4062, TLV4082
THERMAL METRIC(1)
DBV (SOT-23)
DRY (µSON)
6 PINS
306.7
UNIT
6 PINS
193.9
134.5
39.0
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
174.1
173.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
30.4
30.9
ψJB
38.5
171.6
RθJC(bot)
N/A
65.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
all specifications are over the operating temperature range of –40°C < TJ < +125°C and 1.5 V ≤ VDD ≤ 5.5 V (unless
otherwise noted); typical values are at TJ = 25°C and VDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
5.5
UNIT
V
VDD
Input supply range
1.5
V(POR)
Power-on-reset voltage(1)
VOL (max) = 0.2 V, IOL = 15 µA
VDD = 3.3 V, no load
0.8
V
2.09
2.29
5.80
6.50
IDD
Supply current (into VDD pin)
µA
V
VDD = 5.5 V, no load
1.194
Positive-going (rising) input
threshold voltage
VIT+
V(INx) rising
V(INx) falling
–1%
–1%
–15
1%
1%
1.134
60
V
Negative-going (falling) input
threshold voltage
VIT–
VHYS
I(INx)
In-built Hysteresis
Input current
mV
nA
V(INx) = 0 V or VDD
15
0.25
0.25
0.30
VDD ≥ 1.5 V, ISINK = 0.4 mA
VDD ≥ 2.7 V, ISINK = 2 mA
VDD ≥ 4.5 V, ISINK = 3.2 mA
VDD ≥ 1.5 V, ISOURCE = 0.4 mA
VDD ≥ 2.7 V, ISOURCE = 1 mA
VDD ≥ 4.5 V, ISOURCE = 2.5 mA
VOL
Low-level output voltage
V
0.8 VDD
0.8 VDD
0.8 VDD
High-level output voltage
(TLV4062 only)
VOH
V
Open-drain output leakage
current (TLV4082 only)
Ilkg(OD)
High impedance, V(INx) = V(OUTx) = 5.5 V
–250
250
nA
(1) Outputs are undetermined below V(POR)
.
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6.6 Timing Requirements
typical values are at TJ = 25°C and VDD = 3.3 V; INx transitions between 0 V and 1.3 V
MIN
NOM
5.5
MAX
UNIT
µs
tPD(r)
tPD(f)
tSD
INx (rising) to OUTx propagation delay
INx (falling) to OUTx propagation delay
Startup delay(1)
10
µs
570
µs
(1) During power-on or when a VDD transient is below VDD(min), the outputs reflect the input conditions 570 µs after VDD transitions
through VDD(min).
V+(min)
V+
V(POR)
VIT+
VITœ
INx
VHYS
OUTx
tPD(f)
tSD
tPD(r)
tSD
Figure 1. Timing Diagram
6
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SBVS404A –APRIL 2020–REVISED JUNE 2020
6.7 Typical Characteristics
at TJ = 25°C with a 0.1-µF capacitor close to V+ (unless otherwise noted)
0.4
0.32
0.24
0.16
0.08
0
5
4.5
4
IN1 V+ = 1.5 V
IN1 V+ = 5.5 V
IN2 V+ = 1.5 V
IN2 V+ = 5.5 V
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
3.5
3
2.5
2
-0.08
-0.16
-0.24
-0.32
-0.4
1.5
1
0.5
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
0
0.5
1
1.5
2
2.5 3
V+ (V)
3.5
4
4.5
5
5.5
IN1 = IN2 = 1.5 V
Figure 2. Supply Current vs Supply Voltage
Figure 3. INx Threshold (VIT+) Deviation vs Temperature
0.4
4500
4000
3500
3000
2500
2000
1500
1000
500
IN1 V+ = 1.5 V
IN1 V+ = 5.5 V
IN2 V+ = 1.5 V
IN2 V+ = 5.5 V
0.32
0.24
0.16
0.08
0
-0.08
-0.16
-0.24
-0.32
-0.4
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VIT+ Accuracy (%)
V+ = 5.5 V
Figure 4. INx Threshold (VIT–) Deviation vs Temperature
Figure 5. INx Threshold (VIT+
)
1.3
1.2
1.1
1
5500
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0
1
2
3
Output Sink Current (mA)
4
5
VIT- Accuracy (%)
V+ = 5.5 V
Figure 7. Output Voltage Low vs Output Current
(V+ = 1.5 V)
Figure 6. INx Threshold (VIT–
)
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Typical Characteristics (continued)
at TJ = 25°C with a 0.1-µF capacitor close to V+ (unless otherwise noted)
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
0
1
2
Output Sink Current (mA)
3
4
5
0
1
2
Output Sink Current (mA)
3
4
5
Figure 8. Output Voltage Low vs Output Current
(V+ = 3.3 V)
Figure 9. Output Voltage Low vs Output Current
(V+ = 5.5 V)
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
3.75
3.5
3.25
3
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
2.75
2.5
2.25
2
0.9
0.8
0.7
1.75
1.5
0.1
0.2
0.3
Output Source Current (mA)
0.4
0.5
0.6
0.7
0.8
0
0.5
1
1.5
2
Output Source Current (mA)
2.5
3
3.5
4
4.5
5
Figure 10. Output Voltage High vs Output Current
(V+ = 1.5 V)
Figure 11. Output Voltage High vs Output Current
(V+ = 3.3 V)
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
5.75
5.5
5.25
5
IN1 V+ = 1.5 V
IN1 V+ = 5.5 V
IN2 V+ = 1.5 V
IN2 V+ = 5.5 V
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
4.75
4.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
0
0.5
1
1.5
2
2.5
3
3.5
Output Source Current (mA)
4
4.5
5
IN1 = IN2 = 0 V to 1.3 V
Figure 12. Output Voltage High vs Output Current
(V+ = 5.5 V)
Figure 13. Propagation Delay from
INx High to Output High
8
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Typical Characteristics (continued)
at TJ = 25°C with a 0.1-µF capacitor close to V+ (unless otherwise noted)
14
12
10
8
1150
1050
950
850
750
650
550
450
350
250
V+ = 1.5 V
V+ = 5.5 V
IN1 V+ = 1.5 V
IN1 V+ = 5.5 V
IN2 V+ = 1.5 V
IN2 V+ = 5.5 V
6
4
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
IN1 = IN2 = 1.3 V to 0 V
Figure 14. Propagation Delay from
INx Low to Output Low
Figure 15. Startup Delay
55
50
45
40
35
30
25
20
15
10
5
55
50
45
40
35
30
25
20
15
10
5
TJ = -40°C
TJ = 0°C
TJ = +25°C
TJ = +85°C
TJ = +105°C
TJ = +125°C
TJ = -40°C
TJ = 0°C
TJ = +25°C
TJ = +85°C
TJ = +105°C
TJ = +125°C
0
0
0
3
6
9
12
Overdrive (%)
15
18
21
24
27
30
0
3
6
9
12
Overdrive (%)
15
18
21
24
27
30
High-to-low transition occurs above the curve
High-to-low transition occurs above the curve
Figure 16. Propagation Delay vs Overdrive
(V+ = 1.5 V)
Figure 17. Propagation Delay vs Overdrive
(V+ = 5.5 V)
35
35
TJ = -40°C
TJ = 0°C
TJ = +25°C
TJ = +85°C
TJ = +105°C
TJ = +125°C
TJ = -40°C
TJ = 0°C
TJ = +25°C
TJ = +85°C
TJ = +105°C
TJ = +125°C
32.5
30
32.5
30
27.5
25
27.5
25
22.5
20
22.5
20
17.5
15
17.5
15
12.5
10
12.5
10
7.5
5
7.5
5
2.5
0
2.5
0
0
3
6
9
12
Overdrive (%)
15
18
21
24
27
30
0
3
6
9
12
Overdrive (%)
15
18
21
24
27
30
Low-to-high transition occurs above the curve
Low-to-high transition occurs above the curve
Figure 18. Propagation Delay vs Overdrive
(V+ = 1.5 V)
Figure 19. Propagation Delay vs Overdrive
(V+ = 5.5 V)
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7 Detailed Description
7.1 Overview
The TLV4062 and TLV4082 are small, low quiescent current (IDD), dual-channel comparators. These devices
have high-accuracy, rising and falling input thresholds, and assert the output as shown in Table 1. The output
(OUTx) transitions high when the input (INx) is rising and greater than VIT+; the output (OUTx) will remain high
until the input is falling and drops below VIT- . The TLV4062 and TLV4082 can be used in systems where multiple
voltage rails are required to be monitored, or where one channel can be used as an early warning signal and the
other channel can be used as the system reset signal.
Table 1. TLV4062 and TLV4082 Truth Table
OUTPUT
LOGIC
LEVEL
OUTPUT
TOPOLOGY
DEVICE
(VIT+, VIT-
)
INPUT VOLTAGE
IN1 < VIT–
IN1 falling
IN2 falling
IN1 rising
IN2 rising
IN1 falling
IN2 falling
IN1 rising
IN2 rising
OUT1 = low
OUT2 = low
OUT1 = high
OUT2 = high
OUT1 = low
OUT2 = low
OUT1 = high
OUT2 = high
IN2 < VIT–
IN1 > VIT+
IN2 > VIT+
IN1 < VIT–
IN2 < VIT–
IN1 > VIT+
IN2 > VIT+
TLV4062
Push-Pull
1.194V, 1.134V
TLV4082
Open-Drain
7.2 Functional Block Diagrams
V+
V+
VPU
Rpu1
IN1
IN1
OUT1
OUT1
VPU
IN2
Rpu2
IN2
OUT2
OUT2
VIT+
VIT+
V-
V-
Figure 20. TLV4062 (Push-Pull Output) Block
Diagram
Figure 21. TLV4082 (Open-Drain Output) Block
Diagram
10
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7.3 Feature Description
The TLV4062 (push-pull) and TLV4082 (open-drain) devices are micro-power, dual-channel comparators that are
capable of operating at low voltages. The TLV4062 and TLV4082 features high-accuracy integrated reference
thresholds with internal hysteresis of 60mV. If the voltage at the inputs, INx, rises above the threshold, the
outputs, OUTx, are driven high; if the voltage at the inputs, INx, falls below the threshold, the outputs, OUTx, are
driven low.
7.4 Device Functional Modes
When the voltage on V+ is lower than V(POR), both outputs are undefined and are not to be relied upon for proper
system function.
7.4.1 Inputs (IN1, IN2)
The TLV4062 and TLV4082 each have two comparators for voltage detection. Each comparator has one external
input; the other input is connected to the internal reference. The comparator rising threshold is designed and
trimmed to be equal to VIT+, and the falling threshold is trimmed to be equal to VIT–. The difference between VIT+
and VIT- is referred to as the comparator hysteresis and is 60 mV. The integrated hysteresis makes the TLV40x2
less sensitive to supply-rail nose and provides stable operation in noisy environments without having to add
external positive feedback to create hysteresis.
The comparator inputs can swing from ground to 5.5 V, regardless of the device supply voltage used. This
includes the instance when no supply voltage is applied to the comparator (V+ = 0 V). As a result, the TLV40x2
is referred to as fault tolerant, meaning it mainitains the same high input impedance when V+ is unpowered or
ramping up. Although not required in most cases, for extremely noisy applications, good analog design practice
is to place a 1-nF to 10-nF bypass capacitor at the comparator input in order to reduce sensitivity to transients
and layout parasitic.
For each INx input, the corresponding output (OUTx) is driven to logic low when the input voltage drops below
VIT–. When the voltage exceeds VIT+, the output (OUTx) is driven high; see Figure 1.
7.4.2 Outputs (OUT1, OUT2)
The TLV4062 features push-pull output stages which eliminates the need for an external pull-up resistor, thus
saving board space, while providing a low impedance output driver. The logic high level of the outputs is
determined by the V+ pin voltage.
The TLV4082 features open-drain output stages which enables the output logic levels to be pulled-up to an
external source as high as 5.5 V independent of the supply voltage. Pull-up resistors must be used to hold these
lines high when the output goes to a high-impedance condition (not asserted). By connecting pull-up resistors to
the proper voltage rails, the outputs can be connected to other devices at correct interface voltage levels. To
ensure proper voltage levels, make sure to choose the correct pull-up resistor values. The pull-up resistor value
is determined by VOL, the sink current capability, and the output leakage current (Ilkg(OD)). These values are
specified in the Electrical Characteristics table. By using wired-OR logic, OUT1 and OUT2 can be combined into
one logic signal. The Inputs (IN1, IN2) section describes how the outputs are asserted or de-asserted. See
Figure 1 for a description of the relationship between threshold voltages and the respective output.
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Device Functional Modes (continued)
7.4.3 Switching Threshold and Hysteresis
The TLV40x2 transfer curve is show in Figure 22.
•
•
•
VIT+ represents the rising input threshold that causes the comparator output to change from a logic low state
to a logic high state.
VIT- represents the falling input threshold that causes the comparator output to change from logic high state to
a logic low state.
VHYS represents the difference between VIT+ and VIT- and is 60 mV for TLV40x2.
VHYS = (VIT+) œ (VIT-)
VIT-
VIT+
Figure 22. TLV40x2 Transfer Curve
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV4062 and TLV4082 are used as precision, dual-voltage monitors. The monitored voltage, V+ voltage,
and output pullup voltage (TLV4082 only) can be independent voltages or connected in any configuration.
In a typical device application, the outputs are connected to a reset or enable input of another device, such as a
digital signal processor (DSP), central processing unit (CPU), field-programmable gate array (FPGA), or
application-specific integrated circuit (ASIC); or the outputs are connected to the enable input of a voltage
regulator, such as a dc-dc or low-dropout (LDO) regulator.
8.1.1 Threshold Overdrive
Threshold overdrive is how much VIN1 or VIN2 exceeds the specified threshold, and is important to know because
a smaller overdrive results in a slower OUTx response. Threshold overdrive is calculated as a percent of the
threshold in question, as shown in Equation 1:
Overdrive = | (VIN1,2 / VIT – 1) × 100% |
(1)
where
•
VIT is either VIT– or VIT+, depending on whether calculating the overdrive for the falling input threshold or the
rising input threshold, respectively
•
VIN1,2 is the voltage at the IN1 or IN2 input
Figure 16 and Figure 17illustrates the minimum detectable pulse on the INx inputs versus overdrive, and is used
to visualize the relationship that overdrive has on tPD(f) for high to low transitions. Figure 18 and Figure 19 is used
to visual the relationship that overdrive has on tPD(r) for low to high transitions.
8.2 Typical Applications
8.2.1 Monitoring Two Separate Rails
The TLV40x2 series can be used to monitor two separate rails for over voltage detection. Over-voltage
monitoring is frequently used for system protection to alert the system to shutdown to prevent from damage. The
TLV4062 and TLV4082 also have adjustable INx inputs that can be configured to monitor voltages using external
resistor divider, as shown in Figure 23.
V+ = 1.5 V to 6.5 V
0.1 ꢀF
TLV4082 Only
VMON1
VPULLUP
V+
R1
RPU1
To a reset or enable
VMON2
IN1
IN2
OUT1
OUT2
input of the system
R3
R2
RPU1
To a reset or enable
input of the system
R4
V-
Figure 23. Monitoring Two Separate Rails Schematic
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Typical Applications (continued)
8.2.1.1 Design Requirements
For this design, follow these requirements:
•
•
•
VMON1 = 5 V and VMON2 = 3.3 V
Set VMON1 over-voltage condition at 6.5 V
Set VMON2 over-voltage condition at 4 V
8.2.1.2 Detailed Design Procedure
Configure the circuit as shown in Figure 23. Connect V+ to a power supply that is compatible with the input logic
level of the device connected to the output, and connect V- to ground. Resistors R1 and R2 create the over-
voltage alert level at 6.5 V and resistors R3 and R4 create the over-voltage alert level at 4 V. When the VMON
rises, the resistor divider voltage crosses VIT+. This causes the comparator output to transition from a logic low
level (normal operation), to a logic high level. When VMON falls back down and the resistor divider voltage
crosses VIT- and signal that the system is approaching normal operating voltage levels once again. Make sure to
set VMON at a value below the absolute maximum voltage of the system in question.
(2)
where
•
•
•
R1/R3 and R2/R4 are the resistor values for the resistor divider connected to INx
VMON is the voltage source that is being monitored for an over-voltage condition
VIT+ is the rising edge threshold where the comparator output changes state from low to high
Rearranging Equation 2 and solving for R1 yields Equation 3. Set R2/R4 to a fixed value.
(3)
Using the nearest 1% resistors and the equation above, R1 = 300 kΩ, R2 =1.33 MΩ, R3 = 953 kΩ, and R4 = 407
kΩ. To get the trip point as close as possible to rising threshold, VIT+, VMON are adjusted so that VMON1 = 6.49 V
and VMON2 = 3.99 V. Using equation Equation 4 will determine when the output will fall low (crossing VIT-). The
over-voltage signal will go low when VMON1 = 6.16 V and VMON2 = 3.79 V.
(4)
where
•
VMON is the voltage at which the resistor divider crosses the falling threshold, VIT-
Choose RTOTAL (equal to R1 + R2 & R3 + R4) so that the current through the divider is approximately 100 times
higher than the input current at the INx pins. The resistors can have high values to minimize current consumption
as a result of low input bias current without adding significant error to the resistive divider. For details on sizing
input resistors, see the Optimizing Resistor Dividers at a Comparator Input application report (SLVA450),
available for download from www.ti.com.
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Typical Applications (continued)
8.2.1.3 Application Curve
Figure 24 shows the simulated results of monitoring two independent voltage rails for an over-voltage event.
6.49 V
6.14 V
VMON1
tPLH
tPHL
VPU
OUTx
0 V
3.99 V
3.79 V
VMON2
tPLH
tPHL
Figure 24. Overvoltage Detection
8.2.2 Early Warning Detection
The TLV40x2 series can be used to monitor for early warning detection where OUT1 sends an early warning
alert signal and OUT2 sends an alert signal. This type of topology can be used for sensitive systems so a
warning alert can trigger before system shutdown occurs. The TLV4062 and TLV4082 also have adjustable INx
inputs that can be configured to monitor voltages using external resistor divider, as shown in Figure 25.
VMON
0.1 ꢀF
TLV4082 Only
VPULLUP
V+
R1
RPU1
To a reset or enable
IN1
IN2
OUT1
OUT2
input of the system.
R2
R3
RPU1
To a reset or enable
input of the system.
V-
Figure 25. Early Warning Detection Schematic
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Typical Applications (continued)
8.2.2.1 Design Requirements
For this design, follow these requirements:
•
•
VMON = 3.3V
Set the transition points VMON1 = 3.5 V and VMON2= 3.9 V
8.2.2.2 Detailed Design Procedure
Configure the circuit as shown in Figure 25. Connect V+ to a 3.3 V power rail and connect V- to ground. The
resistor network is used to create an early warning detection signal at OUT2, which will give a warning alert as
VMON approaches the max limit, changing state from a logic low to a logic high. OUT2 will stay high for a longer
period until VMON is no longer in the warning zone. OUT1 will be used when VMON reaches the max limit and
transition from a logic low to a logic high. This type of topology can be used for sensitive systems where
advanced notice of the power supply over-voltage detection is needed.
Use VMON2, the threshold for a low to high transition at OUT2, IIN_RES, the current flow through the resistor
network, to determine the minimum total resistance necessary to achieve the current consumption specification.
(5)
where
•
•
VMON2 is the target voltage at which OUT2 goes high when VMON rises
IIN_RES is the current flowing through the resistor network
After RTOTAL is determined, R3 can be calculated using Equation 6. Select the nearest 1% resistor value for R3.
In this case, 845 kΩ is the closest value.
(6)
Use the voltage divider equation Equation 7 The voltage divider equation controls the V
OUT1 will transition from a logic high to a logic low.
voltage at which
MON1
(7)
where
•
VMON1 is the target voltage at which OUT1 goes low when VMON falls
Rearranging Equation 7 to solve for R2 yields Equation 8Select the nearest 1% resistor value for R2. In this
case, 55.6kΩ is the closest value.
(8)
Use Equation 9 to calculate R1. Select the nearest 1% resistor value for R1. In this case, 1.87 MΩ is a 1%
resistor.
(9)
8.2.2.3 Application Curve
Figure 26 shows the simulated results of the early warning detection circuit. OUT2 provides the early warning
alert whereas OUT1 provides the warning alert.
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Typical Applications (continued)
VPU
OUT1
0 V
3.915 V
3.674 V
3.718 V
3.49 V
VMON
VPU
OUT2
Figure 26. Early Warning Detection
8.2.3 Additional Application Information
8.2.3.1 Pull-Up Resistor Selection
For the TLV4082 (open-drain outputs), care should be taken in selecting the pull-up resistor (RPU) value to
ensure proper output voltage levels. First, consider the required output high logic level requirement of the logic
device that is being drive by the comparator when calculating the maximum RPU value. When in a logic high
output state, the output impedance of the comparator is very high but there is finite amount of leakage current
that needs to be accounted for. Use the | Ilkg(OD)| from the EC table and the VIH (min) of the logic device being
driven by the TLV4082 to determine RPU using Equation 10 .
(10)
Next determine the minimum value for RPU by using the VIL (max) of the logic device being driven by the TLV4082.
In order for the comparator output to be recognized as a logic low, VIL
is used to determine the upper
(max)
boundary of the comparator's VOL. VOL
for the comparator is available in the EC table from specific sink
(max)
current levels and can be found from the VOUT versus ISINK curve in the Typical Applications curve. A good design
practice is to choose a value for VOL that is ½ the value of VIL for the input logic device. The corresponding sink
current and VOL value will be needed to calculate the minimum RPU. This method will ensure enough noise
margin for the logic low level. With iSINK determined and the corresponding RPU obtained, the minimum ) is
calculated with Equation 11.
(11)
Since the range of possible RPU values is large, a value between 5 kΩ and 100kΩ is generally recommended. A
smaller RPU value provides faster output transition time and better noise immunity, while a larger RPU value
consumes less power when in a logic low output state.
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Typical Applications (continued)
8.2.3.2 INx Capacitor
Although not required in most cases, for extremely noisy applications, place a 1 nF to 100 nF bypass capacitor
from the comparator input (INx) to the (V-) for good analog design practice. This capacitor placement reduces
device sensitivity to transients.
9 Power Supply Recommendations
The TLV4062 and TLV4082 are designed to operate from an input voltage supply range between 1.5 V and
5.5V. An input supply capacitor is not required for this device; however, good analog practice is to place a 0.1-µF
or greater capacitor between the V+ pin and the GND pin. This device has a 7-V absolute maximum rating on the
V+ pin. If the voltage supply providing power to V+ is susceptible to any large voltage transient that can exceed 7
V, additional precautions must be taken.
For applications where INx is greater than 0 V before V+, and is subject to a startup slew rate of less than 200
mV per 1 ms, the output can be driven to logic high in error. To correct the output, cycle the INx lines below VIT–
or sequence INx after V+.
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10 Layout
10.1 Layout Guidelines
Place the V+ decoupling capacitor close to the device.
Avoid using long traces for the V+ supply node. The V+ capacitor, along with parasitic inductance from the
supply to the capacitor, can form an LC tank circuit that creates ringing with peak voltages above the maximum
V+ voltage.
10.2 Layout Example
CIN
VDD
VMON1
R1
VPU
1
2
3
6
5
R5
R2
OUT1
OUT2
VPU
R4
4
R6
R3
VMON2
Figure 27. Example SOT-23 Layout
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
Optimizing Resistor Dividers at a Comparator Input application report (SLVA450)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 2. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
TLV4062
TLV4082
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
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11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV4062DBVR
TLV4062DRYR
TLV4082DBVR
TLV4082DRYR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SON
DBV
DRY
DBV
DRY
6
6
6
6
3000 RoHS & Green
5000 RoHS & Green
3000 RoHS & Green
5000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
29FE
IC
NIPDAUAG
NIPDAU
SOT-23
SON
29GE
ID
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV4062, TLV4082 :
Automotive: TLV4062-Q1, TLV4082-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jun-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV4062DBVR
TLV4062DRYR
TLV4082DBVR
TLV4082DRYR
SOT-23
SON
DBV
DRY
DBV
DRY
6
6
6
6
3000
5000
3000
5000
178.0
180.0
178.0
180.0
9.0
8.4
9.0
8.4
3.23
1.25
3.23
1.25
3.17
1.6
1.37
0.7
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q1
Q3
Q1
SOT-23
SON
3.17
1.6
1.37
0.7
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jun-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV4062DBVR
TLV4062DRYR
TLV4082DBVR
TLV4082DRYR
SOT-23
SON
DBV
DRY
DBV
DRY
6
6
6
6
3000
5000
3000
5000
180.0
183.0
180.0
183.0
180.0
183.0
180.0
183.0
18.0
20.0
18.0
20.0
SOT-23
SON
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRY 6
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4207181/G
PACKAGE OUTLINE
DRY0006A
USON - 0.6 mm max height
S
C
A
L
E
8
.
5
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
A
B
PIN 1 INDEX AREA
1.5
1.4
C
0.6 MAX
SEATING PLANE
0.08 C
0.05
0.00
3X 0.6
SYMM
(0.127) TYP
(0.05) TYP
3
4
4X
0.5
SYMM
2X
1
6
1
0.25
6X
0.15
0.4
0.3
0.1
C A B
C
0.05
PIN 1 ID
(OPTIONAL)
0.35
0.25
5X
4222894/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
6
1
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
EXPOSED
EXPOSED
METAL
METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222894/A 01/2018
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
1
6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
4222894/A 01/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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Copyright © 2021, Texas Instruments Incorporated
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