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TLV4379 [TI]

四路、5.5V、90kHz、低静态电流 (4μA)、RRIO 运算放大器;
TLV4379
型号： TLV4379
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

四路、5.5V、90kHz、低静态电流 (4μA)、RRIO 运算放大器

放大器 运算放大器
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TLV379, TLV2379, TLV4379  
ZHCSEY0B –APRIL 2016–REVISED AUGUST 2017  
TLVx379  
低电压、4μA 轨到轨 I/O 成本优化型运算放大器  
1 特性  
3 说明  
1
•
•
•
•
•
•
•
成本优化型精密放大器  
TLV379 系列单通道、双通道和四通道运算放大器是成  
本优化型低电压、微功耗放大器的典型代表。该器件系  
列的工作电源电压低至 1.8V (±0.9V) 且静态电流消耗  
极低（每通道为 4µA），非常适合功耗敏感型 应用进  
行了优化。此外，TLV379 系列具有轨到轨输入和输出  
功能，几乎适用于所有单电源应用。  
微功耗：4μA（典型值）  
低失调电压：0.8mV（典型值）  
轨到轨输入和输出  
单位增益稳定  
宽电源电压范围：1.8V 至 5.5V  
微型封装：  
TLV379（单通道）采用 5 引脚 SC70 和小外形尺寸晶  
体管 (SOT)-23 封装以及 8 引脚小外形尺寸集成电路  
(SOIC) 封装。TLV2379（双通道）采用 8 引脚 SOIC  
封装。TLV4379（四通道）采用 14 引脚薄型小外形尺  
寸 (TSSOP) 封装。所有器件版本的额定工作温度范围  
为 -40°C 至 +125°C。  
–
–
–
–
5 引脚 SC70  
5 引脚小外形尺寸晶体管 (SOT)-23  
8 引脚小外形尺寸集成电路 (SOIC) 封装  
14 引脚薄型小外形尺寸 (TSSOP) 封装  
2 应用  
器件信息(1)  
•
•
•
•
•
•
•
移动电源  
器件型号  
封装  
SC70 (5)  
封装尺寸（标称值）  
2.00mm × 1.25mm  
2.90mm × 1.60mm  
4.90mm x 3.91mm  
4.90mm x 3.91mm  
太阳能逆变器  
低功耗电机控制  
电池供电仪器  
便携式设备  
TLV379  
SOT-23 (5)  
SOIC (8)  
SOIC (8)  
TLV2379  
TLV4379  
医疗仪器  
薄型小外形尺寸封装  
(TSSOP) (14)  
5.00mm x 4.40mm  
手持测试设备  
(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。  
电池监控应用中的 TLV379  
RF  
R1  
+IN  
+
IBIAS  
OUT  
TLV379  
VSTATUS  
VBATT  
-IN  
VREF  
RBIAS  
R2  
REF1112  
Copyright © 2016, Texas Instruments Incorporated  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
English Data Sheet: SBOS785  
 
 
 
TLV379, TLV2379, TLV4379  
ZHCSEY0B –APRIL 2016–REVISED AUGUST 2017  
www.ti.com.cn  
目录  
8.4 Device Functional Modes........................................ 13  
Application and Implementation ........................ 14  
9.1 Application Information............................................ 14  
9.2 Typical Application ................................................. 14  
9.3 System Examples ................................................... 15  
1
2
3
4
5
6
7
特性.......................................................................... 1  
应用.......................................................................... 1  
说明.......................................................................... 1  
修订历史记录 ........................................................... 2  
Device Comparison Table..................................... 3  
Pin Configuration and Functions......................... 3  
Specifications......................................................... 6  
7.1 Absolute Maximum Ratings ...................................... 6  
7.2 ESD Ratings.............................................................. 6  
7.3 Recommended Operating Conditions....................... 6  
7.4 Thermal Information: TLV379 ................................... 7  
7.5 Thermal Information: TLV2379 ................................. 7  
7.6 Thermal Information: TLV4379 ................................. 7  
7.7 Electrical Characteristics: VS = 1.8 V to 5.5 V .......... 8  
7.8 Typical Characteristics.............................................. 9  
Detailed Description ............................................ 12  
8.1 Overview ................................................................. 12  
8.2 Functional Block Diagram ....................................... 12  
8.3 Feature Description................................................. 12  
9
10 Power Supply Recommendations ..................... 17  
10.1 Input and ESD Protection ..................................... 17  
11 Layout................................................................... 18  
11.1 Layout Guidelines ................................................. 18  
11.2 Layout Example .................................................... 18  
12 器件和文档支持 ..................................................... 19  
12.1 文档支持 ............................................................... 19  
12.2 相关链接................................................................ 19  
12.3 接收文档更新通知 ................................................. 19  
12.4 社区资源................................................................ 19  
12.5 商标....................................................................... 19  
12.6 静电放电警告......................................................... 19  
12.7 Glossary................................................................ 19  
13 机械、封装和可订购信息....................................... 19  
8
4 修订历史记录  
注：之前版本的页码可能与当前版本有所不同。  
Changes from Revision A (September 2016) to Revision B  
Page  
•
Added underscores to pin names in Pin Functions tables to match connection diagrams ................................................... 4  
Changes from Original (April 2016) to Revision A  
Page  
•
Changed DBV pinout ............................................................................................................................................................. 3  
2
Copyright © 2016–2017, Texas Instruments Incorporated  
 
TLV379, TLV2379, TLV4379  
www.ti.com.cn  
ZHCSEY0B –APRIL 2016–REVISED AUGUST 2017  
5 Device Comparison Table  
FEATURES  
1 μA, 70 kHz, 2-mV VOS, 1.8-V to 5.5-V supply  
1 μA, 5.5 kHz, 390-μV VOS, 2.5-V to 16-V supply  
1 μA, 5.5 kHz, 0.6-mV VOS, 2.5-V to 12-V supply  
7 μA, 160 kHz, 0.5-mV VOS, 2.7-V to 16-V supply  
7 μA, 160 kHz, 0.5-mV VOS, 2.7-V to 16-V supply  
20 μA, 350 kHz, 2-mV VOS, 2.3-V to 5.5-V supply  
20 μA, 500 kHz, 550-μV VOS, 1.8-V to 3.6-V supply  
45 μA, 1 MHz, 1-mV VOS, 2.1-V to 5.5-V supply  
PRODUCT  
OPAx349  
TLV240x  
TLV224x  
TLV27Lx  
TLV238x  
OPAx347  
TLV276x  
OPAx348  
6 Pin Configuration and Functions  
TLV379: DCK Package  
5-Pin SC70  
TLV379: DBV Package  
5-Pin SOT23  
Top View  
Top View  
+IN  
Vœ  
1
2
3
5
V+  
OUT  
Vœ  
1
2
3
5
V+  
œIN  
4
OUT  
+IN  
4
œIN  
Not to scale  
Not to scale  
TLV379: D Package  
8-Pin SOIC  
Top View  
NC  
œIN  
+IN  
Vœ  
1
2
3
4
8
7
6
5
NC  
V+  
OUT  
NC  
Not to scale  
Pin Functions: TLV379  
NO.  
DBV  
4
NAME  
I/O  
DESCRIPTION  
DCK  
D
–IN  
+IN  
NC  
OUT  
V–  
3
1
2
I
Negative (inverting) input  
Positive (noninverting) input  
3
3
I
—
4
—
1
1, 5, 8  
—
O
—
—
No internal connection (can be left floating)  
Output  
6
4
7
2
2
Negative (lowest) power supply  
Positive (highest) power supply  
V+  
5
5
Copyright © 2016–2017, Texas Instruments Incorporated  
3
TLV379, TLV2379, TLV4379  
ZHCSEY0B –APRIL 2016–REVISED AUGUST 2017  
www.ti.com.cn  
TLV2379: D Package  
8-Pin SOIC  
Top View  
OUT_A  
œIN_A  
+IN_A  
Vœ  
1
2
3
4
8
7
6
5
V+  
OUT_B  
œIN_B  
+IN_B  
Not to scale  
Pin Functions: TLV2379  
NAME  
–IN_A  
+IN_A  
–IN_B  
+IN_B  
OUT_A  
OUT_B  
V–  
NO.  
2
I/O  
I
DESCRIPTION  
Inverting input, channel A  
Noninverting input, channel A  
Inverting input, channel B  
Noninverting input, channel B  
Output, channel A  
3
I
6
I
5
I
1
O
O
—
—
7
Output, channel B  
4
Negative (lowest) power supply  
Positive (highest) power supply  
V+  
8
4
Copyright © 2016–2017, Texas Instruments Incorporated  
TLV379, TLV2379, TLV4379  
www.ti.com.cn  
ZHCSEY0B –APRIL 2016–REVISED AUGUST 2017  
TLV4379: PW Package  
14-Pin TSSOP  
Top View  
OUT_A  
œIN_A  
+IN_A  
V+  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
OUT_D  
œIN_D  
+IN_D  
Vœ  
+IN_B  
œIN_B  
OUT_B  
+IN_C  
œIN_C  
OUT_C  
8
Not to scale  
Pin Functions: TLV4379  
NAME  
–IN_A  
+IN_A  
–IN_B  
+IN_B  
–IN_C  
+IN_C  
–IN_D  
+IN_D  
OUT_A  
OUT_B  
OUT_C  
OUT_D  
V–  
NO.  
2
I/O  
I
DESCRIPTION  
Inverting input, channel A  
3
I
Noninverting input, channel A  
Inverting input, channel B  
Noninverting input, channel B  
Inverting input, channel C  
Noninverting input, channel C  
Inverting input, channel D  
Noninverting input, channel D  
Output, channel A  
6
I
5
I
9
I
10  
13  
12  
1
I
I
I
O
O
O
O
—
—
7
Output, channel B  
8
Output, channel C  
14  
11  
4
Output, channel D  
Negative (lowest) power supply  
Positive (highest) power supply  
V+  
Copyright © 2016–2017, Texas Instruments Incorporated  
5
TLV379, TLV2379, TLV4379  
ZHCSEY0B –APRIL 2016–REVISED AUGUST 2017  
www.ti.com.cn  
7 Specifications  
7.1 Absolute Maximum Ratings  
over operating free-air temperature range (unless otherwise noted)(1)  
MIN  
MAX  
7
UNIT  
V
Supply, VS = (V+) – (V–)  
Signal input pin(2)  
Voltage  
(V–) – 0.5  
(V+) + 0.5  
±10  
Signal input pin(2)  
Output short-circuit(3)  
mA  
Current  
Continuous  
Operating, TA  
–40  
–65  
125  
150  
150  
Temperature  
Junction, TJ  
Storage, Tstg  
°C  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended  
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be  
current-limited to 10 mA or less.  
(3) Short-circuit to ground, one amplifier per package.  
7.2 ESD Ratings  
VALUE  
±2000  
±1000  
UNIT  
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)  
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)  
V(ESD)  
Electrostatic discharge  
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.  
7.3 Recommended Operating Conditions  
over operating free-air temperature range (unless otherwise noted)  
MIN  
1.8  
NOM  
MAX  
5.5  
UNIT  
V
Single supply  
Dual supply  
VS  
TA  
Supply voltage  
±0.9  
–40  
±2.75  
125  
Operating temperature  
°C  
6
Copyright © 2016–2017, Texas Instruments Incorporated  
 
TLV379, TLV2379, TLV4379  
www.ti.com.cn  
ZHCSEY0B –APRIL 2016–REVISED AUGUST 2017  
7.4 Thermal Information: TLV379  
TLV379  
THERMAL METRIC(1)  
DCK (SC70)  
5 PINS  
262.2  
99.7  
DBV (SOT23)  
5 PINS  
220.8  
148.3  
48.2  
D (SOIC)  
8 PINS  
130.8  
77.2  
UNIT  
RθJA  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
RθJC(top)  
RθJB  
49.0  
71.1  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
3.3  
28.6  
30.7  
ψJB  
18.2  
47.3  
70.6  
RθJC(bot)  
n/a  
n/a  
n/a  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report.  
7.5 Thermal Information: TLV2379  
TLV2379  
THERMAL METRIC(1)  
D (SOIC)  
8 PINS  
116.4  
59.5  
UNIT  
RθJA  
Junction-to-ambient thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
RθJC(top)  
RθJB  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
57.6  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
17.2  
ψJB  
57.0  
RθJC(bot)  
n/a  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report.  
7.6 Thermal Information: TLV4379  
TLV4379  
THERMAL METRIC(1)  
PW (TSSOP)  
14 PINS  
110.8  
35.2  
UNIT  
RθJA  
Junction-to-ambient thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
RθJC(top)  
RθJB  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
53.6  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
2.6  
ψJB  
52.9  
RθJC(bot)  
n/a  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report.  
Copyright © 2016–2017, Texas Instruments Incorporated  
7
TLV379, TLV2379, TLV4379  
ZHCSEY0B –APRIL 2016–REVISED AUGUST 2017  
www.ti.com.cn  
7.7 Electrical Characteristics: VS = 1.8 V to 5.5 V  
at TA = 25°C, RL = 25 kΩ connected to VS / 2, and VCM < (V+) – 1 V (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
OFFSET VOLTAGE  
VOS  
Input offset voltage  
VOS drift  
VS = 5 V  
0.8  
3
2.5  
mV  
μV/°C  
dB  
dVOS/dT  
PSRR  
TA = –40°C to +125°C  
(V–) < VCM < (V+) – 1 V  
Power-supply rejection ratio  
92  
104  
INPUT VOLTAGE RANGE  
VCM  
Common-mode voltage range  
(V–) – 0.1  
85  
(V+) + 0.1  
V
100  
CMRR  
Common-mode rejection ratio(1)  
dB  
TA = –40°C to +125°C,  
(V–) < VCM < (V+) – 1 V  
62  
INPUT BIAS CURRENT  
IIB  
IIO  
Input bias current  
Input offset current  
VS = 5 V, VCM ≤ VS / 2  
±5  
±5  
pA  
pA  
VS = 5 V  
INPUT IMPEDANCE  
Differential  
1013 || 3  
1013 || 6  
Ω || pF  
Ω || pF  
Common-mode  
NOISE  
Input voltage noise  
f = 0.1 Hz to 10 Hz  
f = 1 kHz  
2.8  
83  
μVPP  
en  
Input voltage noise density  
nV/√Hz  
OPEN-LOOP GAIN  
VS = 5 V, RL = 5 kΩ,  
500 mV < VO < (V+) – 500 mV  
AOL  
Open-loop voltage gain  
90  
110  
dB  
OUTPUT  
RL = 5 kΩ  
25  
±5  
50  
75  
Voltage output swing from rail  
mV  
mA  
TA = –40°C to +125°C, RL = 5 kΩ  
ISC  
Short-circuit current  
CLOAD  
ROUT  
RO  
Capacitive load drive  
See Capacitive Load and Stability section  
Closed-loop output impedance  
Open-loop output impedance  
G = 1, f = 1 kHz, IO = 0  
f = 100 kHz, IO = 0  
10  
28  
Ω
kΩ  
FREQUENCY RESPONSE (CLOAD = 30 pF)  
GBW  
SR  
Gain bandwidth product  
Slew rate  
90  
0.03  
25  
kHz  
V/μs  
μs  
G = 1  
Overload recovery time  
Turn-on time  
VIN × Gain > VS  
tON  
1
ms  
POWER SUPPLY  
VS  
IQ  
Specified, operating voltage range  
Quiescent current per amplifier  
1.8  
5.5  
12  
V
VS = 5 V, TA = –40°C to +125°C  
4
μA  
TEMPERATURE  
TA  
Specified, operating range  
Storage range  
–40  
–65  
125  
150  
°C  
°C  
Tstg  
(1) See typical characteristic graph, Common-Mode Rejection Ratio vs Frequency (Figure 2).  
8
Copyright © 2016–2017, Texas Instruments Incorporated  
TLV379, TLV2379, TLV4379  
www.ti.com.cn  
ZHCSEY0B –APRIL 2016–REVISED AUGUST 2017  
7.8 Typical Characteristics  
at TA = 25°C, VS = 5 V, and RL = 25 kΩ connected to VS / 2 (unless otherwise noted)  
120  
100  
80  
60  
40  
20  
0
120  
100  
80  
60  
40  
20  
0
0
-30  
-60  
-90  
-120  
-150  
-180  
-PSRR  
+PSRR  
CMRR  
0.1  
1
10  
100  
1k  
10k  
100k  
0.1  
1
10  
100  
1k  
10k  
100k  
Frequency (Hz)  
Frequency (Hz)  
Figure 2. Common-Mode and Power-Supply Rejection Ratio  
vs Frequency  
Figure 1. Open-Loop Gain and Phase vs Frequency  
5
4.5  
4
2.5  
2
1.5  
1
3.5  
3
0.5  
125°C  
85°C  
25°C  
-40°C  
2.5  
2
0
-0.5  
-1  
1.5  
1
-1.5  
-2  
0.5  
0
-2.5  
1k  
10k  
100k  
0
1
2
3
4
5
6
7
8
9
10  
Frequency (Hz)  
IOUT (mA)  
VS = ±2.5 V  
Figure 3. Maximum Output Voltage vs Frequency  
Figure 4. Output Voltage vs Output Current  
25  
20  
15  
10  
5
ISC  
-ISC  
1.5  
2
2.5  
3
3.5  
4
4.5  
5
5.5  
Supply Voltage (V)  
Offset Voltage (mV)  
Figure 5. Short-Circuit Current vs Supply Voltage  
Figure 6. Offset Voltage Production Distribution  
Copyright © 2016–2017, Texas Instruments Incorporated  
9
 
TLV379, TLV2379, TLV4379  
ZHCSEY0B –APRIL 2016–REVISED AUGUST 2017  
www.ti.com.cn  
Typical Characteristics (continued)  
at TA = 25°C, VS = 5 V, and RL = 25 kΩ connected to VS / 2 (unless otherwise noted)  
10000  
1000  
100  
10  
15  
12.5  
10  
Unit 1  
Common-Mode Input Range  
CMRR Specified Range  
7.5  
5
2.5  
0
-2.5  
-5  
1
-7.5  
-10  
-12.5  
-15  
-40°C  
0.1  
85°C  
Unit 2  
4.5  
125°C  
0.01  
-50  
-25  
0
25  
50  
75  
100  
125  
-0.5  
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
5
5.5  
Temperature (°C)  
Common-Mode Voltage (V)  
Figure 8. Input Bias Current vs Temperature  
Figure 7. Offset Voltage vs Common-Mode Voltage  
and Temperature  
1000  
100  
10  
1
10  
100  
1k  
10k  
2.5s/div  
Frequency (Hz)  
Figure 10. Noise vs Frequency  
Figure 9. 0.1-Hz to 10-Hz Noise  
60  
50  
40  
30  
20  
10  
0
G = +1  
G = -1  
25ms/div  
10  
100  
1000  
Capacitive Load (pF)  
Figure 12. Small-Signal Step Response  
Figure 11. Small-Signal Overshoot vs Capacitive Load  
10  
Copyright © 2016–2017, Texas Instruments Incorporated  
 
 
TLV379, TLV2379, TLV4379  
www.ti.com.cn  
ZHCSEY0B –APRIL 2016–REVISED AUGUST 2017  
Typical Characteristics (continued)  
at TA = 25°C, VS = 5 V, and RL = 25 kΩ connected to VS / 2 (unless otherwise noted)  
50ms/div  
Figure 13. Large-Signal Step Response  
Copyright © 2016–2017, Texas Instruments Incorporated  
11  
TLV379, TLV2379, TLV4379  
ZHCSEY0B –APRIL 2016–REVISED AUGUST 2017  
www.ti.com.cn  
8 Detailed Description  
8.1 Overview  
The TLV379 devices are a family of micropower, low-voltage, rail-to-rail input and output operational amplifiers  
designed for battery-powered applications. This family of amplifiers features impressive bandwidth (90 kHz), low  
bias current (5 pA), low noise (83 nV/√Hz), and consumes very low quiescent current of only 12 µA (maximum)  
per channel.  
8.2 Functional Block Diagram  
V+  
Reference  
Current  
VIN+  
VIN-  
VBIAS1  
Class AB  
Control  
Circuitry  
VO  
VBIAS2  
V-  
(Ground)  
Copyright © 2016, Texas Instruments Incorporated  
8.3 Feature Description  
8.3.1 Operating Voltage  
The TLV379 series is fully specified and tested from 1.8 V to 5.5 V (±0.9 V to ±2.75 V). Parameters that vary with  
supply voltage are illustrated in the Typical Characteristics section.  
8.3.2 Rail-to-Rail Input  
The input common-mode voltage range of the TLV379 family typically extends 100 mV beyond each supply rail.  
This rail-to-rail input is achieved using a complementary input stage. CMRR is specified from the negative rail to  
1 V below the positive rail. Between (V+) – 1 V and (V+) + 0.1 V, the amplifier operates with higher offset voltage  
because of the transition region of the input stage. See the typical characteristic graph, Offset Voltage vs  
Common-Mode Voltage vs Temperature (Figure 7).  
12  
Copyright © 2016–2017, Texas Instruments Incorporated  
TLV379, TLV2379, TLV4379  
www.ti.com.cn  
ZHCSEY0B –APRIL 2016–REVISED AUGUST 2017  
Feature Description (continued)  
8.3.3 Rail-to-Rail Output  
Designed as a micropower, low-noise operational amplifier, the TLV379 delivers a robust output drive capability.  
A class AB output stage with common-source transistors is used to achieve full rail-to-rail output swing capability.  
For resistive loads up to 25 kΩ, the output typically swings to within 5 mV of either supply rail, regardless of the  
power-supply voltage applied.  
8.3.4 Capacitive Load and Stability  
Follower configurations with load capacitance in excess of 30 pF can produce extra overshoot (see the typical  
characteristic graph, Small-Signal Overshoot vs Capacitive Load, Figure 11) and ringing in the output signal.  
Increasing the gain enhances the ability of the amplifier to drive greater capacitive loads. In unity-gain  
configurations, capacitive load drive can be improved by inserting a small (10 Ω to 20 Ω) resistor, RS, in series  
with the output as shown in Figure 14. This resistor significantly reduces ringing and maintains direct current (dc)  
performance for purely capacitive loads. However, if a resistive load is in parallel with the capacitive load, a  
voltage divider is created, introducing a dc error at the output and slightly reducing the output swing. The error  
introduced is proportional to the ratio of RS / RL and is generally negligible.  
VS  
RS  
VOUT  
TLV379  
10 W to  
20 W  
VIN  
CL  
RL  
Figure 14. Series Resistor in Unity-Gain Buffer Configuration Improves Capacitive Load Drive  
In unity-gain inverter configuration, phase margin can be reduced by the reaction between the capacitance at the  
operational amplifier (op amp) input and the gain-setting resistors. Best performance is achieved by using  
smaller-value resistors. However, when large-value resistors cannot be avoided, a small (4 pF to 6 pF) capacitor  
(CFB) can be inserted in the feedback, as shown in Figure 15. This configuration significantly reduces overshoot  
by compensating the effect of capacitance (CIN) that includes the amplifier input capacitance (3 pF) and printed  
circuit board (PCB) parasitic capacitance.  
CFB  
RF  
RIN  
VIN  
TLV379  
VOUT  
CIN  
Figure 15. Improving Stability for Large RF and RIN  
8.4 Device Functional Modes  
The TLV379 family has a single functional mode. These devices are powered on as long as the power-supply  
voltage is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).  
Copyright © 2016–2017, Texas Instruments Incorporated  
13  
 
 
TLV379, TLV2379, TLV4379  
ZHCSEY0B –APRIL 2016–REVISED AUGUST 2017  
www.ti.com.cn  
9 Application and Implementation  
NOTE  
Information in the following applications sections is not part of the TI component  
specification, and TI does not warrant its accuracy or completeness. TI’s customers are  
responsible for determining suitability of components for their purposes. Customers should  
validate and test their design implementation to confirm system functionality.  
9.1 Application Information  
When designing for ultra-low power, choose system components carefully. To minimize current consumption,  
select large-value resistors. Any resistors can react with stray capacitance in the circuit and the input capacitance  
of the operational amplifier. These parasitic RC combinations can affect the stability of the overall system. Use of  
a feedback capacitor assures stability and limits overshoot or gain peaking.  
9.2 Typical Application  
A typical application for an operational amplifier is an inverting amplifier, as shown in Figure 16. An inverting  
amplifier takes a positive voltage on the input and outputs a signal inverted to the input, making a negative  
voltage of the same magnitude. In the same manner, the amplifier also makes negative input voltages positive on  
the output. In addition, amplification can be added by selecting the input resistor RI and the feedback resistor RF.  
RF  
VSUP+  
RI  
VOUT  
+
VIN  
VSUPœ  
Copyright © 2016, Texas Instruments Incorporated  
Figure 16. Application Schematic  
9.2.1 Design Requirements  
The supply voltage must be chosen to be larger than the input voltage range and the desired output range. The  
limits of the input common-mode range (VCM) and the output voltage swing to the rails (VO) must also be  
considered. For instance, this application scales a signal of ±0.5 V (1 V) to ±1.8 V (3.6 V). Setting the supply at  
±2.5 V is sufficient to accommodate this application.  
9.2.2 Detailed Design Procedure  
Determine the gain required by the inverting amplifier using Equation 1 and Equation 2:  
VOUT  
AV  
=
V
IN  
(1)  
(2)  
1.8  
AV  
=
= -3.6  
-0.5  
14  
Copyright © 2016–2017, Texas Instruments Incorporated  
 
 
 
TLV379, TLV2379, TLV4379  
www.ti.com.cn  
ZHCSEY0B –APRIL 2016–REVISED AUGUST 2017  
Typical Application (continued)  
When the desired gain is determined, choose a value for RI or RF. Choosing a value in the kilohm range is  
desirable for general-purpose applications because the amplifier circuit uses currents in the milliamp range. This  
milliamp current range ensures the device does not draw too much current. The trade-off is that very large  
resistors (100s of kilohms) draw the smallest current but generate the highest noise. Very small resistors (100s of  
ohms) generate low noise but draw high current. This example uses 10 kΩ for RI, meaning 36 kΩ is used for RF.  
These values are determined by Equation 3:  
RF  
AV = -  
RI  
(3)  
9.2.3 Application Curve  
2
1.5  
1
Input  
Output  
0.5  
0
-0.5  
-1  
-1.5  
-2  
Time  
Figure 17. Inverting Amplifier Input and Output  
9.3 System Examples  
Figure 18 shows the basic configuration for a bridge amplifier using the TLV379.  
VEX  
R1  
VS  
R
R
R
R
VOUT  
TLV379  
R1  
VREF  
Figure 18. Single Op Amp Bridge Amplifier  
Copyright © 2016–2017, Texas Instruments Incorporated  
15  
 
 
TLV379, TLV2379, TLV4379  
ZHCSEY0B –APRIL 2016–REVISED AUGUST 2017  
www.ti.com.cn  
System Examples (continued)  
Figure 19 shows the TLV2379 used as a window comparator. The threshold limits are set by VH and VL, with VH  
> VL. When VIN < VH, the output of A1 is low. When VIN > VL, the output of A2 is low. Therefore, both op amp  
outputs are at 0 V as long as VIN is between VH and VL. This architecture results in no current flowing through  
either diode, Q1 in cutoff, with the base voltage at 0 V, and VOUT forced high.  
If VIN falls below VL, the output of A2 is high, current flows through D2, and VOUT is low. Likewise, if VIN rises  
above VH, the output of A1 is high, current flows through D1, and VOUT is low.  
The window comparator threshold voltages are set using Equation 4 and Equation 5.  
R2  
VH =  
´ VS  
R1 + R2  
R4  
(4)  
(5)  
VL =  
´ VS  
R3 + R4  
VS  
VS  
R1  
R2  
RIN  
VH  
A1  
D1(2)  
1/2  
VS  
TLV2379  
R7  
5.1 kW  
VOUT  
R5  
(1)  
2 kW  
10 kW  
Q1(3)  
VIN  
R6  
5.1 kW  
VS  
VS  
D2(2)  
A2  
1/2  
R3  
R4  
TLV2379  
VL  
(1) RIN protects A1 and A2 from possible excess current flow.  
(2) IN4446 or equivalent diodes.  
(3) 2N2222 or equivalent NPN transistor.  
Figure 19. TLV2379 as a Window Comparator  
16  
Copyright © 2016–2017, Texas Instruments Incorporated  
 
 
 
TLV379, TLV2379, TLV4379  
www.ti.com.cn  
ZHCSEY0B –APRIL 2016–REVISED AUGUST 2017  
10 Power Supply Recommendations  
The TLV379 family is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply  
from –40°C to +125°C. The Typical Characteristics section presents parameters that can exhibit significant  
variance with regard to operating voltage or temperature.  
CAUTION  
Supply voltages larger than 7 V can permanently damage the device (see the Absolute  
Maximum Ratings table).  
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-  
impedance power supplies. For more detailed information on bypass capacitor placement; see the Layout  
Guidelines section.  
10.1 Input and ESD Protection  
The TLV379 family incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case  
of input and output pins, this protection primarily consists of current-steering diodes connected between the input  
and power-supply pins. These ESD protection diodes also provide in-circuit, input overdrive protection, as long  
as the current is limited to 10 mA as stated in the Absolute Maximum Ratings table. Figure 20 shows how a  
series input resistor can be added to the driven input to limit the input current. The added resistor contributes  
thermal noise at the amplifier input that must be kept to a minimum in noise-sensitive applications.  
V+  
IOVERLOAD  
10-mA max  
VOUT  
Device  
VIN  
5 kW  
Figure 20. Input Current Protection  
Copyright © 2016–2017, Texas Instruments Incorporated  
17  
 
TLV379, TLV2379, TLV4379  
ZHCSEY0B –APRIL 2016–REVISED AUGUST 2017  
www.ti.com.cn  
11 Layout  
11.1 Layout Guidelines  
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:  
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the  
operational amplifier. Use bypass capacitors to reduce the coupled noise by providing low-impedance  
power sources local to the analog circuitry.  
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as  
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-  
supply applications.  
•
•
Separate grounding for analog and digital portions of the circuitry is one of the simplest and most  
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to  
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to  
physically separate digital and analog grounds, paying attention to the flow of the ground current. For  
more detailed information, see Circuit Board Layout Techniques, SLOA089.  
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as  
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much  
better than crossing in parallel with the noisy trace.  
•
•
•
Place the external components as close as possible to the device. Keep RF and RG close to the inverting  
input in order to minimize parasitic capacitance, as shown in Figure 21.  
Keep the length of input traces as short as possible. Always remember that the input traces are the most  
sensitive part of the circuit.  
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly  
reduce leakage currents from nearby traces that are at different potentials.  
11.2 Layout Example  
Place components  
close to the device and  
to each other to reduce  
parasitic errors.  
Run the input traces  
as far away from  
the supply lines  
as possible.  
VS+  
RF  
N/C  
N/C  
RG  
GND  
VIN  
GND  
œIN  
+IN  
Vœ  
V+  
OUTPUT  
N/C  
Use a low-ESR, ceramic  
bypass capacitor.  
GND  
Use a low-ESR,  
ceramic bypass  
capacitor.  
VOUT  
VSœ  
Ground (GND) plane on another layer.  
Figure 21. Operational Amplifier Board Layout for Noninverting Configuration  
VIN  
+
VOUT  
RG  
RF  
Figure 22. Schematic Representation of Figure 21  
18  
版权 © 2016–2017, Texas Instruments Incorporated  
 
TLV379, TLV2379, TLV4379  
www.ti.com.cn  
ZHCSEY0B –APRIL 2016–REVISED AUGUST 2017  
12 器件和文档支持  
12.1 文档支持  
12.1.1 相关文档  
相关文档如下：  
•
•
•
•
《运算放大器的 EMI 抑制比》（文献编号：SBOA128）  
《电路板布局布线技巧》（文献编号：SLOA089）  
《QFN/SON PCB 连接》（文献编号：SLUA271）  
《四方扁平无引线逻辑器件封装》（文献编号：SCBA017）  
12.2 相关链接  
表 1 列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链  
接。  
表 1. 相关链接  
器件  
产品文件夹  
请单击此处  
请单击此处  
请单击此处  
样片与购买  
请单击此处  
请单击此处  
请单击此处  
技术文档  
请单击此处  
请单击此处  
请单击此处  
工具和软件  
请单击此处  
请单击此处  
请单击此处  
支持和社区  
请单击此处  
请单击此处  
请单击此处  
TLV379  
TLV2379  
TLV4379  
12.3 接收文档更新通知  
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。请单击右上角的通知我进行注册，即可收到所有的  
产品更改信息每周摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。  
12.4 社区资源  
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，  
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。  
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在  
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。  
设计支持  
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。  
12.5 商标  
E2E is a trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
12.6 静电放电警告  
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可  
能会损坏集成电路。  
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可  
能会导致器件与其发布的规格不相符。  
12.7 Glossary  
SLYZ022 — TI Glossary.  
This glossary lists and explains terms, acronyms, and definitions.  
13 机械、封装和可订购信息  
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知  
和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。  
版权 © 2016–2017, Texas Instruments Incorporated  
19  
 
PACKAGE OPTION ADDENDUM  
www.ti.com  
28-May-2023  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
TLV2379IDR  
TLV379IDBVR  
TLV379IDBVT  
TLV379IDCKR  
TLV379IDCKT  
TLV379IDR  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOT-23  
SOT-23  
SC70  
D
8
5
5
5
5
8
2500 RoHS & Green  
3000 RoHS & Green  
NIPDAU  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
V2379  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
DBV  
DBV  
DCK  
DCK  
D
NIPDAU | SN  
NIPDAU | SN  
NIPDAU  
12N  
12N  
12O  
12O  
250  
3000 RoHS & Green  
250 RoHS & Green  
RoHS & Green  
SC70  
NIPDAU  
SOIC  
2500 RoHS & Green  
2000 RoHS & Green  
NIPDAU  
TLV  
379  
TLV4379IPWR  
ACTIVE  
TSSOP  
PW  
14  
NIPDAU  
Level-2-260C-1 YEAR  
-40 to 125  
TLV4379  
Samples  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
28-May-2023  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
3-Jun-2022  
TAPE AND REEL INFORMATION  
REEL DIMENSIONS  
TAPE DIMENSIONS  
K0  
P1  
W
B0  
Reel  
Diameter  
Cavity  
A0  
A0 Dimension designed to accommodate the component width  
B0 Dimension designed to accommodate the component length  
K0 Dimension designed to accommodate the component thickness  
Overall width of the carrier tape  
W
P1 Pitch between successive cavity centers  
Reel Width (W1)  
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE  
Sprocket Holes  
Q1 Q2  
Q3 Q4  
Q1 Q2  
Q3 Q4  
User Direction of Feed  
Pocket Quadrants  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TLV2379IDR  
TLV379IDBVR  
TLV379IDBVT  
TLV379IDCKR  
TLV379IDCKT  
TLV379IDR  
SOIC  
SOT-23  
SOT-23  
SC70  
D
8
5
2500  
3000  
250  
330.0  
178.0  
178.0  
178.0  
178.0  
330.0  
330.0  
12.4  
9.0  
6.4  
3.3  
3.3  
2.4  
2.4  
6.4  
6.9  
5.2  
3.2  
3.2  
2.5  
2.5  
5.2  
5.6  
2.1  
1.4  
1.4  
1.2  
1.2  
2.1  
1.6  
8.0  
4.0  
4.0  
4.0  
4.0  
8.0  
8.0  
12.0  
8.0  
Q1  
Q3  
Q3  
Q3  
Q3  
Q1  
Q1  
DBV  
DBV  
DCK  
DCK  
D
5
9.0  
8.0  
5
3000  
250  
9.0  
8.0  
SC70  
5
9.0  
8.0  
SOIC  
8
2500  
2000  
12.4  
12.4  
12.0  
12.0  
TLV4379IPWR  
TSSOP  
PW  
14  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
3-Jun-2022  
TAPE AND REEL BOX DIMENSIONS  
Width (mm)  
H
W
L
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TLV2379IDR  
TLV379IDBVR  
TLV379IDBVT  
TLV379IDCKR  
TLV379IDCKT  
TLV379IDR  
SOIC  
SOT-23  
SOT-23  
SC70  
D
8
5
2500  
3000  
250  
356.0  
180.0  
180.0  
180.0  
180.0  
356.0  
356.0  
356.0  
180.0  
180.0  
180.0  
180.0  
356.0  
356.0  
35.0  
18.0  
18.0  
18.0  
18.0  
35.0  
35.0  
DBV  
DBV  
DCK  
DCK  
D
5
5
3000  
250  
SC70  
5
SOIC  
8
2500  
2000  
TLV4379IPWR  
TSSOP  
PW  
14  
Pack Materials-Page 2  
PACKAGE OUTLINE  
DCK0005A  
SOT - 1.1 max height  
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR  
C
2.4  
1.8  
0.1 C  
1.4  
1.1  
B
1.1 MAX  
A
PIN 1  
INDEX AREA  
1
2
5
NOTE 4  
(0.15)  
(0.1)  
2X 0.65  
1.3  
2.15  
1.85  
1.3  
4
3
0.33  
5X  
0.23  
0.1  
0.0  
(0.9)  
TYP  
0.1  
C A B  
0.15  
0.22  
0.08  
GAGE PLANE  
TYP  
0.46  
0.26  
8
0
TYP  
TYP  
SEATING PLANE  
4214834/C 03/2023  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. Refernce JEDEC MO-203.  
4. Support pin may differ or may not be present.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
DCK0005A  
SOT - 1.1 max height  
SMALL OUTLINE TRANSISTOR  
PKG  
5X (0.95)  
1
5
5X (0.4)  
SYMM  
(1.3)  
2
3
2X (0.65)  
4
(R0.05) TYP  
(2.2)  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE:18X  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
METAL  
EXPOSED METAL  
EXPOSED METAL  
0.07 MIN  
ARROUND  
0.07 MAX  
ARROUND  
NON SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
(PREFERRED)  
SOLDER MASK DETAILS  
4214834/C 03/2023  
NOTES: (continued)  
4. Publication IPC-7351 may have alternate designs.  
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
DCK0005A  
SOT - 1.1 max height  
SMALL OUTLINE TRANSISTOR  
PKG  
5X (0.95)  
1
5
5X (0.4)  
SYMM  
(1.3)  
2
3
2X(0.65)  
4
(R0.05) TYP  
(2.2)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 THICK STENCIL  
SCALE:18X  
4214834/C 03/2023  
NOTES: (continued)  
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
7. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
PACKAGE OUTLINE  
DBV0005A  
SOT-23 - 1.45 mm max height  
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR  
C
3.0  
2.6  
0.1 C  
1.75  
1.45  
1.45  
0.90  
B
A
PIN 1  
INDEX AREA  
1
2
5
(0.1)  
2X 0.95  
1.9  
3.05  
2.75  
1.9  
(0.15)  
4
3
0.5  
5X  
0.3  
0.15  
0.00  
(1.1)  
TYP  
0.2  
C A B  
NOTE 5  
0.25  
GAGE PLANE  
0.22  
0.08  
TYP  
8
0
TYP  
0.6  
0.3  
TYP  
SEATING PLANE  
4214839/G 03/2023  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. Refernce JEDEC MO-178.  
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not  
exceed 0.25 mm per side.  
5. Support pin may differ or may not be present.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
DBV0005A  
SOT-23 - 1.45 mm max height  
SMALL OUTLINE TRANSISTOR  
PKG  
5X (1.1)  
1
5
5X (0.6)  
SYMM  
(1.9)  
2
3
2X (0.95)  
4
(R0.05) TYP  
(2.6)  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE:15X  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
METAL  
EXPOSED METAL  
EXPOSED METAL  
0.07 MIN  
ARROUND  
0.07 MAX  
ARROUND  
NON SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
(PREFERRED)  
SOLDER MASK DETAILS  
4214839/G 03/2023  
NOTES: (continued)  
6. Publication IPC-7351 may have alternate designs.  
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
DBV0005A  
SOT-23 - 1.45 mm max height  
SMALL OUTLINE TRANSISTOR  
PKG  
5X (1.1)  
1
5
5X (0.6)  
SYMM  
(1.9)  
2
3
2X(0.95)  
4
(R0.05) TYP  
(2.6)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
SCALE:15X  
4214839/G 03/2023  
NOTES: (continued)  
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
9. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
PACKAGE OUTLINE  
D0008A  
SOIC - 1.75 mm max height  
SCALE 2.800  
SMALL OUTLINE INTEGRATED CIRCUIT  
C
SEATING PLANE  
.228-.244 TYP  
[5.80-6.19]  
.004 [0.1] C  
A
PIN 1 ID AREA  
6X .050  
[1.27]  
8
1
2X  
.189-.197  
[4.81-5.00]  
NOTE 3  
.150  
[3.81]  
4X (0 -15 )  
4
5
8X .012-.020  
[0.31-0.51]  
B
.150-.157  
[3.81-3.98]  
NOTE 4  
.069 MAX  
[1.75]  
.010 [0.25]  
C A B  
.005-.010 TYP  
[0.13-0.25]  
4X (0 -15 )  
SEE DETAIL A  
.010  
[0.25]  
.004-.010  
[0.11-0.25]  
0 - 8  
.016-.050  
[0.41-1.27]  
DETAIL A  
TYPICAL  
(.041)  
[1.04]  
4214825/C 02/2019  
NOTES:  
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.  
Dimensioning and tolerancing per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not  
exceed .006 [0.15] per side.  
4. This dimension does not include interlead flash.  
5. Reference JEDEC registration MS-012, variation AA.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
D0008A  
SOIC - 1.75 mm max height  
SMALL OUTLINE INTEGRATED CIRCUIT  
8X (.061 )  
[1.55]  
SYMM  
SEE  
DETAILS  
1
8
8X (.024)  
[0.6]  
SYMM  
(R.002 ) TYP  
[0.05]  
5
4
6X (.050 )  
[1.27]  
(.213)  
[5.4]  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE:8X  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
METAL  
EXPOSED  
METAL  
EXPOSED  
METAL  
.0028 MAX  
[0.07]  
.0028 MIN  
[0.07]  
ALL AROUND  
ALL AROUND  
SOLDER MASK  
DEFINED  
NON SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
4214825/C 02/2019  
NOTES: (continued)  
6. Publication IPC-7351 may have alternate designs.  
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
D0008A  
SOIC - 1.75 mm max height  
SMALL OUTLINE INTEGRATED CIRCUIT  
8X (.061 )  
[1.55]  
SYMM  
1
8
8X (.024)  
[0.6]  
SYMM  
(R.002 ) TYP  
[0.05]  
5
4
6X (.050 )  
[1.27]  
(.213)  
[5.4]  
SOLDER PASTE EXAMPLE  
BASED ON .005 INCH [0.125 MM] THICK STENCIL  
SCALE:8X  
4214825/C 02/2019  
NOTES: (continued)  
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
9. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
重要声明和免责声明  
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，  
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担  
保。  
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验  
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。  
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。  
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成  
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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改  
TI 针对 TI 产品发布的适用的担保或担保免责声明。  
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2023，德州仪器 (TI) 公司  

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