TLV5580IDWR_技术文档

TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

DW OR PW PACKAGE

(TOP VIEW)

8-Bit Resolution 80 MSPS Sampling

Analog-to-Digital Converter (ADC)

Low Power Consumption: 165 mW Typ

Using External references

DRV

AV

1

28

27

26

25

24

23

22

21

20

19

18

DD

D0

SS

DD

2

Wide Analog Input Bandwidth: 700 MHz Typ

3.3 V Single-Supply Operation

D1

D2

D3

D4

D5

D6

D7

AIN

3

CML

4

PWDN_REF

3.3 V TTL/CMOS-Compatible Digital I/O

5

AV

6

SS

Internal Bottom and Top Reference

Voltages

REFBO

REFBI

REFTI

REFTO

7

8

Adjustable Reference Input Range

Power Down (Standby) Mode

9

DRV

DV

10

11

SS

Separate Power Down for Internal Voltage

References

AV

SS

CLK 12

OE 13

17 BG

16 AV

Three-State Outputs

DD

DV

14

15 STBY

DD

28-Pin Small Outline IC (SOIC) and Thin

Shrink SOP (TSSOP) Packages

Applications

– Digital Communications (IF Sampling)

– Flat Panel Displays

– High-Speed DSP Front-End

(TMS320C6000)

– Medical Imaging

– Graphics Processing (Scan Rate/Format

Conversion)

– DVD Read Channel Digitization

description

The TLV5580 is an 8-bit 80 MSPS high-speed A/D converter. It converts the analog input signal into 8-bit

binary-coded digital words up to a sampling rate of 80 MHz. All digital inputs and outputs are 3.3 V

TTL/CMOS-compatible.

The device consumes very little power due to the 3.3 V supply and an innovative single-pipeline architecture

implemented in a CMOS process. The user obtains maximum flexibility by setting both bottom and top voltage

references from user-supplied voltages. If no external references are available, on-chip references are

available for internal and external use. The full-scale range is 1 Vpp up to 1.6 Vpp, depending on the analog

supply voltage. If external references are available, the internal references can be disabled independently from

the rest of the chip, resulting in an even greater power saving.

While usable in a wide variety of applications, the device is specifically suited for the digitizing of high-speed

graphics and for interfacing to LCD panels or LCD/DMD projection modules . Other applications include DVD

read channel digitization, medical imaging and communications. This device is suitable for IF sampling of

communication systems using sub-Nyquist sampling methods because of its high analog input bandwidth.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

SOIC-28

TSSOP-28

TLV5580CPW

TLV5580IPW

0°C to 70°C

TLV5580CDW

TLV5580IDW

–40°C to 85°C

functional block diagram

+

ADC

–

SHA

2

ADC

DAC

2

Correction Logic

Output Buffers

D0(LSB)–D7(MSB)

The single-pipeline architecture uses 6 ADC/DAC stages and one final flash ADC. Each stage produces a

resolution of 2 bits. The correction logic generates its result using the 2-bit result from the first stage, 1 bit from

each of the 5 succeeding stages, and 1 bit from the final stage in order to arrive at an 8-bit result. The correction

logic guarantees no missing codes over the full operating temperature range.

2

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TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

circuit diagrams of inputs and outputs

ALL DIGITAL INPUT CIRCUITS

AIN INPUT CIRCUIT

DV

AV

DD

0.5 pF

REFERENCE INPUT CIRCUIT

AV

D0–D7 OUTPUT CIRCUIT

DRV

DD

Internal

Reference

Generator

REFTO

or

REFBO

D

AV

DD

D_Out

OE

REFBI

or

REFTI

DRV

SS

3

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TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

Terminal Functions

TERMINAL

NAME

AIN

I/O

DESCRIPTION

NO.

26

I

Analog input

AV

16, 27

18, 23, 28

17

Analog supply voltage

Analog ground

DD

SS

AV

I

BG

O

Band gap reference voltage. A 1 µF capacitor (with an optional 0.1 µF capacitor in parallel) should be

connected between this terminal and AV for external filtering.

SS

Clock input. The input is sampled on each rising edge of CLK.

Common mode level. This voltage is equal to (AV – AV ) ÷ 2. An external 0.1 µF capacitor should be

CLK

CML

12

25

I

O

DD SS

connected between this terminal and AV

.

SS

D0 – D7

2 – 9

1

O

I

Data outputs. D7 is the MSB

DRV

Supply voltage for digital output drivers

Ground for digital output drivers

Digital supply voltage

DD

SS

10

14

13

11

I

DV

OE

DV

I

DD

I

Output enable. When high the D0 – D7 outputs go in high-impedance mode.

Digital ground

I

SS

PWDN_REF

24

I

Power down for internal reference voltages. A high on this terminal will disable the internal reference

circuit.

REFBI

21

I

Reference voltage bottom input. The voltage at this terminal defines the bottom reference voltage for the

ADC. It can be connected to REFBO or to an externally generated reference level. Sufficient filtering

should be applied to this input. The use a 0.1 µF capacitor connected between REFBI and AV

recommended. Additionaly, a 0.1 µF capacitor can be connected between REFTI and REFBI.

is

SS

REFBO

REFTI

22

20

O

I

Reference voltage bottom output. An internally generated reference is available at this terminal. It can be

connected to REFBI or left unconnected. A 1 µF capacitor between REFBO and AV

sufficient decoupling required for this output.

will provide

SS

Reference voltage top input. The voltage at this terminal defines the top reference voltage for the ADC.

It can be connected to REFTO or to an externally generated reference level. Sufficient filtering should be

appliedtothisinput.Theuseofa0.1µFcapacitorbetweenREFTIandAV isrecommended. Additionaly,

SS

a 0.1 µF capacitor can be connected between REFTI and REFBI.

REFTO

STBY

19

15

O

I

Reference voltage top output. An internally generated reference is available at this terminal. It can be

connectedtoREFTIorleftunconnected.A1µFcapacitorbetweenREFTOandAV willprovidesufficient

SS

decoupling required for this output.

Standby input. A high level on this input enables a powerdown mode.

4

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TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage: AV

to AGND, DV

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.5 V

DD

to DV , AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 0.5 V

DD

Digital input voltage range to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to DV

Analog input voltage range to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to AV

Digital output voltage applied from external source to DGND . . . . . . . . . . . . . . . . . . . –0.5 V to DV

+ 0.5 V

DD

Reference voltage input range to AGND: V

, V

–0.5 V to AV

(REFTI) (REFTO) (REFBI) (REFBO)

Operating free-air temperature range, T : TLV5580C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A

TLV5580I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions over operating free-temperature range

power supply

MIN NOM

MAX

UNIT

AV

DD

Supply voltage

DV

3

3.3

3.6

V

DD

DRV

DD

analog and reference inputs

MIN

NOM

MAX

UNIT

Reference input voltage (top), V

(NOM) – 0.2 2 + (AV

– 3)

DD

(NOM) + 0.2

1.2

V

(REFTI)

Reference input voltage (bottom), V

0.8

1

(REFBI)

– V

Reference voltage differential, V

1 + (AV – 3)

DD

(REFTI)

(REFBI)

Analog input voltage, V

V

(REFTI)

(AIN)

(REFBI)

digital inputs

MIN NOM

MAX

UNIT

V

High-level input voltage, V

2.0

DV

IH

DD

0.2xDV

Low-level input voltage, V

DGND

V

IL

DD

Clock period, t

12.5

5.25

ns

c

Pulse duration, clock high, t

w(CLKH)

Pulse duration, clock low, t

5.25

ns

w(CLKL)

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

electrical characteristics over recommended operating conditions with f

of external voltage references (unless otherwise noted)

= 80 MSPS and use

CLK

power supply

PARAMETER

TEST CONDITIONS

MIN

TYP

57

3

MAX

71

UNIT

AV

DD

AV

DD

L

= DV

= 3.3 V, DRV

= 3 V,

DD

= 15 pF, V = 1 MHz, –1 dBFS

I

Operating supply current

DV

3.6

7.5

270

210

15

mA

DD

DRV

C

I

5

DD

PWDN_REF = L

213

165

11

P

Power dissipation

Standby power

D

PWDN_REF = H

mW

STBY = H, CLK held high or low

D(STBY)

digital logic inputs

PARAMETER

High-level input current on CLK

TEST CONDITIONS

MIN

TYP

MAX

UNIT

†

I

AV

= DV

= DRV

= CLK = 3.6 V

= 3.6 V,

10

µA

IH

DD

Low-level input current on digital inputs

(OE, STDBY, PWDN_REF, CLK)

DD

10

µA

IL

Digital inputs at 0 V

C

Input capacitance

5

pF

I

†

I

leakage current on other digital inputs (OE, STDBY, PWDN_REF) is not measured since these inputs have an internal pull-down resistor of

IH

4 KΩ to DGND.

logic outputs

PARAMETER

TEST CONDITIONS

= DRV = 3 V at I

MIN

TYP

MAX

UNIT

AV

DD

= DV

= 50 µA,

OH

DD

V

High-level output voltage

2.8

V

OH

Digital output forced high

AV = DV = DRV

Digital output forced low

= 3.6 V at I = 50 µA,

OL

DD DD

DD

Low-level output voltage

Output capacitance

0.1

V

OL

C

5

pF

µA

O

High-impedance state output current to

high level

I

10

OZH

AV

DD

= DV

= DRV = 3.6 V

DD

High-impedance state output current to

low level

I

µA

OZL

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

electrical characteristics over recommended operating conditions with f

of external voltage references (unless otherwise noted)

= 80 MSPS and use

CLK

dc accuracy

PARAMETER

TEST CONDITIONS

MIN

TYP

±1

MAX

2

UNIT

LSB

%FS

T

= 25°C

–2

–2.4

–1

A

Integral nonlinearity (INL), best-fit

Internal references (see Note 1)

Internal references (see Note 2),

T

A

= –40°C to 85°C

±1

2.4

1.3

5

Differential nonlinearity (DNL)

Zero error

T

A

±0.6

AV

DD

= DV

= 3.3 V, DRV = 3 V See Note 3

DD

Full scale error

5

NOTES: 1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero

occurs 1/2 LSB before the first code transition. The full–scale point is defined as a level 1/2 LSB beyond the last code transition.

The deviation is measured from the center of each particular code to the true straight line between these two endpoints.

2. AnidealADCexhibitscodetransitionsthatareexactly1LSBapart. DNListhedeviationfromthisidealvalue.Thereforethismeasure

indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under

n

test (i.e., (last transition level – first transition level) ÷ (2 – 2)). Using this definition for DNL separates the effects of gain and offset

error. A minimum DNL better than –1 LSB ensures no missing codes.

3. Zero error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch

the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the

bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by

the number of ADC output levels (256).

Full-scaleerrorisdefinedasthedifferenceinanaloginputvoltage–betweentheidealvoltageandtheactualvoltage–thatwillswitch

the ADC output from code 254 to code 255. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5

LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references

divided by the number of ADC output levels (256).

analog input

PARAMETER

Input capacitance

TEST CONDITIONS

MIN

TYP

MAX

UNIT

C

4

pF

I

reference input (AV

= DV

= DRV

= 3.6 V)

DD

PARAMETER

Reference input resistance

Reference input current

TYP

200

5

UNIT

Ω

R

ref

I

mA

ref

reference outputs

PARAMETER

TEST CONDITIONS

Absolute min/max values valid

and tested for AV = 3.3 V

MIN

2.07

1.09

TYP

MAX

2.21

1.21

UNIT

V

Reference top offset voltage

2 + [(AV

– 3) ÷ 2]

(REFTO)

DD

Reference bottom offset voltage

1 + [(AV

V

(REFBO)

DD

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

electrical characteristics over recommended operating conditions with f

of external voltage references (unless otherwise noted) (continued)

= 80 MSPS and use

CLK

†

dynamic performance

PARAMETER

TEST CONDITIONS

MIN

TYP

7.0

MAX

UNIT

f

= 1 MHz

6.6

in

= 4.43 MHz

= 15 MHz

= 76 MHz

= 1 MHz

7.0

Effective number of bits, ENOB

Bits

6.5

6.6

41.5

43.5

41

= 4.43 MHz

= 15 MHz

= 76 MHz

= 1 MHz

Signal-to-total harmonic distortion + noise, S/(THD+N)

Total harmonic distortion (THD)

dB

41.5

–50

–49

–44

–45.5

53

–46

= 4.43 MHz

= 15 MHz

= 76 MHz

= 1 MHz

–45.5

48

= 4.43 MHz

= 15 MHz

= 76 MHz

53

Spurious free dynamic range (SFDR)

46.5

48.5

700

0.8

Analog input full-power bandwidth, BW

Differential phase, DP

See Note 4

MHz

°

f

= 40 MHz, f = 4.43 MHz,

clk

in

20 IRE amplitude vs. full-scale of 140 IRE

Differential gain, DG

0.6

%

†

Based on analog input voltage of –1 dBFS referenced to a 1.3 V

full-scale input range and using the external voltage references at

pp

= 3.0 V at 25°C.

f

= 80 MSPS with AV

= DV

= 3.3 V and DRV

DD DD

clk

DD

NOTE 4: The analog input bandwidth is defined as the maximum frequency of a –1 dBFS input sine that can be applied to the device for which

an extra 3 dB attenuation is observed in the reconstructed output signal.

8

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TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

electrical characteristics over recommended operating conditions with f

of external voltage references (unless otherwise noted) (continued)

= 80 MSPS and use

CLK

timing requirements

PARAMETER

Maximum conversion rate

Minimum conversion rate

Output delay time (see Figure 1)

Output hold time

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MHz

kHz

ns

f

t

80

clk

10

9

clk

C

= 10 pF,

= 2 pF,

See Notes 5 and 6

See Note 5

d(o)

h(o)

L

2

ns

CLK

cycles

t

Pipeline delay (latency)

See Note 6

4.5

d(pipe)

t

Aperture delay time

3

1.5

5

ns

ps, rms

ns

d(a)

j(a)

dis

en

Aperture jitter

See Note 5

Disable time, OE rising to Hi-Z

Enable, OE falling to valid data

8

5

ns

NOTES: 5. Outputtiming t

is measured from the 1.5 V level oftheCLKinputfallingedgetothe10%/90%levelofthedigitaloutput. Thedigital

d(o)

output load is not higher than 10 pF.

Output hold time t

is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The

h(o)

digital output is load is not less than 2 pF.

Aperture delay t

is measured from the 1.5 V level of the CLK input to the actual sampling instant.

d(A)

The OE signal is asynchronous.

OE timing t is measured from the V

level of OE to the high-impedance state of the output data. The digital output load is

IH(MIN)

dis

not higher than 10 pF.

OE timing t is measured from the V

en

level of OE to the instant when the output data reaches V

or V output

OL(max)

IL(MAX)

levels. The digital output load is not higher than 10 pF.

OH(min)

6. The number of clock cycles between conversion initiation on an input sample and the corresponding output data being made

available from the ADC pipeline. Once the data pipeline is full, new valid output data is provided on every clock cycle. In order to

know when data is stable on the output pins, the output delay time t

(i.e., the delay time through the digital output buffers) needs

is more than 1/2 clock period at 80 MHz; data cannot be reliably

d(o)

to be added to the pipeline latency. Note that since the max. t

d(o)

clocked in on a rising edge of CLK at this speed. The falling edge should be used.

N+3

N

N+1

N+5

N+2

N+4

t

j(A)

t

d(A)

V

IL

(max)

V

(min)

CLK

IH

1.5 V

t

w(CLKH)

1/f

CLK

t

w(CLKL)

t

d(o)

t

h(o)

V

OH(min)

90%

10%

D0–D7

N–4

N–3

N–2

N–1

N

N+1

V

OL(max)

t

dis

t

en

t

d(pipe)

V

IH(min)

OE

V

IL(max)

Figure 1. Timing Diagram

9

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TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

performance plots at 25°C

1

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1

0

50

100

150

200

250

ADC Code

Figure 2. DNL vs Input Code At 80 MSPS (With External Reference, PW Package)

2

1.5

1

0.5

0

–0.5

–1

–1.5

–2

0

50

100

150

200

250

ADC Code

Figure 3. INL vs Input Code At 80 MSPS (With External Reference, PW Package)

10

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TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

performance plots at 25°C (continued)

50

45

40

35

30

25

20

15

10

60 MSPS

80 MSPS

40 MSPS

5

0

10 20 30 40 50 60 70 80 90 100

Analog Input Frequency – MHz

Figure 4. S/(THD+N) vs V At 80 MSPS (Internal Reference),

IN

60 MSPS (External Reference), 40 MSPS (External Reference)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

5

10

15

20

25

30

f – Frequency – MHz

Figure 5. Spectral Plot f = 1.011 MHz At 60 MSPS

IN

11

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TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

performance plots at 25°C (continued)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

5

10

15

20

25

30

35

40

f – Frequency – MHz

Figure 6. Spectral Plot f = 0.996 MHz At 80MSPS

IN

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

5

10

15

20

25

30

35

40

f – Frequency – MHz

Figure 7. Spectral Plot f = 15.527 MHz At 80 MSPS

IN

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

5

10

15

20

25

30

35

40

f – Frequency – MHz

Figure 8. Spectral Plot f = 75.02 MHz At 80MSPS

IN

(Plot shows folded spectrum of undersampled input signal)

12

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TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

performance plots at 25°C (continued)

250

5

4.5

4

200

150

100

3.5

3

2.5

2

1.5

1

50

0

0.5

0

10 20 30 40 50 60 70 80 90 100

Sampling Frequency – MHz

0

10 20 30 40 50 60 70 80 90 100

Sampling Frequency – MHz

Figure 9. Power vs f

Figure 10. IDRVDD vs f

CLK

At V = 1 MHz, –1 dBFS

IN

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

–10

6

7

10

8

10

9

10

Analog Input Frequency – Hz

Figure 11. ADC Output Power With Respect To –1 dBFS V

(Internal Reference, DW Package)

IN

13

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TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

PRINCIPLE OF OPERATION

The TLV5580 implements a high-speed 80 Msps converter in a cost-effective CMOS process. Powered from

3.3 V, the single-pipeline design architecture ensures low-power operation and 8 bit accuracy. Signal input and

clock signals are all single-ended. The digital inputs are 3.3 V TTL/CMOS compatible. Internal voltage

references are included for both bottom and top voltages. Therefore the converter forms a self-contained

solution. Alternatively the user may apply externally generated reference voltages. In doing so, both input offset

and input range can be modified to suit the application.

A high-speed sampling-and-hold captures the analog input signal. Multiple stages will generate the output code

with a pipeline delay of 4.5 CLK cycles. Correction logic combines the multistage data and aligns the 8-bit output

word. All digital logic operates at the rising edge of CLK.

analog input

TLV5580

S1

R

S

AIN

R

SW

C

I

V

S

Figure 12. Simplified Equivalent Input Circuit

A first-order approximation for the equivalent analog input circuit of the TLV5580 is shown in Figure 12. The

equivalent input capacitance C is 4 pF typical. The input must charge/discharge this capacitance within the

I

sample period of one half clock cycle. When a full-scale voltage step is applied, the input source provides the

charging current through the switch resistance R

impedance is low. Alternatively, when the source voltage equals the value previously stored on C , the hold

capacitor requires no input current and the equivalent input impedance is very high.

(200 Ω) of S1 and quickly settles. In this case the input

SW

I

To maintain the frequency performance outlined in the specifications, the total source impedance should be

limited to about 80 Ω, as follows from the equation with f

= 80 MHz, C = 4 pF, R

= 200 Ω:

CLK

I

SW

R

1 ÷ 2f

C

In(256) –R

S

CLK

I

SW

So, for applications running at a lower f

, the total source resistance can increase proportionally.

CLK

14

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TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

PRINCIPLE OF OPERATION

dc coupled input

REFTI

R

IN

REFTO

R

IN

V

IN

V

IN

_

TLV5580

+

_

AIN

V

REF

+

R

1

AV

DD

REFBI

REFBO

R

2

(b)

(a)

Figure 13. DC-Coupled Input Circuit

For dc-coupled systems an opamp can level-shift a ground-referenced input signal. A circuit as shown in

Figure 13(a) is acceptable. Alternatively, the user might want a bipolar shift together with the bottom reference

voltage as seen in Figure 13(b). In this case the AIN voltage is given by:

AIN

2

R

÷ R

R

V

– V

2

REF

IN

1

ac coupled input

C1

C2

TLV5580

R1

V

IN

AIN

R2

+

V

BIAS

–

Figure 14. AC-Coupled Input Circuit

For many applications, especially in single supply operation, ac coupling offers a convenient way for biasing

the analog input signal at the proper signal range. Figure 14 shows a typical configuration. To maintain the

outlined specifications, the component values need to be carefully selected. The most important issue is the

positioning of the 3 dB high-pass corner point f

, which is a function of R and the parallel combination of

–3 dB

2

C and C , called C . This is given by the following equation:

1

2

eq

f

1 ÷ 2π x R x C

eq

2

–3 dB

where C is the parallel combination of C and C .

eq

1

2

Since C1 is typically a large electrolytic or tantalum capacitor, the impedance becomes inductive at higher

frequencies. Adding a small ceramic or polystyrene capacitor, C2 of approximately 0.01 µF, which is not

inductive within the frequency range of interest, maintains low impedance. If the minimum expected input signal

frequency is 20 kHz, and R2 equals 1 kΩ and R1 equals 50 Ω, the parallel capacitance of C1 and C2 must be

a minimum of 8 nF to avoid attenuating signals close to 20 kHz.

15

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TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

PRINCIPLE OF OPERATION

reference terminals

The voltages on terminals REFBI and REFTI determine the TLV5580’s input range. Since the device has an

internal voltage reference generator with outputs available on REFBO respectively REFTO, corresponding

terminals can be directly connected externally to provide a contained ADC solution. Especially at higher

sampling rates, it is advantageous to have a wider analog input range. The wider analog input range is

achievable by using external voltage references (e.g., at AVDD = 3.3 V, the full scale range can be extended

from 1 Vpp (internal reference) to 1.3 Vpp (external reference) as shown in Table 1). These voltages should not

be derived via a voltage divider from a power supply source. Instead, use a bandgap-derived voltage reference

to derive both references via an opamp circuit. Refer to the schematic of the TLV5580 evaluation module for

an example circuit.

When using external references, the full-scale ADC input range and its dc position can be adjusted. The

full-scale ADC range is always equal to V

asshowninthespecificationsection.Inadditiontothelimitationontheirdifference,V

have limits on their useful range. These limits are also dependent on AV

– V

. The maximum full-scale range is dependent on AV

REFT

REFB DD

andV

eachalso

REFT

REFB

.

DD

Table 3 summarizes these limits for 3 cases.

Table 1. Recommended Operating Modes

AV

DD

V

[V

–V

]

REFB(min)

REFB(max)

REFT(min)

REFT(max)

REFT REFB max

3 V

0.8 V

1.2 V

1.8 V

2.2 V

1 V

3.3 V

3.6 V

0.8 V

1.2 V

2.1 V

2.4 V

2.5 V

2.8 V

1.3 V

1.6 V

digital inputs

The digital inputs are CLK, STDBY, PWDN_REF, and OE. All these signals, except CLK, have an internal

pull-down resistor to connect to digital ground. This provides a default active operation mode using internal

references when left unconnected.

The CLK signal at high frequencies should be considered as an analog input. Overshoot/undershoot should be

minimized by proper termination of the signal close to the TLV5580. An important cause of performance

degradation for a high-speed ADC is clock jitter. Clock jitter causes uncertainty in the sampling instant of the

ADC, in addition to the inherent uncertainty on the sampling instant caused by the part itself, as specified by

N

its aperture jitter. There is a theoretical relationship between the frequency (f) and resolution (2 ) of a signal

that needs to be sampled and the maximum amount of aperture error dt

formula shows the relation:

that is tolerable. The following

max

N

1

dt

1

f 2

max

As an example, for an 8–bit converter with a 15-MHz input, the jitter needs to be kept <41 pF in order not to have

changes in the LSB of the ADC output due to the total aperture error.

16

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8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

PRINCIPLE OF OPERATION

digital outputs

The output of TLV5580 is a standard binary code. Capacitive loading on the output should be kept as low as

possible (a maximum loading of 10 pF is recommended) to provide best performance. Higher output loading

causes higher dynamic output currents and can increase noise coupling into the device’s analog front end. To

drive higher loads, use an output buffer is recommended.

When clocking output data from TLV5580, it is important to observe its timing relation to CLK. Pipeline ADC

delay is 4.5 clock cycles to which the maximum output propagation delay is added. See Note 6 in the

specification section for more details.

layout, decoupling and grounding rules

It is necessary for any PCB using the TLV5580 to have proper grounding and layout to achieve the stated

performance. Separate analog and digital ground planes that are spliced underneath the device are advisable.

TLV5580 has digital and analog terminals on opposite sides of the package to make proper grounding easier.

Since there is no internal connection between analog and digital grounds, they have to be joined on the PCB.

Joining the digital and analog grounds at a point in close proximity to the TLV5580 is advised.

As for power supplies, separate analog and digital supply terminals are provided on the device (AV /DV ).

DD

The supply to the digital output drivers is kept separate also (DRV ). Lowering the voltage on this supply from

DD

the nominal 3.3 V to 3 V improves performance because of the lower switching noise caused by the output

buffers.

Due to the high sampling rate and switched-capacitor architecture, TLV5580 generates transients on the supply

and reference lines. Proper decoupling of these lines is essential. Decoupling as shown in the schematic of the

TLV5580 EVM is recommended.

17

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TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

TLV5580 EVALUATION MODULE

TLV5580 evaluation module

TI provides an evaluation module (EVM) for TLV5580. The EVM also includes a 10b 80 MSPS DAC so that the

user can convert the digitized signal back to the analog domain for functional testing. Performance

measurements can be done by capturing the ADC’s output data.

The EVM provides the following additional features:

Provision of footprint for the connection of an onboard crystal oscillator, instead of using an external clock

input.

Use of TLV5580 internal or external voltage references. In the case of external references, an onboard

circuit is used that derives adjustable bottom and top reference voltages from a bandgap reference. Two

potentiometers allow for the independent adjustments of both references. The full scale ADC range can be

adjusted to the input signal amplitude.

All digital output, control signal I/O (output enable, standby, reference powerdown) and clock I/O are

provided on a single connector. The EVM can thus be part of a larger (DSP) system for prototyping.

Onboard prototyping area with analog and digital supply and ground connections.

Figure 15 shows the EVM schematic.

The EVM is factory shipped for use in the following configuration:

Use of external (onboard) voltage references

External clock input

analog input

AsignalintherangebetweenV

andV

shouldbeappliedtoavoidoverflow/underflowonconnector

(REFBI)

(REFTI)

J10. This signal is onboard terminated with 50Ω. There is no onboard biasing of the signal. When using external

(onboard) references, these levels can be adjusted with R7 (V ) and R6 (V ). Adjusting R7 causes

(REFTI)

(REFBI)

both references to shift. R6 only impacts the bottom reference. The range of these signals for which the device

is specified depends on AV and is shown under the Recommended Operating Conditions.

DD

Internally generated reference levels are also dependent on AV

section.

as shown in the electrical characteristics

DD

clock input

A clock signal should be applied with amplitudes ranging from 0 to AV

with a frequency equal to the desired

DD

sampling frequency on connector J9. This signal is onboard terminated with 50 Ω. Both ADC and DAC run off

the same clock signal. Alternatively the clock can be applied from terminal 1 on connector J11. A third option

is using a crystal oscillator. The EVM board provides the footprint for a crystal oscillator that can be populated

by the end-user, depending on the desired frequency. The footprint is compatible with the Epson EG-8002DC

series of programmable high-frequency crystal oscillators. Refer to the TLV5580 EVM Settings for selecting

between the different clock modes.

18

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TLV5580 EVALUATION MODULE

power supplies

The board provides seven power supply connectors (see Table 2). For optimum performance, analog and digital

supplies should be kept separate. Using separate supplies for the digital logic portion of TLV5580 (DV ) and

DD

its output drivers (DRV ) benefits dynamic performance, especially when DRV

is put at the minimum

DD

required voltage (3 V), while DV

caused by the output drivers.

might be higher (up to 3.6 V). This lowers the switching noise on the die

DD

Table 2. Power Supplies

SIGNAL

BOARD

LABEL

CONNECTOR

DESCRIPTION

NAME

DRV3

DV3

J1

J2

J3

J4

J5

3DRV

3VD

5VD

3VA

3.3 V digital supply for TLV5580 (digital output drivers)

3.3 V digital supply for TLV5580 (digital logic) and peripherals

5 V digital supply for D/A converter and peripherals

3.3 V analog supply for TLV5580

DV5

AV3

AV5

5VA

5 V analog supply for onboard reference circuit and D/A converter. Can be left unconnected if

internal references are used and no D/A conversion is required.

AV+12

AV–12

J6

J7

12VA

12 V analog supply for onboard reference circuit. Can be left unconnected if internal references

are used.

–12VA

–12 V analog supply for onboard reference circuit. Can be left unconnected if internal

references are used.

voltage references

SW1 and SW2 switch between internal and external top and bottom references respectively. The external

references are onboard generated from a stable bandgap-derived 3.3 V signal (using TI’s TPS7133 and

quad-opamp TLE2144). They can be adjusted via potentiometers R6 (V

to power down the internal voltage references by asserting PWN_REF when onboard references are used.

) and R7 (V

). It isadvised

(REFBI)

(REFTI)

The references are measured at test points TP3 (V ) and TP4 (V ).

(REFB)

(REFT)

DAC output

The onboard DAC is a 10-bit 80 MSPS converter. It is connected back-to-back to the TLV5580. While the user

could use its analog output for measurements, the DAC output is directly connected to connector J8 and does

not pass through an analog reconstruction filter. So mirror spectra from aliased signal components feed through

into the analog output.

For this reason and to separate ADC and DAC contributions, performance measurements should be made by

capturing the ADC output data available on connector J11 and not by evaluating the DAC output.

19

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SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

TLV5580 EVALUATION MODULE

TLV5580 EVM settings

clock input settings

REFERENCE

DESIGNATOR

FUNCTION

W1

W2

Clock selection switch

1–2 J11: clock from pin1 on J11 connector

2–3 J9: clock from J9 SMA connector

Clock source switch

XTL: clock from onboard crystal oscillator

CLK: clock from pin 1 on J11 connector (if W1/1–2) or J9 SMA connector (if W1/2–3)

NOTE: If set to XTL and a XTL oscillator is populated, no clock signal should be applied to J9 or J11, depending on the W1

setting.

W3

Clock output switch

1–2 Rising: clock output on J11 connector is the same phase as the clock to the digital output buffer. Data changes on rising

CLK edge.

2–3Falling: clockoutputonJ11connectoristheoppositephaseasthedigitaloutputbuffer.DatachangesonfallingCLKedge.

reference settings

REFERENCE

DESIGNATOR

FUNCTION

SW1

SW2

REFT external/internal switch

REFT internal: REFT from TLV5580 internal reference

REFT external: REFT from onboard voltage reference circuit

REFB external/internal switch

REFB internal: REFB from TLV5580 internal reference

REFB external: REFB from onboard voltage reference circuit

control settings

REFERENCE

DESIGNATOR

FUNCTION

W4

TLV5580 and digital output buffer output enable control (1)

5580-574 OE-connected: Connects OEs of TLV5580 and digital output buffer (574 buffer). Use this when no

board-external OE is used. In addition, close W5 to have both OEs permanently enabled.

5580-574 OE-disconnected: Disconnects OEs of TLV5580 and digital output buffer (574 buffer). The OE for the output

buffer needs to be pulled low from pin 5 on J11 connector to enable. The OE for TLV5580 is independently controlled from

pin 7 on J11 connector (W5 open) or is permanently enabled if W5 is closed.

W5

W6

TLV5580 and digital output buffer output enable control (2)

5580OE to GND: Connects OEs of TLV5580 to GND. Additionally connects OE of 74ALS574 to GND if W4 is 5580-574

OE-connected.

5580 OE external: Enables control of OE of TLV5580 via pin 7 on J11 connector. When taken high (internal pulldown)

the output can be disabled.

TLV5580 STDBY control

Stdby: STDBY is active (high).

Active: STDBY is low, via internal pulldown. STDBY can be taken high from pin 9 on J11 connector to enable standby

mode.

20

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8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

TLV5580 EVALUATION MODULE

control settings (continued)

REFERENCE

DESIGNATOR

FUNCTION

W7

TLV5580 PWDN REF control

Pwdn_ref: PWDN_REF is active (high).

Active: PWDN_REFislow, viainternalpulldown. PWDN_REFcanbetakenhighfrompin10onJ11connectortoenable

pwdn_ref mode.

W8

DAC enable

Active: D/A on

Standby: D/A off

21

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8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

2 6

2 5

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

9

8

7

6

5

4

3

2

1

I R E F

N C

8

1 7

S R E F

V R E F

V A D D

D 9

D 8

D 7

D 6

D 5

D 4

D 3

1 8

1 9

2 0

2 1

2 2

2 3

2 4

7

R 1 8

R 1 9

R 2 0

R 2 1

R 2 2

R 2 3

2 0

6

5

4

3

2

1

V A D D

V G

I O

2 0

R 2 5

Figure 15. EVM Schematic

22

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8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

TLV5580 EVALUATION MODULE

Digital +5 V

Analog +12 V

L3

J3

1

L6

J6

1

DV5

C17

AV +12 V

C20

4.7 µH

+

C5

1 µF

C6

10 µF

C11

1 µF

C12

10 µF

2

Digital +3.3 V (DVDD)

Analog –12 V

L2

L7

J2

1

J7

1

DV3

C16

AV –12 V

4.7 µH

+

C13

1 µF

C3

1 µF

C4

10 µF

C14

10 µF

C21

10 µF

+

10 µF

2

Analog +5 V

Digital +3.3 V (DRVDD)

L5

L1

J5

1

J1

1

AV5

C19

DRV3

C15

4.7 µH

+

C9

C10

C1

C2

1 µF

10 µF

1 µF

10 µF

2

Analog +3.3 V

L4

J4

1

AV3

C18

4.7 µH

+

C7

C8

1 µF

10 µF

2

Figure 15. EVM Schematic (Continued)

23

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TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

TLV5580 EVALUATION MODULE

Top Overlay

Figure 15. EVM Schematic (Continued)

24

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8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

TLV5580 EVALUATION MODULE

Top Layer

Figure 15. EVM Schematic (Continued)

25

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8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

TLV5580 EVALUATION MODULE

Internal Plane 1

Figure 15. EVM Schematic (Continued)

26

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8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

TLV5580 EVALUATION MODULE

Internal Plane 2

Figure 15. EVM Schematic (Continued)

27

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8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

TLV5580 EVALUATION MODULE

4200 (mil)

Drill Drawing for Through Hole

Figure 15. EVM Schematic (Continued)

28

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TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

TLV5580 EVALUATION MODULE

Bottom Layer

Figure 15. EVM Schematic (Continued)

29

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TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

TLV5580 EVALUATION MODULE

Table 3. TLV5580EVM Bill of Material

MANUFACTURER/

PART NUMBER

QTY. REFERENCE DESIGNATOR

VALUE

SIZE

DESCRIPTION

†

7

C1, C11, C13, C3, C5, C7, C9

1 µF

1206

3216

ceramic multilayer capacitor

Any

18

C10, C12, C14, C15, C16,

C17, C18, C19, C2, C20, C21,

C22, C23, C4, C6, C8, C38,

C44

10 µF

16 V, 10 µF, tantalum capacitor

Any

2

C36, C43

0.01 µF

0.1 µF

805

Ceramic multilayer

Any

19

C24, C25, C26, C27, C28,

C29, C30, C31, C32, C33,

C34, C35, C37, C39, C40,

C41, C42, C45, C46

Ceramic multilayer capacitor

7

3

1

7

J1, J2, J3, J4, J5, J6, J7

Screw Con

SMA

2 terminal screw connector

PCM mount, SMA Jack

Lumberg

KRMZ2

J10, J8, J9

Johnson Components

142-0701-206

J11

IDC26

13 × 2.025 square pin header Samtec

TSW-113-07-L-D

L1, L2, L3, L4, L5, L6, L7

4.7 µH

4.7 µH DO1608C-472-Coil Craft Coil Craft

DO1608-472

1

2

R2

0

1206

Chip resistor

Any

R26, R27

10

Any

12

R1, R11, R14, R40, R41, R42,

R43, R44, R45, R46, R47, R48

10 K

6

1

R10, R12, R15, R16, R8, R9

R5

1 K

2.1 K

20

1206

Chip resistor

Any

20

R13, R17, R18, R19, R20,

R21, R22, R23, R24, R25,

R29, R30, R31, R32, R33,

R35, R36, R37, R38, R39

1

2

1

R3

200

3.24 K

49.9

1206

Chip resistor

Any

R4

Chip resistor

R28, R34

R6

Chip resistor

5 K

4 mm SM pot-top adjust

Bourns

3214W-5K

1

2

4

R7

1 K

SPDT

TP

4 mm SM pot-top adjust

Bourns

3214W-1K

SW1, SW2

TP1, TP2, TP3, TP4

C&K tiny series–slide switch

Test point, single 0.025 pin

C&K

TS01CLE

Samtec

TSW-101-07-L-S

or equivalent

1

U3

U2

U5

CXD2306Q

SN74ALVC00D

SN74LVT574DW

Sony

CXD2306Q

14-SOIC (D)

Quad 2-input positive NAND

Texas Instruments

SN74ALVC00D

20-SOP (DW)

Texas Instruments

SN74LVT574DW

†

Manufacturer and part number data for reference only. Equivalent parts might be substituted on the EVM.

30

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TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

TLV5580 EVALUATION MODULE

Table 3. TLV5580EVM Bill of Material (Continued)

MANUFACTURER/

PART NUMBER

QTY. REFERENCE DESIGNATOR

VALUE

SIZE

DESCRIPTION

Quad op amp

†

1

U4

TLE2144CDW

16-SOP(D)

Texas Instruments

TLE2144CDW/

TLE2144IDW

1

6

U6

TLV5580PW

TPS7133

SPST

28-TSSOP (PW)

8-SOP(D)

Texas Instruments

TLV5580PW

U1

Low-dropout voltage regulator

2 position jumper, 0.1 spacing

Texas Instruments

TPS7133QD

W2, W4, W5, W6, W7, W8

Samtec

TSW-102-07-L-S

or equivalent

2

1

W1, W3

X1

DPFT

NA

3 position jumper, 0.1 spacing

Crystal oscillator

Samtec

TSW-103-07-L-S

or equivalent

Epson

SG-8002DC series

†

Manufacturer and part number data for reference only. Equivalent parts might be substituted on the EVM.

31

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TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

MECHANICAL DATA

DW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

16 PIN SHOWN

0.050 (1,27)

16

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

M

9

0.419 (10,65)

0.400 (10,15)

0.010 (0,25) NOM

0.299 (7,59)

0.293 (7,45)

Gage Plane

0.010 (0,25)

1

8

0°–8°

0.050 (1,27)

0.016 (0,40)

A

Seating Plane

0.004 (0,10)

0.012 (0,30)

0.004 (0,10)

0.104 (2,65) MAX

PINS **

16

20

24

28

0.710

DIM

0.410

0.510

0.610

A MAX

A MIN

(10,41) (12,95) (15,49) (18,03)

0.400

0.500

0.600

0.700

(10,16) (12,70) (15,24) (17,78)

4040000/C 07/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).

D. Falls within JEDEC MS-013

32

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TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

MECHANICAL DATA

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0,30

0,19

0,65

M

0,10

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

0,75

A

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

A MAX

A MIN

4040064/E 08/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

33

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型号：	TLV5580IDWR
厂家：	TEXAS INSTRUMENTS
描述：	8-BIT, 80 MSPS LOW-POWER A/D CONVERTER 光电二极管转换器
文件：	总34页 (文件大小：531K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLV5580IDWR [TI]

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