TLV5608 [TI]
8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN; 8通道， 12位/ 10位/ 8位， 2.7 V至5.5 V的低功耗数字 - 模拟与电源转换器的降压
| 型号： | TLV5608 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN |
| 文件： | 总16页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV5608
TLV5610
TLV5629
www.ti.com
SLAS268E–MAY 2000–REVISED MARCH 2004
8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER
DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
FEATURES
APPLICATIONS
•
•
•
•
•
Digital Servo Control Loops
Digital Offset and Gain Adjustment
Industrial Process Control
Machine and Motion Control Devices
Mass Storage Devices
•
Eight Voltage Output DACs in One Package
– TLV5610 . . . 12-Bit
– TLV5608 . . . 10-Bit
– TLV5629 . . . 8-Bit
•
•
Programmable Settling Time vs Power
Consumption
DW OR PW PACKAGE
(TOP VIEW)
– 1 µs In Fast Mode
– 3 µs In Slow Mode
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DGND
DIN
SCLK
FS
DV
DD
Compatible With TMS320 and SPI™ Serial
Ports
DOUT
LDAC
MODE
REF
OUTD
OUTC
OUTB
OUTA
•
•
Monotonic Over Temperature
Low Power Consumption:
PRE
OUTE
OUTF
OUTG
OUTH
AGND
– 18 mW In Slow Mode at 3-V
– 48 mW In Fast Mode at 3-V
Reference Input Buffers
•
•
•
•
AV
DD
Power-Down Mode
Buffered, High Impedance Reference Inputs
Data Output for Daisy-Chaining
DESCRIPTION
The TLV5610, TLV5608, and TLV5629 are pin-compatible, eight-channel, 12-/10-/8-bit voltage output DACs
each with a flexible serial interface. The serial interface allows glueless interface to TMS320 and SPI, QSPI, and
Microwire serial ports. It is programmed with a 16-bit serial string containing 4 control and 12 data bits.
Additional features are a power-down mode, an LDAC input for simultaneous update of all eight DAC outputs,
and a data output which can be used to cascade multiple devices.
The resistor string output voltage is buffered by a rail-to-rail output amplifier with a programmable settling time to
allow the designer to optimize speed vs power dissipation. The buffered, high-impedance reference input can be
connected to the supply voltage.
Implemented with a CMOS process, the DACs are designed for single-supply operation from 2.7 V to 5.5 V. The
devices are available in 20-pin SOIC and TSSOP packages.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE (DW)
TLV5610IDW
TSSOP (PW)
TLV5610IPW
TLV5608IPW
TLV5629IPW
RESOLUTION
12
10
8
-40°C to 85°C
TLV5608IDW
TLV5629IDW
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola, Inc.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TLV5608
TLV5610
TLV5629
www.ti.com
SLAS268E–MAY 2000–REVISED MARCH 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
REF
12/10/8
12/10/8
12/10/8
X2
OUTA
DAC A
Holding
Latch
DAC A
Latch
SCLK
DIN
12
8
DOUT
FS
Serial
Interface
OUT
MODE
PRE
B, C, D,
E, F, G
and H
DAC B, C, D, E, F, G and H
Same as DAC A
LDAC
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AGND
AVDD
DGND
DIN
10
11
1
I
I
Analog ground
Analog power supply
Digital ground
I
2
I
Digital serial data input
Digital serial data output
Digital power supply
Frame sync input
DOUT
DVDD
FS
19
20
4
O
I
I
Load DAC. The DAC outputs are only updated, if this signal is low. It is an
asynchronous input.
LDAC
18
I
MODE
PRE
17
5
I
I
DSP/µC mode pin. High = µC mode, NC = DSP mode.
Preset input
REF
16
3
I
Voltage reference input
SCLK
I
Serial clock input
OUTA-OUTH
6-9, 12-15
O
DAC outputs A, B, C, D, E, F, G and H
2
TLV5608
TLV5610
TLV5629
www.ti.com
SLAS268E–MAY 2000–REVISED MARCH 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
7 V
Supply voltage (AVDD, DVDD to GND)
Reference input voltage
- 0.3 V to AVDD + 0.3 V
- 0.3 V to DVDD + 0.3 V
-40°C to 85°C
-65°C to 150°C
260°C
Digital input voltage range
Operating free-air temperature range, TA
Storage temperature range, Tstg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
Supply voltage, AVDD, DVDD
5-V operation
3-V operation
DVDD = 2.7 V
DVDD = 5.5 V
DVDD = 2.7 V
DVDD = 5.5 V
AVDD = 5 V
4.5
2.7
2
5
3
5.5
3.3
V
V
High-level digital input voltage, VIH
V
V
2.4
0.6
1
Low-level digital input voltage, VIL
Reference voltage, Vref
GND 4.096
GND 2.048
2
AVDD
AVDD
V
V
AVDD = 3 V
Load resistance, RL
kΩ
pF
MHz
°C
Load capacitance, CL
100
30
Clock frequency, fCLK
Operating free-air temperature, TA
-40
85
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted)
POWER SUPPLY
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Fast
16
6
21
8
No load, Vref = 4.096 V,
All inputs = DVDD or GND
IDD
Power supply current
mA
Slow
Power down supply current
Power on threshold
0.1
2
µA
V
POR
(1)
PSRR
Power supply rejection ratio
Full scale
-60
dB
(1) Power supply rejection ratio at full scale is measured by varying AVDD and is given by:
PSRR = 20 log [(EG(AVDDmax) - EG(AVDDmin))/VDDmax]
3
TLV5608
TLV5610
TLV5629
www.ti.com
SLAS268E–MAY 2000–REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS (CONTINUED)
over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted)
STATIC DAC SPECIFICATIONS
PARAMETER
TEST CONDITIONS
MIN
TYP
12
MAX
UNIT
TLV5610
TLV5608
TLV5629
TLV5610
TLV5608
TLV5629
TLV5610
Resolution
10
Bits
8
Code 40 to 4095
±2
±6
±2
Integral nonlinearity (INL)
Vref = 2 V, 4V
Vref = 2 V, 4V
Code 20 to 1023
Code 6 to 255
±0.5
±0.3
±0.5
±0.1
±0.1
LSB
LSB
±1
Code 40 to 4095
Code 20 to 1023
Code 6 to 255
±1
Differential nonlinearity (DNL) TLV5608
TLV5629
±1
±1
EZS
Zero-scale error (offset error at zero scale)
±30
mV
EZS TC Zero-scale-error temperature coefficient
30
µV/°C
% of FS
voltage
EG
Gain error
±0.6
EG TC
Gain error temperature coefficient
10
ppm/°C
OUTPUT SPECIFICATIONS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VO
Voltage output range
RL = 10 kΩ
0
AVDD-0.4
V
% of FS
voltage
Output load regulation accuracy
RL = 2 kΩ vs 10 kΩ
±0.3
REFERENCE INPUT
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
VI
Ri
Ci
Reference input voltage
0
AVDD
Reference input resistance
Reference input capacitance
100
5
kΩ
pF
Fast
2.2
1.9
-84
Reference input bandwidth
Reference feedthrough
Vref = 0.4 Vpp + 2.048 V dc, Input code = 0x800
Vref = 2 Vpp at 1 kHz + 2.048 V dc(1)
MHz
dB
Slow
DIGITAL INPUT
IIH
IIL
Ci
High-level digital input current
VI = VDD
VI = 0 V
1
µA
µA
pF
Low-level digital input current
Input capacitance
-1
8
DIGITAL OUTPUT
VOH
VOL
High-level digital output voltage
RL= 10 kΩ
2.6
V
V
Low-level digital output voltage
Output voltage rise time
RL= 10 kΩ
0.4
20
RL= 10 kΩ, CL = 20 pF, Includes propogation delay
7
ns
(1) Reference feedthrough is measured at the DAC output with an input code = 0x000.
4
TLV5608
TLV5610
TLV5629
www.ti.com
SLAS268E–MAY 2000–REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS (CONTINUED)
over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted)
ANALOG OUTPUT DYNAMIC PERFORMANCE
PARAMETER
TEST CONDITIONS
Fast
MIN
TYP
1
MAX UNIT
3
ts(FS)
ts(CC)
SR
Output settling time (full scale)
RL = 10 kΩ, CL = 100 pF(1)
RL = 10 kΩ, CL = 100 pF(2)
RL = 10 kΩ, CL = 100 pF(3)
µs
7
Slow
Fast
Slow
Fast
Slow
3
0.5
1
1
Output settling time, code to code
Slew rate
µs
2
4
1
10
3
V/µs
(4)
Glitch energy
See note
4
nV-s
dB
Channel crosstalk
10 kHz sine, 4 VPP
-90
(1) Settling time is the time for the output signal to remain within +0.5 LSB of the final measured value for a digital input code change of
0x80 to 0xFFF and 0xFFF to 0x080, respectively. Assured by design; not tested.
(2) Settling time is the time for the output signal to remain within +0.5 LSB of the final measured value for a digital input code change of one
count. The max time applies to code changes near zero scale or full scale. Assured by design; not tested.
(3) Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full scale voltage.
(4) Code transition: TLV5610 - 0x7FF to 0x800, TLV5608 - 0x7FC to 0x800, TLV5629 - 0x7F0 to 0x800
TIMING REQUIREMENTS
DIGITAL INPUTS
MIN
NOM
MAX
UNIT
tsu(FS-CK)
tsu(C16-FS)
Setup time, FS low before next negative SCLK edge
Setup time, 16th negative edge after FS low on which bit D0 is sampled before
rising edge of FS. µC mode only
8
ns
10
ns
tsu(FS-C17)
tsu(CK-FS)
twL(LDAC)
twH
µC mode, setup time, FS high before 17th positive SCLK.
DSP mode, setup time, SLCK low before FS low.
LDAC duration low
10
5
ns
ns
ns
ns
10
16
16
8
SCLK pulse duration high
twL
SCLK pulse duration low
tsu(D)
Setup time, data ready before SCLK falling edge
Hold time, data held valid after SCLK falling edge
FS duration high
ns
ns
ns
ns
th(D)
5
twH(FS)
twL(FS)
10
10
FS duration low
See AC
specs
ts
Settling time
5
TLV5608
TLV5610
TLV5629
www.ti.com
SLAS268E–MAY 2000–REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
t
wH
t
wL
SCLK
X
1
2
3
4
16
17
X
t
h(D)
t
su(D)
DIN
X
D15
D14
D13
D13
D12
D12
D1
D1
D0
X
X
†
†
†
†
†
†
DOUT
X
D15
t
D14
D0
t
su(FS - C17)
su(FS - CK)
t
t
su(C16 - FS)
wH(FS)
FS
(µC mode)
t
su(CK - FS)
t
wL(FS)
FS
X
(DSP Mode)
†
Previous input data
Figure 1. Serial Interface Timing
t
wL(LDAC)
LDAC
OUTx
±0.5 LSB
t
s
Figure 2. Output Timing
6
TLV5608
TLV5610
TLV5629
www.ti.com
SLAS268E–MAY 2000–REVISED MARCH 2004
TYPICAL CHARACTERISTICS
OUTPUT LOAD REGULATION
OUTPUT LOAD REGULATION
1
1
V
V
= 5 V,
= 4 V,
V
= 3 V,
= 2 V,
DD
DD
0.9
0.8
0.7
0.9
0.8
0.7
V
ref
ref
Zero Scale
Zero Scale
Fast
Fast
0.6
0.5
0.4
0.6
0.5
0.4
0.3
0.2
0.3
0.2
0.1
0
0.1
0
Slow
Slow
0.5
1.5
0.5
1.5
0
1
2
0
1
2
Sinking Current − mA
Sinking Current − mA
Figure 3.
Figure 4.
OUTPUT LOAD REGULATION
OUTPUT LOAD REGULATION
2.06
2.055
2.05
4.12
4.11
4.1
V
= 5 V,
= 4 V,
DD
V
= 3 V,
= 2 V,
DD
V
ref
V
ref
Full Scale
Full Scale
Fast
Slow
Fast
Slow
4.09
4.08
4.07
2.045
2.04
2.035
2.03
4.06
4.05
4.04
2.025
0
−0.5 −1
−1.5 −2
−2.5 −3
−3.5 −4
−0.05 −0.5 −1
−1.5 −2
−2.5 −3
−3.5 −4
Sourcing Current − mA
Sourcing Current − mA
Figure 5.
Figure 6.
7
TLV5608
TLV5610
TLV5629
www.ti.com
SLAS268E–MAY 2000–REVISED MARCH 2004
TYPICAL CHARACTERISTICS (CONTINUED)
TLV5610
INTEGRAL NONLINEARITY
vs
CODE
4
3
2
1
0
−1
−2
−3
−4
0
1024
2048
3072
4096
Code
Figure 7.
TLV5610
DIFFERENTIAL NONLINEARITY
vs
CODE
1.0
0.8
0.6
0.4
0.2
−0.0
−0.2
−0.4
−0.6
−0.8
−1.0
0
1024
2048
3072
4096
Code
Figure 8.
8
TLV5608
TLV5610
TLV5629
www.ti.com
SLAS268E–MAY 2000–REVISED MARCH 2004
TYPICAL CHARACTERISTICS (CONTINUED)
TLV5608
INTEGRAL NONLINEARITY
vs
CODE
2.0
1.5
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
0
256
512
768
1024
Code
Figure 9.
TLV5608
DIFFERENTIAL NONLINEARITY
vs
CODE
1.0
0.8
0.6
0.4
0.2
−0.0
−0.2
−0.4
−0.6
−0.8
−1.0
0
256
512
768
1024
Code
Figure 10.
9
TLV5608
TLV5610
TLV5629
www.ti.com
SLAS268E–MAY 2000–REVISED MARCH 2004
TYPICAL CHARACTERISTICS (CONTINUED)
TLV5629
INTEGRAL NONLINEARITY
vs
CODE
0.5
0.4
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
0
50
100
150
200
250
Code
Figure 11.
TLV5629
DIFFERENTIAL NONLINEARITY
vs
CODE
0.5
0.4
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
0
50
100
150
200
250
Code
Figure 12.
10
TLV5608
TLV5610
TLV5629
www.ti.com
SLAS268E–MAY 2000–REVISED MARCH 2004
APPLICATION INFORMATION
GENERAL FUNCTION
The TLV5610, TLV5608, and TLV5629 are 8-channel, 12-bit, single-supply DACs, based on a resistor string
architecture. They consist of a serial interface, a speed and power-down control logic, a reference input buffer, a
resistor string, and a rail-to-rail output buffer.
The output voltage (full scale determined by external reference) for each channel is given by:
CODE
0x1000
REF
[V]
(1)
where REF is the reference voltage and CODE is the digital input value. The input range is 0x000 to 0xFFF for
the TLV5610, 0x000 to 0xFFC for the TLV5608, and 0x000 to 0xFF0 for the TLV5629. A power-on-reset initially
puts the internal latches to a defined state (all bits zero).
SERIAL INTERFACE
A falling edge of FS starts shifting the data on DIN starting with the MSB to the internal register on the falling
edges of SCLK. After 16 bits have been transferred, the content of the shift register is moved to one of the DAC
holding registers, depending on the address bits within the data word. A logic 0 on the LDAC pin is required to
transfer the content of the DAC holding register to the DAC latch and to update the DAC outputs. LDAC is an
asynchronous input. It can be held low if a simultaneous update of all eight channels is not needed.
For daisy-chaining, DOUT provides the data sampled on DIN with a delay of 16 clock cycles.
DSP Mode:
SCLK
FS
DIN
X
D15
D14
D1
D0
E15
E14
E1
E0
X
X
X
F15
F15
µC Mode:
SCLK
FS
DIN
X
D15
D14
D1
D0
X
E15
E14
E1
E0
X
X
F15
F15
Figure 13. Data Sampled on DIN
Difference between DSP mode (MODE = N.C. or 0) and µC (MODE = 1) mode:
•
In µC mode, FS needs to be held low until all 16 data bits have been transferred. If FS is driven high before
the 16th falling clock edge, the data transfer is cancelled. The DAC is updated after a rising edge on FS.
•
•
In DSP mode, FS needs to stay low for 20 ns and can go high before the 16th falling clock edge.
In DSP mode there needs to be one falling SCLK edge before FS goes low to start the write (DIN) cycle.
This extra falling SCLK edge has to happen at least 5 ns before FS goes low, tsu(CK-FS) ≥ 5 ns.
•
In µC mode, the extra falling SCLK edge is not necessary. However, if it does happen, the extra negative
SCLK edge is not allowed to occur within 10 ns after FS goes HIGH to finish the WRITE cycle (tsu(FS-C17)).
11
TLV5608
TLV5610
TLV5629
www.ti.com
SLAS268E–MAY 2000–REVISED MARCH 2004
APPLICATION INFORMATION (continued)
SERIAL CLOCK FREQUENCY AND UPDATE RATE
The maximum serial clock frequency is given by:
1
) t
f
+
+ 30 MHz
sclkmax
t
whmin
wlmin
(2)
(3)
The maximum update rate is:
1
f
+
+ 1.95 MHz
updatemax
16 ǒtwhmin
Ǔ
) t
wlmin
Note, that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the
DAC has to be considered also.
DATA FORMAT
The 16-bit data word consists of two parts:
•
•
Address bits (D150D12)
Data bits (D110D0)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A3
A2
A1
A0
DATA
Register Map
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FUNCTION
DAC A
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
CTRL0
CTRL1
Preset
Reserved
DAC A and B
DAC C and D
DAC E and F
DAC G and H
DAC A-H AND TWO-CHANNEL REGISTERS
Writing to DAC A-H sets the output voltage of channel A-H. It is possible to automatically generate the
complement of one channel by writing to one of the four two-channel registers (DAC A and B etc.).
The TLV5610 decodes all 12 data bits. The TLV5608 decodes D11 to D2 (D1 and D0 are ignored). The TLV5629
decodes D11 to D4 (D3 to D0 are ignored).
12
TLV5608
TLV5610
TLV5629
www.ti.com
SLAS268E–MAY 2000–REVISED MARCH 2004
PRESET
The outputs of all DAC channels can be driven to a predefined value stored in the Preset register by driving the
PRE input low. The PRE input is asynchronous to the clock.
CTRL0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
PD
DO
X
X
IM
PD
: Full device power down
: Digital output enable
: Input mode
0 = normal
1 = power down
1 = enable
DO
IM
X
0 = disable
0 = straight binary
1 = twos complement
: Reserved
If DOUT is enabled, the data input on DIN is output on DOUT with a 16-cycle delay. That makes it possible to
daisy-chain multiple DACs on one serial bus.
CTRL1
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
PGH
PEF
PCD
PAB
SGH
SEF
SCD
SAB
PXY
: Power down DACXY 0 = normal
: Speed DACXY 0 = slow
: DAC pair AB, CD, EF, or GH
1 = power down
1 = fast
SXY
XY
In power-down mode, the amplifiers of the selected DAC pair within the device are disabled and the total power
consumption of the device is significantly reduced. Power-down mode of a specific DAC pair can be selected by
setting the PXY bit within the data word to 1.
There are two settling time modes: fast and slow. Fast mode of a DAC pair is selected by setting SXY to 1 and
slow mode is selected by setting SXY to 0.
13
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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