TLV5614CPW [TI]
2.7-V TO 5.5-V 12-BIT 3-mS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN; 2.7 V至5.5 V 12 - BIT 3毫秒翻两番DIGITAL- TO- ANALOG与电源降压转换器
| 型号： | TLV5614CPW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.7-V TO 5.5-V 12-BIT 3-mS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN |
| 文件： | 总27页 (文件大小：369K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
Four 12-Bit D/A Converters
Dual 2.7-V to 5.5-V Supply (Separate Digital
and Analog Supplies)
Programmable Settling Time of Either 3 µs
or 9 µs Typ
Hardware Power Down (10 nA)
Software Power Down (10 nA)
Simultaneous Update
TMS320, (Q)SPI, and Microwire Compatible
Serial Interface
Internal Power-On Reset
applications
Low Power Consumption:
8 mW, Slow Mode – 5-V Supply
3.6 mW, Slow Mode – 3-V Supply
Battery Powered Test Instruments
Digital Offset and Gain Adjustment
Industrial Process Controls
Reference Input Buffer
Voltage Output Range . . . 2× the Reference
Input Voltage
Machine and Motion Control Devices
Communications
Monotonic Over Temperature
Arbitrary Waveform Generation
D OR PW PACKAGE
(TOP VIEW)
description
The TLV5614 is a quadruple 12-bit voltage output
digital-to-analog converter (DAC) with a flexible
4-wire serial interface. The 4-wire serial interface
allows glueless interface to TMS320, SPI, QSPI,
and Microwire serial ports. The TLV5614 is
programmed with a 16-bit serial word comprised
ofaDACaddress, individualDACcontrolbits, and
a 12-bit DAC value. The device has provision for
two supplies: one digital supply for the serial
AV
REFINAB
OUTA
OUTB
OUTC
OUTD
REFINCD
AGND
DV
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DD
DD
PD
LDAC
DIN
SCLK
CS
FS
DGND
interface (via pins DV
and DGND), and one for
DD
the DACs, reference buffers, and output buffers (via pins AV
and AGND). Each supply is independent of the
DD
other, and can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical application where the
DAC will be controlled via a microprocessor operating on a 3 V supply (also used on pins DV and DGND),
DD
with the DACs operating on a 5 V supply. Of course, the digital and anlog supplies can be tied together.
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB
output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode
makes it ideal for single voltage, battery based applications. The settling time of the DAC is programmable to
allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits
within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD
terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow
DACs A and B to have a different reference voltage then DACs C and D.
The TLC5614 is implemented with a CMOS process and is available in a 16-terminal SOIC package. The
TLV5614C is characterized for operation from 0°C to 70°C. The TLV5614I is characterized for operation from
–40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
AVAILABLE OPTIONS
PACKAGE
T
A
SOIC
(D)
TSSOP
(PW)
0°C to 70°C
TLV5614CD
TLV5614ID
TLV5614CPW
TLV5614IPW
–40°C to 85°C
functional block diagram
AV
16
DV
1
DD
DD
15
REFINAB
DAC A
+
_
Power-On
Reset
+
_
14
OUTA
10
12
12-Bit
DAC
Latch
14-Bit
Data
and
2
Control
Register
2-Bit
Control
Data
2
2
14
Serial
4
Power-Down/
Speed Control
DIN
Input
Latch
Register
2
7
DAC Select/
Control
FS
SCLK
CS
5
6
13
12
11
OUTB
OUTC
OUTD
DAC B
Logic
DAC C
DAC D
10
REFINCD
3
2
9
8
PD
AGND
DGND
LDAC
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
Terminal Functions
TERMINAL
NAME NO.
AGND
AV
I/O
DESCRIPTION
9
16
6
Analog ground
Analog supply
DD
CS
I
I
Chip select. This terminal is active low.
Digital ground
DGND
DIN
8
4
Serial data input
DV
1
Digital supply
DD
7
I
I
I
Frame sync input. The falling edge of the frame sync pulse indicates the start of a serial data frame shifted out to
the TLV5614.
FS
2
3
Power down pin. Powers down all DACs (overriding their individual power down settings), and all output stages.
This terminal is active low.
PD
Load DAC. When the LDAC signal is high, no DAC output updates occur when the input digital data is read into
the serial interface. The DAC outputs are only updated when LDAC is low.
LDAC
REFINAB
REFINCD
SCLK
15
10
5
I
Voltage reference input for DACs A and B.
Voltage reference input for DACs C and D.
Serial Clock input
I
I
OUTA
14
13
12
11
O
O
O
O
DACA output
OUTB
DACB output
OUTC
DACC output
OUTD
DACD output
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, (DV , AV
Supply voltage difference, (AV
to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
DD
to DV
)
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –2.8 V to 2.8 V
DD
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DV
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AV
+ 0.3 V
+ 0.3 V
DD
DD
Operating free-air temperature range, T : TLV5614C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
TLV5614I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
recommended operating conditions
MIN NOM
MAX
5.5
UNIT
5-V supply
3-V supply
4.5
2.7
2
5
3
Supply voltage, AV , DV
DD
V
DD
3.3
High-level digital input, V
IH
DV
DV
= 2.7 V to 5.5 V
= 2.7 V to 5.5 V
V
V
DD
DD
Low-level digital input, V
IL
0.8
5-V supply, See Note 1
3-V supply, See Note 1
0
0
2
2.048
1.024
10
V
V
–1.5
–1.5
DD
Reference voltage, V to REFINAB, REFINCD terminal
ref
V
DD
Load resistance, R
kΩ
pF
L
Load capacitance, C
100
20
L
Serial clock rate, SCLK
MHz
TLV5614C
TLV5614I
0
70
Operating free-air temperature
°C
–40
85
NOTE 1: Voltages greater than AV /2 will cause output saturation for large DAC codes.
DD
electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)
static DAC specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
bits
Resolution
12
Integral nonlinearity (INL), end point adjusted
Differential nonlinearity (DNL)
See Note 2
±1.5
±0.5
±4
±1
LSB
See Note 3
See Note 4
See Note 5
LSB
E
E
Zero scale error (offset error at zero scale)
Zero scale error temperature coefficient
±12
mV
ZS
10
ppm/°C
% of FS
voltage
Gain error
See Note 6
See Note 7
±0.6
G
Gain error temperature coefficient
10
–80
–80
ppm/°C
dB
Zero scale
Power supply rejection ratio
Full scale
PSRR
See Notes 8 and 9
dB
NOTES: 2. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
3. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal
1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
4. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
6
5. Zero-scale-error temperature coefficient is given by: E
ZS
TC = [E
(T
) – E
(T
)]/V × 10 /(T
– T
).
min
ZS max
ZS min
ref max
6. Gain error is the deviation from the ideal output (2 V – 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.
ref
6
7. Gain temperature coefficient is given by: E TC = [E (T
) – E (T
)]/V × 10 /(T
– T
).
min
G
G
max
G
min ref max
8. Zero-scale-error rejection ratio (EZS–RR) is measured by varying the AV
proportion of this signal imposed on the zero-code output voltage.
from 5 ± 0.5 V and 3 ± 0.5 V dc, and measuring the
DD
9. Full-scale rejection ratio (EG-RR) is measured by varying the AV
from 5 ± 0.5 V and 3 ± 0.5 V dc and measuring the proportion
DD
of this signal imposed on the full-scale output voltage after subtracting the zero scale change.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted) (continued)
individual DAC output specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
O
Voltage output range
R
R
= 10 kΩ
0
AV –0.4
DD
V
L
L
% of FS
voltage
Output load regulation accuracy
= 2 kΩ vs 10 kΩ
0.1
0.25
reference inputs (REFINAB, REFINCD)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
I
Input voltage range
Input resistance
See Note 10
0
AV –1.5
DD
R
C
10
5
MΩ
pF
I
I
Input capacitance
REFIN = 1 V at 1 kHz + 1.024 V dc
pp
(see Note 11)
Reference feed through
–75
dB
Slow
Fast
0.5
1
Reference input bandwidth
REFIN = 0.2 V + 1.024 V dc large signal
pp
MHz
NOTES: 10. Reference input voltages greater than V /2 will cause output saturation for large DAC codes.
DD
11. Reference feedthrough is measured at the DAC output with an input code = 000 hex and a V
ref (REFINAB or REFINCD)
input = 1.024 Vdc + 1 V at 1 kHz.
pp
digital inputs (DIN, CS, LDAC, PD)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±1
UNIT
µA
I
I
High-level digital input current
Low-level digital input current
Input capacitance
V = V
I
IH
DD
V = 0 V
±1
µA
IL
I
C
3
pF
I
power supply
PARAMETER
TEST CONDITIONS
5-V supply,
No load, Clock running,
MIN
TYP
MAX
UNIT
Slow
Fast
Slow
Fast
1.6
2.4
mA
3.8
1.2
5.6
1.8
4.8
All inputs 0 V or V
DD
I
Power supply current
DD
3-V supply,
mA
nA
No load, Clock running,
All inputs 0 V or DV
3.2
10
DD
Power down supply current (see Figure 12)
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted) (continued)
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
C
= 100 pF,
= 10% to 90%,
= 2.048 V, 1024 V
R
= 10 kΩ,
L
Fast
5
V/µs
L
SR
Output slew rate
V
V
O
Slow
1
V/µs
µs
ref
To ± 0.5 LSB,
= 10 kΩ, See Notes 12 and 14
Fast
Slow
Fast
Slow
3
9
5.5
20
C
= 100 pF,
L
t
t
Output settling time
s
R
L
1
To ± 0.5 LSB,
R
C = 100 pF,
L
Output settling time, code to code
µs
s(c)
= 10 kΩ, See Note 15
2
L
Glitch energy
Code transition from 7FF to 800
10
74
nV-sec
SNR
Signal-to-noise ratio
Sinewave generated by DAC,
Reference voltage = 1.024 at 3 V and 2.048 at 5 V,
f = 400 KSPS,
S/(N+D) Signal to noise + distortion
66
s
dB
f
C
= 1.1 kHz sinewave,
THD
Total harmonic Distortion
–68
OUT
= 100 pF,
R = 10 kΩ,
L
L
SFDR
Spurious free dynamic range
70
BW = 20 kHz
NOTES: 12. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
ofFFF hex to 080 hex for 080 hex to FFF hex.
13. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of one count.
14. Limits are ensured by design and characterization, but are not production tested.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted) (continued)
digital input timing requirements
MIN NOM
MAX
UNIT
ns
t
t
Setup time, CS low before FS↓
10
8
su(CS–FS)
Setup time, FS low before first negative SCLK edge
ns
su(FS–CK)
Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising
edge of FS
t
10
ns
su(C16–FS)
su(C16–CS)
Setuptime,sixteenthpositiveSCLKedge(firstpositiveafterD0issampled)beforeCSrising
edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup
time is between the FS rising edge and CS rising edge.
t
10
ns
t
t
t
Pulse duration, SCLK high
25
25
8
ns
ns
ns
wH
Pulse duration, SCLK low
wL
Setup time, data ready before SCLK falling edge
su(D)
t
Hold time, data held valid after SCLK falling edge
Pulse duration, FS high
5
ns
ns
h(D)
t
20
wH(FS)
PARAMETER MEASUREMENT INFORMATION
t
t
wH
wL
SCLK
DIN
1
2
3
4
5
15
16
t
t
su(D)
h(D)
D14
D15
D13
D12
D1
D0
t
su(FS-CK)
t
su(C16-CS)
t
su(CS-FS)
CS
FS
t
wH(FS)
t
su(C16-FS)
Figure 1. Timing Diagram
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
TYPICAL CHARACTERISTICS
LOAD REGULATION
LOAD REGULATION
0.2
0.18
0.16
0.14
0.12
0.10
0.08
0.35
0.30
0.25
V
= 3 V,
= 1 V,
= Full Scale
V
= 5 V,
= 2 V,
= Full Scale
DD
DD
V
V
ref
V
ref
V
O
O
3 V Slow Mode, Sink
5 V Slow Mode, Sink
5 V Fast Mode, Sink
0.20
3 V Fast Mode, Sink
0.15
0.10
0.06
0.04
0.05
0
0.02
0
0
0.01 0.02 0.05 0.1 0.2 0.5
Load Current – mA
1
2
0
0.02 0.04 0.1 0.2 0.4
Load Current – mA
1
2
4
Figure 2
Figure 3
LOAD REGULATION
LOAD REGULATION
3 V Slow Mode, Source
4.01
2.001
2.001
5 V Slow Mode, Source
5 V Fast Mode, Source
4.005
2.000
2.000
1.999
1.999
1.998
3 V Fast Mode, Source
4
3.995
1.998
1.997
3.99
V
= 5 V,
= 2 V,
= Full Scale
V
V
= 3 V,
= 1 V,
DD
DD
V
ref
ref
V = Full Scale
O
1.997
1.996
V
O
3.985
0
0.02 0.04 0.1 0.2 0.4
1
2
4
0
0.01 0.02 0.05 0.1 0.2 0.5
Load Current – mA
1
2
Load Current – mA
Figure 4
Figure 5
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
TEMPERATURE
TEMPERATURE
4
4
V
= 3 V,
= 1.024 V,
DD
V
ref
Full Scale
3.5
3.5
V
O
Fast Mode
(Worst Case For I
DD
)
Fast Mode
3
3
V
= 5 V,
= 1.024 V,
Full Scale
2.5
DD
2.5
V
ref
V
O
2
2
(Worst Case For I )
DD
1.5
1.5
1
1
Slow Mode
Slow Mode
0.5
0.5
–55 –40 –25
0
25
40 70
85 125
–55 –40 –25
0
25 40
70
85 125
T – Temperature – °C
T – Temperature – °C
Figure 6
Figure 7
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION
vs
vs
FREQUENCY
FREQUENCY
0
0
V
= 1 V dc + 1 V p/p Sinewave,
ref
V
= 1 V dc + 1 V p/p Sinewave,
ref
–10
Output Full Scale
–10
Output Full Scale
–20
–30
–20
–30
––40
––40
–50
–60
–50
–60
Fast Mode
Slow Mode
–70
–80
–70
–80
0
5
10
20
30
50
100
0
5
10
20
30
50
100
f – Frequency – kHz
f – Frequency – kHz
Figure 8
Figure 9
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION AND NOISE
TOTAL HARMONIC DISTORTION AND NOISE
vs
vs
FREQUENCY
FREQUENCY
0
0
V
= 1 V dc + 1 V p/p Sinewave,
V
= 1 V dc + 1 V p/p Sinewave,
ref
Output Full Scale
ref
Output Full Scale
–10
–10
–20
–30
–20
–30
––40
––40
–50
–60
–50
–60
Fast Mode
Slow Mode
–70
–80
–70
–80
0
5
10
20
30
50
100
0
5
10
20
30
50
100
f – Frequency – kHz
f – Frequency – kHz
Figure 10
Figure 11
SUPPLY CURRENT
vs
TIME
(WHEN ENTERING POWER-DOWN MODE)
4000
3500
3000
2500
2000
1500
1000
500
0
0
200
400
600
800
1000
t – Time – ns
Figure 12
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY
0.3
V
CC
= 5 V, V = 2 V, SCLK = 1 MHz)
0.25
0.2
ref
0.15
0.1
0.05
0
–0.05
–0.1
–0.15
–0.2
–0.25
–0.3
0
256 512 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840
Digital Code
Figure 13
INTEGRAL NONLINEARITY
1
V
= 5 V, V = 2 V,
ref
CC
SCLK = 1 MHz
0.5
0
–0.5
–1
–1.5
0
256 512 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840
Digital Code
Figure 14
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
APPLICATION INFORMATION
general function
TheTLV5614isa12-bitsinglesupplyDACbasedonaresistorstringarchitecture. Thedeviceconsistsofaserial
interface, speed and power down control logic, a reference input buffer, a resistor string, and a rail-to-rail output
buffer.
The output voltage (full scale determined by external reference) is given by:
CODE
2 REF
[V]
0x1000
Where REF is the reference voltage and CODE is the digital input value within the range of 0x000 to 0xFFF.
A power-on reset initially resets the internal latches to a defined state (all bits zero).
serial interface
Explanation of data transfer: First, the device has to be enabled with CS set to low. Then, a falling edge of FS
starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK.
After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch which
updates the voltage output to the new level.
The serial interface of the TLV5614 can be used in two basic modes:
four wire (with chip select)
three wire (without chip select)
Using chip select (four wire mode), it is possible to have more than one device connected to the serial port of
the data source (DSP or microcontroller). The interface is compatible with the TMS320 family. Figure 15 shows
an example with two TLV5614s connected directly to a TMS320 DSP.
TLV5614
TLV5614
CS FS DIN SCLK
CS FS DIN SCLK
TMS320
DSP
XF0
XF1
FSX
DX
CLKX
Figure 15. TMS320 Interface
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
APPLICATION INFORMATION
serial interface (continued)
If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows
an example of how to connect the TLV5614 to a TMS320, SPI, or Microwire port using only three pins.
TMS320
DSP
TLV5614
SPI
TLV5614
Microwire
TLV5614
FSX
FS
SS
FS
I/O
FS
DIN
DIN
DIN
DX
MOSI
SCLK
SO
SK
CLKX
SCLK
CS
SCLK
CS
SCLK
CS
Figure 16. Three-Wire Interface
Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling
edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must
be performed to program the TLV5614. After the write operation(s), the DAC output is updated automatically
on the sixteenth positive clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
1
f
20 MHz
SCLKmax
t
t
wH(min)
wL(min)
The maximum update rate is:
1
f
1.25 MHz
UPDATEmax
16
t
t
wH(min)
wL(min)
Note that the maximum update rate is a theoretical value for the serial interface since the settling time of the
TLV5614 has to be considered also.
data format
The 16-bit data word for the TLV5614 consists of two parts:
Control bits
(D15 . . . D12)
(D11 . . . D0)
New DAC value
D15
A1
D14
A0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PWR
SPD
New DAC value (12 bits)
X: don’t care
SPD: Speed control bit.
1 → fast mode
0 → slow mode
PWR: Power control bit. 1 → power down
0 → normal operation
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
APPLICATION INFORMATION
In power down mode, all amplifiers within the TLV5614 are disabled. A particular DAC (A, B, C, D) of the
TLV5614 is selected by A1 and A0 within the input word.
A1
0
A0
0
DAC
A
0
1
B
1
0
C
1
1
D
TLV5614 interfaced to TMS320C203 DSP
hardware interfacing
Figure 17 shows an example of how to connect the TLV5614 to a TMS320C203 DSP. The serial port is
configured in burst mode, with FSX generated by the TMS320C203 to provide the frame sync (FS) input to the
TLV5614. Data is transmitted on the DX line, with the serial clock input on the CLKX line. The general-purpose
input/outputportbitsIO0andIO1areusedtogeneratethechipselect(CS)andDAClatchupdate(LDAC)inputs
to the TLV5614. The active low power down (PD) is pulled high all the time to ensure the DACs are enabled.
TMS320C203
TLV5614
SDIN
SCLK
FS
V
DX
DD
PD
CLKX
FSX
I/O 0
I/O 1
CS
VOUTA
VOUTB
VOUTC
VOUTD
LDAC
REFINAB
REFINCD
REF
V
SS
Figure 17. TLV5614 Interfaced with TMS320C203
software
The application example outputs a differential in-phase (sine) signal between the VOUTA and VOUTB pins, and
it’s quadrature (cosine) signal as the differential signal between VOUTC and VOUTD.
The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine pulses
LDAC low to update all 4 DACs simultaneously, then fetches and writes the next sample to all 4 DACs. The
samples are stored in a look-up table, which describes two full periods of a sine wave.
The synchronous serial port of the DSP is used in burst mode. In this mode, the processor generates an FS
pulse preceding the MSB of every data word. If multiple, contiguous words are transmitted, a violation of the
tsu(C16–FS)timingrequirementwilloccur. Toavoidthis, theprogramwaitsuntilthetransmissionoftheprevious
word has been completed.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
APPLICATION INFORMATION
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Processor: TMS320C203 runnning at 40 MHz
;
; Description:
;
; This program generates a differential in–phase (sine) on (OUTA–OUTB) and it’s
; quadrature (cosine) as a differential signal on (OUTC–OUTD).
;
; The DAC codes for the signal samples are stored as a table of 64 12–bit values,
; describing 2 periods of a sine function. A rolling pointer is used to address the
; table location in the first period of this waveform, from which the DAC A samples
; are read. The samples for the other 3 DACs are read at an offset to this rolling
; pointer:
;
;
;
;
;
;
DAC
A
Function
sine
Offset from rolling pointer
0
B
inverse sine 16
C
D
cosine
inverse cosine24
8
; The on–chip timer is used to generate interrupts at a fixed rate. The interrupt
; service routine first pulses LDAC low to update all DACs simultaneously
; with the values which were written to them in the previous interrupt. Then all
; 4 DAC values are fetched and written out through the synchronous serial interface
; Finally, the rolling pointer is incremented to address the next sample, ready for
; the next interrupt.
;
;
1998, Texas Instruments Inc.
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
;–––––––––––––––––––––––––––––– I/O and memory mapped regs –––––––––––––––––––––––––––––
.include ”regs.asm”
;–––––––jump vectors –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
.ps
b
0h
start
int1
b
b
b
int23
timer_isr;
––––––––––– variables –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
temp
.equ
.equ
.equ
.equ
.equ
.equ
.equ
0060h
0061h
0062h
0063h
0064h
0065h
0066h
r_ptr
iosr_stat
DACa_ptr
DACb_ptr
DACc_ptr
DACd_ptr
;–––––––––––constants––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; DAC control bits to be OR’ed onto data
; all fast mode
DACa_control .equ
DACb_control .equ
DACc_control .equ
DACd_control .equ
01000h
05000h
09000h
0d000h
;––––––––––– tables ––––––––––––––––––––––––––––––––
.ds
sinevals
02000h
.word 00800h
.word 0097Ch
.word 00AE9h
.word 00C3Ah
.word 00D61h
.word 00E53h
.word 00F07h
.word 00F76h
.word 00F9Ch
.word 00F76h
.word 00F07h
.word 00E53h
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
APPLICATION INFORMATION
.word 00D61h
.word 00C3Ah
.word 00AE9h
.word 0097Ch
.word 00800h
.word 00684h
.word 00517h
.word 003C6h
.word 0029Fh
.word 001ADh
.word 000F9h
.word 0008Ah
.word 00064h
.word 0008Ah
.word 000F9h
.word 001ADh
.word 0029Fh
.word 003C6h
.word 00517h
.word 00684h
.word 00800h
.word 0097Ch
.word 00AE9h
.word 00C3Ah
.word 00D61h
.word 00E53h
.word 00F07h
.word 00F76h
.word 00F9Ch
.word 00F76h
.word 00F07h
.word 00E53h
.word 00D61h
.word 00C3Ah
.word 00AE9h
.word 0097Ch
.word 00800h
.word 00684h
.word 00517h
.word 003C6h
.word 0029Fh
.word 001ADh
.word 000F9h
.word 0008Ah
.word 00064h
.word 0008Ah
.word 000F9h
.word 001ADh
.word 0029Fh
.word 003C6h
.word 00517h
.word 00684h
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
APPLICATION INFORMATION
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Main Program
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
.ps
.entry
1000h
start
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; disable interrupts
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
setc
splk
splk
INTM
; disable maskable interrupts
#0ffffh, IFR; clear all interrupts
#0004h, IMR; timer interrupts unmasked
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; set up the timer
; timer period set by values in PRD and TDDR
; period = (CLKOUT1 period) x (1+PRD) x (1+TDDR)
; examples for TMS320C203 with 40MHz main clock
; Timer rate
TDDR
9
9
PRD
24 (18h)
39 (27h)
;
;
80 kHz
50 kHz
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
prd_val.equ
tcr_val.equ
splk
0018h
0029h
#0000h, temp; clear timer
out
temp, TIM
splk
#prd_val, temp; set PRD
out
temp, PRD
splk
#tcr_val, temp; set TDDR, and TRB=1 for auto–reload
temp, TCR
out
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Configure IO0/1 as outputs to be :
; IO0 CS – and set high
; IO1 LDAC
– and set high
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
in
temp, ASPCR; configure as output
lacl
or
temp
#0003h
sacl
out
in
lacl
or
sacl
out
temp
temp, ASPCR
temp, IOSR; set them high
temp
#0003h
temp
temp, IOSR
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; set up serial port for
; SSPCR.TXM=1
; SSPCR.MCM=1
; SSPCR.FSM=1
Transmit mode – generate FSX
Clock mode – internal clock source
Burst mode
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
splk
out
splk
out
#0000Eh, temp
temp, SSPCR; reset transmitter
#0002Eh, temp
temp,SSPCR
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; reset the rolling pointer
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
lacl
sacl
#000h
r_ptr
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; enable interrupts
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
clrc
INTM
; enable maskable interrupts
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; loop forever!
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
APPLICATION INFORMATION
next
idle
b
;wait for interrupt
next
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; all else fails stop here
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
done
b
done
;hang there
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Interrupt Service Routines
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
int1
ret
; do nothing and return
; do nothing and return
int23 ret
timer_isr:
in
iosr_stat, IOSR; store IOSR value into variable space
lacl
and
iosr_stat
#0FFFDh
temp
temp, IOSR
#0002h
temp
temp, IOSR
#0FFFEh
temp
temp, IOSR
r_ptr
; load acc with iosr status
; reset IO1 – LDAC low
sacl
out
;
;
or
; set IO1 – LDAC high
sacl
out
;
;
and
; reset IO0 – CS low
sacl
out
;
;
lacl
add
; load rolling pointer to accumulator
; add pointer to table start
; to get a pointer for next DAC a sample
; add 8 to get to DAC C pointer
#sinevals
DACa_ptr
#08h
sacl
add
sacl
add
DACc_ptr
#08h
; add 8 to get to DAC B pointer
; add 8 to get to DAC D pointer
; set ar0 as current AR
sacl
add
DACb_ptr
#08h
sacl
mar
DACd_ptr
*,ar0
; DAC A
lar
ar0, DACa_ptr; ar0 points to DAC a sample
* ; get DAC a sample into accumulator
lacl
or
#DACa_control; OR in DAC A control bits
sacl
out
temp
;
temp, SDTR
; send data
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; We must wait for transmission to complete before writing next word to the SDTR.;
TLV5614/04 interface does not allow the use of burst mode with the full packet; rate, as
we need a CLKX –ve edge to clock in last bit before FS goes high again,; to allow SPI
compatibility.
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
rpt
nop
#016h
; wait long enough for this configuration
; of MCLK/CLKOUT1 rate
; DAC B
lar
ar0, dacb_ptr; ar0 points to DAC a sample
* ; get DAC a sample into accumulator
lacl
or
#DACb_control; OR in DAC B control bits
sacl
out
rpt
nop
temp
;
temp, SDTR
#016h
; send data
; wait long enough for this configuration
; of MCLK/CLKOUT1 rate
; DAC C
lar
ar0, dacc_ptr; ar0 points to dac a sample
; get DAC a sample into accumulator
#DACc_control; OR in DAC C control bits
temp
temp, SDTR; send data
lacl
or
*
sacl
out
rpt
nop
;
#016h
; wait long enough for this configuration
; of MCLK/CLKOUT1 rate
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
APPLICATION INFORMATION
; DAC D
lar
ar0, dacd_ptr; ar0 points to DAC a sample
lacl
or
*
; get DAC a sample into accumulator
#dacd_control; OR in DAC D control bits
sacl
out
temp
temp, SDTR
;
; send data
lacl
add
r_ptr
#1h
#001Fh
r_ptr
#016h
; load rolling pointer to accumulator
; increment rolling pointer
and
; count 0–31 then wrap back round
; store rolling pointer
sacl
rpt
nop
; wait long enough for this configuration
; of MCLK/CLKOUT1 rate
; now take CS high again
lacl
or
iosr_stat
#0001h
temp
temp, IOSR
intm
; load acc with iosr status
; set IO0 – CS high
sacl
out
clrc
ret
;
;
; re-enable interrupts
; return from interrupt
.end
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
APPLICATION INFORMATION
TLV5614 interfaced to MCS 51 microcontroller
hardware iInterfacing
Figure 18 shows an example of how to connect the TLV5614 to an MCS 51 Microcontroller. The serial DAC
input data and external control signals are sent via I/O Port 3 of the controller. The serial data is sent on the RxD
line, with the serial clock output on the TxD line. Port 3 bits 3, 4, and 5 are configured as outputs to provide the
DAC latch update (LDAC), chip select (CS) and frame sync (FS) signals for the TLV5614. The active low power
down pin (PD) of the TLV5614 is pulled high to ensure that the DACs are enabled.
MCS 51
TLV5614
SDIN
V
DD
PD
RxD
SCLK
TxD
LDAC
CS
P3.3
P3.4
P3.4
VOUTA
VOUTB
VOUTC
VOUTD
FS
REFINAB
REFINCD
REF
V
SS
Figure 18. TLV5614 Interfaced with MCS 51
software
The example is the same as for the TMS320C203 in this datasheet, but adapted for a MCS 51 controller. It
generates a differential in-phase (sine) signal between the VOUTA and VOUTB pins, and it’s quadrature
(cosine) signal as the differential signal between VOUTC and VOUTD.
The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine pulses
LDAC low to update all 4 DACs simultaneously, then fetches and writes the next sample to all 4 DACs. The
samples are stored as a look-up table, which describes one full period of a sine wave.
The serial port of the controller is used in Mode 0, which transmits 8 bits of data on RxD, accompanied by a
synchronous clock on TxD. Two writes concatenated together are required to write a comlpete word to the
TLV5614. The CS and FS signals are provided in the required fashion through control of IO port 3, which has
bit addressable outputs.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
APPLICATION INFORMATION
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Processor: 80C51
;
; Description:
;
; This program generates a differential in-phase
(sine) on (OUTA–OUTB) ; and it’s quadrature (cosine)
as a differential signal on (OUTC–OUTD).
;
;
1998, Texas Instruments Inc.
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
NAME
MAIN
ISR
GENIQ
SEGMENT
SEGMENT
CODE
CODE
CODE
DATA
IDATA
SINTBL SEGMENT
VAR1
SEGMENT
STACK SEGMENT
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Code start at address 0, jump to start
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
CSEG AT
0
LJMP start
; Execution starts at address 0 on power–up.
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Code in the timer0 interrupt vector
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
CSEG AT
0BH
LJMP timer0isr
; Jump vector for timer 0 interrupt is 000Bh
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Global variables need space allocated
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG
VAR1
DS
temp_ptr:
rolling_ptr: DS
1
1
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––;
Interrupt service routine for timer 0 interrupts
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG
timer0isr:
PUSH
ISR
PSW
PUSH
ACC
CLR
INT1
INT1
; pulse LDAC low
SETB
; to latch all 4 previous values at the same time
; 1st thing done in timer isr => fixed period
; set CS low
CLR
T0
; The signal to be output on each DAC is a sine function.
; One cycle of a sine wave is held in a table @ sinevals
; as 32 samples of msb, lsb pairs (64 bytes).
; We have ; one pointer which rolls round this table, rolling_ptr,
; incrementing by 2 bytes (1 sample) on each interrupt (at the end of
; this routine).
; The DAC samples are read at an offset to this rolling pointer:
; DAC Function Offset from rolling_ptr
;
A
B
C
D
sine
0
;
inverse sine 32
;
;
MOV
cosine
inverse cosine48
16
DPTR,#sinevals; set DPTR to the start of the table
; of sine signal values
MOV
R7,rolling_ptr; R7 holds the pointer
;into the sine table
MOV
MOVC
A,R7
A,@A+DPTR
; get DAC A msb
; msb of DAC A is in the ACC
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
APPLICATION INFORMATION
CLR
MOV
T1
SBUF,A
; transmit it – set FS low
; send it out the serial port
INC
R7
; increment the pointer in R7
MOV
A,R7
; to get the next byte from the table
; which is the lsb of this sample, now in ACC
MOVC
A_MSB_TX:
JNB
CLR
MOV
A,@A+DPTR
TI,A_MSB_TX ; wait for transmit to complete
TI
SBUF,A
; clear for new transmit
; and send out the lsb of DAC A
; DAC C next
; DAC C codes should be taken from 16 bytes (8 samples) further on
; in the sine table – this gives a cosine function
MOV
ADD
ANL
MOV
A,R7
; pointer in R7
A,#0FH
; add 15 – already done one INC
; wrap back round to 0 if > 64
; pointer back in R7
A,#03FH
R7,A
MOVC
ORL
A,@A+DPTR
A,#01H
; get DAC C msb from the table
; set control bits to DAC C address
A_LSB_TX:
JNB
TI,A_LSB_TX ; wait for DAC A lsb transmit to complete
SETB
CLRT1
CLR
T1
; toggle FS
TI
; clear for new transmit
MOV
SBUF,A
R7
; and send out the msb of DAC C
; increment the pointer in R7
INC
MOV
A,R7
A,@A+DPTR
; to get the next byte from the table
; which is the lsb of this sample, now in ACC
MOVC
C_MSB_TX:
JNB
TI,C_MSB_TX ; wait for transmit to complete
CLR
MOV
TI
SBUF,A
; clear for new transmit
; and send out the lsb of DAC C
; DAC B next
; DAC B codes should be taken from 16 bytes (8 samples) further on
; in the sine table – this gives an inverted sine function
MOV
ADD
ANL
MOV
A,R7
; pointer in R7
A,#0FH
; add 15 – already done one INC
; wrap back round to 0 if > 64
; pointer back in R7
A,#03FH
R7,A
MOVC
ORL
A,@A+DPTR
A,#02H
; get DAC B msb from the table
; set control bits to DAC B address
C_LSB_TX:
JNB
TI,C_LSB_TX ; wait for DAC C lsb transmit to complete
SETB
CLR
T1
; toggle FS
T1
CLR
MOV
TI
SBUF,A
; clear for new transmit
; and send out the msb of DAC B
; get DAC B LSB
INC
R7
; increment the pointer in R7
; to get the next byte from the table
; which is the lsb of this sample, now in ACC
MOV
A,R7
A,@A+DPTR
MOVC
B_MSB_TX:
JNB
TI,B_MSB_TX ; wait for transmit to complete
CLR
TI
; clear for new transmit
MOV
SBUF,A
; and send out the lsb of DAC B
; DAC D next
; DAC D codes should be taken from 16 bytes (8 samples) further on
; in the sine table – this gives an inverted cosine function
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
APPLICATION INFORMATION
MOV
ADD
ANL
MOV
MOVC
ORL
A,R7
; pointer in R7
A,#0FH
; add 15 – already done one INC
; wrap back round to 0 if > 64
; pointer back in R7
A,#03FH
R7,A
A,@A+DPTR
A,#03H
; get DAC D msb from the table
; set control bits to DAC D address
B_LSB_TX:
JNB
TI,B_LSB_TX ; wait for DAC B lsb transmit to complete
SETB
CLR
T1
T1
; toggle FS
CLR
TI ; clear for new transmit
MOV
SBUF,A
; and send out the msb of DAC D
INC
R7
; increment the pointer in R7
; to get the next byte from the table
; which is the lsb of this sample, now in ACC
MOV
A,R7
MOVC
A,@A+DPTR
D_MSB_TX:
JNB
TI,D_MSB_TX ; wait for transmit to complete
CLR
TI
; clear for new transmit
MOV
SBUF,A
; and send out the lsb of DAC D
; increment the rolling pointer to point to the next sample
; ready for the next interrupt
MOV
ADD
A,rolling_ptr
A,#02H
; add 2 to the rolling pointer
; wrap back round to 0 if > 64
ANL
A,#03FH
MOV
rolling_ptr,A; store in memory again
D_LSB_TX:
JNB
TI,D_LSB_TX ; wait for DAC D lsb transmit to complete
CLR
TI
; clear for next transmit
; FS high
SETB
SETB
POP
POP
RETI
T1
T0
; CS high
ACC
PSW
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Stack needs definition
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG STACK
DS
10h
; 16 Byte Stack!
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Main program code
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG
start:
MAIN
MOV
CLRA
MOV
MOV
MOV
SETB
SETB
SETB
SETB
SETB
MOV
SP,#STACK–1 ; first set Stack Pointer
SCON,A
TMOD,#02H
TH0,#038H
INT1
; set serial port 0 to mode 0
; set timer 0 to mode 2 – auto–reload
; set TH0 for 5kHs interrupts
; set LDAC = 1
T1
; set FS = 1
T0
; set CS = 1
; enable timer 0 interrupts
; enable all interrupts
ET0
EA
rolling_ptr,A; set rolling pointer to 0
SETB
always:
SJMP
RET
TR0
; start timer 0
; while(1) !
always
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Table of 32 sine wave samples used as DAC data
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG
SINTBL
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
APPLICATION INFORMATION
sinevals:
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
01000H
0903EH
05097H
0305CH
0B086H
070CAH
0F0E0H
0F06EH
0F039H
0F06EH
0F0E0H
070CAH
0B086H
0305CH
05097H
0903EH
01000H
06021H
0A0E8H
0C063H
040F9H
080B5H
0009FH
00051H
00026H
00051H
0009FH
080B5H
040F9H
0C063H
0A0E8H
DW 06021H
END
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.010 (0,25)
M
0.014 (0,35)
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–8°
0.044 (1,12)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 – SEPTEMBER 1998
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,30
0,19
0,65
M
0,10
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
0,75
0,50
A
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/E 08/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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Copyright 1999, Texas Instruments Incorporated
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