TLV5617AIDG4 [TI]

2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOGnull;


型号：	TLV5617AIDG4
厂家：	TEXAS INSTRUMENTS
描述：	2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOGnull
文件：	总20页 (文件大小：823K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLV5617A

2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOG

CONVERTER WITH POWER DOWN

SLAS234F – JULY 1999 – REVISED JULY 2002

features

applications

Dual 10-Bit Voltage Output DAC

Digital Servo Control Loops

Digital Offset and Gain Adjustment

Industrial Process Control

Programmable Settling Time

– 3 µs in Fast Mode

– 10 µs in Slow Mode

Machine and Motion Control Devices

Mass Storage Devices

Compatible With TMS320 and SPI Serial

Ports

Differential Nonlinearity <0.1 LSB Typ

Monotonic Over Temperature

D PACKAGE

(TOP VIEW)

Direct Replacement for TLC5617A

DIN

SCLK

OUTB

REF

description

TheTLV5617Aisadual10-bitvoltageoutputDAC

with a flexible 3-wire serial interface. The serial

interface is compatible with TMS320, SPI ,

OUTA

AGND

QSPI , and Microwire

serial ports. It is

programmed with a 16-bit serial string containing

4 control bits and 10 data bits.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class-AB

output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows

the designer to optimize speed versus power dissipation.

Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It

is available in an 8-pin SOIC package in standard commercial and industrial temperature ranges.

AVAILABLE OPTIONS

PACKAGE

SOIC

(D)

0°C to 70°C

TLV5617ACD

TLV5617AID

–40°C to 85°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI and QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor Corporation.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5617A

2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOG

CONVERTER WITH POWER DOWN

SLAS234F – JULY 1999 – REVISED JULY 2002

functional block diagram

REF

AGND

Power and

Speed Control

Power-On

Reset

OUTA

DIN

10-Bit

DAC A

Latch

SCLK

Serial

Interface

and

Buffer

Control

10-Bit

DAC B

Latch

OUTB

Terminal Functions

TERMINAL

I/O/P

DESCRIPTION

NAME

NO.

AGND

Ground

Chip select. Digital input active low, used to enable/disable inputs.

Digital serial data input

DIN

OUTA

OUTB

REF

DAC A analog voltage output

DAC B analog voltage output

Analog reference voltage input

Digital serial clock input

SCLK

Positive power supply

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5617A

2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOG

CONVERTER WITH POWER DOWN

SLAS234F – JULY 1999 – REVISED JULY 2002

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage (V

to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to V

Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to V

+ 0.3 V

Operating free-air temperature range, T : TLV5617AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

TLV5617AI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM

MAX

5.5

3.3

UNIT

= 5 V

= 3 V

4.5

2.7

Supply voltage, V

Power on reset, POR

0.55

= 2.7 V

High-level digital input voltage, V

= 5.5 V

2.4

= 2.7 V

0.6

Low-level digital input voltage, V

= 5.5 V

= 5 V (see Note 1)

= 3 V (see Note 1)

AGND 2.048

AGND 1.024

–1.5

Reference voltage, V to REF terminal

ref

Load resistance, R

kΩ

Load capacitance, C

100

Clock frequency, f

MHz

CLK

TLV5617AC

TLV5617AI

Operating free-air temperature, T

°C

–40

NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (V –0.4 V)/2 causes clipping of the transfer function.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5617A

2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOG

CONVERTER WITH POWER DOWN

SLAS234F – JULY 1999 – REVISED JULY 2002

electrical characteristics over recommended operating conditions (unless otherwise noted)

power supply

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Fast

1.6

2.5

No load, All inputs = AGND or V

DAC latch = 0x800

Power supply current

µA

Slow

0.6

Power down supply current

Power supply rejection ratio

Zero scale, See Note 2

Full scale, See Note 3

–65

PSRR

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying V

and is given by:

PSRR = 20 log [(E (V max) – E (V min)/V max]

ZS DD ZS DD DD

3. Power supply rejection ratio at full scale is measured by varying V

PSRR = 20 log [(E (V max) – E (V min)/V max]

DD DD DD

static DAC specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

bits

Resolution

INL

Integral nonlinearity

See Note 4

See Note 5

See Note 6

See Note 7

±0.7

±0.1

±1

±0.5

±12

LSB

DNL

Differential nonlinearity

LSB

Zero-scale error (offset error at zero scale)

TC Zero-scale-error temperature coefficient

ppm/°C

= 2.7 V to 3.3 V

= 4.5 V to 5.5 V

±0.6

% full

scale V

Gain error

See Note 8

See Note 9

±0.29

Gain-error temperature coefficient

ppm/°C

NOTES: 4. The relative accuracy of integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output

from the line between zero and full scale, excluding the effects of zero-code and full-scale errors.

5. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal

1-LSB amplitude change of any two adjacent codes.

6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

7. Zero-scale-error temperature coefficient is given by: E

TC = [E

ZS max

) – E

)]/2V × 10 /(T

ref max

– T

min

ZS min

8. Gain error is the deviation from the ideal output (2V – 1 LSB) with an output load of 10 kΩ.

ref

= [E (T

9. Gain temperature coefficient is given by: E

) – E (T

)]/2V × 10 /(T – T

max

min

max

min

ref

output specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

–0.4

UNIT

Output voltage range

= 10 kΩ

Output load regulation accuracy

= 4.096 V, 2.048 V,

= 2 kΩ to 10 kΩ

±0.1

% FS

reference input

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input voltage range

Input resistance

DD–1.5

MΩ

Input capacitance

Fast

1.3

525

–80

MHz

kHz

Reference input bandwidth

Reference feedthrough

REF = 0.2 V + 1.024 V dc

Slow

REF = 1 V at 1 kHz + 1.024 V dc (see Note 10)

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5617A

2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOG

CONVERTER WITH POWER DOWN

SLAS234F – JULY 1999 – REVISED JULY 2002

electrical characteristics over recommended operating conditions (unless otherwise noted)

(Continued)

digital inputs

PARAMETER

High-level digital input current

TEST CONDITIONS

V = V

MIN

TYP

MAX

UNIT

µA

Low-level digital input current

Input capacitance

V = 0 V

–1

µA

analog output dynamic performance

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Fast

Slow

Fast

Slow

Fast

Slow

Output settling time, full scale

Output settling time, code to code

Slew rate

= 10 kΩ,

= 100 pF, See Note 11

= 100 pF, See Note 12

= 100 pF, See Note 13

µs

s(FS)

µs

s(CC)

V/µs

0.5

Glitch energy

DIN = 0 to 1,

FCLK = 100 kHz, CS = V

nV–s

SNR

Signal-to-noise ratio

–62

SINAD

THD

Signal-to-noise + distortion

Total harmonic distortion

Spurious free dynamic range

f = 102 kSPS,

f = 1 kHz, R = 10 kΩ,

out L

= 100 pF

SFDR

NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change

of 0x020 to 0xFDC and 0xFDC to 0x020 respectively. Not tested, assured by design.

12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change

of one count. Not tested, assured by design.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% of full-scale voltage.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5617A

2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOG

CONVERTER WITH POWER DOWN

SLAS234F – JULY 1999 – REVISED JULY 2002

digital input timing requirements

MIN NOM

MAX

UNIT

= 2.7 V to 3.3 V

= 4.5 V to 5.5 V

Setup time, CS low before first negative SCLK edge

su(CS–CK)

Setup time, 16 negative SCLK edge before CS rising edge

su(C16-CS)

SCLK pulse width high

SCLK pulse width low

= 2.7 V to 3.3 V

= 4.5 V to 5.5 V

= 2.7 V to 3.3 V

Setup time, data ready before SCLK falling edge

Hold time, data held valid after SCLK falling edge

su(D)

h(D)

= 4.5 V to 5.5 V

timing requirements

SCLK

DIN

su(D) h(D)

D15

D14

D13

D12

su(C16-CS)

su(CS-CK)

Figure 1. Timing Diagram

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5617A

2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOG

CONVERTER WITH POWER DOWN

SLAS234F – JULY 1999 – REVISED JULY 2002

TYPICAL CHARACTERISTICS

OUTPUT VOLTAGE

LOAD CURRENT

2.050

2.048

2.046

2.044

2.042

2.040

2.038

2.036

4.105

4.100

4.095

4.090

4.085

4.080

4.075

4.070

3-V Slow Mode, SOURCE

=3 V

REF

=5 V

=1 V

=2 V

REF

5-V Slow Mode, SOURCE

Full scale

3-V Fast Mode, SOURCE

5-V Fast Mode, SOURCE

0 –0.01 –0.02 –0.5 –0.1 –0.2 –0.5 –0.8 –1

–2

0 –0.02 –0.04 –0.1 –0.2 –0.4 –0.8 –1

Load Current – mA

–2

–4

Load Current – mA

Figure 2

Figure 3

OUTPUT VOLTAGE

LOAD CURRENT

OUTPUT VOLTAGE

LOAD CURRENT

0.20

0.18

0.16

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0.00

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

=3 V

REF

=5 V

REF

=1 V

=2 V

Zero scale

3-V Slow Mode, SINK

5-V Slow Mode, SINK

5-V Fast Mode, SINK

3-V Fast Mode, SINK

0.01 0.02 0.05 0.1 0.2 0.5 0.8

0.02 0.04 0.1 0.2 0.4 0.8

Load Current – mA

Figure 4

Figure 5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5617A

2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOG

CONVERTER WITH POWER DOWN

SLAS234F – JULY 1999 – REVISED JULY 2002

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

FREE-AIR TEMPERATURE

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

=3 V

REF

=1 V

Full scale

Fast Mode

=5 V

REF

=2 V

Full scale

Slow Mode

–40 –20

100 120

–40 –20

100 120

- Free-Air Temperature - C

Figure 6

Figure 7

TOTAL HARMONIC DISTORTION

FREQUENCY

= 1 V + 1 V

Sinewave,

= 1 V + 1 V

Sinewave,

P/P

REF

P/P

REF

Output Full Scale

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10

Output Full Scale

–20

–30

–40

–50

–60

–70

–80

–90

3-V Slow Mode

3-V Fast Mode

5 V Slow Mode

5 V Fast Mode

100

f – Frequency – kHz

Figure 8

Figure 9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5617A

2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOG

CONVERTER WITH POWER DOWN

SLAS234F – JULY 1999 – REVISED JULY 2002

TYPICAL CHARACTERISTICS

INTEGRAL NONLINEARITY ERROR

DIGITAL CODE

0.75

0.5

0.25

–0.25

–0.5

–0.75

–1

128

256

384

512

640

768

896

1024

Digital Code

Figure 10

DIFFERENTIAL NONLINEARITY ERROR

DIGITAL CODE

0.2

0.15

0.1

0.05

–0.05

–0.1

–0.15

–0.2

128

256

384

512

640

768

896

1024

Digital Code

Figure 11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5617A

2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOG

CONVERTER WITH POWER DOWN

SLAS234F – JULY 1999 – REVISED JULY 2002

APPLICATION INFORMATION

general function

The TLV5617A is a dual 10-bit, single-supply DAC, based on a resistor-string architecture. It consists of a serial

interface, speed and power-down control logic, a resistor string, and a rail-to-rail output buffer.

The output voltage (full scale determined by the reference) is given by:

CODE

2 REF

[V]

Where REF is the reference voltage and CODE is the digital input value within the range of 0 to 2 –1, where

n=10 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data

format section. A power-on reset initially resets the internal latches to a defined state (all bits zero).

serial interface

A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling

edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the

target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.

Figure 12 shows examples of how to connect the TLV5617A to TMS320, SPI, and Microwire.

TMS320

DSP

TLV5617A

DIN

SPI

TLV5617A

DIN

Microwire

I/O

TLV5617A

DIN

FSX

I/O

MOSI

SCK

CLKX

SCLK

Figure 12. Three-Wire Interface

Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling

edge on the pin connected to CS. If the word width is 8 bits (SPI and Microwire) two write operations must be

performed to program the TLV5617A. After the write operation(s), the holding registers or the control register

of the DAC update automatically on the rising CS edge, ending the write cycle to the DAC. Note: After transfer

oftheLSBduringadataorcontrolwritecycle, oneadditionalrisingedgeonSCLKisrequiredtoresettheinternal

state machine. This edge can occur when CS is high or low, but must occur before the next falling CS edge that

begins the following write cycle. Refer to the timing diagram for more information.

serial clock frequency and update rate

The maximum serial clock frequency is given by:

+ 20 MHz

sclkmax

) t

whmin

wlmin

The maximum update rate is:

+ 1.25 MHz

updatemax

₁₆ǒ_t

wlmin

) t

whmin

Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the

TLV5617A should also be considered.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5617A

2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOG

CONVERTER WITH POWER DOWN

SLAS234F – JULY 1999 – REVISED JULY 2002

APPLICATION INFORMATION

data format

The 16-bit data word for the TLV5617A consists of two parts:

Program bits

New data

(D15..D12)

(D11..D0)

D15

D14

D13

D12

D11

D10

SPD

PWR

MSB

10 Data bits

LSB

SPD: Speed control bit

PWR: Power control bit

1 → fast mode

1 → power down

0 → slow mode

0 → normal operation

On power up, SPD and PWD are reset to 0 (slow mode and normal operation)

The following table lists all possible combinations of register-select bits:

Write data to DAC B and BUFFER

Write data to BUFFER

Write data to DAC A and update DAC B with BUFFER content

Reserved

The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected,

then the 12 data bits determine the new DAC value:

examples of operation

Set DAC A output, select fast mode:

Write new DAC A value and update DAC A output:

D15

D14

D13

D12

D11

D10

New DAC A output value

The DAC A output is updated on the rising clock edge after D0 is sampled.

Set DAC B output, select fast mode:

Write new DAC B value to BUFFER and update DAC B output:

D15

D14

D13

D12

D11

D10

New BUFFER content and DAC B output value

The DAC A output is updated on the rising clock edge after D0 is sampled.

Set DAC A value, set DAC B value, update both simultaneously, select slow mode:

1. Write data for DAC B to BUFFER:

D15

D14

D13

D12

D11

D10

New DAC B value

2. Write new DAC A value and update DAC A and B simultaneously:

D15

D14

D13

D12

D11

D10

New DAC A value

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5617A

2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOG

CONVERTER WITH POWER DOWN

SLAS234F – JULY 1999 – REVISED JULY 2002

APPLICATION INFORMATION

examples of operation (continued)

Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled.

Set powerdown mode:

D15

D14

D13

D12

D11

D10

X = Don’t care

linearity, offset, and gain error using single ended supplies

When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With

a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage

may not change with the first code, depending on the magnitude of the offset voltage.

The output amplifier attempts to drive the output to a negative voltage. However, because the most negative

supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.

The output voltage then remains at zero until the input code value produces a sufficient positive output voltage

to overcome the negative offset voltage, resulting in the transfer function shown in Figure 13.

Output

Voltage

0 V

DAC Code

Negative

Offset

Figure 13. Effect of Negative Offset (Single Supply)

This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the

dotted line if the output buffer could drive below the ground rail.

For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after

offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not

allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity

is measured between full-scale code and the lowest code that produces a positive output voltage.

definitions of specifications and terminology

integral nonlinearity (INL)

The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum

deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale

errors.

differential nonlinearity (DNL)

The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the

measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage

changes in the same direction (or remains constant) as a change in the digital input code.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5617A

2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOG

CONVERTER WITH POWER DOWN

SLAS234F – JULY 1999 – REVISED JULY 2002

definitions of specifications and terminology (continued)

zero-scale error (E

)

Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.

gain error (E )

Gain error is the error in slope of the DAC transfer function.

total harmonic distortion (THD)

THD is the ratio of the rms value of the first six harmonic components to the value of the fundamental signal.

The value for THD is expressed in decibels.

signal-to-noise ratio + distortion (S/N+D)

S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below

the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.

spurious free dynamic range (SFDR)

Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of

the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

22-Jun-2013

PACKAGING INFORMATION

Orderable Device

TLV5617ACD

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

0 to 70

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

TV5617

TLV5617ACDG4

TLV5617ACDR

TLV5617ACDRG4

TLV5617AID

ACTIVE

2500

Green (RoHS

& no Sb/Br)

0 to 70

TV5617

TY5617

Green (RoHS

& no Sb/Br)

0 to 70

Green (RoHS

& no Sb/Br)

0 to 70

Green (RoHS

& no Sb/Br)

-40 to 85

TLV5617AIDG4

TLV5617AIDR

Green (RoHS

& no Sb/Br)

2500

Green (RoHS

& no Sb/Br)

TLV5617AIDRG4

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

22-Jun-2013

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV5617AIDR

SOIC

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

TLV5617AIDR

2500

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

Medical

Logic

Security

www.ti.com/security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense

Video and Imaging

www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TLV5617AIDG4 [TI]

相关型号：

TLV5617AIDR

TLV5617AIDRG4

TLV5618A

TLV5618A-EP

TLV5618ACD

TLV5618ACDG4

TLV5618ACDR

TLV5618ACDRG4

TLV5618ACP

TLV5618ACPE4

TLV5618AD

TLV5618AFK