TLV5620I [TI]
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS; 翻两番8位数字 - 模拟转换器
| 型号： | TLV5620I |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS |
| 文件： | 总14页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV5620C, TLV5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B – JANUARY 1995 – REVISED APRIL 1997
D OR N PACKAGE
(TOP VIEW)
Four 8-Bit Voltage Output DACs
3-V Single-Supply Operation
Serial Interface
GND
REFA
REFB
REFC
REFD
DATA
CLK
V
1
2
3
4
5
6
7
14
13
12
11
10
9
DD
High-Impedance Reference Inputs
LDAC
DACA
DACB
DACC
DACD
LOAD
Programmable for 1 or 2 Times Output
Range
Simultaneous Update Facility
Internal Power-On Reset
Low-Power Consumption
Half-Buffered Output
8
applications
Programmable Voltage Sources
Digitally Controlled Amplifiers/Attenuators
Mobile Communications
Automatic Test Equipment
Process Monitoring and Control
Signal Synthesis
description
The TLV5620C and TLV5620I are quadruple 8-bit voltage output digital-to-analog converters (DACs) with
buffered reference inputs (high impedance). The DACs produce an output voltage that ranges between either
one or two times the reference voltages and GND; and, the DACs are monotonic. The device is simple to use,
because it runs from a single supply of 3 V to 3.6 V. A power-on reset function is incorporated to ensure
repeatable start-up conditions.
Digital control of the TLV5620C and TLV5620I is over a simple three-wire serial bus that is CMOS compatible
and easily interfaced to all popular microprocessor and microcontroller devices. The 11-bit command word
comprises eight bits of data, two DAC select bits, and a range bit, the latter allowing selection between the times
1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be
written to the device, then all DAC outputs update simultaneously through control of LDAC. The digital inputs
feature Schmitt triggers for high noise immunity.
The 14-terminal small-outline (SO) package allows digital control of analog functions in space-critical
applications. The TLV5620C is characterized for operation from 0°C to 70°C. The TLV5620I is characterized
for operation from –40°C to 85°C. The TLV5620C and TLV5620I do not require external trimming.
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE
(D)
PLASTIC DIP
(N)
T
A
0°C to 70°C
TLV5620CD
TLV5620ID
TLV5620CN
TLV5620IN
–40°C to 85°C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5620C, TLV5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B – JANUARY 1995 – REVISED APRIL 1997
functional block diagram
2
REFA
+
–
12
DAC
DAC
DAC
DAC
+
–
DACA
DACB
DACC
DACD
× 2
× 2
× 2
× 2
8
8
8
8
8
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
3
REFB
+
–
11
10
9
+
–
8
8
4
5
REFC
REFD
+
–
+
–
+
–
+
–
8
7
6
8
CLK
DATA
LOAD
Power-On
Reset
Serial
Interface
13
LDAC
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
CLK
NO.
7
I
Serialinterface clock. The input digital data is shifted into the serial interface register on the falling edge of the clock
applied to the CLK terminal.
DACA
DACB
DACC
DACD
DATA
12
11
10
9
O
O
O
O
I
DAC A analog output
DAC B analog output
DAC C analog output
DAC D analog output
6
Serial interface digital data input. The digital code for the DAC is clocked into the serial interface register serially.
Each data bit is clocked into the register on the falling edge of the clock signal.
GND
1
I
I
Ground return and reference terminal
LDAC
13
Load DAC. When this signal is high, no DAC output updates occur when the input digital data is read into the serial
interface. The DAC outputs are only updated when LDAC is taken from high to low.
LOAD
8
I
Serial interface load control. When the LDAC terminal is low, the falling edge of the LOAD signal latches the digital
data into the output latch and immediately produces the analog voltage at the DAC output terminal.
REFA
REFB
REFC
REFD
2
3
4
5
I
I
I
I
Reference voltage input to DAC A. This voltage defines the output analog range.
Reference voltage input to DAC B. This voltage defines the analog output range.
Reference voltage input to DAC C. This voltage defines the analog output range.
Reference voltage input to DAC D. This voltage defines the analog output range.
V
DD
14
I
Positive supply voltage
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5620C, TLV5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B – JANUARY 1995 – REVISED APRIL 1997
detailed description
The TLV5620 is implemented using four resistor-string DACs. The core of each DAC is a single resistor with
256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected
to GND and the other end is fed from the output of the reference input buffer. Monotonicity is maintained by use
of the resistor strings. Linearity depends upon the matching of the resistor segments and upon the performance
of the output buffer. Since the inputs are buffered, the DACs always presents a high-impedance load to the
reference source.
Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times 1 or
times 2 gain.
On power up, the DACs are reset to CODE 0.
Each output voltage is given by:
CODE
V (DACA|B|C|D)
REF
(1 RNG bit value)
O
256
where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial control word.
Table 1. Ideal Output Transfer
D7
0
0
•
D6
0
0
•
D5
0
0
•
D4
0
0
•
D3
0
0
•
D2
0
0
•
D1
0
0
•
D0
0
1
•
OUTPUT VOLTAGE
GND
(1/256) × REF (1+RNG)
•
•
•
•
•
•
•
•
•
•
0
1
•
1
0
•
1
0
•
1
0
•
1
0
•
1
0
•
1
0
•
1
0
•
(127/256) × REF (1+RNG)
(128/256) × REF (1+RNG)
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
(255/256) × REF (1+RNG)
data interface
With LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have
been clocked in, LOAD is pulsed low to transfer the data from the serial input register to the selected DAC as
shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated when LOAD goes low. When
LDAC is high during serial programming, the new value is stored within the device and can be transferred to
the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered MSB first. Data
transfers using two 8-clock-cycle periods are shown in Figures 3 and 4.
Table 2 lists the A1 and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC output
range. When RNG = low, the output range is between the applied reference voltage and GND, and when
RNG = high, the range is between twice the applied reference voltage and GND.
Table 2. Serial Input Decode
A1
0
A0
0
DAC UPDATED
DACA
0
1
DACB
1
0
DACC
1
1
DACD
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5620C, TLV5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B – JANUARY 1995 – REVISED APRIL 1997
CLK
t
su(DATA-CLK)
t
su(LOAD-CLK)
D2 D1
su(CLK-LOAD)
t
v(DATA-CLK)
DATA
LOAD
A1
A0 RNG
D7
D6
D5
D4
D3
D0
t
t
w(LOAD)
DAC Update
Figure 1. LOAD-Controlled Update (LDAC = Low)
CLK
t
su(DATA-CLK)
t
v(DATA-CLK)
DATA
A1
A0 RNG
D7
D6
D5
D4
D3
D2
D1
D0
t
su(LOAD-LDAC)
LOAD
LDAC
t
w(LDAC)
DAC Update
Figure 2. LDAC-Controlled Update
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CLK Low
CLK
A1
A0
RNG
D7
D6
D5
D4
D3
D2
D1
D0
DATA
LOAD
LDAC
Figure 3. Load Controlled Update Using 8-Bit Serial Word (LDAC = Low)
CLK Low
CLK
A1
A0
RNG
D7
D6
D5
D4
D3
D2
D1
D0
DATA
LOAD
LDAC
Figure 4. LDAC Controlled Update Using 8-Bit Serial Word
TLV5620C, TLV5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B – JANUARY 1995 – REVISED APRIL 1997
linearity, offset, and gain error using single-end supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset voltage, the output voltage changes on the first code change. With a negative offset the output
voltage may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier, therefore, attempts to drive the output to a negative voltage. However, because the most
negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage remains at zero until the input code value produces a sufficient positive output voltage to
overcome the negative offset voltage, resulting in the transfer function shown in Figure 5.
Output
Voltage
0 V
DAC Code
Negative
Offset
Figure 5. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below ground.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single-supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full-scale code and the lowest code that produces a positive output voltage. The code is
calculated from the maximum specification for the negative offset.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5620C, TLV5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B – JANUARY 1995 – REVISED APRIL 1997
equivalent inputs and outputs
INPUT CIRCUIT
OUTPUT CIRCUIT
V
DD
V
DD
_
Input from
Decoded DAC
Register String
+
DAC
Voltage Output
V
Input
ref
× 1
× 2
84 kΩ
84 kΩ
Output
Range
Select
To DAC
Resistor
String
I
SINK
60 µA
Typical
GND
GND
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (V
– GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND – 0.3 V to V
Reference input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND – 0.3 V to V
Operating free-air temperature range, T : TLV5620C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
+ 0.3 V
+ 0.3 V
DD
DD
ID
A
TLV5620I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
NOM
MAX
UNIT
V
Supply voltage, V
DD
2.7
3.3
5.25
High-level input voltage, V
IH
0.8 V
V
DD
Low-level input voltage, V
0.8
V
IL
Reference voltage, V [A|B|C|D], x1 gain
V
–1.5
V
ref
DD
Load resistance, R
10
kΩ
ns
ns
L
Setup time, data input, t
(see Figures 1 and 2)
50
50
su(DATA-CLK)
Valid time, data input valid after CLK↓, t
(see Figures 1 and 2)
v(DATA-CLK)
Setup time, CLK eleventh falling edge to LOAD, t
(see Figure 1)
50
ns
ns
su(CLK-LOAD)
(see Figure 1)
Setup time, LOAD↑ to CLK↓, t
50
su(LOAD-CLK)
Pulse duration, LOAD, t
Pulse duration, LDAC, t
(see Figure 1)
(see Figure 2)
250
250
0
ns
w(LOAD)
w(LDAC)
ns
Setup time, LOAD↑ to LDAC↓, t
(see Figure 2)
ns
su(LOAD-LDAC)
CLK frequency
1
70
85
MHz
TLV5620C
TLV5620I
0
Operating free-air temperature, T
°C
A
–40
7
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TLV5620C, TLV5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B – JANUARY 1995 – REVISED APRIL 1997
electrical characteristics over recommended operating free-air temperature range,
V
= 3 V to 3.6 V, V = 2 V, × 1 gain output range (unless otherwise noted)
DD
ref
PARAMETER
High-level input current
Low-level input current
Output sink current
TEST CONDITIONS
MIN
TYP
MAX
±10
±10
UNIT
µA
I
I
I
I
V = V
I
IH
DD
V = 0 V
µA
IL
I
20
1
µA
O(sink)
O(source)
Each DAC output
Output source current
mA
Input capacitance
15
15
C
pF
i
Reference input capacitance
Supply current
I
I
V
V
= 3.3 V
= 3.3 V,
2
±10
±1
mA
µA
DD
DD
Reference input current
Linearity error (end point corrected)
Differential linearity error
Zero-scale error
V
ref
= 1.5 V
ref
DD
E
E
E
V
ref
= 1.25 V, × 2 gain, See Note 1
= 1.25 V, × 2 gain, See Note 2
= 1.25 V, × 2 gain, See Note 3
= 1.25 V, × 2 gain, See Note 4
= 1.25 V, × 2 gain, See Note 5
= 1.25 V, × 2 gain, See Note 6
LSB
LSB
mV
L
V
ref
±0.9
30
D
V
ref
0
ZS
Zero-scale error temperature coefficient
Full-scale error
V
ref
10
µV/°C
mV
E
FS
V
ref
±60
Full-scale error temperature coefficient
Power-supply sensitivity
V
±25
µV/°C
mV/V
ref
See Notes 7 and 8
PSRR
0.5
NOTES: 1. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects
of zero code and full-scale errors).
2. Differentialnonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes.
Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
6
4. Zero-scale error temperature coefficient is given by: ZSETC = [ZSE(T
) – ZSE(T
)]/V × 10 /(T
– T
).
min
max
min ref max
5. Full-scale error is the deviation from the ideal full-scale output (V – 1 LSB) with an output load of 10 kΩ.
ref
6
6. Full-scale error temperature coefficient is given by: FSETC = [FSE(T
7. Zero-scale error rejection ratio (ZSE-RR) is measured by varying the V
of this signal on the zero-code output voltage.
) – FSE (T
)]/V × 10 /(T
ref max
– T
).
min
max
min
voltage from 4.5 V to 5.5 V dc and measuring the effect
DD
8. Full-scale error rejection ratio (FSE-RR) is measured by varing the V
this signal on the full-scale output voltage.
voltage from 3 V to 3.6 V dc and measuring the effect of
DD
operating characteristics over recommended operating free-air temperature range,
= 3 V to 3.6 V, V = 2 V, × 1 gain output range (unless otherwise noted)
V
DD
ref
TEST CONDITIONS
MIN
TYP
1
MAX
UNIT
V/µs
µs
Output slew rate
C
= 100 pF
R
C
= 10 kΩ
L
L
L
Output settling time
To ±0.5 LSB,
= 100 pF,
R
= 10 kΩ, See Note 9
10
L
Large-signal bandwidth
Digital crosstalk
Measured at –3 dB point
100
–50
–60
–60
100
kHz
dB
CLK = 1-MHz square wave measured at DACA-DACD
Reference feedthrough
Channel-to-channel isolation
Reference input bandwidth
See Note 10
See Note 11
See Note 12
dB
dB
kHz
NOTES: 9. Settling time is the time between a LOAD falling edge and the DAC output reaching full-scale voltage within ± 0.5 LSB starting from
an initial output voltage equal to zero.
10. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a V input = 1 V dc + 1 V
ref PP
at 10 kHz.
11. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex
with V input = 1 V dc + 1 V at 10 kHz.
ref
PP
12. Reference bandwidth is the –3 dB bandwidth with an input at V = 1.25 V dc + 2 V
and with a digital input code of full-scale.
ref
PP
8
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TLV5620C, TLV5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B – JANUARY 1995 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
TLV5620
DACA
DACB
DACC
DACD
10 kΩ
C
= 100 pF
L
Figure 6. Slew, Settling Time, and Linearity Measurements
TYPICAL CHARACTERISTICS
POSITIVE RISE TIME AND SETTLING TIME
NEGATIVE FALL TIME AND SETTLING TIME
3
2.5
2
3
2.5
2
V
T
A
= 3 V
DD
= 25°C
Code FF to
00 Hex
Range = ×2
1.5
1
1.5
1
V
= 1.25 V
ref
V
= 3 V
DD
= 25°C
(see Note A)
T
A
0.5
0.5
Code 00 to
FF Hex
Range = ×2
0
0
V
ref
= 1.25 V
(see Note A)
–0.5
–0.5
–1
–1
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
Time – µs
Time – µs
NOTE A: Fall time = 4.25 µs, negative slew rate = 0.46 V/µs, settling
time = 8.5 µs.
NOTE A: Risetime=2.05µs, positiveslewrate=0.96V/µs,settling
time = 4.5 µs.
Figure 7
Figure 8
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5620C, TLV5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B – JANUARY 1995 – REVISED APRIL 1997
TYPICAL CHARACTERISTICS
DAC OUTPUT VOLTAGE
vs
DAC OUTPUT VOLTAGE
vs
OUTPUT LOAD
OUTPUT LOAD
1.6
3
2.8
2.6
2.4
2.2
2
1.4
1.2
1
0.8
0.6
0.4
1.8
1.6
V
V
= 3 V,
= 1.5 V,
DD
ref
V
= 3 V,
= 1.5 V,
1.4
1.2
1
DD
Range = 2x
V
ref
0.2
0
Range = 1x
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
R
– Output Load – kΩ
R
– Output Load – kΩ
L
L
Figure 9
Figure 10
SUPPLY CURRENT
vs
TEMPERATURE
1.2
1.15
1.1
Range = ×2
Input Code = 255
V
V
= 3 V
= 1.25 V
DD
ref
1.05
1
0.95
0.9
0.85
0.8
–50
0
50
100
t – Temperature – °C
Figure 11
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5620C, TLV5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B – JANUARY 1995 – REVISED APRIL 1997
APPLICATION INFORMATION
_
+
TLV5620
V
O
DACA
DACB
DACC
DACD
R
NOTE A: Resistor R
10 kΩ
Figure 12. Output Buffering Scheme
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5620C, TLV5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B – JANUARY 1995 – REVISED APRIL 1997
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
0.020 (0,51)
8
14
16
DIM
0.010 (0,25)
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
M
0.014 (0,35)
A MAX
14
8
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
7
A
0.010 (0,25)
0°–8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
4040047/B 10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Four center pins are connected to die mount pad
E. Falls within JEDEC MS-012
12
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TLV5620C, TLV5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS110B – JANUARY 1995 – REVISED APRIL 1997
MECHANICAL DATA
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
A
PINS **
14
16
18
20
16
9
DIM
0.775
0.775
0.920
0.975
A MAX
(19,69) (19,69) (23.37) (24,77)
0.260 (6,60)
0.240 (6,10)
0.745
0.745
0.850
0.940
A MIN
(18,92) (18,92) (21.59) (23,88)
1
8
0.070 (1,78) MAX
0.020 (0,51) MIN
0.310 (7,87)
0.290 (7,37)
0.035 (0,89) MAX
0.200 (5,08) MAX
0.125 (3,18) MIN
Seating Plane
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
14 Pin Only
4040049/C 7/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001)
13
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