TLV5626_技术文档

TLV5626

2.7 V TO 5.5 V LOW POWER DUAL 8-BIT DIGITAL-TO-ANALOG

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D PACKAGE

(TOP VIEW)

features

Dual 8-Bit Voltage Output DAC

DIN

SCLK

CS

V

DD

OUTB

REF

1

2

3

4

8

7

6

5

Programmable Internal Reference

Programmable Settling Time:

0.8 µs in Fast Mode ,

OUTA

AGND

2.8 µs in Slow Mode

Compatible With TMS320 and SPI Serial

Ports

Differential Nonlinearity <0.1 LSB Typ

Monotonic Over Temperature

applications

Digital Servo Control Loops

Digital Offset and Gain Adjustment

Industrial Process Control

Machine and Motion Control Devices

Mass Storage Devices

description

The TLV5626 is a dual 8-bit voltage output DAC with a flexible 3-wire serial interface.The serial interface allows

glueless interface to TMS320 and SPI , QSPI , and Microwire serial ports. It is programmed with a 16-bit

serial string containing 2 control and 8 data bits.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB

output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows

the designer to optimize speed versus power dissipation. With its on-chip programmable precision voltage

reference, the TLV5626 simplifies overall system design.

Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented

with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in

an 8-pin SOIC package to reduce board space in standard commercial and industrial temperature ranges.

AVAILABLE OPTIONS

PACKAGE

T

A

SOIC

(D)

0°C to 70°C

TLV5626CD

TLV5626ID

–40°C to 85°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI and QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor Corporation.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

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functional block diagram

REF

AGND

V

DD

PGA With

Output Enable

Voltage

Bandgap

Power

and Speed

Control

Power-On

Reset

2

2-Bit

Control

Latch

x2

OUTA

DIN

8-Bit

DAC A

Latch

8

SCLK

CS

Serial

Interface

and

8

Buffer

Control

8

8-Bit

DAC B

Latch

x2

OUTB

Terminal Functions

TERMINAL

I/O/P

DESCRIPTION

NAME

NO.

5

AGND

CS

P

I

Ground

3

Chip select. Digital input active low, used to enable/disable inputs

Digital serial data input

DIN

1

I

OUTA

OUTB

REF

4

I

DAC A analog voltage output

7

O

I/O

I

DAC B analog voltage output

6

Analog reference voltage input/output

Digital serial clock input

SCLK

2

V

DD

8

P

Positive power supply

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†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage (V

to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

DD

Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to V

Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to V

+ 0.3 V

DD

Operating free-air temperature range, T : TLV5626C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A

TLV5626I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN

4.5

2.7

0.55

2

NOM

MAX

5.5

3.3

2

UNIT

V

= 5 V

= 3 V

5

3

DD

Supply voltage, V

DD

V

DD

Power on threshold voltage, POR

High-level digital input voltage, V

V

DD

V

DD

V

DD

V

DD

= 2.7 V to 5.5 V

= 5 V (see Note 1)

= 3 V (see Note 1)

V

IH

Low-level digital input voltage, V

0.8

V

IL

Reference voltage, V to REF terminal

ref

Reference voltage, V to REF terminal

AGND

2

2.048

1.024

V

–1.5

V

DD

V

ref

DD

Load resistance, R

kΩ

pF

MHz

L

Load capacitance, C

100

20

L

Clock frequency, f

CLK

TLV5626C

TLV5626I

0

70

Operating free-air temperature, T

°C

A

–40

85

NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (V

– 0.4 V)/2 causes clipping of the transfer function. The output buffer of the

DD

internal reference must be disabled, if an external reference is used.

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electrical characteristics over recommended operating conditions (unless otherwise noted)

power supply

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Fast

4.2

5

mA

V

= 5 V,

DD

Int. ref.

Slow

Fast

2

2.5

4.6

mA

3.7

V

= 3 V,

DD

Int. ref.

No load,

Slow

Fast

1.7

3.8

2.2

4.6

mA

All inputs = AGND or V

DAC latch = 0x800

,

I

Power supply current

DD

V

= 5 V,

DD

Ext. ref.

Slow

Fast

1.7

3.4

2.1

4.2

mA

V

= 3 V,

DD

Ext. ref.

Slow

1.4

1

1.8

mA

Power-down supply current

Power supply rejection ratio

µA

Zero scale, See Note 2

Full scale, See Note 3

–65

PSRR

dB

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying V

and is given by:

DD

PSRR = 20 log [(E (V max) – E (V min))/V max]

ZS DD ZS DD DD

3. Power supply rejection ratio at full scale is measured by varying V

DD

PSRR = 20 log [(E (V max) – E (V min))/V max]

DD DD DD

G

static DAC specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

bits

Resolution

8

INL

Integral nonlinearity, end point adjusted

Differential nonlinearity

See Note 4

See Note 5

See Note 6

See Note 7

±0.4

±0.1

±1

±0.5

±24

LSB

DNL

LSB

E

Zero-scale error (offset error at zero scale)

TC Zero-scale-error temperature coefficient

mV

ZS

E

10

ppm/°C

% full

scale V

E

Gain error

See Note 8

See Note 9

±0.6

G

E

G

T

Gain error temperature coefficient

10

ppm/°C

C

NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output

from the line between zero and full scale excluding the effects of zero code and full-scale errors.

5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1

LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains

constant) as a change in the digital input code.

6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

6

7. Zero-scale-error temperature coefficient is given by: E

TC = [E

(T

ZS max

) – E

(T

)]/V × 10 /(T

ref max

– T

).

min

ZS

8. Gain error is the deviation from the ideal output (2V – 1 LSB) with an output load of 10 k excluding the effects of the zero-error.

ZS min

ref

9. Gain temperature coefficient is given by: E TC = [E (T

6

) – E (T

)]/V × 10 /(T

min ref max

– T

).

min

G

max

G

output specifications

PARAMETER

Output voltage

TEST CONDITIONS

MIN

TYP

MAX

–0.4

UNIT

V

O

R

= 10 kΩ

0

V

L

DD

±0.25

% full

scale V

Output load regulation accuracy

V

O

= 4.096 V, 2.048 V,

R = 2 kΩ vs 10 k

L

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electrical characteristics over recommended operating conditions (unless otherwise noted)

(Continued)

reference pin configured as output (REF)

PARAMETER

Low reference voltage

High reference voltage

Output source current

Output sink current

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

1.003 1.024 1.045

ref(OUTL)

V

DD

> 4.75 V

2.027 2.048 2.069

V

ref(OUTH)

I

1

mA

pF

ref(source)

ref(sink)

I

–1

Load capacitance

100

–65

PSRR

Power supply rejection ratio

dB

reference pin configured as input (REF)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

I

Input voltage

0

V

DD–1.5

R

C

Input resistance

Input capacitance

10

5

MΩ

pF

I

Fast

1.3

525

–80

MHz

kHz

dB

Reference input bandwidth

Reference feedthrough

REF = 0.2 V + 1.024 V dc

pp

Slow

REF = 1 V at 1 kHz + 1.024 V dc (see Note 10)

pp

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

digital inputs

PARAMETER

High-level digital input current

TEST CONDITIONS

V = V

MIN

TYP

MAX

UNIT

µA

I

1

IH

I

DD

Low-level digital input current

Input capacitance

V = 0 V

I

–1

µA

IL

C

8

pF

i

analog output dynamic performance

PARAMETER

TEST CONDITIONS

MIN

TYP

0.8

2.8

0.4

0.8

12

MAX

2.4

UNIT

Fast

Slow

Fast

Slow

Fast

Slow

R

= 10 kΩ,

See Note 11

C

= 100 pF,

L

t

Output settling time, full scale

Output settling time, code to code

Slew rate

µs

s(FS)

5.5

1.2

R

= 10 kΩ,

See Note 12

L

µs

s(CC)

1.6

R

= 10 kΩ,

L

SR

V/µs

See Note 13

1.8

DIN = 0 to 1,

f

= 100 kHz,

CLK

Glitch energy

5

nV–S

CS = V

DD

SNR

Signal-to-noise ratio

53

48

57

47

S/(N+D) Signal-to-noise + distortion

f = 480 kSPS,

f

C

= 1 kHz,

= 100 pF

L

s

out

dB

R

= 10 kΩ,

THD

Total harmonic distortion

–50

62

–48

L

SFDR

Spurious free dynamic range

50

NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change

of 0x020 to 0xFD0 or 0xFD0 to 0x020 respectively. Not tested, assured by design.

12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change

of one count. Not tested, assured by design.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

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digital input timing requirements

MIN NOM

MAX

UNIT

ns

t

Setup time, CS low before first negative SCLK edge

10

25

10

5

su(CS–CK)

su(C16-CS)

wH

th

Setup time, 16 negative SCLK edge (when D0 is sampled) before CS rising edge

ns

SCLK pulse width high

ns

SCLK pulse width low

ns

wL

Setup time, data ready before SCLK falling edge

Hold time, data held valid after SCLK falling edge

ns

su(D)

ns

h(D)

PARAMETER MEASUREMENT INFORMATION

t

wL

wH

SCLK

DIN

X

1

2

3

4

5 15

16

t

su(D) h(D)

D15

D14

D13

D12

D1

D0

X

t

su(C16-CS)

t

su(CS-CK)

CS

Figure 1. Timing Diagram

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TYPICAL CHARACTERISTICS

SUPPLY CURRENT

vs

FREE-AIR TEMPERATURE

vs

FREE-AIR TEMPERATURE

4.5

4

3.5

3

4

3.5

3

Fast Mode

2.5

2

Slow Mode

1.5

V

= 5 V

= Int. 2 V

DD

ref

V

= 3 V

= Int. 1 V

DD

1

V

ref

Input Code = 1023 (Both DACs)

0.5

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90

T

A

– Free-Air Temperature – °C

T

A

– Free-Air Temperature – °C

Figure 2

Figure 3

POWER DOWN SUPPLY CURRENT

OUTPUT VOLTAGE

vs

LOAD CURRENT

vs

TIME

2.6

2.4

2.2

2

2.064

2.062

2.06

V

= 3 V

= Int. 1 V

DD

Fast Mode

Slow Mode

V

ref

Input Code = 4095

1.8

1.6

1.4

2.058

1.2

1

2.056

2.054

0.8

0.6

0.4

2.052

2.05

0.2

0

10

20

30

40

50

60

70

80

0

0.5

1

1.5

2

2.5

3

3.5

4

t – Time – µs

Source Current – mA

Figure 4

Figure 5

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TYPICAL CHARACTERISTICS

OUTPUT VOLTAGE

vs

LOAD CURRENT

OUTPUT VOLTAGE

vs

LOAD CURRENT

3

4.128

V = 3 V

DD

ref

Input Code = 0

V

= 5 V

= Int. 2 V

DD

ref

V

= Int. 1 V

Fast Mode

Slow Mode

4.126

4.124

4.122

4.12

2.5

2

Input Code = 4095

Fast Mode

1.5

1

4.118

0.5

0

4.116

4.114

Slow Mode

3

0

0.5

1

1.5

2

2.5

3.5

4

0

0.5

1

1.5

2

2.5

3

3.5

4

Sink Current – mA

Source Current – mA

Figure 6

Figure 7

OUTPUT VOLTAGE

vs

LOAD CURRENT

TOTAL HARMONIC DISTORTION AND NOISE

vs

FREQUENCY

5

0

–10

–20

–30

–40

–50

–60

–70

–80

V

= 5 V

= Int. 2 V

DD

ref

V

= 5 V

DD

4.5

4

V

ref

= 1 V dc + 1 V p/p Sinewave

Input Code = 0

Output Full Scale

3.5

3

Fast Mode

2.5

2

Slow Mode

1.5

Fast Mode

1

0.5

0

–90

Slow Mode

3.5

–100

0

0.5

1

1.5

2

2.5

3

4

100

1000

10000

100000

Sink Current – mA

f – Frequency – Hz

Figure 8

Figure 9

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TYPICAL CHARACTERISTICS

TOTAL HARMONIC DISTORTION

vs

FREQUENCY

0

–10

–20

–30

–40

–50

–60

–70

–80

V

= 5 V

DD

V

ref

= 1 V dc + 1 V p/p Sinewave

Output Full Scale

Slow Mode

Fast Mode

–90

–100

100

1000

10000

100000

f – Frequency – Hz

Figure 10

DIFFERENTIAL NONLINEARITY

vs

DIGITAL OUTPUT CODE

0.20

0.15

0.10

0.05

–0.00

–0.05

–0.10

–0.15

–0.2

0

16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256

Digital Output Code

Figure 11

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TYPICAL CHARACTERISTICS

INTEGRAL NONLINEARITY

vs

DIGITAL OUTPUT CODE

1.0

0.8

0.6

0.4

0.2

–0.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256

Digital Output Code

Figure 12

APPLICATION INFORMATION

general function

The TLV5626 is a dual 8-bit, single supply DAC, based on a resistor string architecture. It consists of a serial

interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a

rail-to-rail output buffer.

The output voltage (full scale determined by reference) is given by:

CODE

2 REF

[V]

0x1000

Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFF0.Bits 3 to

0 must be set to zero. A power on reset initially puts the internal latches to a defined state (all bits zero).

serial interface

A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling

edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the

target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.

Figure 13 shows examples of how to connect the TLV5626 to TMS320, SPI , and Microwire .

TMS320

DSP

TLV5626

CS

DIN

SPI

TLV5626

CS

DIN

Microwire

I/O

TLV5626

CS

DIN

FSX

DX

I/O

MOSI

SCK

SO

SK

CLKX

SCLK

Figure 13. Three-Wire Interface

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APPLICATION INFORMATION

Notes on SPI and Microwire : Before the controller starts the data transfer, the software has to generate a

falling edge on the I/O pin connected to CS. If the word width is 8 bits (SPI and Microwire ), two write

operations must be performed to program the TLV5626. After the write operation(s), the holding registers or the

th

control register are updated automatically on the 16 positive clock edge.

serial clock frequency and update rate

The maximum serial clock frequency is given by:

1

f

20 MHz

sclkmax

t

wlmin

whmin

The maximum update rate is:

1

f

1.25 MHz

updatemax

16 t

t

wlmin

whmin

The maximum update rate is just a theoretical value for the serial interface, as the settling time of the TLV5626

has to be considered, too.

data format

The 16-bit data word for the TLV5626 consists of two parts:

Program bits

New data

(D15..D12)

(D11..D0)

D15

R1

D14

D13

D12

R0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SPD

PWR

12 Data bits

SPD: Speed control bit

PWR: Power control bit

1 → fast mode

1 → power down

0 → slow mode

0 → normal operation

The following table lists the possible combination of the register select bits:

register select bits

R1

0

R0

0

REGISTER

Write data to DAC B and BUFFER

Write data to BUFFER

0

1

0

Write data to DAC A and update DAC B with BUFFER content

Write data to control register

1

The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected,

then the 12 data bits determine the new DAC value:

data bits: DAC A, DAC B and BUFFER

D11

D10

D9

D8

D7

D6

D5

D4

D3

0

D2

0

D1

0

D0

0

New DAC Value

If control is selected, then D1, D0 of the 12 data bits are used to program the reference voltage:

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APPLICATION INFORMATION

data bits: CONTROL

D11

X

D10

X

D9

X

D8

X

D7

X

D6

X

D5

X

D4

X

D3

X

D2

X

D1

D0

REF1

REF0

X: don’t care

REF1 and REF0 determine the reference source and, if internal reference is selected, the reference voltage.

reference bits

REF1

REF0

REFERENCE

External

0

1

0

1

0

1

1.024 V

2.048 V

External

CAUTION:

If external reference voltage is applied to the REF pin, external reference MUST be selected.

examples of operation:

Set DAC A output, select fast mode, select internal reference at 2.048 V:

1. Set reference voltage to 2.048 V (CONTROL register):

D15

1

D14

1

D13

0

D12

1

D11

0

D10

0

D9

0

D8

0

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

1

D0

0

2. Write new DAC A value and update DAC A output:

D15

1

D14

1

D13

0

D12

0

D11

D10

D9

D8

D7

D6

D5

D4

D3

0

D2

0

D1

0

D0

0

New DAC A output value

The DAC A output is updated on the rising clock edge after D0 is sampled.

To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL

register again.

Set DAC B output, select fast mode, select external reference:

3. Select external reference (CONTROL register):

D15

1

D14

1

D13

0

D12

1

D11

0

D10

0

D9

0

D8

0

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

4. Write new DAC B value to BUFFER and update DAC B output:

D15

0

D14

1

D13

0

D12

0

D11

D10

D9

D8

D7

D6

D5

D4

D3

0

D2

0

D1

0

D0

0

New BUFFER content and DAC B output value

X = Don’t care

The DAC A output is updated on the rising clock edge after D0 is sampled.

To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL

register again.

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5626

2.7 V TO 5.5 V LOW POWER DUAL 8-BIT DIGITAL-TO-ANALOG

CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS236 –JUNE 1999

APPLICATION INFORMATION

examples of operation: (continued)

Set DAC A value, set DAC B value, update both simultaneously, select slow mode, select internal reference

at 1.024 V:

1. Set reference voltage to 1.024 V (CONTROL register):

D15

1

D14

0

D13

0

D12

1

D11

0

D10

0

D9

0

D8

0

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

1

2. Write data for DAC B to BUFFER:

D15

0

D14

0

D13

0

D12

1

D11

D10

D9

D8

D7

D6

D5

D4

D3

0

D2

0

D1

0

D0

0

New DAC B value

X = Don’t care

3. Write new DAC A value and update DAC A and B simultaneously:

D15

1

D14

0

D13

0

D12

0

D11

D10

D9

D8

D7

D6

D5

D3

0

D2

0

D1

0

D0

0

New DAC A value

X = Don’t care

Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled.

Set power-down mode:

D15

X

D14

X

D13

1

D12

X

D11

X

D10

X

D9

X

D8

X

D7

X

D6

X

D5

X

D4

X

D3

X

D2

X

D1

X

D0

X

X = Don’t care

linearity, offset, and gain error using single ended supplies

When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With

a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage

may not change with the first code, depending on the magnitude of the offset voltage.

The output amplifier attempts to drive the output to a negative voltage. However, because the most negative

supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.

The output voltage then remains at zero until the input code value produces a sufficient positive output voltage

to overcome the negative offset voltage, resulting in the transfer function shown in Figure 14.

Output

Voltage

0 V

DAC Code

Negative

Offset

Figure 14. Effect of Negative Offset (single supply)

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5626

2.7 V TO 5.5 V LOW POWER DUAL 8-BIT DIGITAL-TO-ANALOG

CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS236 –JUNE 1999

APPLICATION INFORMATION

This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the

dotted line if the output buffer could drive below the ground rail.

For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after

offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not

allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity

is measured between full-scale code and the lowest code that produces a positive output voltage.

definitions of specifications and terminology

integral nonlinearity (INL)

The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum

deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale

errors.

differential nonlinearity (DNL)

The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the

measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage

changes in the same direction (or remains constant) as a change in the digital input code.

zero-scale error (E

)

ZS

Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.

gain error (E )

G

Gain error is the error in slope of the DAC transfer function.

signal-to-noise ratio + distortion (S/N+D)

S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components

below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in

decibels.

spurious free dynamic range (SFDR)

Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of

the spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels.

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5626

2.7 V TO 5.5 V LOW POWER DUAL 8-BIT DIGITAL-TO-ANALOG

CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS236 –JUNE 1999

MECHANICAL DATA

D (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0.050 (1,27)

0.020 (0,51)

0.010 (0,25)

M

0.014 (0,35)

14

8

0.008 (0,20) NOM

0.244 (6,20)

0.228 (5,80)

0.157 (4,00)

0.150 (3,81)

Gage Plane

0.010 (0,25)

1

7

0°–8°

0.044 (1,12)

0.016 (0,40)

A

Seating Plane

0.004 (0,10)

0.010 (0,25)

0.004 (0,10)

0.069 (1,75) MAX

PINS **

8

14

16

DIM

0.197

(5,00)

0.344

(8,75)

0.394

(10,00)

A MAX

0.189

(4,80)

0.337

(8,55)

0.386

(9,80)

A MIN

4040047/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).

D. Falls within JEDEC MS-012

15

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IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.


型号：	TLV5626
厂家：	TEXAS INSTRUMENTS
描述：	2.7 V TO 5.5 V LOW POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN 2.7 V至5.5 V低功耗双通道8位具内部基准和断电数位类比转换器转换器
文件：	总16页 (文件大小：228K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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