TLV5628IDWR [TI]
暂无描述;
| 型号： | TLV5628IDWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 暂无描述 转换器 |
| 文件： | 总14页 (文件大小：215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
DW OR N PACKAGE
(TOP VIEW)
Eight 8-Bit Voltage Output DACs
3-V Single Supply Operation
Serial Interface
DACC
DACD
REF1
DACB
DACA
GND
1
2
3
4
5
6
7
8
16
15
14
High-Impedance Reference Inputs
Programmable for 1 or 2 Times Output
Range
13 LDAC
12 LOAD
DATA
CLK
Simultaneous Update Facility
Internal Power-On Reset
Low Power Consumption
Half-Buffered Output
11
10
9
REF2
DACH
DACG
V
DD
DACE
DACF
applications
Programmable Voltage Sources
Digitally Controlled Amplifiers/Attenuators
Mobile Communications
Automatic Test Equipment
Process Monitoring and Control
Signal Synthesis
description
The TLV5628C and TLV5628I are octal 8-bit voltage output digital-to-analog converters (DACs) with buffered
reference inputs (high impedance). The DACs produce an output voltage that varies between one or two times
the reference voltages and GND, and the DACs are monotonic. The device is simple to use, running from a
single supply of 3 to 3.6 V. A power-on reset function is incorporated to ensure repeatable start-up conditions.
Digital control of the TLV5628C and TLV5628I is over a simple 3-wire serial bus that is CMOS compatible and
easily interfaced to all popular microprocessor and microcontroller devices. The 12-bit command word
comprises 8 bits of data, 3 DAC select bits and a range bit, the latter allowing selection between the times 1
or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be
written to the device, then all DAC outputs are updated simultaneously through control of the LDAC terminal.
The digital inputs feature Schmitt triggers for high noise immunity.
The 16-terminal small-outline D package allows digital control of analog functions in space-critical applications.
The TLV5628C is characterized for operation from 0°C to 70°C. The TLV5628I is characterized for operation
from –40°C to 85°C. The TLV5628C and TLV5628I do not require external trimming.
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE
(DW)
PLASTIC DIP
(N)
T
A
0°C to 70°C
TLV5628CDW
TLV5628IDW
TLV5628CN
TLV5628IN
–40°C to 85°C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
functional block diagram
REF1
+
–
DAC
+
–
DACA
× 2
9
8
Latch
Latch
DAC
DAC
+
–
DACD
DACE
× 2
× 2
8
8
Latch
Latch
Latch
Latch
REF2
+
–
+
–
DAC
+
–
DACH
× 2
8
Latch
Latch
CLK
Power-On
Reset
Serial
Interface
LDAC
DATA
LOAD
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
CLK
NO.
5
I
O
O
O
O
O
O
O
O
I
Serial-interface clock, data enters on the negative edge
DACA analog output
DACA
DACB
DACC
DACD
DACE
DACF
DACG
DACH
DATA
GND
2
1
DACB analog output
16
15
7
DACC analog output
DACD analog output
DACE analog output
8
DACF analog output
9
DACG analog output
10
4
DACH analog output
Serial-interface digital data input
Ground return and reference terminal
DAC-update latch control
Serial-interface load control
Reference voltage input to DACA
Reference voltage input to DACB
Positive supply voltage
3
I
LDAC
LOAD
REF1
REF2
13
12
14
11
6
I
I
I
I
V
I
DD
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
detailed description
The TLV5628 is implemented using eight resistor-string DACs. The core of each DAC is a single resistor with
256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected
to the GND terminal and the other end is fed from the output of the reference input buffer. Monotonicity is
maintainedbyuseoftheresistorstrings. Linearitydependsuponthematchingoftheresistorelementsandupon
the performance of the output buffer. Because the inputs are buffered, the DACs always present a
high-impedance load to the reference sources. There are two input reference terminals; REF1 is used for DACA
through DACD and REF2 is used by DACE through DACH.
Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times 1 or
times 2 gain.
On power-up, the DACs are reset to CODE 0.
Each output voltage is given by:
CODE
V (DACA|B|C|D|E|F|G|H)
REF
(1 RNG bit value)
O
256
where CODE is in the range of 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial-control word.
data interface
With LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have
been clocked in, LOAD is pulsed low to transfer the data from the serial-input register to the selected DAC as
shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated and LOAD goes low. When
LDAC is high during serial programming, the new value is stored within the device and can be transferred to
the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered MSB first. Data
transfers using two 8 clock cycle periods are shown in Figures 3 and 4.
CLK
t
su(DATA-CLK)
t
su(LOAD-CLK)
D2 D1
su(CLK-LOAD)
t
v(DATA-CLK)
DATA
LOAD
A2
A1 A0
RNG
D7
D6
D5
D4
D0
t
t
w(LOAD)
DAC Update
Figure 1. LOAD-Controlled Update (LDAC = Low)
CLK
t
su(DATA-CLK)
t
v(DATA-CLK)
DATA
A2
A1 A0
RNG
D7
D6
D5
D4
D2
D1
D0
t
su(LOAD–LDAC)
LOAD
LDAC
t
w(LDAC)
DAC Update
Figure 2. LDAC-Controlled Update
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CLK Low
CLK
A1
A0
RNG
D7
D6
D5
D4
D3
D2
D1
D0
DATA
LOAD
LDAC
Figure 3. Load Controlled Update Using 8-Bit Serial Word (LDAC = Low)
CLK Low
CLK
A1
A0
RNG
D7
D6
D5
D4
D3
D2
D1
D0
DATA
LOAD
LDAC
Figure 4. LDAC Controlled Update Using 8-Bit Serial Word
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
data interface (continued)
Table 2 lists the A2, A1, and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC output
range. When RNG = low, the output range is between the applied reference voltage and GND, and when
RNG = high, the range is between twice the applied reference voltage and GND.
Table 1. Ideal Output Transfer
D7
0
0
•
D6
0
0
•
D5
0
0
•
D4
0
0
•
D3
0
0
•
D2
0
0
•
D1
0
0
•
D0
0
1
•
OUTPUT VOLTAGE
GND
(1/256) × REF (1+RNG)
•
•
•
•
•
•
•
•
•
•
0
1
•
1
0
•
1
0
•
1
0
•
1
0
•
1
0
•
1
0
•
1
0
•
(127/256) × REF (1+RNG)
(128/256) × REF (1+RNG)
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
(255/256) × REF (1+RNG)
Table 2. Serial Input Decode
A2
0
A1
0
A0
0
DAC UPDATED
DACA
0
0
1
DACB
0
1
0
DACC
0
1
1
DACD
1
0
0
DACE
1
0
1
DACF
1
1
0
DACG
1
1
1
DACH
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
linearity, offset, and gain error
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage
may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier, with a negative voltage offset, attempts to drive the output to a negative voltage. However,
since the most negative supply rail is ground, the output cannot drive to a negative voltage.
So when the output offset voltage is negative, the output voltage remains at 0 volts until the input code value
produces a sufficient output voltage to overcome the inherent negative offset voltage resulting in the transfer
function shown in Figure 5.
Output
Voltage
0 V
DAC Code
Negative
Offset
Figure 5. Effect of Negative Offset (Single Supply)
The negative offset error produces a breakpoint, not a linearity error. The transfer function would follow the
dotted line if the output buffer could drive to a negative voltage.
For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after
offset and full scale is adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. The linearity in
the unipolar mode is measured between full scale code and the lowest code which produces a positive output
voltage.
The code is calculated from the maximum specification for the negative offset.
equivalent inputs and outputs
INPUT CIRCUIT
OUTPUT CIRCUIT
V
DD
V
DD
_
+
Input from
Decoded DAC
Register String
DAC
Voltage Output
V
ref
Input
× 1
84 kΩ
Output
Range
Select
To DAC
Resistor
String
I
× 2
SINK
60 µA
Typical
84 kΩ
GND
GND
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (V
Digital input voltage range, V
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND – 0.3 V to V
Operating free-air temperature range, T : TLV5628C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
– GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND – 0.3 V to V
+ 0.3 V
+ 0.3 V
ID
DD
DD
A
TLV5628I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
NOM
MAX
UNIT
V
Supply voltage, V
2.7
3.3
5.25
DD
High-level digital input voltage, V
0.8 V
V
IH
DD
Low-level digital input voltage, V
0.8
V
IL
Reference voltage, V [A|B|C|D|E|F|G|H], X1 gain
V
–1.5
V
ref
DD
Load resistance, R
10
kΩ
ns
ns
ns
ns
L
Setup time, data input, t
su(DATA-CLK)
Valid time, data input valid after CLK↓, t
(see Figures 1 and 2)
50
50
(see Figures 1 and 2)
v(DATA-CLK)
Setup time, CLK eleventh falling edge to LOAD, t
(see Figure 1)
50
su(CLK-LOAD)
(see Figure 1)
Setup time, LOAD↑ to CLK↓, t
50
su(LOAD-CLK)
Pulse duration, LOAD, t
Pulse duration, LDAC, t
(see Figure 1)
(see Figure 2)
250
250
0
ns
ns
ns
w(LOAD)
w(LDAC)
Setup time, LOAD↑ to LDAC↓, t
(see Figure 2)
su(LOAD-LDAC)
CLK frequency
1
MHz
°C
TLV5628C
TLV5628I
0
70
85
Operating free-air temperature, T
A
–40
°C
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
electrical characteristics over recommended operating free-air temperature range,
V
= 3 V to 3.6 V, V = 2 V, × 1 gain output range (unless otherwise noted)
DD
ref
PARAMETER
High-level digital input current
Low-level digital input current
Output sink current
TEST CONDITIONS
MIN
TYP
MAX
±10
±10
UNIT
µA
I
I
I
I
V = V
I
IH
DD
V = 0 V
µA
IL
I
20
1
µA
O(sink)
O(source)
Each DAC output
Output source current
mA
Input capacitance
15
15
C
pF
i
Reference input capacitance
Supply current
I
I
V
V
= 3.3 V
= 3.3 V,
4
±10
±1
mA
µA
DD
DD
Reference input current
Linearity error (end point corrected)
Differential linearity error
Zero-scale error
V
ref
= 1.5 V
ref
DD
E
E
E
V
ref
= 1.25 V, × 2 gain (see Note 1)
= 1.25 V, × 2 gain (see Note 2)
= 1.25 V, × 2 gain (see Note 3)
= 1.25 V, × 2 gain (see Note 4)
= 1.25 V, × 2 gain (see Note 5)
= 1.25 V, × 2 gain (see Note 6)
LSB
LSB
mV
L
V
ref
±0.9
30
D
V
ref
0
ZS
Zero-scale error temperature coefficient
Full-scale error
V
ref
10
µV/°C
mV
E
FS
V
ref
±60
Full-scale error temperature coefficient
Power supply sensitivity
V
±25
µV/°C
mV/V
ref
See Notes 7 and 8
PSRR
0.5
NOTES: 1. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero-scale and full scale (excluding the
effects of zero code and full-scale errors).
2. Differentialnonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes.
Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
6
4. Zero-scale error temperature coefficient is given by: ZSETC = [ZSE(T
) – ZSE(T
)]/V × 10 /(T
– T
).
min
max
min ref max
5. Full-scale error is the deviation from the ideal full-scale output (V – 1 LSB) with an output load of 10 kΩ.
ref
6
6. Full-scale temperature coefficient is given by: FSETC = [FSE(T
max
) – FSE (T
)]/V × 10 /(T
ref max
voltage from 4.5 V to 5.5 V dc and measuring the effect
– T
).
min
min
7. Zero-scale error rejection ratio (ZSE-RR) is measured by varying the V
of this signal on the zero-code output voltage.
DD
8. Full-scale error rejection ratio (FSE-RR) is measured by varing the V
this signal on the full-scale output voltage.
voltage from 3 V to 3.6 V dc and measuring the effect of
DD
operating characteristics over recommended operating free-air temperature range,
= 3 V to 3.6 V, V = 2 V, × 1 gain output range (unless otherwise noted)
V
DD
ref
TEST CONDITIONS
MIN
TYP
1
MAX
UNIT
V/µs
µs
Output slew rate
C
= 100 pF,
R
C
= 10 kΩ
L
L
L
Output settling time
To 0.5 LSB,
= 100 pF,
R
= 10 kΩ, See Note 9
10
L
Large-signal bandwidth
Digital crosstalk
Measured at –3 dB point
100
–50
–60
–60
100
kHz
dB
CLK = 1-MHz square wave measured at DACA-DACH
Reference feedthrough
Channel-to-channel isolation
Reference input bandwidth
See Note 10
See Note 11
See Note 12
dB
dB
kHz
NOTES: 9. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of 00 hex to FF hex or FF hex to 00 hex. For TLC5628C V = 5 V, V = 2 V and range = ×2. For TLC5628I V = 3 V,
DD ref DD
V
ref
= 1.25 V and range ×2.
10. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a V input = 1 V dc + 1 V
at 10 kHz.
ref PP
11. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex
with V input = 1 V dc + 1 V at 10 kHz.
ref PP
12. Reference bandwidth is a –3 dB bandwidth with an input at V = 1.25 V dc + 2 V
ref
and with a full-scale digital input code.
PP
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
TLV5628
DACA
DACB
•
•
•
10 kΩ
C
= 100 pF
L
DACH
Figure 6. Slewing Settling Time and Linearity Measurements
TYPICAL CHARACTERISTICS
POSITIVE RISE TIME AND SETTLING TIME
NEGATIVE FALL TIME AND SETTLING TIME
3
2.5
2
3
2.5
2
V
T
A
= 3 V
DD
= 25°C
Code FF to
00 Hex
Range = ×2
1.5
1
1.5
1
V
= 1.25 V
ref
V
= 3 V
DD
= 25°C
(see Note B)
T
A
0.5
0.5
Code 00 to
FF Hex
Range = ×2
0
0
V
ref
= 1.25 V
(see Note A)
–0.5
–0.5
–1
–1
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
Time – µs
Time – µs
NOTE A: Rise time = 2.05 µs, positive slew rate = 0.96 V/µs,
settling time = 4.5 µs.
NOTE B: Fall time = 4.25 µs, negative slew rate = 0.46 µs,
settling time = 8.5 µs.
Figure 7
Figure 8
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
TYPICAL CHARACTERISTICS
DAC OUTPUT VOLTAGE
DAC OUTPUT VOLTAGE
vs
vs
LOAD
LOAD
3
2.8
2.6
2.4
2.2
2
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
1.8
1.6
V
= 3 V,
= 1.5 V,
DD
V
ref
1.4
1.2
1
V
= 3 V,
= 1.5 V,
DD
Range = 2x
V
ref
Range = 1x
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
Load – kΩ
Load – kΩ
Figure 9
Figure 10
SUPPLY CURRENT
vs
TEMPERATURE
1.2
1.15
1.1
Range = ×2
Input Code = 255
V
V
= 3 V
1.25 V
DD
ref
1.05
1
0.95
0.9
0.85
0.8
–50
0
50
100
t – Temperature – °C
Figure 11
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
APPLICATION INFORMATION
_
+
TLV5628
V
O
DACA
DACB
•
•
•
R
DACH
NOTE A: Resistor R
10 kΩ
Figure 12. Output Buffering Scheme
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
PINS **
0.050 (1,27)
16
20
24
28
DIM
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
0.410
0.510
0.610
0.710
A MAX
(10,41) (12,95) (15,49) (18,03)
16
9
0.400
0.500
0.600
0.700
A MIN
(10,16) (12,70) (15,24) (17,78)
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.293 (7,45)
Gage Plane
0.010 (0,25)
1
8
0°–8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
4040000/B 10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
MECHANICAL DATA
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
A
PINS **
14
16
18
20
16
9
DIM
0.775
0.775
0.920
0.975
A MAX
(19,69) (19,69) (23.37) (24,77)
0.260 (6,60)
0.240 (6,10)
0.745
0.745
0.850
0.940
A MIN
(18,92) (18,92) (21.59) (23,88)
1
8
0.070 (1,78) MAX
0.020 (0,51) MIN
0.310 (7,87)
0.290 (7,37)
0.035 (0,89) MAX
0.200 (5,08) MAX
0.125 (3,18) MIN
Seating Plane
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
14 Pin Only
4040049/C 7/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001)
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
TLV5629
8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
TI
TLV5629IDW
8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
TI
TLV5629IPW
8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
TI
©2020 ICPDF网 联系我们和版权申明