TLV5630IDWG4 [TI]

8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG ONVERTERS WITH POWER DOWN AND INTERNAL REFERENCE; 8通道， 12位/ 10位/ 8位， 2.7 V至5.5 V的低功耗数字 - 模拟ONVERTERS具有掉电内部参考


型号：	TLV5630IDWG4
厂家：	TEXAS INSTRUMENTS
描述：	8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG ONVERTERS WITH POWER DOWN AND INTERNAL REFERENCE 8通道， 12位/ 10位/ 8位， 2.7 V至5.5 V的低功耗数字 - 模拟ONVERTERS具有掉电内部参考转换器数模转换器光电二极管
文件：	总22页 (文件大小：882K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLV5630

TLV5631

TLV5632

www.ti.com .................................................................................................................................................... SLAS269F–MAY 2000–REVISED NOVEMBER 2008

8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG

CONVERTERS WITH POWER DOWN AND INTERNAL REFERENCE

FEATURES

APPLICATIONS

•

Digital Servo Control Loops

Digital Offset and Gain Adjustment

Industrial Process Control

Machine and Motion Control Devices

Mass Storage Devices

•

Eight Voltage Output DACs in One Package

–

TLV5630 . . . 12-Bit

TLV5631 . . . 10-Bit

TLV5632 . . . 8-Bit

1 µs in Fast Mode

3 µs in Slow Mode

DW OR PW PACKAGE

(TOP VIEW)

•

Programmable Settling Time vs Power

Consumption

DGND

DIN

SCLK

DV_DD

DOUT

LDAC

MODE

REF

OUTD

OUTC

OUTB

OUTA

AV_DD

–

1 µs in Fast Mode

3 µs in Slow Mode

18 mW in Slow Mode at 3 V

48 mW in Fast Mode at 3 V

PRE

OUTE

OUTF

OUTG

OUTH

AGND

•

Compatible With TMS320 and SPI Serial Ports

Monotonic Over Temperature

Low Power Consumption:

–

18 mW in Slow Mode at 3 V

48 mW in Fast Mode at 3 V

•

Power-Down Mode

Internal Reference

Data Output for Daisy-Chaining

DESCRIPTION

The TLV5630, TLV5631, and TLV5632 are pin-compatible, eight-channel, 12-/10-/8-bit voltage output DACs

each with a flexible serial interface. The serial interface allows glueless interface to TMS320 and SPI, QSPI, and

Microwire serial ports. It is programmed with a 16-bit serial string containing 4 control and 12 data bits.

Additional features are a power-down mode, an LDAC input for simultaneous update of all eight DAC outputs,

and a data output which can be used to cascade multiple devices, and an internal programmable band-gap

reference.

The resistor string output voltage is buffered by a rail-to-rail output amplifier with a programmable settling time to

allow the designer to optimize speed vs power dissipation. The buffered, high-impedance reference input can be

connected to the supply voltage.

Implemented with a CMOS process, the DACs are designed for single-supply operation from 2.7 V to 5.5 V, and

can operate on two separate analog and digital power supplies. The devices are available in 20-pin SOIC and

TSSOP packages.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TLV5630

TLV5631

TLV5632

SLAS269F–MAY 2000–REVISED NOVEMBER 2008 .................................................................................................................................................... www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

AVAILABLE OPTIONS

PACKAGE

T_A

SOIC (DW)

TLV5630IDW

TLV5631IDW

TLV5632IDW

TSSOP (PW)

TLV5630IPW

TLV5631IPW

TLV5632IPW

RESOLUTION

40°C to 85°C

FUNCTIONAL BLOCK DIAGRAM

REF

Band-Gap

Voltage

12/10/8

OUTA

1 V or 2 V

(Trimmed)

with Enable

DAC A

Holding

Latch

DAC A

Latch

SCLK

DIN

DOUT

Serial

Interface

OUT

MODE

PRE

B, C, D,

E, F, G

and H

DAC B, C, D, E, F, G and H

Same as DAC A

LDAC

Terminal Functions

TERMINAL

NAME NO.

AGND

I/O

DESCRIPTION

Analog ground

AV_DD

Analog power supply

Digital ground

DGND

DIN

Digital serial data input

Digital serial data output

Digital power supply

Frame sync input

DOUT

DV_DD

LDAC

MODE

PRE

Load DAC. The DAC outputs are only updated, if this signal is low. It is an asynchronous input.

DSP/µC mode pin. High = µC mode, NC = DSP mode.

Preset input

REF

I/O Voltage reference input/output

SCLK

OUTA-OUTH

Serial clock input

12-15, 6-9

DAC outputs A, B, C, D, E, F, G and H

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TLV5630

TLV5631

TLV5632

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature (unless otherwise noted)

(1)

UNIT

Supply voltage, (AV_DD, DV_DDto GND)

Reference input voltage range

7 V

- 0.3 V to AV_DD+ 0.3

- 0.3 V to DV_DD+ 0.3

-40°C to 85°C

-65°C to 150°C

260°C

Digital input voltage range

Operating free-air temperature range, T_A

Storage temperature range, T_stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

(1) Stresses beyond those listed under„ absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under„ recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

MIN

4.5

2.7

TYP

MAX

5.5

UNIT

5-V operation

3-V operation

DV_DD= 2.7 V

DV_DD= 5.5 V

DV_DD= 2.7 V

DV_DD= 5.5 V

AV_DD= 5 V, See

AV_DD= 3 V, See

Supply voltage, AV_DD, DV_DD

High-level digital input, V_IH

Low-level digital input, V_IL

Reference voltage, V_ref

3.3

2.4

0.6

1.0

(1)

GND

2.048

1.024

AV_DD

Analog output load resistance, R_L

Analog output load capacitance, C_L

Clock frequency, f_CLK

kΩ

100

MHz

°C

Operating free-air temperature, T_A

-40

(1) Reference input voltages greater than AV_DD/2 causes saturation for large DAC codes.

ELECTRICAL CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER

POWER SUPPLY

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Fast

No load, All inputs = DV_DDor GND,

V_ref= 2.048 V, See

I_DD

Power supply current

(1)

Slow

Power-down supply

current

0.1

µA

POR

Power on threshold

Power supply rejection

ratio

(2)

PSRR

Full scale, See

-50

(1) I_DDis measured while continuously writing code 2048 to the DAC. For V_IH< DV_DD- 0.7 V and V_IL> 0.7 V, supply current increases.

(2) Power supply rejection ratio at full scale is measured by varying AV_DDand is given by: PSRR = 20 log [(E_G(AV_DDmax) -

E_G(AV_DDmin))/V_DDmax]

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TLV5631

TLV5632

ELECTRICAL CHARACTERISTICS (continued)

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

STATIC DAC SPECIFICATIONS

TLV5630

TLV5631

TLV5632

TLV5630

TLV5631

TLV5632

TLV5630

Bits

LSB

Resolution

Code 40 to 4095

Code 20 to 1023

Code 6 to 255

±2

±6

±2

±1

INL

Integral nonlinearity

V_ref= 1 V, 2 V

±0.5

±0.3

±0.5

±0.1

Code 40 to 4095

Code 20 to 1023

Code 6 to 255

DNL

Differential nonlinearity TLV5631

TLV5632

V_ref= 1 V, 2 V

Zero scale error (offset error at zero

scale)

E_ZS

±30

Zero scale error temperature

coefficient

E_ZSTC

µV/°C

%Full

Scale V

E_G

Gain error

±0.6

EGTC

Gain error temperature coefficient

ppm/°C

OUTPUT SPECIFICATIONS

V_O

Voltage output range

R_L= 10 kΩ

AV_DD-0.4

±0.3

Output load regulation

accuracy

%Full

Scale V

R_L= 2 kΩ vs 10 kΩ

REFERENCE OUTPUT

V_REFOUTL

Low reference voltage

V_DD> 4.75 V

1.010 1.024

2.020 2.048

1.040

2.096

V_REFOUTHHigh reference voltage

I_ref(Source)

I_ref(Sink)

Output source current

Output sink current

Load capacitance

µF

-1

(3)

See

Power supply rejection

ratio

PSRR

REFERENCE INPUT

V_I

R_I

C_I

Input voltage range

AV_DD

Input resistance

kΩ

Input capacitance

Fast

2.2

1.9

MHz

Reference input

bandwidth

V_ref= 0.4 V_pp+ 2.048 Vdc,

Input code = 0x800

Slow

(4)

Reference feedthrough V_ref= 2 V_ppat 1 kHz + 2.048 Vdc, See

DIGITAL INPUTS

High-level digital input

current

I_IH

V_I= DV_DD

V_I= 0 V

µA

Low-level digital input

current

I_IL

C_I

µA

Input capacitance

(3) In parallel with a 100-nF capacitor

(4) Reference feedthrough is measured at the DAC output with an input code = 0x000.

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ELECTRICAL CHARACTERISTICS (continued)

over recommended operating conditions (unless otherwise noted)

PARAMETER

DIGITAL OUTPUT

TEST CONDITIONS

MIN

TYP

MAX

UNIT

High-level digital output R_L= 10 kΩ

voltage

V_OH

V_OL

2.6

Low-level digital output R_L= 10 kΩ

voltage

0.4

Output voltage rise time R_L= 10 kΩ, C_L= 20 pF, Includes propagation delay

ANALOG OUTPUT DYNAMIC PERFORMANCE

Fast

Slow

Fast

Slow

Fast

Slow

Output settling time, full

scale

(5)

(6)

(7)

t_s(FS)

t_s(CC)

R_L= 10 kΩ, C_L= 100 pF, See

µs

0.5

Output settling time,

code to code

R_L= 10 kΩ, C_L= 100 pF, See

Slew rate

V/µs

(8)

Glitch energy

See

nV-s

Channel crosstalk

10 kHz sine, 4 V_PP

(5) Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of

0x080 to 0xFFF and 0xFFF to 0x080, respectively. Assured by design; not tested.

(6) Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of one

count. The max time applies to code changes near zero scale or full scale. Assured by design; not tested.

(7) Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

(8) Code transition: TLV5630 - 0x7FF to 0x800, TLV5631 - 0x7FCto 0x800, TLV5632 - 0x7F0 to 0x800.

DIGITAL INPUT TIMING REQUIREMENTS

PARAMETER

MIN TYP MAX UNIT

t_su(FS-CK)

t_su(C16-FS)

Setup time, FS low before next negative SCLK edge

Setup time, 16^thnegative edge after FS low on which bit D0 is sampled before rising edge

of FS. µC mode only

t_su(FS-C17)

t_su(CK-FS)

t_wL(LDAC)

t_wH

µC mode, setup time, FS high before 17^thnegative edge of SCLK.

DSP mode, setup time, SLCK low before FS low.

LDAC duration low

SCLK pulse duration high

t_wL

SCLK pulse duration low

t_su(FS-CK)

t_su(D)

Setup time, FS low before first negative SCLK edge

Setup time, data ready before SCLK falling edge

Hold time, data held valid after SCLK falling edge

FS duration high

t_h(D)

t_wH(FS)

t_wL(FS)

FS duration low

See AC

specs

t_s

Settling time

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TLV5632

TYPICAL CHARACTERISTICS

OUTPUT LOAD REGULATION

= 5 V,

= 2 V,

= 3 V,

= 1 V,

0.9

0.8

0.7

0.9

0.8

0.7

ref

Zero Scale

Fast

0.6

0.5

0.4

0.6

0.5

0.4

0.3

0.2

0.3

0.2

0.1

Slow

0.5

1.5

0.5

1.5

Sinking Current − mA

Figure 2.

Sinking Current − mA

Figure 1.

OUTPUT LOAD REGULATION

2.06

2.055

2.05

4.12

4.11

4.1

= 5 V,

= 2 V,

= 3 V,

= 1 V,

ref

Full Scale

Fast

Slow

Fast

Slow

4.09

4.08

4.07

2.045

2.04

2.035

2.03

4.06

4.05

4.04

2.025

−0.5 −1

−1.5 −2

−2.5 −3

−3.5 −4

−0.05 −0.5 −1

−1.5 −2

−2.5 −3

−3.5 −4

Sourcing Current − mA

Figure 3.

Figure 4.

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TLV5632

TYPICAL CHARACTERISTICS (continued)

TLV5630 INTEGRAL NONLINEARITY

CODE

−1

−2

−3

−4

1024

2048

3072

4096

Code

Figure 5.

TLV5630 DIFFERENTIAL NONLINEARITY

CODE

1.0

0.8

0.6

0.4

0.2

−0.0

−0.2

−0.4

−0.6

−0.8

−1.0

1024

2048

3072

4096

Code

Figure 6.

TLV5631 INTEGRAL NONLINEARITY

CODE

2.0

1.5

1.0

0.5

0.0

−0.5

−1.0

−1.5

−2.0

256

512

768

1024

Code

Figure 7.

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TLV5632

TYPICAL CHARACTERISTICS (continued)

TLV5631 DIFFERENTIAL NONLINEARITY

CODE

1.0

0.8

0.6

0.4

0.2

−0.0

−0.2

−0.4

−0.6

−0.8

−1.0

256

512

768

1024

Code

Figure 8.

TLV5632 INTEGRAL NONLINEARITY

CODE

0.5

0.4

0.3

0.2

0.1

−0.1

−0.2

−0.3

−0.4

−0.5

100

150

200

250

Code

Figure 9.

TLV5632 DIFFERENTIAL NONLINEARITY

CODE

0.5

0.4

0.3

0.2

0.1

−0.1

−0.2

−0.3

−0.4

−0.5

100

150

200

250

Code

Figure 10.

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PARAMETER MEASUREMENT INFORMATION

SCLK

h(D)

su(D)

DIN

D15

D14

D13

D12

†

DOUT

D14

su(FS - C17)

su(FS - CK)

su(C16 - FS)

wH(FS)

(mC mode)

su(CK - FS)

wL(FS)

(DSP Mode)

†

Previous input data

Figure 11. Serial Interface Timing

wL(LDAC)

LDAC

OUTx

±0.5 LSB

Figure 12. Output Timing

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APPLICATION INFORMATION

GENERAL FUNCTION

The TLV5630/31/32 are 8-channel, single-supply DACs, based on a resistor string architecture. They consist of a

serial interface, a speed and power-down control logic, an internal reference, a resistor string, and a rail-to-rail

output buffer.

The output voltage (full scale determined by reference) for each channel is given by:

CODE

0x1000

2REF

[V]

where REF is the reference voltage and CODE is the digital input value. The input range is 0x000 to 0xFFF for

the TLV5630, 0x000 to 0xFFC for the TLV5631, and 0x000 to 0xFF0 for the TLV5632.

POWER ON RESET (POR)

The built-in power-on-reset circuit controls the output voltage after power up. On power up, all latches including

the preset register are set to zero, but the DAC outputs are only set to zero if the LDAC is low. The DAC outputs

may have a small offset error produced by the output buffer. The registers remains at zero until a valid write

sequence is made to the DAC, changing the DAC register data. This is useful in applications where it is

important to know the state of the outputs of the DAC after power up. All digital inputs must be logic low until the

digital and analog supplies are applied. Any logic high voltages applied to the logic input pins when power is not

applied to AV_DDand DV_DD, may power the device logic circuit through the overvoltage protection diode causing

an undesired operation. When separate analog (AV_DD) and digital (DV_DD) supplies are used, AV_DDmust come up

first before DV_DD, to ensure that the power-on-reset circuit operates correctly.

SERIAL INTERFACE

A falling edge of FS starts shifting the data on DIN starting with the MSB to the internal register on the falling

edges of SCLK. After 16 bits have been transferred, the content of the shift register is moved to one of the DAC

holding registers, depending on the address bits within the data word. A logic 0 on the LDAC pin is required to

transfer the content of the DAC holding register to the DAC latch and to update the DAC outputs. LDAC is an

asynchronous input. It can be held low if a simultaneous update of all eight channels is not needed.

For daisy-chaining, DOUT provides the data sampled on DIN with a delay of 16 clock cycles.

DSP Mode:

SCLK

DIN

D15

D14

E15

E14

F15

µC Mode:

SCLK

DIN

D15

D14

E15

E14

F15

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Difference between DSP mode (MODE = N.C. or 0) and µC (MODE = 1) mode:

•

In µC mode, FS needs to be held low until all 16 data bits have been transferred. If FS is driven high before

the 16^thfalling clock edge, the data transfer is cancelled. The DAC is updated after a rising edge on FS.

•

In DSP mode, FS needs to stay low for 20 ns and can go high before the 16^thfalling clock edge.

In DSP mode there needs to be one falling SCLK edge before FS goes low to start the write (DIN) cycle. This

extra falling SCLK edge has to happen at least 5 ns before FS goes low, t_su(CK-FS)≥ 5 ns.

•

In µC mode, the extra falling SCLK edge is not necessary. However, if it does happen, the extra negative

SCLK edge is not allowed to occur within 10 ns after FS goes HIGH to finish the WRITE cycle (t_su(FS-C17)).

SERIAL CLOCK FREQUENCY AND UPDATE RATE

The maximum serial clock frequency is given by:

) t

+ 30 MHz

sclkmax

whmin

wlmin

The maximum update rate is:

+ 1.95 MHz

updatemax

₁₆ǒ_twhmin

) t

wlmin

Note, that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the

DAC has to be considered also.

DATA FORMAT

The 16-bit data word consists of two parts:

•

Address bits (D15…D12)

Data bits (D11…D0)

D15

D14

D13

D12

D11

D10

Data

Ax: Address bits. See table.

FUNCTION

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

DAC G

DAC H

CTRL0

CTRL1

Preset

Reserved

DAC A and B

DAC C and D

DAC E and F

DAC G and H

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TLV5632

DAC A-H AND TWO-CHANNEL REGISTERS

Writing to DAC A-H sets the output voltage of channel A-H. It is possible to automatically generate the

complement of one channel by writing to one of the four two-channel registers (DAC A and B etc.).

The TLV5630 decodes all 12 data bits. The TLV5631 decodes D11 to D2 (D1 and D0 are ignored). The TLV5632

decodes D11 to D4 (D3 to D0 are ignored).

PRESET

The outputs of the DAC channels can be driven simultaneously to a predefined value stored in the preset register

by driving the PRE input pin low and asserting the LDAC input pin. The preset register is cleared (set to zero) by

the POR circuit after power up. Therefore, it must be written with a predefined value before asserting the PRE

pin low, unless zero is the desired preset value. The PRE input is asynchronous to the clock.

CTRL0

BIT

D11

D10

Function

Default

: Full device power down

: DOUT enable

0 = normal

0 = disabled

0 = external

1 = power down

1 = enabled

R1:0 : Reference select bits

1 = external, 2 = internal 1 V, 3 = internal 2 V

1 = twos complement

: Input mode

: Reserved

0 = straight binary

If DOUT is enabled, the data input on DIN is output on DOUT with a 16-cycle delay. That makes it possible to

daisy-chain multiple DACs on one serial bus.

CTRL1

BIT

D11

D10

P_GH

P_EF

P_CD

P_AB

S_GH

S_EF

S_CD

S_AB

Function

Default

P_XY

S_XY

: Power Down DAC_XY

: Speed DAC_XY

0 = normal 1 = power down

0 = slow 1 = fast

: DAC pair AB, CD, EF or GH

In power-down mode, the amplifiers of the selected DAC pair are disabled and the total power consumption of

the device is significantly reduced. Power-down mode of a specific DAC pair can be selected by setting the P_XY

bit within the data word to 1.

There are two settling time modes: fast and slow. Fast mode of a DAC pair is selected by setting S_XYto 1 and

slow mode is selected by setting S_XYto 0.

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REFERENCE

The DAC reference can be sourced internally or externally by programming bits D2 (R1) and D1 (R0) of the

CTRL0 register (address = 08h). If an external source of reference is applied to the REF pin, the device must be

configured to accept the external reference source by setting R1 and R0 to 00 or 01. If R1 and R0 is set to select

for internal reference, a voltage of 1.024 V (if R1 and R0 = 10) or 2.048 V (if R1 and R0 = 11) is available. The

internal reference can source up to 1 mA, therefore. it can be used as an external system reference. A

decoupling capacitor must be connected to the REF pin if internal reference is selected to ensure output stability.

A 1 µF to 10 µF capacitor in parallel to a 100 pF capacitor should be sufficient, see Figure 13.

(REF)

Pin 16

REF

TLV56xx

10 mF

100 pF

Figure 13. Reference Pin Decoupling Connection

BUFFERED AMPLIFIER

The DAC outputs are buffered by an amplifier with a gain of two, which are configurable as Class A (fast mode)

or Class AB (slow or low-power mode). The output buffers have near rail-to-rail output with short-circuit

protection, and can reliably drive a 2-kΩ load with a 100-pF load capacitance.

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PACKAGE OPTION ADDENDUM

www.ti.com

10-Mar-2011

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

TLV5630IDW

TLV5630IDWG4

TLV5630IPW

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Add to cart

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Add to cart

TSSOP

SOIC

Green (RoHS

& no Sb/Br)

TLV5630IPWG4

TLV5630IPWR

TLV5630IPWRG4

TLV5631IDW

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TLV5631IDWG4

TLV5631IDWR

TLV5631IDWRG4

TLV5631IPW

SOIC

Green (RoHS

& no Sb/Br)

SOIC

2000

Green (RoHS

& no Sb/Br)

SOIC

Green (RoHS

& no Sb/Br)

TSSOP

SOIC

Green (RoHS

& no Sb/Br)

TLV5631IPWG4

TLV5631IPWR

TLV5631IPWRG4

TLV5632IDW

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TLV5632IDWG4

TLV5632IDWR

SOIC

Green (RoHS

& no Sb/Br)

SOIC

2000

Green (RoHS

& no Sb/Br)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Mar-2011

Status ⁽¹⁾

ACTIVE

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

TLV5632IDWRG4

TLV5632IPW

SOIC

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Add to cart

TSSOP

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Add to cart

TLV5632IPWG4

TLV5632IPWR

TLV5632IPWRG4

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jan-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV5630IPWR

TLV5631IDWR

TLV5631IPWR

TLV5632IDWR

TLV5632IPWR

TSSOP

SOIC

2000

330.0

16.4

24.4

16.4

24.4

16.4

6.95

10.8

6.95

10.8

6.95

7.1

13.3

7.1

1.6

2.7

1.6

2.7

1.6

8.0

12.0

8.0

16.0

24.0

16.0

24.0

16.0

TSSOP

SOIC

13.3

7.1

12.0

8.0

TSSOP

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jan-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLV5630IPWR

TLV5631IDWR

TLV5631IPWR

TLV5632IDWR

TLV5632IPWR

TSSOP

SOIC

2000

367.0

38.0

45.0

38.0

45.0

38.0

TSSOP

SOIC

TSSOP

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

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supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

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e2e.ti.com

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TLV5630IDWG4 [TI]

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