TLV61070A [TI]
具有 0.5V 超低输入电压的 5V、2A 升压转换器;
| 型号： | TLV61070A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 0.5V 超低输入电压的 5V、2A 升压转换器 升压转换器 |
| 文件： | 总23页 (文件大小：2736K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV61070A
ZHCSP20 –SEPTEMBER 2022
TLV61070A 具有0.5V 超低输入电压的2.5A 升压转换器
1 特性
3 说明
• 输入电压范围：0.5V 至5.5V
• 启动时的最小输入电压为1.3V
• 输出电压设置范围：2.2V 至5.5V
• 两个69mΩ(LS)/89mΩ(HS) MOSFET
• 2.5A 谷值开关电流限制
TLV61070A 器件是一款具有 0.5V 超低输入电压的同
步升压转换器。该器件可以为由多种电池和超级电容器
供电的便携式设备和智能设备提供电源解决方案。在整
个温度范围内，TLV61070A 具有 2.5A 的典型谷值开
关电流限制。在 0.5V 至 5.5V 的宽输入电压范围内，
TLV61070A 支持超级电容器备用电源应用，这可能导
致超级电容器深度放电。
• VIN = 3.6V、VOUT = 5V 且IOUT = 1.0 A 时效率为
92.3%
• VIN > 1.5V 时开关频率为1MHz，VIN < 1V 时开关
频率为0.55MHz
• VIN 和SW 关断电流典型值为0.1µA
• 在–40°C 至+125°C 温度范围内，基准电压精度
为±2.5%
• 轻负载下采用自动PFM 运行模式
• VIN > VOUT 时切换为直通模式
• 在关断期间真正断开输入域输出之间的连接
• 输出过压和热关断保护
• 输出短路保护
• 2.9mm × 1.6mm SOT23-6 (DDC) 6 引脚封装
当输入电压高于 1.5V 时，TLV61070A 的工作频率为
1MHz。当输入电压低于1.5V 甚至降至1V 时，开关频
率逐渐降至 0.55MHz。TLV61070A 在轻负载条件下会
进入省电模式，以便在整个负载电流范围内保持高效
率。在轻负载条件下，TLV61070A 在 VOUT 处消耗
20µA 的静态电流。在关断期间，TLV61070A 与输入
电源完全断开，仅消耗 0.1µA 的电流，从而能够实现
较长的电池寿命。TLV61070A 具有 5.7V 输出过压保
护、输出短路保护和热关断保护。
TLV61070A 采用 2.9mm × 1.6mm SOT23-6 (DBV) 封
装，更大限度地减少了外部元件的数量，因而拥有非常
小巧的解决方案尺寸。
2 应用
• 电子货架标签
• 可视门铃
• 远程控制器
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TLV61070A
SOT-23 (6)
2.90mm × 1.60mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
L1
2.7 V ~ 4.35 V
C1
VIN
SW
5.0 V
VOUT
GND
C2
TLV61070A
R1
R2
FB
EN
ON
OFF
典型应用电路
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSGK6
TLV61070A
ZHCSP20 –SEPTEMBER 2022
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes............................................9
8 Application and Implementation.................................. 11
8.1 Application Information..............................................11
8.2 Typical Application.................................................... 11
8.3 Power Supply Recommendations.............................16
8.4 Layout....................................................................... 16
9 Device and Documentation Support............................18
9.1 Device Support......................................................... 18
9.2 接收文档更新通知..................................................... 18
9.3 支持资源....................................................................18
9.4 Trademarks...............................................................18
9.5 Electrostatic Discharge Caution................................18
9.6 术语表....................................................................... 18
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................6
7 Detailed Description........................................................7
7.1 Overview.....................................................................7
7.2 Functional Block Diagram...........................................7
7.3 Feature Description.....................................................8
Information.................................................................... 18
4 Revision History
DATE
REVISION
NOTES
September 2022
*
Initial release
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5 Pin Configuration and Functions
1
6
5
SW
GND
EN
VIN
2
VOUT
FB
3
4
图5-1. DBV Package 6-Pin SOT236 Top View
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
The switch pin of the converter. It is connected to the drain of the internal low-side power
MOSFET and the source of the internal high-side power MOSFET.
1
SW
PWR
2
3
4
GND
EN
PWR
Ground pin of the IC
Enable logic input. Logic high voltage enables the device. Logic low voltage disables the
device and turns it into shutdown mode.
I
I
FB
Voltage feedback of adjustable output voltage
5
6
VOUT
VIN
PWR
I
Boost converter output
IC power supply input
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.7
–0.7
–40
–65
MAX
7
UNIT
V
VIN, EN, FB, SW, VOUT
Voltage range at terminals(2)
SW spike at 10ns
SW spike at 1ns
8
V
9
V
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0.5
2.2
0.7
1.0
4
NOM
MAX
5.5
UNIT
VIN
VOUT
L
Input voltage range
V
V
Output voltage setting range
Effective inductance range
Effective input capacitance range
Effective output capacitance range
Operating junction temperature
5.5
1.0
4.7
10
6.1
µH
µF
µF
°C
CIN
COUT
TJ
1000
125
–40
6.4 Thermal Information
TLV61070A
DBV - 6 PINS
Standard
139.1
THERMAL METRIC(1)
UNIT
RθJA
RθJC
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
34.8
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
42.5
1.4
40.7
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 3.6 V and VOUT = 5.0 V. Typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VIN
Input voltage range
0.5
5.5
1.3
0.5
V
V
V
VIN rising
VIN falling
1.0
0.4
VIN_UVLO
Under-voltage lockout threshold
IC enabled, No load, No switching VIN
=
Quiescent current into VIN pin
1.3 V to 5.5 V, VFB = VREF + 0.1 V, TJ up
to 85°C
0.9
3.0
µA
IQ
IC enabled, No load, No switching VOUT
2.2 V to 5.5 V, VFB = VREF + 0.1 V, TJ up
to 85°C
=
Quiescent current into VOUT pin
20
30
µA
µA
ISD
Shutdown current into VIN and SW pin
IC disabled, VIN = VSW = 3.6 V, TJ = 25°C
0.1
0.2
OUTPUT
VOUT
Output voltage setting range
2.2
5.5
V
mV
mV
V
PWM mode
PFM mode
485
500
505
5.7
0.1
4
515
VREF
Reference voltage at the FB pin
VOVP
Output over-voltage protection threshold VOUT rising
Over-voltage protection hysteresis
5.5
6.0
VOVP_HYS
IFB_LKG
V
Leakage current at FB pin
50
3
nA
IC disabled, VIN = 0 V, VSW = 0 V, VOUT
5.5 V, TJ = 25°C
=
IVOUT_LKG
Leakage current into VOUT pin
Soft startup time
1
µA
From active EN to VOUT regulation.
VIN = 2.5 V, VOUT = 5.0 V, COUT_EFF
=
tSS
750
μs
10μF, IOUT = 0
POWER SWITCH
High-side MOSFET on resistance
Low-side MOSFET on resistance
VOUT = 5.0 V
89
69
mohm
mohm
MHz
MHz
ns
RDS(on)
VOUT = 5.0 V
VIN = 3.6 V, VOUT = 5.0 V, PWM mode
VIN = 1.0 V, VOUT = 5.0 V, PWM mode
1.0
0.55
96
fSW
Switching frequency
tON_min
tOFF_min
ILIM_SW
Minimum on time
Minimum off time
Valley current limit
40
130
120
80
ns
VIN = 3.6 V, VOUT = 5.0 V,TJ = 25°C
2.00
1.80
2.45
A
VIN = 3.6 V, VOUT = 5.0 V,TJ = –40°C to
125°C
ILIM_SW
Valley current limit
Pre-charge current
2.45
A
VIN = 1.3 - 5.5 V, VOUT < 0.4 V
VIN = 2.4 V, VOUT = 2.15 V
100
200
185
385
mA
mA
ILIM_CHG
LOGIC INTERFACE
VEN_H
EN logic high threshold
VIN > 1.3 V or VOUT > 2.2 V
VIN > 1.3 V or VOUT > 2.2 V
1.2
V
VEN_L
EN logic low threshold
0.35
0.42
0.45
PROTECTION
TSD
Thermal shutdown threshold
Thermal shutdown hysteresis
TJ rising
150
20
°C
°C
TSD_HYS
TJ falling below TSD
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6.6 Typical Characteristics
VIN = 3.6 V, VOUT = 5 V, TJ = 25°C, unless otherwise noted
100
95
90
85
80
5.15
5.1
5.05
5
VIN=1.3V
VIN=2.7V
VIN=3.3V
VIN=3.6V
VIN=4.2V
VIN=1.3 V
VIN=2.7 V
VIN=3.3 V
VIN=3.6 V
VIN=4.2V
75
70
4.95
0.0001
65
0.0001
0.001
0.01
0.05
0.2 0.5
1
2
0.001
0.01
0.05
0.2 0.5
1
2
Output Current (A)
Output Current (A)
VIN = 1.3 V, 2.7 V, 3.3 V, 3.6 V4.2 V; VOUT = 5 V
VIN = 1.3 V, 2.7 V, 3.3 V, 3.6 V4.2 V; VOUT = 5 V
图6-2. Load Regulation
图6-1. Load Efficiency with Different Input
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7 Detailed Description
7.1 Overview
The TLV61070A synchronous step-up converter is designed to operate from an input voltage supply range
between 0.5 V and 5.5 V with 2.5-A valley switch current limit. The TLV61070A typically operates at a quasi-
constant frequency pulse width modulation (PWM) at moderate to heavy load currents. The switching frequency
is 1 MHz when the input voltage is above 1.5 V. The switching frequency reduces down to 0.55 MHz gradually
when the input voltage goes down from 1.5 V to 1 V and keeps at 0.55 MHz when the input voltage is below 1 V.
At light load conditions, the TLV61070A converter operates in Power Save mode with pulse frequency
modulation (PFM). During PWM operation, the converter uses adaptive constant on-time valley current mode
control scheme to achieve excellent line regulation and load regulation and allows the use of a small inductor
and ceramic capacitors. Internal loop compensation simplifies the design process while minimizing the number
of external components.
7.2 Functional Block Diagram
SW
5
Undervoltage
Lockout
VIN
VOUT
VIN
3
6
VOUT
Valley Current Sense
EN
2
Gate Driver
Logic
4
GND
Thermal
Shutdown
PWM Control
1
FB
Overvoltage
Protection and Short
Circuit Protection
VOUT
EA
1
Soft Start-up
VREF
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7.3 Feature Description
7.3.1 Undervoltage Lockout
The TLV61070A has a built-in undervoltage lockout (UVLO) circuit to ensure the device working properly. When
the input voltage is above the UVLO rising threshold of 1.3 V, the TLV61070A can be enabled to boost the output
voltage. After the TLV61070A starts up and the output voltage is above 2.2 V, the TLV61070A works with input
voltage as low as 0.5 V.
7.3.2 Enable and Soft Start
When the input voltage is above the UVLO rising threshold and the EN pin is pulled to a voltage above 1.2 V, the
TLV61070A is enabled and starts up. At the beginning, the TLV61070A charges the output capacitors with a
current of about 185 mA when the output voltage is below 0.4 V. When the output voltage is charged above 0.4
V, the output current is changed to having output current capability to drive the 5-Ω resistance load. After the
output voltage reaches the input voltage, the TLV61070A starts switching, and the output voltage ramps up
further. The typical start-up time is 700 µs accounting from EN high to output, reaching target voltage for the
application with input voltage is 2.5 V. Output voltage is 5 V, output effective capacitance is 10 µF, and no load.
When the voltage at the EN pin is below 0.4 V, the internal enable comparator turns the device into Shutdown
mode. In shutdown mode, the device is entirely turned off. The output is disconnected from the input power
supply.
7.3.3 Switching Frequency
The TLV61070A switches at a quasi-constant 1-MHz frequency when the input voltage is above 1.5 V. When the
input voltage is lower than 1.5 V, the switching frequency is reduced gradually to 0.55 MHz to improve the
efficiency and get higher boost ratio. When the input voltage is below 1 V, the switching frequency is fixed at a
quasi-constant 0.55 MHz.
7.3.4 Current Limit Operation
The TLV61070A uses a valley current limit sensing scheme. Current limit detection occurs during the off time by
sensing of the voltage drop across the synchronous rectifier.
When the load current is increased such that the inductor current is above the current limit within the whole
switching cycle time, the off-time is increased to allow the inductor current to decrease to this threshold before
the next on time begins (so called frequency foldback mechanism). When the current limit is reached, the output
voltage decreases during further load increase.
The maximum continuous output current (IOUT(LC)) before entering current limit (CL) operation can be defined by
方程式1.
1
≈
’
IOUT(CL) = 1-D ì I
+
DIL P-P
(
)
LIM
∆
÷
◊
(
)
2
«
(1)
where
• D is the duty cycle
• ΔIL(P-P) is the inductor ripple current
The duty cycle can be estimated by 方程式2.
V
IN ì h
D = 1-
VOUT
(2)
where
• VOUT is the output voltage of the boost converter
• VIN is the input voltage of the boost converter
• ηis the efficiency of the converter, use 90% for most applications
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The peak-to-peak inductor ripple current is calculated by 方程式3.
V ìD
L ì fSW
IN
DIL P-P
=
(
)
(3)
where
• L is the inductance value of the inductor
• fSW is the switching frequency
• D is the duty cycle
• VIN is the input voltage of the boost converter
7.3.5 Pass-Through Operation
When the input voltage is higher than the setting output voltage, the output voltage is higher than the target
regulation voltage. When the output voltage is 101% of the setting target voltage, the TLV61070A stops
switching and fully turns on the high-side PMOS FET. The device works in pass-through mode. The output
voltage is the input voltage minus the voltage drop across the DCR of the inductor and the RDS(on) of the PMOS
FET. When the output voltage drops below the 97% of the setting target voltage as the input voltage declines or
the load current increases, the TLV61070A resumes switching again to regulate the output voltage.
7.3.6 Overvoltage Protection
The TLV61070A has an output overvoltage protection (OVP) to protect the device if the external feedback
resistor divider is wrongly populated. When the output voltage is above 5.7 V typically, the device stops
switching. Once the output voltage falls 0.1 V below the OVP threshold, the device resumes operating again.
7.3.7 Output Short-to-Ground Protection
The TLV61070A starts to limit the output current when the output voltage is below 1.8 V. The lower the output
voltage reaches, the smaller the output current is. When the VOUT pin is short to ground, and the output voltage
becomes less than 0.4 V, the output current is limited to approximately 185 mA. Once the short circuit is
released, the TLV61070A goes through the soft start-up again to the regulated output voltage.
7.3.8 Thermal Shutdown
The TLV61070A goes into thermal shutdown once the junction temperature exceeds 150°C. When the junction
temperature drops below the thermal shutdown recovery temperature, typically 130°C, the device starts
operating again.
7.4 Device Functional Modes
The TLV61070A has two switching operation modes: PWM mode in moderate to heavy load conditions and
power save mode with pulse frequency modulation (PFM) in light load conditions.
7.4.1 PWM Mode
The TLV61070A uses a quasi-constant 1.0-MHz frequency pulse width modulation (PWM) at moderate-to-heavy
load current. Based on the input voltage to output voltage ratio, a circuit predicts the required on time. At the
beginning of the switching cycle, the NMOS switching FET. The input voltage is applied across the inductor and
the inductor current ramps up. In this phase, the output capacitor is discharged by the load current. When the on
time expires, the main switch NMOS FET is turned off, and the rectifier PMOS FET is turned on. The inductor
transfers its stored energy to replenish the output capacitor and supply the load. The inductor current declines
because the output voltage is higher than the input voltage. When the inductor current hits the valley current
threshold determined by the output of the error amplifier, the next switching cycle starts again.
The TLV61070A has a built-in compensation circuit that can accommodate a wide range of input voltage, output
voltage, inductor value, and output capacitor value for stable operation.
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7.4.2 Power Save Mode
The TLV61070A integrates a Power Save mode with PFM to improve efficiency at light load. When the load
current decreases, the inductor valley current set by the output of the error amplifier no longer regulates the
output voltage. When the inductor valley current hits the low limit, the output voltage exceeds the setting voltage
as the load current decreases further. When the FB voltage hits the PFM reference voltage, the TLV61070A
goes into the Power Save mode. In Power Save mode, when the FB voltage rises and hits the PFM reference
voltage, the device continues switching for several cycles because of the delay time of the internal comparator,
then it stops switching. The load is supplied by the output capacitor, and the output voltage declines. When the
FB voltage falls below the PFM reference voltage, after the delay time of the comparator, the device starts
switching again to ramp up the output voltage.
Output voltage
PFM mode at light load
1.01 × VOUT_NOM
VOUT_NOM
PWM mode at heavy load
图7-1. Output Voltage in PWM Mode and PFM Mode
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TLV61070A is a synchronous boost converter designed to operate from an input voltage supply range
between 0.5 V and 5.5 V with a typical 2.5-A valley switch current limit. The TLV61070A typically operates at a
quasi-constant 1-MHz frequency PWM at moderate-to-heavy load currents when the input voltage is above 1.5
V. The switching frequency changes to 0.55 MHz gradually with the input voltage changing from 1.5 V to 1 V for
better efficiency and high step-up ratio. When the input voltage is below 1 V, the switching frequency is fixed at a
quasi-constant 0.55 MHz. At light load currents, the TLV61070A converter operates in Power Save mode with
PFM to achieve high efficiency over the entire load current range.
8.2 Typical Application
The TLV61070A provides a power supply solution for portable devices powered by batteries or backup
applications powered by super-capacitors. The TLV61070A can output 5 V and 1.0 A from a single-cell Li-ion
battery.
L1
2.7 V ~ 4.35 V
C1
VIN
SW
5.0 V
VOUT
GND
C2
TLV61070A
R1
R2
FB
EN
ON
OFF
图8-1. Li-ion Battery to 5-V Boost Converter
8.2.1 Design Requirements
The design parameters are listed in 表8-1.
表8-1. Design Parameters
PARAMETERS
Input voltage
VALUES
2.7 V to 4.35 V
5 V
Output voltage
Output current
1.0 A
Output voltage ripple
±50 mV
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8.2.2 Detailed Design Procedure
8.2.2.1 Setting the Output Voltage
The output voltage is set by an external resistor divider (R1, R2 in 图 8-1). When the output voltage is regulated,
the typical voltage at the FB pin is VREF. Thus, the resistor divider is determined by 方程式4.
≈
∆
«
’
VOUT
VREF
R1=
-1 ìR2
÷
◊
(4)
where
• VOUT is the regulated output voltage
• VREF is the internal reference voltage at the FB pin
For the best accuracy, keep R2 smaller than 100 kΩ to ensure the current flowing through R2 is at least 100
times larger than the FB pin leakage current. Changing R2 towards a lower value increases the immunity against
noise injection. Changing the R2 towards a higher value reduces the quiescent current for achieving highest
efficiency at low load currents.
8.2.2.2 Inductor Selection
Since the selection of the inductor affects steady-state operation, transient behavior, and loop stability, the
inductor is the most important component in power regulator design. There are three important inductor
specifications: inductor value, saturation current, and DC resistance (DCR).
The TLV61070A is designed to work with inductor values between 2.2 µH and 4.7 µH. Follow 方程式 5 to 方程式
7 to calculate the inductor peak current for the application. To calculate the current in the worst case, use the
minimum input voltage, maximum output voltage, and maximum load current of the application. To have enough
design margins, choose the inductor value with –30% tolerances and low power-conversion efficiency for the
calculation.
In a boost regulator, the inductor DC current can be calculated by 方程式5.
VOUT ìIOUT
IL DC
=
(
)
V ì h
IN
(5)
where
• VOUT is the output voltage of the boost converter
• IOUT is the output current of the boost converter
• VIN is the input voltage of the boost converter
• ηis the power conversion efficiency, use 90% for most applications
The inductor ripple current is calculated by 方程式6.
V ìD
L ì fSW
IN
DIL P-P
=
(
)
(6)
where
• D is the duty cycle, which can be calculated by 方程式2
• L is the inductance value of the inductor
• fSW is the switching frequency
• VIN is the input voltage of the boost converter
Therefore, the inductor peak current is calculated by 方程式7.
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DIL P-P
(
)
IL P = IL DC
+
(
)
(
)
2
(7)
Normally, it is advisable to work with an inductor peak-to-peak current of less than 40% of the average inductor
current for maximum output current. A smaller ripple from a larger valued inductor reduces the magnetic
hysteresis losses in the inductor and EMI. But in the same way, load transient response time is increased. The
saturation current of the inductor must be higher than the calculated peak inductor current. 表 8-2 lists the
recommended inductors for the TLV61070A.
表8-2. Recommended Inductors for the TLV61070A
DCR MAX
(mΩ)
SATURATION CURRENT
(A)
PART NUMBER(1)
L (µH)
SIZE (LxWxH)
VENDOR
XGL4030-222ME
74438357022
2.2
2.2
15.0
13.5
7.0
7.0
4.0 × 4.0 × 3.1
4.1 x 4.1 x 3.1
Coilcraft
Wurth Elecktronik
(1) See the Third-party Products disclaimer.
8.2.2.3 Output Capacitor Selection
The output capacitor is mainly selected to meet the requirements for output ripple and loop stability. The ripple
voltage is related to capacitor capacitance and its equivalent series resistance (ESR). Assuming a ceramic
capacitor with zero ESR, the minimum capacitance needed for a given ripple voltage can be calculated by 方程
式8.
IOUT ìDMAX
fSW ì VRIPPLE
COUT
=
(8)
where
• DMAX is the maximum switching duty cycle
• VRIPPLE is the peak-to-peak output ripple voltage
• IOUT is the maximum output current
• fSW is the switching frequency
The ESR impact on the output ripple must be considered if tantalum or aluminum electrolytic capacitors are
used. The output peak-to-peak ripple voltage caused by the ESR of the output capacitors can be calculated by
方程式9.
VRIPPLE(ESR) = IL(P) ìRESR
(9)
Take care when evaluating the derating of a ceramic capacitor under DC bias voltage, aging, and AC signal. For
example, the DC bias voltage can significantly reduce capacitance. A ceramic capacitor can lose more than 50%
of its capacitance at its rated voltage. Therefore, always leave margin on the voltage rating to ensure adequate
capacitance at the required output voltage. Increasing the output capacitor makes the output ripple voltage
smaller in PWM mode.
TI recommends using the X5R or X7R ceramic output capacitor in the range of 4-μF to 1000-μF effective
capacitance. The output capacitor affects the small signal control loop stability of the boost regulator. If the
output capacitor is below the range, the boost regulator can potentially become unstable. Increasing the output
capacitor makes the output ripple voltage smaller in PWM mode.
8.2.2.4 Loop Stability, Feedforward Capacitor Selection
When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows
oscillations, the regulation loop can be unstable.
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The load transient response is another approach to check the loop stability. During the load transient recovery
time, VOUT can be monitored for settling time, overshoot or ringing that helps judge the stability of the converters.
Without any ringing, the loop has usually more than 45° of phase margin.
A feedforward capacitor (C3 in the 图 8-2) in parallel with R1 induces a pair of zero and pole in the loop transfer
function. By setting the proper zero frequency, the feedforward capacitor can increase the phase margin to
improve the loop stability. For large output capacitance more than 40 μF application, TI recommends a
feedforward capacitor to set the zero frequency (fFFZ) to 1 kHz. As for the input voltage lower than 1-V
application, TI recommends to use the effective output capacitance is about 100 µF and set the zero frequency
(fFFZ) to 1 kHz. The value of the feedforward capacitor can be calculated by 方程式10.
1
C3 =
2pì fFFZ ìR1
(10)
where
• R1 is the resistor between the VOUT pin and FB pin
• fFFZ is the zero frequency created by the feedforward capacitor
L1
C1
VIN
SW
VOUT
GND
C2
C3
TLV61070A
R1
R2
FB
EN
ON
OFF
图8-2. TLV61070A Circuit With Feedforward Capacitor
8.2.2.5 Input Capacitor Selection
Multilayer X5R or X7R ceramic capacitors are excellent choices for the input decoupling of the step-up converter
as they have extremely low ESR and are available in small footprints. Input capacitors must be located as close
as possible to the device. While a 10-μF input capacitor is sufficient for most applications, larger values may be
used to reduce input current ripple without limitations. Take care when using only ceramic input capacitors.
When a ceramic capacitor is used at the input and the power is being supplied through long wires, a load step at
the output can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop
instability or could even damage the part. In this circumstance, place additional bulk capacitance (tantalum or
aluminum electrolytic capacitor) between the ceramic input capacitor and the power source to reduce ringing that
can occur between the inductance of the power source leads and ceramic input capacitor.
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8.2.3 Application Curves
Vout(5V o set)
20mV/div
Vout(5V o set)
50mV/div
Inductor Current
500mA/div
Inductor Current
500mA/div
SW
2V/div
SW
2V/div
Time Scale: 500ns/div
VIN = 3.6 V, VOUT = 5 V, IOUT = 1 A
Time Scale: 5μs/div
VIN = 3.6 V, VOUT = 5 V, IOUT = 50 mA
图8-3. Switching Waveform at Heavy Load
图8-4. Switching Waveform at Light Load
EN
EN
2.0V/div
2.0V/div
Vout
2.0V/div
Vout
2.0V/div
Inductor Current
200mA/div
Inductor Current
200mA/div
Time Scale: 200 s/div
Time Scale: 10 s/div
VIN = 3.6 V, VOUT = 5 V, 250 mA load current
VIN = 3.6 V, VOUT = 5 V, 250 mA load current
图8-5. Start-Up Waveform
图8-6. Shutdown Waveform
Vout (5V o set)
200mV/div
Vout (5V o set)
500mV/div
Output Current
500mA/div
Vin
1V/div
Time Scale: 100μs/div
Time Scale: 200μs/div
VIN = 3.6 V, VOUT = 5 V, IOUT = 800 mA to 1.5 A with 20-μs
VIN = 2.7 V to 4.35 V with 20-μs slew rate, VOUT = 5 V
slew rate
IOUT = 1 A
图8-7. Load Transient
图8-8. Line Transient
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Vin
1V/div
Vout (5V o set)
100mV/div
Vout (5V o set)
100mV/div
Output Current
500mA/div
Inductor Current
1A/div
Time Scale: 2ms/div
Time Scale: 10ms/div
VIN = 3.6 V, VOUT = 5 V, IOUT = 0 A to 1.5 A Sweep
VIN = 0 V to 4.35 V Sweep, VOUT = 5 V, 250 mA load current
图8-9. Load Sweep
图8-10. Line Sweep
Vout
2V/div
SW
2V/div
Vout
2V/div
SW
2V/div
Inductor Current
1A/div
Inductor Current
1A/div
Time Scale: 5 s/div
Time Scale: 100 s/div
VIN = 3.6 V, VOUT = 5 V, IOUT = 250 mA
VIN = 3.6 V, VOUT = 5 V, IOUT = 250 mA
图8-12. Output Short Protection (Recover)
图8-11. Output Short Protection (Entry)
8.3 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 0.5 V to 5.5 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the converter, additional bulk
capacitance may be required in addition to the ceramic bypass capacitors. A typical choice is a tantalum or
aluminum electrolytic capacitor with a value of 100 μF. Output current of the input power supply must be rated
according to the supply voltage, output voltage, and output current of the TLV61070A.
8.4 Layout
8.4.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design, especially at high-peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.
Use a common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at any place close to the ground pin of the IC.
The feedback divider should be placed as close as possible to the ground pin of the IC. To lay out the control
ground, it is recommended to use short traces as well, separated from the power ground traces. This avoids
ground shift problems, which can occur due to superimposition of power ground current and control ground
current.
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8.4.2 Layout Example
图8-13. PCB Layout
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9 Device and Documentation Support
9.1 Device Support
9.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
9.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV61070ADBVR
ACTIVE
SOT-23
DBV
6
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
2N5F
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
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EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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相关型号：
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