TLV6742SIRUGR [TI]

TLV6741, TLV6742, TLV6744 10-MHz, Low Broadband Noise, RRO, Operational Amplifier;
TLV6742SIRUGR
型号: TLV6742SIRUGR
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

TLV6741, TLV6742, TLV6744 10-MHz, Low Broadband Noise, RRO, Operational Amplifier

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TLV6741, TLV6742  
SBOS817G JUNE 2017REVISED APRIL 2020  
TLV6741, TLV6742, TLV6744 10-MHz, Low Broadband Noise, RRO, Operational Amplifier  
1 Features  
3 Description  
The TLV674x family includes single (TLV6741), dual  
(TLV6742), and quad-channel (TLV6744) general-  
purpose CMOS operational amplifiers (op amp) that  
provide a low noise figure of 3.5 nV/Hz and a wide  
bandwidth of 10 MHz. The low noise and wide  
bandwidth make the TLV674x family of devices  
attractive for a variety of precision applications that  
1
Low broadband noise: 3.5 nV/Hz  
Gain bandwidth: 10 MHz  
Low input bias current: ±3 pA  
Low offset voltage: 0.15 mV  
Low offset voltage drift: ±0.2 µV/°C  
Rail-to-rail output  
require  
a
good balance between cost and  
performance. Additionally, the input bias current of  
the TLV674x family supports applications with high  
source impedance.  
Unity-gain stable  
Low IQ:  
TLV6741: 890 µA/ch  
TLV6742/4: 990 µA/ch  
The robust design of the TLV674x family provides  
ease-of-use to the circuit designer due to its unity-  
gain stability, integrated RFI/EMI rejection filter, no  
phase reversal in overdrive conditions and high  
electrostatic discharge (ESD) protection (2-kV HBM).  
Wide supply range:  
TLV6741: 2.25 V to 5.5 V  
TLV6742/4: 1.7 V to 5.5 V  
Additionally,  
the  
resistive  
open-loop  
output  
Robust EMIRR performance: 71 dB at 2.4 GHz  
impedance makes them easy to stabilize with much  
higher capacitive loads.  
2 Applications  
This op amp family is optimized for low-voltage  
operation as low as 2.25 V (±1.125 V) for the  
TLV6741 and 1.7 V (±0.85 V) for the TLV6742 and  
TLV6744. All of the devices operate up to 5.5 V  
(±2.75 V), and are specified over the temperature  
range of –40°C to 125°C.  
Solid state drive  
Wearables (non-medical)  
Professional audio amplifier (rack mount)  
Transimpedance Amplifier Circuit  
Test & measurement  
The single-channel TLV6741 is available in a small-  
size SC70-5 package. The dual-channel TLV6742 is  
available in multiple package options including a tiny  
1.5 mm × 2.0 mm X2QFN package.  
Motor drives  
Pressure transmitter  
Lab & field instrumentation  
Bridge amplifier circuit  
Gaming applications  
Device Information(1)  
PART NUMBER  
PACKAGE  
BODY SIZE (NOM)  
1.25 mm × 2.00 mm  
3.91 mm × 4.90 mm  
3.00 mm × 4.40 mm  
1.60 mm × 2.90 mm  
2.00 mm × 2.00 mm  
1.50 mm × 2.00 mm  
TLV6741  
SC70 (5)  
Noise Spectral Density vs Frequency  
SOIC (8)  
100  
70  
TSSOP (8)  
SOT-23 (8)  
WSON (8)  
X2QFN (10)(2)  
TLV6742  
50  
30  
20  
TLV6742S  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
10  
7
(2) Package is for preview only.  
5
3
2
1
10  
100  
1k  
Frequency (Hz)  
10k  
100k  
D012  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
 
 
 
 
 
 
 
 
 
 
TLV6741, TLV6742  
SBOS817G JUNE 2017REVISED APRIL 2020  
www.ti.com  
Table of Contents  
8.4 Device Functional Modes........................................ 32  
Application and Implementation ........................ 33  
9.1 Application Information............................................ 33  
1
2
3
4
5
6
7
Features.................................................................. 1  
Applications ........................................................... 1  
Description ............................................................. 1  
Revision History..................................................... 2  
Device Comparison Table..................................... 3  
Pin Configuration and Functions......................... 4  
Specifications......................................................... 6  
7.1 Absolute Maximum Ratings ...................................... 6  
7.2 ESD Ratings ............................................................ 6  
7.3 Recommended Operating Conditions....................... 6  
7.4 Thermal Information for Single Channel ................... 6  
7.5 Thermal Information for Dual Channel...................... 7  
7.6 Electrical Characteristics........................................... 8  
7.7 TLV6741: Typical Characteristics ........................... 12  
7.8 TLV6742: Typical Characteristics ........................... 20  
Detailed Description ............................................ 27  
8.1 Overview ................................................................. 27  
8.2 Functional Block Diagram ....................................... 27  
8.3 Feature Description................................................. 27  
9
9.2 Single-Supply Electret Microphone Preamplifier With  
Speech Filter............................................................ 33  
10 Power Supply Recommendations ..................... 36  
11 Layout................................................................... 36  
11.1 Layout Guidelines ................................................. 36  
11.2 Layout Example .................................................... 37  
12 Device and Documentation Support ................. 38  
12.1 Device Support...................................................... 38  
12.2 Receiving Notification of Documentation Updates 38  
12.3 Related Links ........................................................ 38  
12.4 Support Resources ............................................... 38  
12.5 Trademarks........................................................... 38  
12.6 Electrostatic Discharge Caution............................ 38  
12.7 Glossary................................................................ 38  
8
13 Mechanical, Packaging, and Orderable  
Information ........................................................... 38  
4 Revision History  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
Changes from Revision F (January 2020) to Revision G  
Page  
Added end equipment links in Applications section ............................................................................................................... 1  
Deleted preview tags for TSSOP, SOT-23, WSON, and X2QFN packages in Device Information section ......................... 1  
Deleted VSSOP (8) package in Device Information section .................................................................................................. 1  
Added preview tag to TLV6742S X2QFN in Device Information section .............................................................................. 1  
Deleted VSSOP (DGK) in Device Comparison Table section................................................................................................ 3  
Added preview tag to X2QFN in Device Comparison Table ................................................................................................. 3  
Deleted DGK package in pin out drawing for TLV6742 packages in Pin Configuration and Functions section ................... 4  
Deleted DGK VSSOP in Thermal Information for Dual Channel section ............................................................................... 6  
Added shutdown electrical characteristic information ........................................................................................................... 9  
Deleted Example layout for VSSOP-8 (DGK) package in Layout Example section ............................................................ 37  
Changes from Revision E (December 2019) to Revision F  
Page  
Deleted TLV6744 product folder link from the data sheet page header ................................................................................ 1  
Changes from Revision D (January 2019) to Revision E  
Page  
Added IQ definition for TLV6742 and TLV744 in Features section......................................................................................... 1  
Added EMIRR, Supply Range, IQ, and Offset Voltage Drift to Features section.................................................................... 1  
Changed Noise Spectral Density vs Frequency plot on front page to the TLV6742 and TLV6744 noise plot ...................... 1  
Changed wording of Description section to incorporate release of TLV6742 and TLV6744 devices ................................... 1  
Changed TLV6742 packages in Device Information.............................................................................................................. 1  
Added Device Comparison Table section .............................................................................................................................. 3  
Added note regarding single supply operation to Pin Functions: TLV6741 table .................................................................. 4  
2
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Copyright © 2017–2020, Texas Instruments Incorporated  
Product Folder Links: TLV6741 TLV6742  
 
TLV6741, TLV6742  
www.ti.com  
SBOS817G JUNE 2017REVISED APRIL 2020  
Added pin out drawings for TLV6742 packages in Pin Configuration and Functions section................................................ 4  
Added pin functions for TLV6742 packages........................................................................................................................... 4  
Added X2QFN Package Drawing and Pin Functions for TLV6742S in Pin Configuration and Functions section................. 5  
Changed combined the TLV6741 and TLV6742 Absolute Maximum Ratings, ESD Ratings, Recommended  
Operating Conditions, Thermal Information, and Electrical Characteristics in the Specifications section ............................. 6  
Added TLV6742 typical characteristic graphs in the Specifications section ........................................................................ 19  
Changed wording throughout Detailed Description section to incorporate addition of TLV6742 and TLV6744 devices..... 27  
Added EMI Rejection section with description information to Detailed Description section................................................. 28  
Added Electrical Overstress section and diagram to Detailed Description section.............................................................. 29  
Added Typical Specification and Distributions section to Detailed Description section ....................................................... 30  
Added Shutdown Function section with description for TLV6742S to Detailed Description section.................................... 31  
Added Packages With an Exposed Thermal Pad section to Detailed Description section.................................................. 31  
Changed wording in Application and Implementation section to include the addition of TLV6742 and TLV6744............... 33  
Added TLV6742 and TLV6744 information to Power Supply Recommendations section ................................................... 36  
Changes from Revision C (October 2017) to Revision D  
Page  
Changed Operating temperature from 125 to 150 in Absolute Maximum Ratings ............................................................... 6  
Added Junction temperature spec to Absolute Maximum Ratings......................................................................................... 6  
Changes from Revision B (October 2017) to Revision C  
Page  
Added test conditions to input offset voltage parameter in Electrical Characteristics table................................................... 8  
Changed typical input current noise density value from 2 fAHZ to 23 fAHz ...................................................................... 8  
Changed total supply voltage total from 5V to 5.5V in Electrical Characteristics condition statement .................................. 8  
Deleted "Vs = 2.25 V to 5.5 V" test conditions for common-mode rejection ratio parameter in Electrical Characteristics .... 8  
Added Table 1 ..................................................................................................................................................................... 11  
Deleted "CL = 0" test condition from Figure 25 and Figure 26, Figure 27 and Figure 28 .................................................... 16  
Changed voltage step from 5 V to 2 V in Figure 32 ............................................................................................................ 17  
Changes from Revision A (September 2017) to Revision B  
Page  
Changed Human-body model (HBM) value from: ±1000 to ±3000 and Charged-device mode (CDM) value  
from ±250 to ±1000 ................................................................................................................................................................ 6  
Changes from Original (June 2017) to Revision A  
Page  
Changed device document status from: Advance Information to: Production Data............................................................... 1  
5 Device Comparison Table  
PACKAGE LEADS  
WSON TSSOP  
NO. OF  
CHANNELS  
DEVICE  
SOIC  
D
SC-70  
DCK  
SOT-23  
DDF  
X2QFN(1)  
RUG  
DSG  
PW  
8
TLV6741  
TLV6742  
TLV6742S  
1
2
8
5
8
8
10  
(1) Package is preview only.  
Copyright © 2017–2020, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Links: TLV6741 TLV6742  
TLV6741, TLV6742  
SBOS817G JUNE 2017REVISED APRIL 2020  
www.ti.com  
6 Pin Configuration and Functions  
TLV6741 DCK Package  
5-Pin SC70  
Top View  
IN+  
Vœ  
1
2
3
5
V+  
INœ  
4
OUT  
Not to scale  
Pin Functions: TLV6741  
PIN  
I/O  
DESCRIPTION  
NAME  
IN+  
NO.  
1
I
Noninverting input  
Inverting input  
IN–  
3
I
OUT  
V+  
4
O
Output  
5
Positive (highest) supply  
V–  
2
Negative (lowest) supply or ground (for single-supply operation)  
TLV6742 D, PW, DDF Packages  
8-Pin SOIC, TSSOP, SOT-23  
Top View  
TLV6742 DSG Package  
8-Pin WSON With Exposed Thermal Pad  
Top View  
OUT1  
IN1œ  
IN1+  
Vœ  
1
2
3
4
8
7
6
5
V+  
OUT1  
IN1œ  
IN1+  
Vœ  
1
2
3
4
8
7
6
5
V+  
OUT2  
IN2œ  
IN2+  
OUT2  
IN2œ  
IN2+  
Thermal  
Pad  
Not to scale  
Not to scale  
Connect thermal pad to V–. See Packages  
With an Exposed Thermal Pad for more  
information.  
Pin Functions: TLV6742  
PIN  
I/O  
DESCRIPTION  
NAME  
NO.  
2
IN1–  
IN1+  
IN2–  
IN2+  
OUT1  
OUT2  
V–  
I
I
Inverting input, channel 1  
Noninverting input, channel 1  
Inverting input, channel 2  
Noninverting input, channel 2  
Output, channel 1  
3
6
I
5
I
1
O
O
7
Output, channel 2  
4
Negative (lowest) supply or ground (for single-supply operation)  
4
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Copyright © 2017–2020, Texas Instruments Incorporated  
Product Folder Links: TLV6741 TLV6742  
TLV6741, TLV6742  
www.ti.com  
SBOS817G JUNE 2017REVISED APRIL 2020  
Pin Functions: TLV6742 (continued)  
PIN  
I/O  
DESCRIPTION  
NAME  
NO.  
V+  
8
Positive (highest) supply  
TLV6742S RUG Package  
10-Pin X2QFN  
Top View  
Vœ  
SHDN1  
SHDN2  
IN2+  
1
2
3
4
9
8
7
6
IN1œ  
OUT1  
V+  
OUT2  
Not to scale  
(1) Package is preview only  
Pin Functions: TLV6742S  
PIN  
I/O  
DESCRIPTION  
NAME  
X2QFN  
IN1–  
IN1+  
IN2–  
IN2+  
OUT1  
OUT2  
9
10  
5
I
I
Inverting input, channel 1  
Noninverting input, channel 1  
Inverting input, channel 2  
Noninverting input, channel 2  
Output, channel 1  
I
4
I
8
O
O
6
Output, channel 2  
Shutdown: low = amp disabled, high = amp enabled. Channel 1. See Shutdown Function  
section for more information.  
SHDN1  
SHDN2  
2
3
I
I
Shutdown: low = amp disabled, high = amp enabled. Channel 2. See Shutdown Function  
section for more information.  
V–  
V+  
1
7
I or —  
I
Negative (lowest) supply or ground (for single-supply operation)  
Positive (highest) supply  
Copyright © 2017–2020, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Links: TLV6741 TLV6742  
TLV6741, TLV6742  
SBOS817G JUNE 2017REVISED APRIL 2020  
www.ti.com  
7 Specifications  
7.1 Absolute Maximum Ratings  
over operating ambient temperature range (unless otherwise noted)  
(1)  
MIN  
0
MAX  
6
UNIT  
V
Supply voltage, VS = (V+) – (V–)  
(2)  
Common-mode voltage  
(V–) – 0.5  
(V+) + 0.5  
VS + 0.2  
10  
V
(2)  
Signal input pins  
Differential voltage  
V
(2)  
Current  
–10  
–55  
–65  
mA  
(3)  
Output short-circuit  
Continuous  
Operating ambient temperature, TA  
Junction temperature, TJ  
150  
150  
150  
°C  
°C  
°C  
Storage temperature, Tstg  
(1) Operating the device beyond the ratings listed under Absolute Maximum Ratings will cause permanent damage to the device. These are  
stress ratings only, based on process and design limitations, and this device has not been designed to function outside the conditions  
indicated under Recommended Operating Conditions. Exposure to any condition outside Recommended Operating Conditions for  
extended periods, including absolute-maximum-rated conditions, may affect device reliability and performance.  
(2) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be  
current limited to 10 mA or less.  
(3) Short-circuit to ground, one amplifier per package.  
7.2 ESD Ratings  
VALUE  
±3000  
±2000  
UNIT  
(1)  
(1)  
TLV6741: Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001  
TLV6742: Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001  
V(ESD)  
Electrostatic discharge  
V
All Devices: Charged-device model (CDM), per JEDEC specification JESD22-C101  
±1500  
(2)  
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.  
7.3 Recommended Operating Conditions  
over operating ambient temperature range (unless otherwise noted)  
MIN  
MAX  
5.5  
UNIT  
VS  
VS  
VI  
Supply voltage, (V+) – (V–) , for TLV6742 and TLV6744  
Supply voltage, (V+) – (V–), for TLV6741 only  
Input voltage range  
1.7(1)  
2.25  
(V–)  
–40  
V
V
5.5  
(V+) – 1.2  
125  
V
TA  
Specified temperature  
°C  
(1) Operation between 1.7V and 1.8V is only recommened for TA = 0 - 85  
7.4 Thermal Information for Single Channel  
TLV6741  
DCK  
(SC70)  
(1)  
THERMAL METRIC  
UNIT  
5 PINS  
240.9  
151.7  
64  
RθJA  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
/W  
/W  
/W  
/W  
/W  
/W  
RθJC(top)  
RθJB  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
34.8  
63.3  
n/a  
ψJB  
RθJC(bot)  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report SPRA953C.  
6
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Copyright © 2017–2020, Texas Instruments Incorporated  
Product Folder Links: TLV6741 TLV6742  
 
TLV6741, TLV6742  
www.ti.com  
SBOS817G JUNE 2017REVISED APRIL 2020  
7.5 Thermal Information for Dual Channel  
TLV6742, TLV6742S  
(2)  
D
DDF  
(SOT-23-8)  
DSG  
(WSON)  
PW  
(TSSOP)  
RUG  
(1)  
THERMAL METRIC  
(SOIC)  
UNIT  
(X2QFN)  
8 PINS  
8 PINS  
8 PINS  
8 PINS  
10 PINS  
Junction-to-ambient thermal  
resistance  
RθJA  
131.1  
73.2  
74.5  
24.4  
73.3  
n/a  
153.8  
78.2  
185.6  
140.3  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
Junction-to-case (top) thermal  
resistance  
RθJC(top)  
RθJB  
80.2  
73.1  
6.6  
97.5  
44.6  
4.7  
74.5  
116.3  
12.6  
114.6  
n/a  
52.6  
69.7  
1.0  
Junction-to-board thermal  
resistance  
Junction-to-top characterization  
parameter  
ψJT  
Junction-to-board characterization  
parameter  
ψJB  
72.7  
n/a  
44.6  
19.8  
67.5  
n/a  
Junction-to-case (bottom) thermal  
resistance  
RθJC(bot)  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report, SPRA953C.  
(2) This package option is preview for TLV6742.  
Copyright © 2017–2020, Texas Instruments Incorporated  
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7
Product Folder Links: TLV6741 TLV6742  
TLV6741, TLV6742  
SBOS817G JUNE 2017REVISED APRIL 2020  
www.ti.com  
7.6 Electrical Characteristics  
TLV6742/4 Specifications: VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V) at TA = 25°C, RL = 10 kconnected to VS /  
2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.  
TLV6741 Specifications: VS = (V+) – (V–) = 5.5 V at TA = 25°C, RL = 10 kconnected to VS / 2, VCM = VS / 2, and VOUT = VS  
/ 2, unless otherwise noted.  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
OFFSET VOLTAGE  
±0.15  
±1.0  
±1.2  
VOS  
Input offset voltage  
VS = 5.0 V  
mV  
TA = –40°C to 125°C  
TA = –40°C to 125°C  
TLV6742/4(1)  
TLV6741(2)  
TLV6742/4(1)  
TLV6741(2)  
TLV6742/4(1)  
±0.35  
±0.2  
±0.32  
±0.7  
130  
dVOS/dT  
PSRR  
Input offset voltage drift  
µV/℃  
VCM = V–  
VCM = V–  
f = 20 kHz  
±6.3  
±5.8  
Input offset voltage  
versus power supply  
μV/V  
Channel separation  
dB  
INPUT BIAS CURRENT  
TLV6741(2)  
TLV6742/4(1)  
TLV6741(2)  
TLV6742/4(1)  
±10  
±3  
IB  
Input bias current  
pA  
pA  
±10  
±0.5  
IOS  
Input offset current  
Input voltage noise  
NOISE  
EN  
1.2  
0.227  
30  
μVPP  
f = 0.1 to 10 Hz  
f = 10 Hz  
µVRMS  
TLV6742/4(1)  
TLV6741(2)  
TLV6742/4(1)  
TLV6741(2)  
TLV6742/4(1)  
5.0  
f = 1 kHz  
Input voltage noise  
density  
eN  
4.6  
nV/Hz  
3.7  
f = 10 kHz  
f = 1 kHz  
3.5  
iN  
Input current noise  
23  
fA/Hz  
V
INPUT VOLTAGE RANGE  
Common-mode voltage  
range  
VCM  
(V–)  
(V+) -1.2  
(V–) < VCM < (V+) – 1.2 V  
TLV6741(2)  
95  
87  
94  
120  
100  
110  
Common-mode  
rejection ratio  
CMRR  
VS = 1.8 V, (V–) < VCM < (V+) – 1.2 V  
VS = 5.5, (V–) < VCM < (V+) – 1.2 V  
dB  
TLV6742/4(1)  
INPUT CAPACITANCE  
ZID  
Differential  
10 || 6  
10 || 6  
MΩ || pF  
GΩ || pF  
ZICM  
Common-mode  
OPEN-LOOP GAIN  
(V–) + 40 mV < VO < (V+) – 40 mV, RL = 10 kΩ  
to VS/2  
125  
130  
120  
140  
120  
140  
TLV6741(2)  
(V–) + 150 mV < VO < (V+) – 150 mV, RL = 2 kΩ  
to VS/2  
110  
107  
VS= 1.8 V, (V–) + 150 mV < VO < (V+) – 150 mV,  
RL = 2 kto VS/2  
AOL  
Open-loop voltage gain  
dB  
VS= 5.5 V, (V–) + 150 mV < VO < (V+) – 150 mV,  
RL = 2 kto VS/2  
TLV6742/4(1)  
VS = 1.8 V, (V–) + 40m V < VO < (V+) – 40 mV,  
RL = 10 kto VS/2  
110  
VS = 5.5 V, (V–) + 40m V < VO < (V+) – 40 mV,  
RL = 10 kto VS/2  
FREQUENCY RESPONSE  
GBW  
SR  
Gain-bandwidth product  
Slew rate  
10  
MHz  
VS = 5.5 V, G = +1, CL = 20 pF  
4.5  
V/μs  
(1) This electrical characteristic only applies to the dual-channel TLV6742 and quad-channel TLV6744  
(2) This electrical characteristic only applies to the single-channel, TLV6741  
8
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Copyright © 2017–2020, Texas Instruments Incorporated  
Product Folder Links: TLV6741 TLV6742  
 
TLV6741, TLV6742  
www.ti.com  
SBOS817G JUNE 2017REVISED APRIL 2020  
Electrical Characteristics (continued)  
TLV6742/4 Specifications: VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V) at TA = 25°C, RL = 10 kconnected to VS /  
2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.  
TLV6741 Specifications: VS = (V+) – (V–) = 5.5 V at TA = 25°C, RL = 10 kconnected to VS / 2, VCM = VS / 2, and VOUT = VS  
/ 2, unless otherwise noted.  
PARAMETER  
Settling time  
Phase margin  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
To 0.1%, VS = 5.5 V, VSTEP = 2 V, G = +1, CL =  
20pF  
0.65  
tS  
μs  
To 0.01%, VS = 5.5 V, VSTEP = 2 V, G = +1, CL =  
20pF  
1.2  
G = +1, RL = 10k, CL = 20 pF  
55  
0.2  
°
Overload recovery time VIN × gain > VS  
μs  
TLV6741(2)  
TLV6742/4(1)  
0.00035%  
0.00015%  
Total harmonic  
distortion + noise  
VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1, f =  
1 kHz, RL = 10 kΩ  
THD+N  
Electro-magnetic  
interference rejection  
ratio  
EMIRR  
f = 1 GHz  
TLV6742/4(1)  
TLV6741(2)  
51  
dB  
OUTPUT  
Positive/Negative rail  
headroom  
VS = 5.5 V, RL = 10k  
8
10  
7
VS = 5.5 V, RL = no  
load  
Positive rail headroom  
Negative rail headroom  
VS = 5.5 V, RL = 2 kΩ  
VS = 5.5 V, RL = 10 kΩ  
35  
14  
Voltage output swing  
from rail  
mV  
5
TLV6742/4(1)  
TLV6742/4(1)  
VS = 5.5 V, RL = no  
load  
7
VS = 5.5 V, RL = 2 kΩ  
VS = 5.5 V, RL = 10 kΩ  
35  
14  
5
ISC  
Short-circuit current  
Capacitive load drive  
±68  
mA  
See  
Figure 58  
CLOAD  
f = 10 MHz, IO = 0 A  
f = 2 MHz, IO = 0 A  
TLV6741(2)  
TLV6742/4(1)  
160  
165  
Open-loop output  
impedance  
ZO  
POWER SUPPLY  
890  
990  
TLV6741(2)  
TA = –40°C to 125°C  
TA = –40°C to 125°C  
1100  
1200  
1250  
Quiescent current per  
amplifier  
IQ  
VS = 5.5 V, IO = 0 A  
µA  
TLV6742/4(1)  
TLV6742/4(1)  
At TA = 25°C, VS = 5.5 V, VS ramp rate > 0.3  
V/µs  
Turn-On Time  
10  
μs  
SHUTDOWN  
Quiescent current per  
amplifier  
IQSD  
All amplifiers disabled, SHDN = V–  
Amplifier disabled  
1
3.5  
µA  
Output impedance  
during shutdown  
ZSHDN  
10 || 6  
GΩ || pF  
Logic high threshold  
voltage (amplifier  
enabled)  
(V–) + 1.1  
V
VIH  
V
Logic low threshold  
voltage (amplifier  
disabled)  
(V–) + 0.2  
V
VIL  
Amplifier enable time  
(full shutdown)  
G = +1, VCM = V-, VO = 0.1 × VS/2  
G = +1, VCM = V-, VO = 0.1 × VS/2  
VCM = V-, VO = VS/2  
15  
8
(3)  
tON  
Amplifier enable time  
(partial shutdown)(3)  
µs  
Amplifier disable time  
tOFF  
3
(3)  
(3) Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin  
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.  
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Electrical Characteristics (continued)  
TLV6742/4 Specifications: VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V) at TA = 25°C, RL = 10 kconnected to VS /  
2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.  
TLV6741 Specifications: VS = (V+) – (V–) = 5.5 V at TA = 25°C, RL = 10 kconnected to VS / 2, VCM = VS / 2, and VOUT = VS  
/ 2, unless otherwise noted.  
PARAMETER  
TEST CONDITIONS  
(V+) SHDN (V–) + 0.9 V  
(V–) SHDN (V–) + 0.7 V  
MIN  
TYP  
0.4  
MAX  
UNIT  
SHDN pin input bias  
current (per pin)  
µA  
0.25  
10  
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Table 1. Table of TLV6741 Graphs  
DESCRIPTION  
FIGURE  
Figure 1  
Offset Voltage Production Distribution  
Offset Voltage Drift Distribution  
Figure 2  
Offset Voltage vs Temperature  
Figure 3  
Offset Voltage vs Common-Mode Voltage  
Offset Voltage vs Common-Mode Voltage  
Offset Voltage vs Power Supply  
Figure 4  
Figure 5  
Figure 6  
IB and IOS vs Common-Mode Voltage  
IB and IOS vs Temperature  
Figure 7  
Figure 8  
Open-Loop Gain and Phase vs Frequency  
Closed-Loop Gain vs Frequency  
VO vs I Sourcing and Sinking  
Figure 9  
Figure 10  
Figure 11  
Figure 12  
Figure 13  
Figure 14  
Figure 15  
Figure 16  
Figure 17  
Figure 18  
Figure 19  
Figure 20  
Figure 21  
Figure 22  
Figure 23  
Figure 24  
Figure 25  
Figure 26  
Figure 27  
Figure 28  
Figure 29  
Figure 30  
Figure 31  
Figure 32  
Figure 33  
Figure 34  
Figure 35  
Figure 36  
PSRR vs Frequency (Referred to Input)  
CMRR vs Frequency (Referred to Input)  
CMRR vs Temperature  
0.1-Hz to 10-Hz Flicker Noise  
Input Voltage Noise Spectral Density vs Frequency  
THD + Noise vs Frequency  
THD + Noise vs Frequency  
THD + Noise vs Amplitude  
Quiescent Current vs Supply Voltage  
Quiescent Current vs Temperature  
Open-Loop Gain vs Temperature  
Open-Loop Gain vs Output Voltage  
Open-Loop Output Impedance vs Frequency  
Small-Signal Overshoot vs Load Capacitance  
Small-Signal Overshoot vs Load Capacitance  
Small-Signal Overshoot vs Load Capacitance  
Small-Signal Overshoot vs Load Capacitance  
No Phase Reversal  
Overload Recovery  
Small-Signal Step Response  
Large Signal Step Response  
Large Signal Settling Time (Positive)  
Large Signal Settling Time (Negative)  
Short-Circuit Current vs Temperature  
Maximum Output Voltage vs Frequency  
Electromagnetic Interference Rejection Ratio Referred to Noninverting Input  
(EMIRR+) vs Frequency  
Figure 37  
Figure 38  
Phase Margin vs Capacitive Load  
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7.7 TLV6741: Typical Characteristics  
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.  
40%  
80  
70  
60  
50  
40  
30  
20  
10  
0
35%  
30%  
25%  
20%  
15%  
10%  
5%  
0
0.4  
0.8  
1.2  
Offset Voltage Drift (mV/èC)  
Figure 2. Offset Voltage Drift Distribution  
1.6  
2
2.4  
2.8  
D001  
D002  
Offset Voltage(µV)  
Figure 1. Offset Voltage Production Distribution  
200  
100  
0
6
4
2
-100  
-200  
-300  
-400  
0
-2  
-4  
-6  
-60 -40 -20  
0
20  
40  
60  
80 100 120 140  
-4  
-3  
-2  
-1  
0
Input Common Mode Voltage (V)  
1
2
3
4
Temperature (èC)  
D003  
D004  
Figure 3. Offset Voltage vs Temperature  
Figure 4. Offset Voltage vs Common-Mode Voltage  
0.5  
0.4  
0.3  
0.2  
0.1  
0
300  
200  
100  
0
-100  
-200  
-300  
-400  
-500  
-0.1  
-0.2  
-0.3  
-0.4  
-0.5  
-2.5  
-2  
-1.5  
-1  
Input Common Mode Voltage (V)  
-0.5  
0
0.5  
1
1.5  
2
1.5  
2.5  
3.5  
VS (V)  
4.5  
5.5  
D004  
D005  
Figure 5. Offset Voltage vs Common-Mode Voltage  
Figure 6. Offset Voltage vs Power Supply  
12  
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TLV6741: Typical Characteristics (continued)  
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.  
8
20  
IB-  
IB+  
IOS  
IB-  
IB+  
IOS  
6
0
4
-20  
-40  
-60  
-80  
-100  
-120  
2
0
-2  
-4  
-6  
-8  
-4  
-3  
-2  
-1  
0
VCM (V)  
1
2
3
4
0
50  
100  
Temperature (èC)  
150  
D043  
D044  
Figure 7. IB and IOS vs Common-Mode Voltage  
Figure 8. IB and IOS vs Temperature  
100  
100  
75  
40  
30  
75  
50  
25  
0
20  
50  
10  
25  
0
0
-10  
-20  
-30  
-40  
-25  
-50  
-75  
-25  
-50  
-75  
Gain = -1  
Gain = 10  
Gain = +1  
Gain  
Phase  
1k  
10k  
100k  
Frequency (Hz)  
1M  
10M  
1k  
10k  
100k  
Frequency (Hz)  
1M  
10M  
D006  
D007  
CL = 10 pF  
Figure 9. Open-Loop Gain and Phase vs Frequency  
Figure 10. Closed-Loop Gain vs Frequency  
3
120  
PSRR- (dB)  
PSRR+ (dB)  
2.5  
2
100  
80  
60  
40  
20  
0
1.5  
1
-40°C  
125°C  
25°C  
85°C  
0.5  
0
-0.5  
-1  
85°C  
25°C  
-40°C  
125°C  
-1.5  
-2  
-2.5  
-3  
10  
15  
20  
25  
30  
35  
40  
Output Current (mA)  
45  
50  
55  
60  
1k  
10k  
100k  
1M  
Frequency (Hz)  
D010  
D011  
Figure 11. VO vs I Sourcing and Sinking  
Figure 12. PSRR vs Frequency (Referred to Input)  
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TLV6741: Typical Characteristics (continued)  
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.  
120  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
10  
5
0
-5  
-10  
1k  
10k  
100k  
1M  
-50  
0
50  
Temperature (èC)  
100  
150  
Frequency (Hz)  
D011  
D012  
VS = 5.5 V, TA = –40°C to 125°C, VCM = 0 V to 4.3 V  
Figure 13. CMRR vs Frequency (Referred to Input)  
Figure 14. CMRR vs Temperature  
100  
10  
1
10  
100  
1k  
Frequency (Hz)  
10k  
100k  
Time (1 s/div)  
D015  
D014  
Figure 16. Input Voltage Noise Spectral Density vs  
Frequency  
Figure 15. 0.1-Hz to 10-Hz Flicker Noise  
-95  
-95  
-97  
-99  
-97  
-99  
-101  
-103  
-105  
-101  
-103  
-105  
100  
1k  
Frequency (Hz)  
10k  
100  
1k  
Frequency (Hz)  
10k  
D017  
D017  
VS = 5.5 V, VICM = 2.5 V, RL = 2 kΩ,  
VS = 5.5 V, VICM = 2.5 V, RL = 10 kΩ,  
Gain = 1, BW = 80 kHz, VOUT = 0.5 Vrms  
Gain = 1, BW = 80 kHz, VOUT = 0.5 Vrms  
Figure 17. THD + N vs Frequency  
Figure 18. THD + N vs Frequency  
14  
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TLV6741: Typical Characteristics (continued)  
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.  
0
1000  
950  
900  
850  
800  
750  
700  
650  
600  
550  
500  
Gain = +1, RL = 2 kW  
Gain = +1, RL = 10 kW  
Gain = -1, RL = 2 kW  
Gain = -1, RL = 10 kW  
-20  
-40  
-60  
-80  
-100  
-120  
0.001  
0.01  
0.1  
VOUT (rms)  
1
5
1.5  
2
2.5  
3
3.5  
4
Supply Voltage (V)  
4.5  
5
5.5  
D018  
VS = 5.5 V, VICM = 2.5 V,  
D020  
BW = 80 kHz, VOUT = 0.5 Vrms  
Figure 20. Quiescent Current vs Supply Voltage  
Figure 19. THD + N vs Amplitude  
1000  
10  
9
8
7
6
5
4
3
2
1
0
AVDD = 5.5 V  
AVDD = 1.8 V  
950  
900  
850  
800  
750  
700  
650  
600  
550  
500  
-50  
0
50  
Temperature (èC)  
100  
150  
-60 -40 -20  
0
20  
40  
60  
80 100 120 140  
Temperature (èC)  
D021  
D022  
RL = 2 kΩ  
Figure 21. Quiescent Current vs Temperature  
Figure 22. Open-Loop Gain vs Temperature  
1000  
100  
10  
200  
160  
120  
80  
40  
0
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
4.5  
5
5.5  
1k  
10k  
100k  
Frequency (Hz)  
1M  
10M  
Output Voltage (V)  
C023  
D024  
AVDD = 5.5 V, VICM = VOCM = 2.75 V  
Figure 23. Open-Loop Gain vs Output Voltage  
Figure 24. Open-Loop Output Impedance vs Frequency  
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TLV6741: Typical Characteristics (continued)  
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.  
50  
40  
30  
20  
10  
0
50  
40  
30  
20  
10  
0
Overshoot (+)  
Overshoot (-)  
Overshoot (+)  
Overshoot (-)  
0
10  
20  
30  
40  
Capacitive Load (pF)  
50  
60  
70  
80  
90 100  
0
10  
20  
30  
40  
Capacitance (pF)  
50  
60  
70  
80  
90 100  
D025  
D025  
VS = 5.5 V, VICM = 2.75 V,  
VOCM = 2.75 V, G = 1, 100-mV output step  
VS = 1.8 V, VICM = 0.9 V  
VOCM = 0.9 V, G = 1, 100-mV output step  
Figure 25. Small-Signal Overshoot vs Load Capacitance  
50  
Figure 26. Small-Signal Overshoot vs Load Capacitance  
50  
40  
30  
20  
10  
0
40  
30  
20  
10  
0
Overshoot (+)  
Overshoot (-)  
Overshoot (+)  
Overshoot (-)  
0
10  
20  
30  
40  
Capacitive Load (pF)  
50  
60  
70  
80  
90 100  
0
10  
20  
30  
40  
Capacitance (pF)  
50  
60  
70  
80  
90 100  
D025  
D025  
VS = 5.5 V, VICM = 2.75 V,  
VOCM = 2.75 V, Gain = –1, 100-mV output step  
VS = 1.8 V, VICM = 0.9 V  
VOCM = 0.9 V, Gain = –1, 100-mV output step  
Figure 27. Small-Signal Overshoot vs Load Capacitance  
Figure 28. Small-Signal Overshoot vs Load Capacitance  
Input  
Output  
Input  
Output  
Time (2 ms/div)  
Time (25 ms/div)  
D028  
D027  
Figure 30. Overload Recovery  
Figure 29. No Phase Reversal  
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TLV6741: Typical Characteristics (continued)  
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.  
VIN  
VOUT  
VIN  
VOUT  
Time (1 ms/div)  
Time (2 ms/div)  
D030  
D031  
VS = 1.8 V, VICM = 0.9 V, VOCM = 0.9 V  
CL = 30 pF, Gain = 1, VIN = 100-mVpp  
VS = 5.5 V, VOCM = 2.75 V, CL = 10 pF  
VICM = 2.75 V, Gain = 1, 2-V step  
Figure 31. Small-Signal Step Response  
Figure 32. Large Signal Step Response  
Time (0.2 ms/div)  
Time (0.1 ms/div)  
D032  
D033  
VS = 5.5 V, VICM = 2.75 V, VOCM = 2.75 V  
CL = 0, Gain = 1, 5-V step  
VS = 5.5 V, VICM = 2.75 V, VOCM = 2.75 V  
CL = 0, Gain = 1, 5-V step  
Figure 33. Large Signal Settling Time (Positive)  
Figure 34. Large Signal Settling Time (Negative)  
100  
80  
6
5
4
3
2
1
0
Sourcing  
Sinking  
VS = 1.8 V  
VS = 5.5 V  
60  
40  
20  
0
-20  
-40  
-60  
-80  
-100  
1
10  
100  
1k  
10k  
Frequency (Hz)  
100k  
1M  
10M 100M  
-50  
0
50  
Temperature (èC)  
100  
150  
D035  
D034  
VICM = VS / 2, VOCM = VS / 2,  
CL = 10 pF, Gain = 1  
Figure 35. Short-Circuit Current vs Temperature  
Figure 36. Maximum Output Voltage vs Frequency  
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TLV6741: Typical Characteristics (continued)  
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.  
120  
100  
80  
60  
50  
40  
30  
20  
10  
0
60  
40  
VS = 1.8 V  
VS = 5.5 V  
20  
10M  
100M  
Frequency (Hz)  
1G  
10G  
0
20  
40  
60  
Capacitive Load (pF)  
D036  
D037  
VICM = VOCM = VS / 2  
Figure 37. Electromagnetic Interference Rejection Ratio  
Referred to Noninverting Input (EMIRR+) vs Frequency  
Figure 38. Phase Margin vs Capacitive Load  
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Table 2. Table of TLV6742 Graphs  
DESCRIPTION  
FIGURE  
Figure 39  
Figure 40  
Figure 41  
Figure 42  
Figure 43  
Figure 44  
Figure 45  
Figure 46  
Figure 47  
Figure 48  
Figure 49  
Figure 50  
Figure 51  
Figure 52  
Figure 53  
Figure 54  
Figure 55  
Figure 56  
Figure 57  
Figure 58  
Figure 59  
Figure 60  
Figure 61  
Figure 62  
Figure 63  
Figure 64  
Figure 65  
Figure 66  
Figure 67  
Figure 68  
Figure 69  
Figure 70  
Figure 71  
Figure 72  
Figure 73  
Figure 74  
Figure 75  
Figure 76  
Figure 77  
Figure 78  
Offset Voltage Production Distribution  
Offset Voltage Drift Distribution  
Offset Voltage vs Temperature (PMOS Input Pair)  
Offset Voltage vs Temperature (NMOS Input Pair)  
Offset Voltage vs Common-Mode Voltage (Full Range)  
Offset Voltage vs Common-Mode Voltage (PMOS Input Pair)  
Offset Voltage vs Common-Mode Voltage (Transition Region)  
Offset Voltage vs Power Supply  
IB and IOS vs Common-Mode Voltage  
IB and IOS vs Temperature  
0.1-Hz to 10-Hz Flicker Noise  
Input Voltage Noise Spectral Density vs Frequency  
CMRR & PSRR vs Frequency (Referred to input)  
CMRR vs Temperature  
PSRR vs Temperature  
Open-Loop Gain and Phase vs Frequency  
Closed-Loop Gain vs Frequency  
Open-Loop Gain vs Temperature  
Open-Loop Gain vs Output Voltage  
Phase Margin vs Capacitive Load  
No Phase Reversal  
Small-Signal Overshoot vs Load Capacitance  
Small-Signal Overshoot vs Load Capacitance  
Overload Recovery  
Small-Signal Step Response  
Small-Signal Step Response  
Large Signal Step Response  
Large Signal Step Response  
Large Signal Settling Time (Positive)  
Large Signal Settling Time (Negative)  
THD + N vs Frequency  
THD + N vs Amplitude  
VOUT vs Sourcing Current  
VOUT vs Sinking Current  
Maximum Output Voltage vs Frequency  
Short Circuit Current vs Temperature  
Quiescent Current vs Supply Voltage  
Quiescent Current vs Temperature  
Open-Loop Output Impedance vs Frequency  
Channel Separation vs Frequency  
Electromagnetic Interference Rejection Ratio Referred to Noninverting Input  
(EMIRR+) vs Frequency  
Figure 79  
Figure 80  
Turn-On Time  
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7.8 TLV6742: Typical Characteristics  
at TA = 25°C, VS = ±2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.  
2500  
2250  
2000  
1750  
1500  
1250  
1000  
750  
22  
20  
18  
16  
14  
12  
10  
8
6
4
500  
2
250  
0
0
-500 -400 -300 -200 -100  
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5  
0
Offset Voltage (µV)  
100 200 300 400 500  
D002  
Offset Voltage Drift (mV/èC)  
D001  
VCM = V–  
Figure 40. Offset Voltage Drift Distribution  
Figure 39. Offset Voltage Production Distribution  
200  
160  
120  
80  
4800  
4000  
3200  
2400  
1600  
800  
40  
0
0
-40  
-80  
-120  
-160  
-200  
-800  
-1600  
-2400  
-3200  
-4000  
-40  
-20  
0
20  
40  
60  
80  
100 120 140  
-40  
-20  
0
20  
40 60  
Temperature (°C)  
80  
100 120 140  
Temperature (èC)  
D003  
D004  
VCM = V–  
VCM = V+  
Figure 41. Offset Voltage vs Temperature (PMOS Input Pair)  
5000  
Figure 42. Offset Voltage vs Temperature (NMOS Input Pair)  
200  
160  
120  
80  
4000  
3000  
2000  
1000  
0
40  
0
-40  
-80  
-120  
-160  
-200  
-1000  
-2000  
-3000  
-4000  
-3 -2.4 -1.8 -1.2 -0.6  
0
Input Common Mode Voltage (V)  
0.6 1.2 1.8 2.4  
3
-3 -2.5 -2 -1.5 -1 -0.5  
0
0.5  
Input Common Mode Voltage (V)  
1
1.5  
2
D005  
D006  
Over full common-mode voltage range  
Figure 43. Offset Voltage vs Common-Mode Voltage (Full  
Range)  
Figure 44. Offset Voltage vs Common-Mode Voltage (PMOS  
Input Pair)  
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TLV6742: Typical Characteristics (continued)  
at TA = 25°C, VS = ±2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.  
300  
4000  
240  
3000  
180  
2000  
120  
1000  
0
60  
0
-60  
-1000  
-2000  
-3000  
-4000  
-120  
-180  
-240  
-300  
1.8  
1.9  
2
2.1  
2.2  
Input Common Mode Voltage (V)  
2.3  
2.4  
1.5  
2
2.5  
3
3.5  
4
Supply Voltage (V)  
4.5  
5
5.5  
6
D007  
D008  
Figure 45. Offset Voltage vs Common-Mode Voltage  
(Transition Region)  
Figure 46. Offset Voltage vs Power Supply  
50  
40  
320  
280  
240  
200  
160  
120  
80  
IB-  
IB+  
IOS  
30  
20  
10  
0
-10  
-20  
-30  
-40  
-50  
40  
IB-  
IB+  
IOS  
0
-40  
-3 -2.5 -2 -1.5 -1 -0.5 0 0.5  
VCM (V)  
1
1.5  
2
2.5  
3
-40  
-20  
0
20  
40 60  
Temperature (°C)  
80  
100 120 140  
D009  
D010  
Figure 47. IB and IOS vs Common-Mode Voltage  
Figure 48. IB and IOS vs Temperature  
100  
70  
50  
30  
20  
10  
7
5
3
2
1
10  
Time (1 s/div)  
100  
1k  
Frequency (Hz)  
10k  
100k  
D011  
D012  
Figure 49. 0.1-Hz to 10-Hz Flicker Noise  
Figure 50. Input Voltage Noise Spectral Density vs  
Frequency  
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TLV6742: Typical Characteristics (continued)  
at TA = 25°C, VS = ±2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.  
130  
110  
90  
120  
115  
110  
105  
100  
CMRR  
PSRR+  
PSRR-  
70  
50  
30  
10  
1k  
10k  
100k  
Frequency (Hz)  
1M  
10M  
-40  
-20  
0
20  
40 60  
Temperature (°C)  
80  
100 120 140  
D013  
D014  
VS = 5.5 V, VCM = V– to (V+) – 1.2 V  
Figure 51. CMRR and PSRR vs Frequency (Referred to  
Input)  
Figure 52. CMRR vs Temperature  
120  
210  
130  
125  
120  
115  
110  
Gain  
Phase  
100  
80  
60  
40  
20  
0
180  
150  
120  
90  
60  
30  
-20  
100  
0
1k  
10k  
100k  
Frequency (Hz)  
1M  
10M  
-40  
-20  
0
20  
40 60  
Temperature (°C)  
80  
100 120 140  
D016  
D015  
CL = 10 pF  
VCM = V–  
Figure 54. Open-Loop Gain and Phase vs Frequency  
Figure 53. PSRR vs Temperature  
80  
60  
0.66  
0.6  
VS=1.8V RL=10kW  
VS=1.8V RL=2kW  
VS=5.5V RL=10kW  
VS=5.5V RL=2kW  
0.54  
0.48  
0.42  
0.36  
0.3  
40  
20  
0
-20  
-40  
-60  
-80  
0.24  
0.18  
0.12  
0.06  
G = 1  
G = -1  
G = 10  
G = 100  
G = 1000  
1k  
10k  
100k  
Frequency (Hz)  
1M  
10M  
-40  
-20  
0
20  
40 60  
Temperature (°C)  
80  
100 120 140  
D017  
D018  
CL = 10 pF  
Figure 55. Closed-Loop Gain vs Frequency  
Figure 56. Open-Loop Gain vs Temperature  
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TLV6742: Typical Characteristics (continued)  
at TA = 25°C, VS = ±2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.  
180  
160  
140  
120  
100  
80  
55  
50  
45  
40  
35  
30  
60  
40  
20  
0
-20  
-0.5  
0.5  
1.5  
2.5 3.5  
Output Voltage (V)  
4.5  
5.5  
10  
20  
30  
40  
50  
Capacitive Load (pF)  
60  
70  
80  
90  
100  
D019  
D020  
Figure 57. Open-Loop Gain vs Output Voltage  
Figure 58. Phase Margin vs Capacitive Load  
4
3
60  
50  
40  
30  
20  
10  
0
Input  
Output  
RISO = 0W, Overshoot (-)  
RISO = 0W,Overshoot (+)  
RISO = 50W, Overshoot (-)  
RISO = 50W,Overshoot (+)  
2
1
0
-1  
-2  
-3  
-4  
0
20  
40 60  
Capacitive Load (pF)  
80  
100  
Time (10 µs/div)  
D021  
D022  
VCM = VS / 2, RL = 1 kΩ  
Gain = –1, 100-mV output step  
Figure 59. No Phase Reversal  
Figure 60. Small-Signal Overshoot vs Load Capacitance  
70  
5
RISO = 0W, Overshoot (-)  
RISO = 0W,Overshoot (+)  
RISO = 50W, Overshoot (-)  
RISO = 50W,Overshoot (+)  
60  
50  
40  
30  
20  
10  
0
2.5  
0
-2.5  
-5  
Input  
Output  
Time (10 µs/div)  
0
25  
50 75  
Capacitive Load (pF)  
100  
125  
D024  
D023  
VIN=0.6 Vpp, G = –10, VIN × gain > VS  
VCM = VS / 2, RL = 1 kΩ  
Gain = +1, 100-mV output step  
Figure 62. Overload Recovery  
Figure 61. Small-Signal Overshoot vs Load Capacitance  
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TLV6742: Typical Characteristics (continued)  
at TA = 25°C, VS = ±2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.  
0.1  
0.08  
0.06  
0.04  
0.02  
0
0.1  
0.08  
0.06  
0.04  
0.02  
0
Input  
Output  
Input  
Output  
-0.02  
-0.04  
-0.06  
-0.08  
-0.1  
-0.02  
-0.04  
-0.06  
-0.08  
-0.1  
Time (1 µs/div)  
Time (1 µs/div)  
D025  
D027  
CL = 20 pF, Gain = 1, VIN = 100-mVpp , RL = 1 kΩ  
CL = 20 pF, Gain = –1, VIN = 100-mVpp, RL = 1 kΩ  
Figure 63. Small-Signal Step Response  
Figure 64. Small-Signal Step Response  
1.25  
1
1.25  
1
Input  
Output  
Input  
Output  
0.75  
0.5  
0.75  
0.5  
0.25  
0
0.25  
0
-0.25  
-0.5  
-0.75  
-1  
-0.25  
-0.5  
-0.75  
-1  
-1.25  
-1.25  
Time (1 µs/div)  
Time (1 µs/div)  
D026  
D028  
CL = 20 pF, Gain = +1, VIN = 2-V step, RL = 1 kΩ  
CL = 20 pF, Gain = –1, VIN = 2-V step, RL = 1 kΩ  
Figure 65. Large Signal Step Response  
Figure 66. Large Signal Step Response  
0.1% Settling Time  
0.1% Settling Time  
Step Applied at t = 0  
Step Applied at t = 0  
Time (0.25 ms/div)  
Time (0.25 ms/div)  
D029  
D050  
CL = 20 pF, Gain = 1, VIN = 2-V step  
CL = 20 pF, Gain = –1, VIN = 2-V step  
Figure 67. Large Signal Settling Time (Positive)  
Figure 68. Large Signal Settling Time (Negative)  
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TLV6742: Typical Characteristics (continued)  
at TA = 25°C, VS = ±2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.  
-80  
-40  
RL = 600 W  
RL = 2 kW  
RL = 10 kW  
-84  
-88  
-60  
-92  
-96  
-100  
-104  
-108  
-112  
-116  
-120  
-80  
-100  
RL = 10 kW  
RL = 2 kW  
RL = 600 W  
-120  
100  
1k  
Frequency (Hz)  
10k  
1m  
10m  
100m  
VOUT (rms)  
1
D030  
D031  
VCM = 2.5 V  
VCM = 2.5 V  
Gain = +1, BW = 80 kHz, VOUT = 0.5 Vrms  
BW = 80 kHz  
Figure 69. THD + N vs Frequency  
Figure 70. THD + N vs Amplitude  
3
2.8  
2.6  
2.4  
2.2  
2
0
-0.2  
-0.4  
-0.6  
-0.8  
-1  
-40è  
-40è  
25è  
25è  
85è  
125è  
85è  
125è  
1.8  
1.6  
1.4  
1.2  
1
-1.2  
-1.4  
-1.6  
-1.8  
-2  
0.8  
0.6  
0.4  
0.2  
0
-2.2  
-2.4  
-2.6  
-2.8  
-3  
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80  
Output Current (mA)  
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80  
Output Current (mA)  
D032  
D033  
Figure 71. VOUT vs Sourcing Current  
Figure 72. VOUT vs Sinking Current  
80  
75  
70  
65  
60  
55  
50  
6
5
4
3
2
1
0
1
10  
100  
1k  
10k  
Frequency (Hz)  
100k  
1M  
10M 100M  
-40  
-20  
0
20  
40 60  
Temperature (°C)  
80  
100 120 140  
D034  
D035  
CL = 10 pF, Gain = +1, VS= 5.5 V  
Figure 73. Maximum Output Voltage vs Frequency  
Figure 74. Short-Circuit Current vs Temperature  
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TLV6742: Typical Characteristics (continued)  
at TA = 25°C, VS = ±2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.  
1000  
990  
980  
970  
960  
950  
940  
930  
920  
910  
900  
1000  
990  
980  
970  
960  
950  
940  
930  
920  
910  
900  
1.5  
2
2.5  
3
3.5  
Supply Voltage (V)  
4
4.5  
5
5.5  
6
-40  
-20  
0
20  
40 60  
Temperature (°C)  
80  
100 120 140  
D036  
D037  
Figure 75. Quiescent Current vs Supply Voltage  
Figure 76. Quiescent Current vs Temperature  
1200  
1100  
1000  
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
-50  
-60  
-70  
-80  
-90  
-100  
-110  
-120  
-130  
-140  
-150  
1k  
10k  
100k  
Frequency (Hz)  
1M  
10M  
100  
1k  
10k 100k  
Frequency (Hz)  
1M  
10M  
D038  
D040  
AVDD = 5.5 V, VICM = VOCM = 2.75 V  
Figure 77. Open-Loop Output Impedance vs Frequency  
Figure 78. Channel Separation vs Frequency  
120  
100  
80  
60  
40  
20  
0
6.5  
5.5  
4.5  
3.5  
2.5  
1.5  
0.5  
-0.5  
Supply Voltage  
Output  
10M  
100M  
Frequency (Hz)  
1G  
10G  
Time (5 ms/div)  
D039  
D041  
VS = 0 to 5.5 V, VOUT = 0 to 2.75 V  
Figure 79. Electromagnetic Interference Rejection Ratio  
Referred to Noninverting Input (EMIRR+) vs Frequency  
Figure 80. Turn-On Time  
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8 Detailed Description  
8.1 Overview  
The TLV674x family is an ultra low-noise, rail-to-rail output operational amplifier family. These devices operate  
from a supply voltage of 2.25 V to 5.5 V (TLV6741) and 1.7 V to 5.5 V (TLV6742 and TLV6744), are unity-gain  
stable, and suitable for a wide range of general-purpose applications. The input common-mode voltage range  
includes the negative rail and allows the TLV674x op amp family to be used in most single-supply applications.  
Rail-to-rail output swing significantly increases dynamic range, especially in low-supply applications, and makes it  
suitable for many audio applications as well as driving sampling analog-to-digital converters (ADCs).  
8.2 Functional Block Diagram  
V+  
Reference  
Current  
VIN+  
VIN-  
VBIAS1  
Class AB  
Control  
Circuitry  
VO  
VBIAS2  
V-  
(Ground)  
8.3 Feature Description  
8.3.1 THD+ Noise Performance  
TLV674x operational amplifier family has excellent distortion characteristics. TLV6742 and TLV6744 THD +  
Noise is below 0.00015% (G = +1, VO = 1 VRMS, VCM = 1.8 V, VS = 5.5 V) throughout the audio frequency range,  
20 Hz to 20 kHz with a 10-kΩ load. TLV6741 THD + Noise is below 0.00035% (G = +1, VO = 1 VRMS, VCM = 2.5  
V, VS = 5.5 V) throughout the audio frequency range, 20 Hz to 20 kHz, with a 10-kΩ load. Broadband noise of  
3.5 nV/Hz (TLV6742/4) and 3.7 nV/Hz (TLV6741) is extremely low for a 10-MHz general purpose amplifier.  
8.3.2 Operating Voltage  
The TLV674x operational amplifier family is fully specified and assured for operation from 1.7 V to 5.5 V  
(TLV6742/4) and 2.25 V to 5.5 V (TLV6741). In addition, many specifications apply from –40°C to 125°C. Power-  
supply pins should be bypassed with 0.1-µF ceramic capacitors.  
8.3.3 Rail-to-Rail Output  
Designed as a low-power, low-voltage operational amplifier, the TLV674x devices deliver a robust output drive  
capability. A class AB output stage with common-source transistors achieves full rail-to-rail output swing  
capability. For resistive loads of 10-kΩ, the output swings to within a few mV of either supply rail, regardless of  
the applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to  
the rails, see Figure 11.  
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Feature Description (continued)  
8.3.4 EMI Rejection  
The TLV674x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from  
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and  
digital components. EMI immunity can be improved with circuit design techniques; the TLV674x benefits from  
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the  
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.  
Figure 81 shows the results of this testing on the TLV674x. Table 3 shows the EMIRR IN+ values for the  
TLV674x at particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of  
Operational Amplifiers application report contains detailed information on the topic of EMIRR performance as it  
relates to op amps and is available for download from www.ti.com.  
120  
100  
80  
60  
40  
20  
0
10M  
100M  
Frequency (Hz)  
1G  
10G  
D039  
Figure 81. EMIRR Testing  
Table 3. TLV674x EMIRR IN+ for Frequencies of Interest  
FREQUENCY  
APPLICATION OR ALLOCATION  
EMIRR IN+  
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)  
applications  
400 MHz  
59.5 dB  
Global system for mobile communications (GSM) applications, radio communication, navigation,  
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications  
900 MHz  
1.8 GHz  
2.4 GHz  
3.6 GHz  
5 GHz  
68.9 dB  
77.8 dB  
78.0 dB  
88.8 dB  
87.6 dB  
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)  
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and  
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)  
Radiolocation, aero communication and navigation, satellite, mobile, S-band  
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite  
operation, C-band (4 GHz to 8 GHz)  
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8.3.5 Electrical Overstress  
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress  
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the  
output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown  
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.  
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from  
accidental ESD events both before and during product assembly.  
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is  
helpful. Figure 82 shows an illustration of the ESD circuits contained in the TLV674x (indicated by the dashed  
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and  
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or  
the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain  
inactive during normal circuit operation.  
TVS  
RF  
+VS  
VDD  
OPAx990  
100 Ω  
100 Ω  
R1  
RS  
INœ  
œ
IN+  
+
Power-Supply  
ESD Cell  
RL  
ID  
+
VIN  
œ
VSS  
œVS  
TVS  
Figure 82. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application  
An ESD event is very short in duration and very high voltage (for example; 1 kV, 100 ns), whereas an EOS event  
is long in duration and lower voltage (for example; 50 V, 100 ms). The ESD diodes are designed for out-of-circuit  
ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).  
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit (labeled  
ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.  
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if  
activated in-circuit. A transient voltage suppressor (TVS) can be used to prevent against damage caused by  
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting  
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.  
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The TLV674x family incorporates internal electrostatic discharge (ESD) protection circuits on all pins, as shown  
above. These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is  
limited to 10 mA as stated in the Absolute Maximum section. Figure 83 shows how a series input resistor may be  
added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier  
input and its value should be kept to a minimum in noise-sensitive applications.  
V+  
IOVERLOAD  
10-mA max  
VOUT  
Device  
VIN  
5 kW  
Figure 83. Input Current Protection  
8.3.6 Typical Specifications and Distributions  
Designers often have questions about a typical specification of an amplifier in order to design a more robust  
circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an  
amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These  
deviations often follow Gaussian ("bell curve"), or normal, distributions and circuit designers can leverage this  
information to guardband their system, even when there is not a minimum or maximum specification in the  
Electrical Characteristics table.  
0.00312% 0.13185%  
0.13185% 0.00312%  
0.00002%  
0.00002%  
2.145% 13.59% 34.13% 34.13% 13.59% 2.145%  
1
1 1 1 1 1 1 1 1  
1
1
1
-61 -51 -41 -31 -21 -1  
+1 +21 +31 +41 +51 +61  
Figure 84. Ideal Gaussian Distribution  
Figure 84 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ, or sigma,  
is the standard deviation of a system. For a specification that exhibits this kind of distribution, approximately two-  
thirds (68.26%) of all units can be expected to have a value within one standard deviation, or one sigma, of the  
mean (from µ–σ to µ+σ).  
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Depending on the specification, values listed in the typical column of the Electrical Characteristics table are  
represented in different ways. As a general rule of thumb, if a specification naturally has a nonzero mean (for  
example, like gain bandwidth), then the typical value is equal to the mean (µ). However, if a specification  
naturally has a mean near zero (like input offset voltage), then the typical value is equal to the mean plus one  
standard deviation (µ + σ) in order to most accurately represent the typical value.  
You can use this chart to calculate approximate probability of a specification in a unit; for example, for TLV6742,  
the typical input voltage offset is 150 µV, so 68.2% of all TLV6742 devices are expected to have an offset from  
–150 µV to 150 µV.  
Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits  
will be removed from production material. For example, the TLV6742 device has a maximum offset voltage of 1.0  
mV at 25°C, and even though this corresponds to 5 σ (1 in 1.7 million units), which is extremely unlikely, TI  
assures that any unit with a larger offset than 1.0 mV will be removed from production material.  
For specifications with no value in the minimum or maximum column, consider selecting a sigma value of  
sufficient guardband for your application, and design worst-case conditions using this value. For example, the 6σ  
value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be an option  
as a wide guardband to design a system around. In this case, the TLV6742 does not have a maximum or  
minimum for offset voltage drift, but based on Figure 40 and the typical value of 0.2 µV/°C in the Electrical  
Characteristics table, it can be calculated that the 6-σ value for offset voltage drift is about 1.0 µV/°C. When  
designing for worst-case system conditions, this value can be used to estimate the worst possible offset across  
temperature without having an actual minimum or maximum value.  
However, process variation and adjustments over time can shift typical means and standard deviations, and  
unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a  
device. This information should be used only to estimate the performance of a device.  
8.3.7 Shutdown Function  
The TLV674xS devices feature SHDN pins that disable the op amp, placing it into a low-power standby mode. In  
this mode, the op amp typically consumes less than 1 µA. The SHDN pins are active-low, meaning that  
shutdown mode is enabled when the input to the SHDN pin is a valid logic low.  
The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown  
feature lies around 800 mV (typical) above the negative rail. Hysteresis has been included in the switching  
threshold to ensure smooth switching characteristics. To ensure optimal shutdown behavior, the SHDN pins  
should be driven with valid logic signals. A valid logic low is defined as a voltage between V– and V– + 0.2 V. A  
valid logic high is defined as a voltage between V– + 1.2 V and V+. The shutdown pin must either be connected  
to a valid high or a low voltage or driven, and not left as an open circuit. There is no internal pull-up to enable the  
amplifier.  
The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled, and  
quad op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature may  
be used to greatly reduce the average current and extend battery life. The enable time is 15 µs for full shutdown  
of all channels; disable time is 3 µs. When disabled, the output assumes a high-impedance state. This  
architecture allows the TLV674xS to be operated as a gated amplifier (or to have the device output multiplexed  
onto a common analog output bus). Shutdown time (tOFF) depends on loading conditions and increases as load  
resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to  
midsupply (VS / 2) is required. If using the TLV674xS without a load, the resulting turnoff time is significantly  
increased.  
8.3.8 Packages With an Exposed Thermal Pad  
The TLV674x family is available in packages such as the WSON-8 (DSG) which feature an exposed thermal pad.  
Inside the package, the die is attached to this thermal pad using an electrically conductive compound. For this  
reason, when using a package with an exposed thermal pad, the thermal pad must either be connected to V– or  
left floating. Attaching the thermal pad to a potential other than V– is not allowed, and performance of the device  
is not assured when doing so.  
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8.4 Device Functional Modes  
The TLV674x family has a single functional mode. The TLV6742 and TLV6744 are powered on as long as the  
power-supply voltage is between 1.7 V (±0.85 V) and 5.5 V (±2.75 V).The TLV6741 is powered on as long as the  
power-supply voltage is between 2.25 V (±1.125 V) and 5.5 V (±2.75 V).  
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9 Application and Implementation  
NOTE  
Information in the following applications sections is not part of the TI component  
specification, and TI does not warrant its accuracy or completeness. TI’s customers are  
responsible for determining suitability of components for their purposes. Customers should  
validate and test their design implementation to confirm system functionality.  
9.1 Application Information  
The TLV674x family features 10-MHz bandwidth and 4.5-V/µs slew rate with only 890-µA (TLV6741), 990-µA  
(TLV6742/4) of supply current per channel, providing good AC performance at very-low-power consumption. DC  
applications are well served with a very-low input noise voltage of 3.5 nV /vHz (TLV6742/4), 3.7 nV / vHz  
(TLV6741) at 10 kHz, low input bias current, and a typical input offset voltage of 0.15 mV.  
9.2 Single-Supply Electret Microphone Preamplifier With Speech Filter  
Electret microphones are commonly used in portable electronics because of their small size, low cost, and  
relatively good signal-to-noise ratio (SNR). The small package size, low operating voltage and excellent AC  
performance of the TLV674x family make it an excellent choice for preamplifier circuits for electret microphones.  
The circuit shown in Figure 85 is a single-supply preamplifier circuit for electret microphones, highlighting the  
TLV6741 device.  
3V  
3V  
R1  
200 k  
RBIAS  
2.2 kꢀ  
3V  
Electret  
Microphone  
+
TLV6741  
VOUT  
CIN  
68 nF  
R2  
200 kꢀ  
RF 10 kꢀ  
RG  
78.7 ꢀ  
CF 3.3 nF  
CG  
10 µF  
Copyright © 2017, Texas Instruments Incorporated  
Figure 85. Microphone Preamplifier  
9.2.1 Design Requirements  
The design requirements are as follows:  
Supply voltage: 3 V  
Input: 7.93 mVRMS (0.63 Pa with a –38 dB SPL microphone)  
Output: 1 VRMS  
Bandwidth: 300 Hz to 3 kHz  
9.2.2 Detailed Design Procedure  
The transfer function defining the relationship between VOUT and the AC input signal is shown in Equation 1:  
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Single-Supply Electret Microphone Preamplifier With Speech Filter (continued)  
÷
R
F
V
= V  
ì 1+  
OUT  
IN _ AC  
R
«
G
(1)  
The required gain can be calculated based on the expected input signal level and desired output level as shown  
in Equation 2:  
VOUT  
1VRMS  
V
GOPA  
=
=
=126  
VIN _ AC 7.93mVRMS  
V
(2)  
Select a standard 10-kΩ feedback resistor and calculate RG.  
RF  
10kW  
V
126 -1  
V
RG =  
=
= 80W ç 78.7W (closest standard value)  
GOPA -1  
(3)  
To minimize the attenuation in the desired passband from 300 Hz to 3 kHz, set the upper (fH) and lower (fL) cutoff  
frequencies outside of the desired bandwidth as:  
fL = 200 Hz  
(4)  
and  
fH = 5 kHz  
(5)  
Select CG to set the fL cutoff frequency using Equation 6:  
1
1
CG =  
=
= 10.11mF ç10mF  
2ìp ì RG ì fL 2ìp ì 78.7Wì 200Hz  
(6)  
(7)  
Select CF to set the fH cutoff frequency using Equation 7:  
1
1
CF =  
=
= 3.18nF ç 3.3nF (Standard Value)  
2ì  
p
ì RF ì fH 2ì  
p
ì10kWì5kHz  
The input signal cutoff frequency should be set low enough such that low-frequency sound waves still pass  
through. Therefore select CIN to achieve a 30-Hz cutoff frequency (fIN) using Equation 8:  
1
1
CIN =  
=
= 53nF ç 68nF (Standard Value)  
2ì  
p
ì(R || R2 )ì fIN 2ì  
p
ì100k30Hz  
1
(8)  
The measured transfer function for the microphone preamplifier circuit is shown in Figure 86 and the measured  
THD+N performance of the microphone preamplifier circuit is shown in Figure 87.  
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Single-Supply Electret Microphone Preamplifier With Speech Filter (continued)  
9.2.3 Application Curves  
50  
40  
30  
20  
10  
0
0
œ20  
œ40  
œ60  
œ80  
œ10  
20  
200  
2000  
Frequency (Hz)  
20000  
0.005  
0.05  
0.5  
5
RMS Output Voltage (V)  
C039  
C040  
Figure 86. Gain vs Frequency  
Figure 87. THD + N vs RMS Output Voltage  
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10 Power Supply Recommendations  
The TLV6742 and TLV6744 devices are specified for operation from 1.7 V to 5.5 V (±0.85 V to ±2.75 V). The  
TLV6741 device is specified for operation from 2.25 V to 5.5 V (±1.125 V to ±2.75 V). Many specifications of the  
TLV674x family apply from –40°C to 125°C.  
CAUTION  
Supply voltages larger than 7 V can permanently damage the device (see the Absolute  
Maximum Ratings section).  
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-  
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout  
Guidelines section.  
11 Layout  
11.1 Layout Guidelines  
For best operational performance of the device, use good PCB layout practices, including:  
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the  
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-  
impedance power sources local to the analog circuitry.  
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as  
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-  
supply applications.  
Separate grounding for analog and digital portions of the circuitry is one of the simplest and most  
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to  
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to  
physically separate digital and analog grounds, paying attention to the flow of the ground current.  
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as  
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much  
better than crossing in parallel with the noisy trace.  
Place the external components as close to the device as possible. Keeping RF and RG close to the  
inverting input minimizes parasitic capacitance, as shown in Figure 88.  
Keep the length of input traces as short as possible. Always remember that the input traces are the most  
sensitive part of the circuit.  
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly  
reduce leakage currents from nearby traces that are at different potentials.  
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11.2 Layout Example  
GND  
GND  
OUTPUT  
V-  
GND  
Figure 88. Operational Amplifier Board Layout for Noninverting Configuration  
V-  
C3  
INPUT  
OUTPUT  
U1  
TLV6741  
2
1
3
R3  
+
4
œ
C4  
C2  
V+  
R1  
C1  
R2  
Copyright © 2017, Texas Instruments Incorporated  
Figure 89. Schematic Used for Layout Example  
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12 Device and Documentation Support  
12.1 Device Support  
12.1.1 Documentation Support  
12.1.1.1 Related Documentation  
For related documentation see the following:  
QFN/SON PCB Attachment.  
Quad Flatpack No-Lead Logic Packages.  
EMI Rejection Ratio of Operational Amplifiers.  
12.2 Receiving Notification of Documentation Updates  
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper  
right corner, click on Alert me to register and receive a weekly digest of any product information that has  
changed. For change details, review the revision history included in any revised document.  
12.3 Related Links  
The table below lists quick access links. Categories include technical documents, support and community  
resources, tools and software, and quick access to order now.  
Table 4. Related Links  
TECHNICAL  
DOCUMENTS  
TOOLS &  
SOFTWARE  
SUPPORT &  
COMMUNITY  
PARTS  
PRODUCT FOLDER  
ORDER NOW  
TLV6741  
TLV6742  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
Click here  
12.4 Support Resources  
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight  
from the experts. Search existing answers or ask your own question to get the quick design help you need.  
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do  
not necessarily reflect TI's views; see TI's Terms of Use.  
12.5 Trademarks  
E2E is a trademark of Texas Instruments.  
Bluetooth is a registered trademark of Bluetooth SIG, Inc.  
All other trademarks are the property of their respective owners.  
12.6 Electrostatic Discharge Caution  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
12.7 Glossary  
SLYZ022 TI Glossary.  
This glossary lists and explains terms, acronyms, and definitions.  
13 Mechanical, Packaging, and Orderable Information  
The following pages include mechanical, packaging, and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
19-Jan-2021  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
TLV6741DCKR  
TLV6741DCKT  
TLV6742IDDFR  
TLV6742IDR  
ACTIVE  
ACTIVE  
SC70  
SC70  
DCK  
DCK  
DDF  
D
5
5
3000 RoHS & Green  
250 RoHS & Green  
NIPDAU  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-1-260C-UNLIM  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
18E  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAUAG  
18E  
ACTIVE SOT-23-THIN  
8
3000 RoHS & Green  
2500 RoHS & Green  
3000 RoHS & Green  
2000 RoHS & Green  
3000 RoHS & Green  
T42D  
ACTIVE  
ACTIVE  
SOIC  
WSON  
TSSOP  
X2QFN  
8
T6742D  
D42S  
TLV6742IDSGR  
TLV6742IPWR  
TLV6742SIRUGR  
DSG  
PW  
8
ACTIVE  
8
T6742P  
HHF  
PREVIEW  
RUG  
10  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
19-Jan-2021  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
18-Nov-2020  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TLV6741DCKR  
TLV6741DCKT  
TLV6742IDDFR  
SC70  
SC70  
DCK  
DCK  
DDF  
5
5
8
3000  
250  
178.0  
178.0  
180.0  
9.0  
9.0  
8.4  
2.4  
2.4  
3.2  
2.5  
2.5  
3.2  
1.2  
1.2  
1.4  
4.0  
4.0  
4.0  
8.0  
8.0  
8.0  
Q3  
Q3  
Q3  
SOT-  
3000  
23-THIN  
TLV6742IDR  
TLV6742IDSGR  
TLV6742IPWR  
SOIC  
WSON  
TSSOP  
D
8
8
8
2500  
3000  
2000  
330.0  
180.0  
330.0  
12.4  
8.4  
6.4  
2.3  
7.0  
5.2  
2.3  
3.6  
2.1  
1.15  
1.6  
8.0  
4.0  
8.0  
12.0  
8.0  
Q1  
Q2  
Q1  
DSG  
PW  
12.4  
12.0  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
18-Nov-2020  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TLV6741DCKR  
TLV6741DCKT  
TLV6742IDDFR  
TLV6742IDR  
SC70  
SC70  
DCK  
DCK  
DDF  
D
5
5
8
8
8
8
3000  
250  
190.0  
190.0  
210.0  
853.0  
210.0  
853.0  
190.0  
190.0  
185.0  
449.0  
185.0  
449.0  
30.0  
30.0  
35.0  
35.0  
35.0  
35.0  
SOT-23-THIN  
SOIC  
3000  
2500  
3000  
2000  
TLV6742IDSGR  
TLV6742IPWR  
WSON  
DSG  
PW  
TSSOP  
Pack Materials-Page 2  
PACKAGE OUTLINE  
D0008A  
SOIC - 1.75 mm max height  
SCALE 2.800  
SMALL OUTLINE INTEGRATED CIRCUIT  
C
SEATING PLANE  
.228-.244 TYP  
[5.80-6.19]  
.004 [0.1] C  
A
PIN 1 ID AREA  
6X .050  
[1.27]  
8
1
2X  
.189-.197  
[4.81-5.00]  
NOTE 3  
.150  
[3.81]  
4X (0 -15 )  
4
5
8X .012-.020  
[0.31-0.51]  
B
.150-.157  
[3.81-3.98]  
NOTE 4  
.069 MAX  
[1.75]  
.010 [0.25]  
C A B  
.005-.010 TYP  
[0.13-0.25]  
4X (0 -15 )  
SEE DETAIL A  
.010  
[0.25]  
.004-.010  
[0.11-0.25]  
0 - 8  
.016-.050  
[0.41-1.27]  
DETAIL A  
TYPICAL  
(.041)  
[1.04]  
4214825/C 02/2019  
NOTES:  
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.  
Dimensioning and tolerancing per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not  
exceed .006 [0.15] per side.  
4. This dimension does not include interlead flash.  
5. Reference JEDEC registration MS-012, variation AA.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
D0008A  
SOIC - 1.75 mm max height  
SMALL OUTLINE INTEGRATED CIRCUIT  
8X (.061 )  
[1.55]  
SYMM  
SEE  
DETAILS  
1
8
8X (.024)  
[0.6]  
SYMM  
(R.002 ) TYP  
[0.05]  
5
4
6X (.050 )  
[1.27]  
(.213)  
[5.4]  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE:8X  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
METAL  
EXPOSED  
METAL  
EXPOSED  
METAL  
.0028 MAX  
[0.07]  
.0028 MIN  
[0.07]  
ALL AROUND  
ALL AROUND  
SOLDER MASK  
DEFINED  
NON SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
4214825/C 02/2019  
NOTES: (continued)  
6. Publication IPC-7351 may have alternate designs.  
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
D0008A  
SOIC - 1.75 mm max height  
SMALL OUTLINE INTEGRATED CIRCUIT  
8X (.061 )  
[1.55]  
SYMM  
1
8
8X (.024)  
[0.6]  
SYMM  
(R.002 ) TYP  
[0.05]  
5
4
6X (.050 )  
[1.27]  
(.213)  
[5.4]  
SOLDER PASTE EXAMPLE  
BASED ON .005 INCH [0.125 MM] THICK STENCIL  
SCALE:8X  
4214825/C 02/2019  
NOTES: (continued)  
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
9. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
GENERIC PACKAGE VIEW  
DSG 8  
2 x 2, 0.5 mm pitch  
WSON - 0.8 mm max height  
PLASTIC SMALL OUTLINE - NO LEAD  
This image is a representation of the package family, actual package may vary.  
Refer to the product data sheet for package details.  
4224783/A  
www.ti.com  
PACKAGE OUTLINE  
DSG0008A  
WSON - 0.8 mm max height  
SCALE 5.500  
PLASTIC SMALL OUTLINE - NO LEAD  
2.1  
1.9  
B
A
PIN 1 INDEX AREA  
2.1  
1.9  
0.32  
0.18  
0.4  
0.2  
ALTERNATIVE TERMINAL SHAPE  
TYPICAL  
C
0.8 MAX  
SEATING PLANE  
0.08 C  
0.05  
0.00  
EXPOSED  
THERMAL PAD  
(0.2) TYP  
0.9 0.1  
5
4
6X 0.5  
2X  
1.5  
9
1.6 0.1  
8
1
0.32  
0.18  
8X  
0.4  
0.2  
PIN 1 ID  
8X  
0.1  
C A B  
C
0.05  
4218900/D 04/2020  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
DSG0008A  
WSON - 0.8 mm max height  
PLASTIC SMALL OUTLINE - NO LEAD  
(0.9)  
(
0.2) VIA  
8X (0.5)  
TYP  
1
8
8X (0.25)  
(0.55)  
SYMM  
9
(1.6)  
6X (0.5)  
5
4
SYMM  
(1.9)  
(R0.05) TYP  
LAND PATTERN EXAMPLE  
SCALE:20X  
0.07 MIN  
ALL AROUND  
0.07 MAX  
ALL AROUND  
SOLDER MASK  
OPENING  
METAL  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
NON SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
(PREFERRED)  
SOLDER MASK DETAILS  
4218900/D 04/2020  
NOTES: (continued)  
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature  
number SLUA271 (www.ti.com/lit/slua271).  
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown  
on this view. It is recommended that vias under paste be filled, plugged or tented.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
DSG0008A  
WSON - 0.8 mm max height  
PLASTIC SMALL OUTLINE - NO LEAD  
8X (0.5)  
METAL  
8
SYMM  
1
8X (0.25)  
(0.45)  
SYMM  
9
(0.7)  
6X (0.5)  
5
4
(R0.05) TYP  
(0.9)  
(1.9)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
EXPOSED PAD 9:  
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE  
SCALE:25X  
4218900/D 04/2020  
NOTES: (continued)  
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
www.ti.com  
PACKAGE OUTLINE  
PW0008A  
TSSOP - 1.2 mm max height  
SCALE 2.800  
SMALL OUTLINE PACKAGE  
C
6.6  
6.2  
SEATING PLANE  
TYP  
PIN 1 ID  
AREA  
A
0.1 C  
6X 0.65  
8
5
1
3.1  
2.9  
NOTE 3  
2X  
1.95  
4
0.30  
0.19  
8X  
4.5  
4.3  
1.2 MAX  
B
0.1  
C A  
B
NOTE 4  
(0.15) TYP  
SEE DETAIL A  
0.25  
GAGE PLANE  
0.15  
0.05  
0.75  
0.50  
0 - 8  
DETAIL A  
TYPICAL  
4221848/A 02/2015  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not  
exceed 0.15 mm per side.  
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.  
5. Reference JEDEC registration MO-153, variation AA.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
PW0008A  
TSSOP - 1.2 mm max height  
SMALL OUTLINE PACKAGE  
8X (1.5)  
SYMM  
8X (0.45)  
(R0.05)  
1
4
TYP  
8
SYMM  
6X (0.65)  
5
(5.8)  
LAND PATTERN EXAMPLE  
SCALE:10X  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
METAL  
0.05 MAX  
ALL AROUND  
0.05 MIN  
ALL AROUND  
SOLDER MASK  
DEFINED  
NON SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
NOT TO SCALE  
4221848/A 02/2015  
NOTES: (continued)  
6. Publication IPC-7351 may have alternate designs.  
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
PW0008A  
TSSOP - 1.2 mm max height  
SMALL OUTLINE PACKAGE  
8X (1.5)  
SYMM  
(R0.05) TYP  
8X (0.45)  
1
4
8
SYMM  
6X (0.65)  
5
(5.8)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
SCALE:10X  
4221848/A 02/2015  
NOTES: (continued)  
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
9. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
PACKAGE OUTLINE  
DDF0008A  
SOT-23 - 1.1 mm max height  
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE  
C
2.95  
2.65  
SEATING PLANE  
TYP  
PIN 1 ID  
AREA  
0.1 C  
A
6X 0.65  
8
1
2.95  
2.85  
NOTE 3  
2X  
1.95  
4
5
0.4  
0.2  
8X  
0.1  
C A  
B
1.65  
1.55  
B
1.1 MAX  
0.20  
0.08  
TYP  
SEE DETAIL A  
0.25  
GAGE PLANE  
0.1  
0.0  
0 - 8  
0.6  
0.3  
DETAIL A  
TYPICAL  
4222047/B 11/2015  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not  
exceed 0.15 mm per side.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
DDF0008A  
SOT-23 - 1.1 mm max height  
PLASTIC SMALL OUTLINE  
8X (1.05)  
SYMM  
1
8
8X (0.45)  
SYMM  
6X (0.65)  
5
4
(R0.05)  
TYP  
(2.6)  
LAND PATTERN EXAMPLE  
SCALE:15X  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
METAL  
SOLDER MASK  
DEFINED  
NON SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
4222047/B 11/2015  
NOTES: (continued)  
4. Publication IPC-7351 may have alternate designs.  
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
DDF0008A  
SOT-23 - 1.1 mm max height  
PLASTIC SMALL OUTLINE  
8X (1.05)  
SYMM  
(R0.05) TYP  
8
1
8X (0.45)  
SYMM  
6X (0.65)  
5
4
(2.6)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
SCALE:15X  
4222047/B 11/2015  
NOTES: (continued)  
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
7. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
IMPORTANT NOTICE AND DISCLAIMER  
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE  
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you  
permission to use these resources only for development of an application that uses the TI products described in the resource. Other  
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party  
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,  
costs, losses, and liabilities arising out of your use of these resources.  
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either  
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s  
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2021, Texas Instruments Incorporated  

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