TLV70018QDDCRQ1 [TI]
具有使能功能的汽车类、300mA、高 PSRR、低 IQ、低压降稳压器，1.8V 输出 | DDC | 5 | -40 to 125;
| 型号： | TLV70018QDDCRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有使能功能的汽车类、300mA、高 PSRR、低 IQ、低压降稳压器，1.8V 输出 | DDC | 5 | -40 to 125 稳压器 |
| 文件： | 总25页 (文件大小：1581K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV70018-Q1, TLV70012-Q1
ZHCS844C –NOVEMBER 2011–REVISED JUNE 2017
TLV700xx-Q1 300mA、低 IQ、低压差稳压器
1 特性
3 说明
1
•
•
符合汽车应用 要求
具有符合 AEC-Q100 标准的下列结果：
TLV70018-Q1 和 TLV70012-Q1 低压差 (LDO) 线性稳
压器为低静态电流器件，具有出色的线路和负载瞬态性
能。高精度带隙与误差放大器支持 2% 的总精度。本
系列器件具有低输出噪声、高电源抑制比 (PSRR) 和
低压差电压等特性，非常适合为功率敏感型负载供电。
所有器件版本均具有热关断保护和电流限制，以便检测
故障状况。
–
–
–
器件温度 1 级：-40°C 至 125°C 的环境运行温
度范围
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 H2
器件组件充电模式 (CDM) ESD 分类等级 C3B
•
•
•
•
•
精度 2%
此外，这些器件在有效输出电容只有 0.1μF 时保持稳
定。这一特性允许使用具有较高偏置电压和温度降额的
成本效益型电容器。这些器件在不产生输出负载的情况
下可调节至特定的精度。
低 IQ：35μA
固定输出电压：1.2V 和 1.8V
高电源抑制比 (PSRR)：频率 1kHz 时为 68dB
可在采用 0.1 μF(1) 的有效电容时保持稳定
热关断保护和过流保护
器件信息(1)
•
(1)
器件型号
TLV70018-Q1
TLV70012-Q1
封装
封装尺寸（标称值）
请参阅 输入和输出电容器要求。
小外形尺寸晶体管
(SOT) (5)
2.90mm x 1.60mm
2 应用
•
•
•
•
汽车音响主机
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
摄像头传感器和模块
抬头显示 (HUD)
空白
空白
空白
空白
空白
空白
远程信息处理控制单元
典型应用
VIN
VOUT
IN
OUT
1 mF
Ceramic
CIN
COUT
TLV700xx
GND
On
EN
Off
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSB67
TLV70018-Q1, TLV70012-Q1
ZHCS844C –NOVEMBER 2011–REVISED JUNE 2017
www.ti.com.cn
目录
8.1 Application Information............................................ 13
8.2 Typical Application .................................................. 13
Power Supply Recommendations...................... 14
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagrams ..................................... 11
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 12
Application and Implementation ........................ 13
9
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
10.3 Thermal Considerations........................................ 15
10.4 Power Dissipation ................................................. 15
11 器件和文档支持 ..................................................... 17
11.1 器件支持................................................................ 17
11.2 文档支持................................................................ 17
11.3 相关链接................................................................ 17
11.4 接收文档更新通知 ................................................. 17
11.5 社区资源................................................................ 17
11.6 商标....................................................................... 17
11.7 静电放电警告......................................................... 17
11.8 Glossary................................................................ 17
12 机械、封装和可订购信息....................................... 17
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (January 2016) to Revision C
Page
•
•
•
已更改 固定输出电压 特性 由固定输出电压组合（可能为 1.2V 至 4.8V）更改为固定输出电压（1.2V 和 1.8V）................. 1
已更改 应用部分...................................................................................................................................................................... 1
已更改 说明部分的第一段：将 TLV700xx-Q1 系列更改为 TLV70018-Q1 和 TLV70012-Q1、删除了第二句、将多种电
池供电型手持设备更改为为功率敏感型负载供电，并将安全更改为检测故障状况.................................................................. 1
•
•
已删除 典型应用标题中的固定电压版本.................................................................................................................................. 1
Changed Input voltage parameter: changed symbol from VI to VIN, moved EN and OUT rows to standalone
parameters ............................................................................................................................................................................. 5
•
•
•
•
Changed maximum specification of Output voltage parameter from 5.5 V to 1.8 V ............................................................. 5
Added IOUT symbol to Current output parameter ................................................................................................................... 5
Deleted TLV70018-Q1 column from Thermal Information table ............................................................................................ 5
Added TLV70018-Q1 to TLV70012-Q1 column in Thermal Information table; all thermal values for TLV70018-Q1
changed to the TLV70012-Q1 thermal values........................................................................................................................ 5
•
•
Changed VOUT(TYP) to VOUT(NOM) in conditions statement of Electrical Characteristics table .................................................. 6
Changed symbols for Line regulation, Load regulation, and Output noise voltage parameters from ΔVO/ΔVIN to
ΔVOUT/ΔVIN, ΔVO/ΔIOUT to ΔVOUT/ΔIOUT, and VN to Vn (respectively) in Electrical Characteristics table.................................. 6
•
•
•
•
•
•
•
•
•
•
•
Changed VOUT(TYP) to VOUT(NOM) in Typical Characteristics conditions statement .................................................................. 7
Deleted Dropout Voltage vs Input Voltage and Dropout Voltage vs Output Current curves ................................................. 7
Changed TLV700xx-Q1 to TLV70018-Q1 and TLV70012-Q1 in Overview section............................................................. 11
Added TLV70012-Q1 to sub-sections of Feature Description and Device Functional Modes sections .............................. 11
Changed 160°C to 165°C, 140°C to 145°C, and 35°C to 40°C in Thermal Shutdown section .......................................... 12
Changed Application Information section: changed first two sentences, deleted second paragraph ................................. 13
Changed Example Value column values for 2nd and 3rd rows in Design Parameters table............................................... 13
Added TLV70012-Q1 to Input and Output Capacitor Requirements section ....................................................................... 14
Deleted first and last paragraphs from Thermal Considerations section ............................................................................ 15
Deleted second sentence from second paragraph of Power Dissipation section ............................................................... 15
Added TLV70012-Q1 to Power Dissipation section ............................................................................................................ 15
2
版权 © 2011–2017, Texas Instruments Incorporated
TLV70018-Q1, TLV70012-Q1
www.ti.com.cn
ZHCS844C –NOVEMBER 2011–REVISED JUNE 2017
修订历史记录 (接下页)
Changes from Revision A (March 2012) to Revision B
Page
•
•
已添加 ESD 额定值表、建议运行条件表、热性能信息表、详细 说明部分、应用和实施部分、应用和实施部分、布局
部分、器件和文档支持部分以及机械、封装和可订购信息部分............................................................................................... 1
Deleted the Dissipation Ratings table..................................................................................................................................... 5
Copyright © 2011–2017, Texas Instruments Incorporated
3
TLV70018-Q1, TLV70012-Q1
ZHCS844C –NOVEMBER 2011–REVISED JUNE 2017
www.ti.com.cn
5 Pin Configuration and Functions
DDC Package
5-Pin SOT
Top View
1
2
3
5
OUT
NC
IN
GND
EN
4
Pin Functions
PIN
DESCRIPTION
NO.
1
NAME
IN
Input pin. A small 1-μF ceramic capacitor is recommended from this pin to ground to assure stability and good
transient performance.(1)
2
GND
EN
Ground pin
Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown
mode and reduces operating current to 1 μA, nominal.
3
4
5
NC
No connection. This pin can be tied to ground to improve thermal dissipation.
Regulated output voltage pin. A small 1-μF ceramic capacitor is needed from this pin to ground to assure stability.(1)
OUT
(1) See Input and Output Capacitor Requirements section for more details.
4
Copyright © 2011–2017, Texas Instruments Incorporated
TLV70018-Q1, TLV70012-Q1
www.ti.com.cn
ZHCS844C –NOVEMBER 2011–REVISED JUNE 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted.(1)
MIN
–0.3
–0.3
–0.3
MAX
6.0
UNIT
IN
V
V
V
Voltage(2)
EN
6.0
OUT
OUT
6.0
Current (source)
Internally Limited
Indefinite
Output short-circuit duration
Operating virtual junction, TJ
Storage temperature, Tstg
–55
–55
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
2000
750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range, unless otherwise noted.
MIN
MAX
5.5
UNIT
V
VIN
Input voltage
IN
2
0
VEN
VOUT
IOUT
TJ
Enable voltage
EN
OUT
5.5
V
Output voltage
0
1.8
V
Current output
0
300
150
mA
°C
Operating junction temperature
–40
6.4 Thermal Information
TLV70018-Q1,
TLV70012-Q1
THERMAL METRIC(1)
UNIT
DDC (SOT)
5 PINS
262.8
68.2
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
81.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.1
ψJB
80.9
RθJC(bot)
NA
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2011–2017, Texas Instruments Incorporated
5
TLV70018-Q1, TLV70012-Q1
ZHCS844C –NOVEMBER 2011–REVISED JUNE 2017
www.ti.com.cn
6.5 Electrical Characteristics
At VIN = VOUT(NOM) + 0.5 V or 2 V (whichever is greater); IOUT = 10 mA, VEN = 0.9 V, COUT = 1.0 μF, and TA = –40°C to 125°C,
unless otherwise noted. Typical values are at TA = 25°C, unless otherwise noted.
PARAMETER
Input voltage range
DC output accuracy
Line regulation
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIN
2
5.5
2%
5
V
VOUT
–40°C ≤ TA ≤ 125°C
–2% 0.5%
ΔVOUT/ΔVIN
VOUT(NOM) + 0.5 V ≤ VIN ≤ 5.5 V, IOUT = 10 mA
0 mA ≤ IOUT ≤ 300 mA, TLV70018-Q1
0 mA ≤ IOUT ≤ 300 mA, TLV70012-Q1
VOUT = 0.9 × VOUT(NOM)
1
1
1
mV
mV
15
20
ΔVOUT/ΔIOUT Load regulation
ICL
Output current limit
Ground pin current
320
500
35
370
400
1
860 mA
IOUT = 0 mA
55
μA
μA
nA
μA
μA
dB
IGND
IOUT = 300 mA, VIN = VOUT + 0.5 V
V
V
V
EN ≤ 0.4 V, VIN = 2.0 V
ISHDN
Ground pin current (shutdown)
EN ≤ 0.4 V, 2.0 V ≤ VIN ≤ 4.5 V, TA = –40°C to 85°C
EN ≤ 0.4 V, 2.0 V ≤ VIN ≤ 4.5 V, TA = 85°C to 125°C
2
1
2.5
PSRR
Vn
Power-supply rejection ratio
Output noise voltage
VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA, f = 1 kHz
68
BW = 100 Hz to 100 kHz,
VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA
48
μVRMS
tSTR
Startup time(1)
COUT = 1.0 μF, IOUT = 300 mA
100
μs
V
VEN(HI)
VEN(LO)
IEN
Enable pin high (enabled)
Enable pin low (disabled)
Enable pin current
0.9
0
VIN
0.4
V
VIN = VEN = 5.5 V
0.04
1.9
μA
V
UVLO
Undervoltage lockout
VIN rising
Shutdown, temperature increasing
Reset, temperature decreasing
165
145
°C
°C
°C
TSD
TA
Thermal shutdown temperature
Operating temperature
–40
125
(1) Startup time = time from EN assertion to 0.98 × VOUT(NOM)
.
6
Copyright © 2011–2017, Texas Instruments Incorporated
TLV70018-Q1, TLV70012-Q1
www.ti.com.cn
ZHCS844C –NOVEMBER 2011–REVISED JUNE 2017
6.6 Typical Characteristics
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(NOM) + 0.5 V or 2 V, whichever is greater; IOUT = 10 mA,
VEN = VIN, COUT = 1.0 μF, unless otherwise noted. Typical values are at TJ = 25°C.
1.90
1.88
1.86
1.84
1.82
1.80
1.78
1.76
1.74
1.72
1.70
1.90
1.88
1.86
1.84
1.82
1.80
1.78
1.76
1.74
1.72
1.70
VOUT = 1.8 V
IOUT = 10 mA
VOUT = 1.8 V
IOUT = 300 mA
+125°C
+85°C
+25°C
-40°C
+125°C
+85°C
+25°C
-40°C
2.1
2.6
3.1
3.6
4.1
4.6
5.1
5.6
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VIN (V)
VIN (V)
Figure 1. Line Regulation 10 mA
Figure 2. Line Regulation 300 mA
1.90
1.88
1.86
1.84
1.82
1.80
1.78
1.76
1.74
1.72
1.70
1.90
1.88
1.86
1.84
1.82
1.80
1.78
1.76
1.74
1.72
1.70
VOUT = 1.8 V
VOUT = 1.8 V
+125°C
+85°C
+25°C
-40°C
10mA
150mA
200mA
0
50
100
150
200
250
300
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
IOUT (mA)
Figure 4. Output Voltage vs Temperature
Figure 3. Load Regulation
50
45
40
35
30
25
20
15
10
5
450
400
350
300
250
200
150
100
50
VOUT = 1.8 V
VOUT = 1.8 V
+125°C
+85°C
+25°C
-40°C
+125°C
+85°C
+25°C
-40°C
0
0
2.1
2.6
3.1
3.6
4.1
4.6
5.1
5.6
0
50
100
150
200
250
300
VIN (V)
IOUT (mA)
Figure 5. Ground Pin Current vs Input Voltage
Figure 6. Ground Pin Current vs Load
Copyright © 2011–2017, Texas Instruments Incorporated
7
TLV70018-Q1, TLV70012-Q1
ZHCS844C –NOVEMBER 2011–REVISED JUNE 2017
www.ti.com.cn
Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(NOM) + 0.5 V or 2 V, whichever is greater; IOUT = 10 mA,
VEN = VIN, COUT = 1.0 μF, unless otherwise noted. Typical values are at TJ = 25°C.
2.5
50
45
40
35
30
25
20
15
10
5
VOUT = 1.8 V
VOUT = 1.8 V
2
1.5
1
+125°C
+85°C
+25°C
-40°C
0.5
0
0
2.1
2.6
3.1
3.6
4.1
4.6
5.1
5.6
-40 -25 -10
5
20 35 50 65 80 95 110 125
VIN (V)
Temperature (°C)
Figure 7. Ground Pin Current vs Temperature
Figure 8. Shutdown Current vs Input Voltage
700
600
500
400
300
200
100
0
100
90
80
70
60
50
40
30
20
10
0
VOUT = 1.8 V
IOUT = 10 mA
IOUT = 150 mA
+125°C
+85°C
+25°C
-40°C
VIN - VOUT = 0.5 V
10
100
1 k
10 k
100 k
1 M
10 M
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VIN (V)
Frequency (Hz)
Figure 9. Current Limit vs Input Voltage
Figure 10. Power-Supply Ripple Rejection vs Frequency
10
80
70
60
50
40
30
20
10
0
VOUT = 1.8 V
VOUT = 1.8 V
1 kHz
IOUT = 10 mA
CIN = COUT = 1 mF
1
10 kHz
100 kHz
0.1
0.01
0.001
10
100
1 k
10 k
100 k
1 M
10 M
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Frequency (Hz)
Input Voltage (V)
Figure 12. Output Spectral Noise Density vs Frequency
Figure 11. Power-Supply Ripple Rejection vs Input Voltage
8
Copyright © 2011–2017, Texas Instruments Incorporated
TLV70018-Q1, TLV70012-Q1
www.ti.com.cn
ZHCS844C –NOVEMBER 2011–REVISED JUNE 2017
Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(NOM) + 0.5 V or 2 V, whichever is greater; IOUT = 10 mA,
VEN = VIN, COUT = 1.0 μF, unless otherwise noted. Typical values are at TJ = 25°C.
tR = tF = 1 ms
tR = tF = 1 ms
200 mA
10 mA
0 mA
IOUT
IOUT
0 mA
VOUT
VOUT
VOUT = 1.8 V
VOUT = 1.8 V
10 ms/div
10 ms/div
Figure 13. Load Transient Response
Figure 14. Load Transient Response
tR = tF = 1 ms
tR = tF = 1 ms
300 mA
IOUT
50 mA
0 mA
IOUT
0 mA
VOUT
VOUT
VOUT = 1.8 V
VOUT = 1.8 V
10 ms/div
10 ms/div
Figure 16. Load Transient Response
Figure 15. Load Transient Response
Slew Rate = 1 V/ms
Slew Rate = 1 V/ms
VIN
2.9 V
2.9 V
2.3 V
VIN
2.3 V
VOUT
VOUT
VOUT = 1.8 V
VOUT = 1.8 V
IOUT = 1 mA
IOUT = 300 mA
1 ms/div
1 ms/div
Figure 17. Line Transient Response
Figure 18. Line Transient Response
Copyright © 2011–2017, Texas Instruments Incorporated
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TLV70018-Q1, TLV70012-Q1
ZHCS844C –NOVEMBER 2011–REVISED JUNE 2017
www.ti.com.cn
Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(NOM) + 0.5 V or 2 V, whichever is greater; IOUT = 10 mA,
VEN = VIN, COUT = 1.0 μF, unless otherwise noted. Typical values are at TJ = 25°C.
Slew Rate = 1 V/ms
VOUT = 1.8 V
VOUT = 1.8 V
IOUT = 1 mA
VIN
5.5 V
IOUT = 300 mA
VIN
2.1 V
VOUT
VOUT
1 ms/div
200 ms/div
Figure 19. Line Transient Response
Figure 20. VIN Ramp Up, Ramp Down Response
10
Copyright © 2011–2017, Texas Instruments Incorporated
TLV70018-Q1, TLV70012-Q1
www.ti.com.cn
ZHCS844C –NOVEMBER 2011–REVISED JUNE 2017
7 Detailed Description
7.1 Overview
The TLV70018-Q1 and TLV70012-Q1 low-dropout (LDO) linear regulators are low-quiescent-current devices with
excellent line and load transient performance. These LDOs are designed for power-sensitive applications. A
precision bandgap and error amplifier provides overall 2% accuracy together with low output noise, very high
power-supply rejection ratio (PSRR), and low dropout voltage.
7.2 Functional Block Diagrams
IN
OUT
Current
Limit
Thermal
Shutdown
UVLO
Bandgap
EN
LOGIC
TLV700xx Series
GND
7.3 Feature Description
7.3.1 Internal Current Limit
The TLV70018-Q1 and TLV70012-Q1 internal current limit helps to protect the regulator during fault conditions.
During current limit, the output sources a fixed amount of current that is largely independent of the output
voltage. In such a case, the output voltage is not regulated, and is VOUT = ILIMIT × RLOAD. The PMOS pass
transistor dissipates (VIN – VOUT) × ILIMIT until thermal shutdown is triggered and the device turns off. As the
device cools, it is turned on by the internal thermal shutdown circuit. If the fault condition continues, the device
cycles between current limit and thermal shutdown. See the Thermal Considerations section for more details.
The PMOS pass element in the TLV70018-Q1 and TLV70012-Q1 has a built-in body diode that conducts current
when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage
operation is anticipated, external limiting to 5% of the rated output current is recommended.
7.3.2 Dropout Voltage
The TLV70018-Q1 and TLV70012-Q1 use a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is
less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-
output resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current
because the PMOS device behaves as a resistor in dropout.
As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout.
Figure 11 illustrates this effect.
Copyright © 2011–2017, Texas Instruments Incorporated
11
TLV70018-Q1, TLV70012-Q1
ZHCS844C –NOVEMBER 2011–REVISED JUNE 2017
www.ti.com.cn
Feature Description (continued)
7.3.3 Undervoltage Lockout (UVLO)
The TLV70018-Q1 and TLV70012-Q1 use an undervoltage lockout circuit to keep the output shut off until internal
circuitry is operating properly.
7.3.4 Thermal Shutdown
Thermal protection disables the output when the junction temperature rises to approximately 165°C, allowing the
device to cool. When the junction temperature cools to approximately 145°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a
result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least 40°C above the maximum expected ambient condition of the particular application. This
configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature
and worst-case load.
The internal protection circuitry of the TLV70018-Q1 and TLV70012-Q1 has been designed to protect against
overload conditions. It was not intended to replace proper heatsinking. Continuously running the TLV70018-Q1 or
TLV70012-Q1 into thermal shutdown degrades device reliability.
7.4 Device Functional Modes
7.4.1 Shutdown
The enable pin (EN) is active high. The device is enabled when voltage at EN pin goes above 0.9 V. This
relatively lower value of voltage required to turn the LDO on can be exploited to power the LDO with a GPIO of
recent processors whose GPIO Logic 1 voltage level is lower than traditional microcontrollers. The device is
turned off when the EN pin is held at less than 0.4 V. When shutdown capability is not required, EN can be
connected to the IN pin.
7.4.2 Operation with VIN Less than 2 V
The TLV70018-Q1 and TLV70012-Q1 devices operate with input voltages above 2 V. The typical UVLO voltage
is 1.9 V and the device operates at an input voltage above 2 V. When input voltage falls below UVLO voltage,
the device will shutdown.
7.4.3 Operation with VIN Greater than 2 V
When VIN is greater than 2 V, if input voltage is higher than desired output voltage plus dropout voltage, the
output voltage is equal to the desired value. Otherwise, output voltage will be VIN minus dropout voltage.
12
Copyright © 2011–2017, Texas Instruments Incorporated
TLV70018-Q1, TLV70012-Q1
www.ti.com.cn
ZHCS844C –NOVEMBER 2011–REVISED JUNE 2017
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV70018-Q1 and TLV70012-Q1 consume low quiescent current and deliver excellent line and load
transient performance. These characteristics, combined with low noise and very good PSRR with little (VIN
–
VOUT) headroom, make this family of devices ideal for portable RF applications. This family of regulators offers
current limit and thermal protection, and is specified from –40°C to 125°C.
8.2 Typical Application
VIN
VOUT
IN
OUT
TLV700xx-Q1
EN
1 uF
1 uF
GND
Figure 21. Simplified Schematic
8.2.1 Design Requirements
For this design example use, the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
PARAMETER
Input voltage range
EXAMPLE VALUE
2 V to 5.5 V
1.2 V, 1.8 V
300 mA
Output voltage
Output current rating
Effective output capacitor range
Maximum output capacitor ESR range
>0.1 µF
<200 mΩ
Copyright © 2011–2017, Texas Instruments Incorporated
13
TLV70018-Q1, TLV70012-Q1
ZHCS844C –NOVEMBER 2011–REVISED JUNE 2017
www.ti.com.cn
8.2.2 Detailed Design Procedure
8.2.2.1 Input and Output Capacitor Requirements
1.0-μF X5R- and X7R-type ceramic capacitors are recommended because these capacitors have minimal
variation in value and equivalent series resistance (ESR) over temperature.
However, the TLV70018-Q1 and TLV70012-Q1 are designed to be stable with an effective capacitance of 0.1 μF
or larger at the output. Thus, the device is stable with capacitors of other dielectric types as well, as long as the
effective capacitance under operating bias voltage and temperature is greater than 0.1 μF. This effective
capacitance refers to the capacitance that the LDO sees under operating bias voltage and temperature
conditions; that is, the capacitance after taking both bias voltage and temperature derating into consideration. In
addition to allowing the use of lower-cost dielectrics, this capability of being stable with 0.1-μF effective
capacitance also enables the use of smaller-footprint capacitors that have higher derating in size- and space-
constrained applications.
NOTE
Using a 0.1-μF rated capacitor at the output of the LDO does not ensure stability because
the effective capacitance under the specified operating conditions would be less than
0.1 μF. Maximum ESR should be less than 200 mΩ.
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to
1.0-μF, low ESR capacitor across the IN pin and GND pin of the regulator. This capacitor counteracts reactive
input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor
may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the
power source. If source impedance is more than 2 Ω, a 0.1-μF input capacitor may be necessary to ensure
stability.
8.2.2.2 Transient Response
As with any regulator, increasing the size of the output capacitor reduces overshoot or undershoot magnitude but
increases the duration of the transient response.
8.2.3 Application Curve
Figure 22. Power Up
9 Power Supply Recommendations
The device is designed to operate from an input-voltage supply range between 2 V and 5.5 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the device, TI recommends
adding a capacitor with a value of 0.1 µF and a ceramic bypass capacitor at the input.
14
Copyright © 2011–2017, Texas Instruments Incorporated
TLV70018-Q1, TLV70012-Q1
www.ti.com.cn
ZHCS844C –NOVEMBER 2011–REVISED JUNE 2017
10 Layout
10.1 Layout Guidelines
Input and output capacitors should be placed as close to the device pins as possible. To improve ac performance
such as PSRR, output noise, and transient response, the board is recommended to be designed with separate
ground planes for VIN and VOUT, with the ground plane connected only at the GND pin of the device. In addition,
the ground connection for the output capacitor should be connected directly to the GND pin of the device. High
ESR capacitors may degrade PSRR performance.
10.2 Layout Example
IN
OUT
N/C
1
2
3
5
4
GND
EN
Figure 23. TLV700xx Layout Example
10.3 Thermal Considerations
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to 125°C maximum.
To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature
until the thermal protection is triggered; use worst-case loads and signal conditions.
10.4 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to the ambient air.
Thermal performance data for TLV70018-Q1 and TLV70012-Q1 were gathered using the TLV700 evaluation
module (EVM), a 2-layer board with two ounces of copper per side. Corresponding thermal performance data are
given in Thermal Information. Note that this board has provision for soldering not only the SOT23-5 package on
the bottom layer, but also the SC-70 package on the top layer. Using heavier copper increases the effectiveness
in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves
heatsink effectiveness.
Copyright © 2011–2017, Texas Instruments Incorporated
15
TLV70018-Q1, TLV70012-Q1
ZHCS844C –NOVEMBER 2011–REVISED JUNE 2017
www.ti.com.cn
Power Dissipation (continued)
10.4.1 Thermal Calculations
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of
the output current and the voltage drop across the output pass element, as shown in Equation 1.
PD = IOUT ´(VIN - VOUT ) +IQ ´ VIN
where
•
•
•
•
PD is continuous power dissipation
IOUT is output current
VIN is input voltage
VOUT is output voltage
(1)
Since IQ << IOUT, the term IQ × VIN is always ignored.
For a device under operation at a given ambient air temperature (TA), use Equation 2 to calculate the junction
temperature (TJ).
TJ = TA + (RqJA ´ PD )
where
•
Z
θJA is the junction-to-ambient air temperature thermal impedance
(2)
(3)
Use Equation 3 to calculate the rise in junction temperature due to power dissipation.
DT = TJ - TA = (RqJA ´PD )
For a given maximum junction temperature (TJ(MAX), use Equation 4 to calculate the maximum ambient air
temperature (TA(MAX) at which the device can operate.
TA max = TJmax - (RqJA ´ P )
D
(4)
16
版权 © 2011–2017, Texas Instruments Incorporated
TLV70018-Q1, TLV70012-Q1
www.ti.com.cn
ZHCS844C –NOVEMBER 2011–REVISED JUNE 2017
11 器件和文档支持
11.1 器件支持
11.1.1 封装
有关 TLV70018-Q1 焊盘尺寸建议，可访问德州仪器 (TI) 网站 www.ti.com.cn。
11.2 文档支持
11.2.1 相关文档
相关文档如下：
TLV700 评估模块
11.3 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即购买的快速链接。
表 2. 相关链接
器件
产品文件夹
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具和软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
TLV70018-Q1
TLV70012-Q1
11.4 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可收到任意产
品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
11.5 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.6 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。
版权 © 2011–2017, Texas Instruments Incorporated
17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV70012QDDCRQ1
TLV70018QDDCRQ1
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDC
DDC
5
5
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
SDO
DAL
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV70012QDDCRQ1
TLV70018QDDCRQ1
SOT-
23-THIN
DDC
DDC
5
5
3000
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
SOT-
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
23-THIN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV70012QDDCRQ1
TLV70018QDDCRQ1
SOT-23-THIN
SOT-23-THIN
DDC
DDC
5
5
3000
3000
213.0
213.0
191.0
191.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DDC0005A
SOT-23 - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
3.05
2.55
1.1
0.7
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
5
1
NOTE 4
(0.15)
0.95
3.05
2.75
1.9
2
3
(0.2)
4
0.1
TYP
0.0
0.5
0.3
5X
0.2
C A B
0.25
GAGE PLANE
0.20
0.12
TYP
0 -8 TYP
C
SEATING PLANE
0.6
0.3
TYP
4220752/A 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0005A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
5X (1.1)
5X (0.6)
1
5
SYMM
2
3
4X (0.95)
4
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4220752/A 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0005A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
5X (1.1)
5X (0.6)
1
5
SYMM
2
3
4X(0.95)
4
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4220752/A 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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