TLV7011DPWR [TI]
具有推挽开路输出的低功耗小型比较器 | DPW | 5 | -40 to 125;
| 型号： | TLV7011DPWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有推挽开路输出的低功耗小型比较器 | DPW | 5 | -40 to 125 放大器 光电二极管 比较器 |
| 文件： | 总51页 (文件大小：3207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV7011, TLV7021, TLV7012, TLV7022
ZHCSGK4E –SEPTEMBER 2017–REVISED NOVEMBER 2019
TLV701x 和 TLV702x 小尺寸、低功耗、低电压比较器
1 特性
TLV701x 和 TLV702x 提供出色的速度功率综合性能，
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超小型封装：X2SON (0.8 x 0.8mm2)
1
其传播延迟为 260ns，静态电源电流为 5μA。得益于
这种微功率下快速响应时间的综合性能，功率敏感型系
统能够监测故障状况并快速做出响应。这些比较器的工
作电压范围为 1.6V 至 6.5V，因此可与 3V 和 5V 系统
兼容。
标准封装：SOT23、SC70、VSSOP
1.6V 至 6.5V 的宽电源电压范围
5µA 静态电源电流
260ns 低传播延迟
轨至轨共模输入电压
此外，这些比较器在发生过驱动输入和内部迟滞时，不
会产生输出相位反转。这些 特性 该系列的比较器非常
适合在恶劣嘈杂环境中进行精密电压监测，其中缓慢输
入信号必须转换为无噪声数字输出。
内部迟滞
推挽和开漏输出选项
过驱动输入无相位反转
–40°C 至 +125°C 的工作环境温度范围
TLV701x 具有推挽式输出级，能够灌/拉毫安级电流，
同时可对 LED 进行控制或驱动容性负载。TLV702x 具
有可上拉到 VCC 之上的漏极开路输出级，因此适用于
电平转换器和双极至单端转换器。
2 应用
•
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手机和平板电脑
便携式电池供电器件
红外接收器
器件信息(1)
电平转换器
器件型号
TLV7011、
封装（引脚）
X2SON (5)
封装尺寸（标称值）
0.80mm × 0.80mm
2.00mm × 1.25mm
2.90mm × 1.60mm
阈值检测器与鉴别器
窗口比较器
SC70 (5)
TLV7021
过零检测器
SOT-23 (5)
TLV7012、
TLV7022
VSSOP (8)
3mm x 3mm
3 说明
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
TLV7011/7021（单通道）和 TLV7012/7022（双通
道）是微功耗比较器，采用低工作电压，具有轨至轨输
入功能。这些比较器采用 0.8mm × 0.8mm 超小型无引
线封装和标准引线式封装，适用于空间紧凑型设计，例
如智能手机和其他便携式或电池供电 应用。
TLV70x1 系列低功耗比较器
部件号
输出
IQ（典型值）
t
PD（典型值）
260ns
260ns
3µs
TLV701x
TLV702x
TLV703x
TLV704x
推挽
5µA
漏极开路
推挽
5µA
335nA
335nA
漏极开路
3µs
X2SON 封装与 SC70 和美元硬币对比
US dime (18x18x1.35 mm3)
传播延迟与过驱动
0.4
0.35
0.3
Rising Edge
Falling Edge
5-Lead SC70
5-Pin X2SON
0.25
0.2
10
20
30
40
50
60
Input Overdrive (mV)
70
80
90
100
TLV7
TA = 25°C，VCC = 5V，CL = 15pF
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSDM5
TLV7011, TLV7021, TLV7012, TLV7022
ZHCSGK4E –SEPTEMBER 2017–REVISED NOVEMBER 2019
www.ti.com.cn
目录
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 16
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Applications ................................................ 20
Power Supply Recommendations...................... 25
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings (Single)......................... 5
6.2 Absolute Maximum Ratings (Dual) ........................... 5
6.3 ESD Ratings.............................................................. 5
6.4 Recommended Operating Conditions (Single) ......... 5
6.5 Recommended Operating Conditions (Dual)............ 6
6.6 Thermal Information (Single) .................................... 6
6.7 Thermal Information (Dual) ....................................... 6
6.8 Electrical Characteristics (Single) ............................. 7
6.9 Switching Characteristics (Single) ............................ 7
6.10 Electrical Characteristics (Dual).............................. 8
6.11 Switching Characteristics (Dual) ............................. 8
6.12 Timing Diagrams..................................................... 8
6.13 Typical Characteristics.......................................... 10
Detailed Description ............................................ 16
8
9
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 器件和文档支持 ..................................................... 26
11.1 器件支持................................................................ 26
11.2 相关链接................................................................ 26
11.3 接收文档更新通知 ................................................. 26
11.4 社区资源................................................................ 26
11.5 商标....................................................................... 26
11.6 静电放电警告......................................................... 26
11.7 Glossary................................................................ 26
12 机械、封装和可订购信息....................................... 26
7
4 修订历史记录
Changes from Revision D (February 2019) to Revision E
Page
•
已添加 添加了双通道选项 ....................................................................................................................................................... 1
Changes from Revision C (March 2018) to Revision D
Page
•
•
•
已添加 添加了引线式封装选项，目标位置： 特性 .................................................................................................................. 1
已删除 SOT23 封装的预览状态 .............................................................................................................................................. 1
Deleted preview status of SOT23 package............................................................................................................................ 3
Changes from Revision B (November 2017) to Revision C
Page
•
将预览 SC70 封装更改为生产数据.......................................................................................................................................... 1
Changes from Revision A (July 2017) to Revision B
Page
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已将传播延迟从 200ns 更改为 260ns .................................................................................................................................... 1
向数据表添加了预览 SC70 和 SOT-23 封装........................................................................................................................... 1
应营销部门请求添加了 TLV70x1 系列微功耗比较器............................................................................................................... 1
已将重要图形标题从传播延迟与过驱电压 (TLV7011) 间的关系更改为传播延迟与过驱电压间的关系.................................... 1
Removed (TLV7011 only) text from several Typical Characteristics graphs ....................................................................... 10
Removed some Typical Characteristics graphs .................................................................................................................. 10
Added 图 14.......................................................................................................................................................................... 10
Added 图 21 ......................................................................................................................................................................... 12
Added content to the Inputs section..................................................................................................................................... 16
Added the IR Receiver Analog Front End section................................................................................................................ 21
2
版权 © 2017–2019, Texas Instruments Incorporated
TLV7011, TLV7021, TLV7012, TLV7022
www.ti.com.cn
ZHCSGK4E –SEPTEMBER 2017–REVISED NOVEMBER 2019
Changes from Original (May 2017) to Revision A
Page
•
将器件状态从“高级信息”更改为“生产数据”.............................................................................................................................. 1
5 Pin Configuration and Functions
DPW Package
5-Pin X2SON
Top View
OUT
1
5
IN+
3
VEE
VCC
2
4
IN
Not to scale
DBV and DCK Package
5-Pin SOT-23 and SC70
Top View
1
2
3
5
VCC
OUT
VEE
IN+
4
IN-
Pin Functions
PIN
I/O/P(1)
DESCRIPTION
NAME
OUT
VCC
X2SON
SOT-23, SC70
1
2
3
4
5
1
5
2
4
3
O
P
P
I
Output
Positive (highest) power supply
Negative (lowest) power supply
Inverting input
VEE
IN–
IN+
I
Noninverting input
(1) I = Input, O = Output, P = Power
Copyright © 2017–2019, Texas Instruments Incorporated
3
TLV7011, TLV7021, TLV7012, TLV7022
ZHCSGK4E –SEPTEMBER 2017–REVISED NOVEMBER 2019
www.ti.com.cn
TLV7012/22 DGK Packages
8-Pin VSSOP
Top View
1
2
3
4
8
7
OUTA
VCC
OUTB
INB-
INB+
INA-
INA+
VEE
6
5
Pin Functions: TLV7012/22
PIN
I/O
DESCRIPTION
NAME
INA–
INA+
INB–
INB+
OUTA
OUTB
VEE
NO.
2
I
I
Inverting input, channel A
3
Noninverting input, channel A
Inverting input, channel B
6
I
5
I
Noninverting input, channel B
Output, channel A
1
O
O
—
—
7
Output, channel B
4
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
VCC
8
4
Copyright © 2017–2019, Texas Instruments Incorporated
TLV7011, TLV7021, TLV7012, TLV7022
www.ti.com.cn
ZHCSGK4E –SEPTEMBER 2017–REVISED NOVEMBER 2019
6 Specifications
6.1 Absolute Maximum Ratings (Single)
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Supply voltage (VS = VCC – VEE
)
6
Input pins (IN+, IN–)(2)
VEE – 0.3
6
±10
V
Current into Input pins (IN+, IN–)(2)
Output (OUT)
mA
TLV7011/7012(3)
TLV7021/7022
VEE – 0.3
VEE – 0.3
VCC + 0.3
6
V
Output short-circuit duration(4)
Junction temperature, TJ
Storage temperature, Tstg
10
s
150
°C
°C
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to VEE. Input signals that can swing 0.3V below VEE must be current-limited to 10mA or less.
(3) Output maximum is (VCC + 0.3V) or 6V, whichever is less.
(4) Short-circuit to ground, one comparator per package.
6.2 Absolute Maximum Ratings (Dual)
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
UNIT
V
Supply voltage VS = VCC - VEE
Input pins (IN+, IN-)(2)
7
VEE – 0.3
7
±10
V
Current into Input pins (IN+, IN-)
Output (OUT) (TLV7012)(3)
Output (OUT) (TLV7022)
Output short-circuit duration(4)
Junction temperature, TJ
mA
V
VEE – 0.3
VEE – 0.3
VCC + 0.3
7
V
10
s
150
°C
°C
Storage temperature, Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to VEE. Input signals that can swing 0.3V below VEE must be current-limited to 10mA or less
(3) Output maximum is (VCC + 0.3 V) or 7 V, whichever is less.
(4) Short-circuit to ground, one comparator per package.
6.3 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions (Single)
over operating free-air temperature range (unless otherwise noted)
MIN
1.6
NOM
MAX
5.5
UNIT
V
Supply voltage (VS = VCC – VEE
)
Input Voltage Range
VEE – 0.1
–40
VCC + 0.2
125
V
Ambient temperature, TA
°C
Copyright © 2017–2019, Texas Instruments Incorporated
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TLV7011, TLV7021, TLV7012, TLV7022
ZHCSGK4E –SEPTEMBER 2017–REVISED NOVEMBER 2019
www.ti.com.cn
6.5 Recommended Operating Conditions (Dual)
over operating free-air temperature range (unless otherwise noted)
MIN
1.6
MAX
6.5
UNIT
V
Supply voltage VS = VCC – VEE
Input voltage range
VCC – 0.1
–40
VEE + 0.2
125
V
Ambient temperature, TA
°C
6.6 Thermal Information (Single)
TLV7011/TLV7021
THERMAL METRIC(1)
DPW (X2SON)
5 PINS
497.5
DBV (SOT23)
5 PINS
306.3
DCK (SC70)
5 PINS
278.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
275.5
228.4
188.6
372.2
166.5
113.2
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
55.5
138.5
82.3
ΨJB
370.3
165.3
112.4
RθJC(bot)
165.1
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.7 Thermal Information (Dual)
TLV7012/TLV7022
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
211.7
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
96.1
133.5
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
28.3
ΨJB
131.7
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
Copyright © 2017–2019, Texas Instruments Incorporated
TLV7011, TLV7021, TLV7012, TLV7022
www.ti.com.cn
ZHCSGK4E –SEPTEMBER 2017–REVISED NOVEMBER 2019
6.8 Electrical Characteristics (Single)
VS = 1.8 V to 5 V, VCM = VS / 2; minimum and maximum values are at TA = –40°C to +125°C (unless otherwise noted).
Typical values are at TA = 25°C.
PARAMETER
Input offset voltage
Hysteresis
TEST CONDITIONS
VS = 1.8 V and 5 V, VCM = VS / 2
VS = 1.8 V and 5 V, VCM = VS / 2
VS = 2.5 V to 5 V
MIN
TYP
±0.5
4.2
MAX
UNIT
VIO
±8
mV
VHYS
1.2
VEE
14
mV
VCC + 0.1
VCC + 0.1
VCM
Common-mode voltage range
V
VS = 1.8 V to 2.5 V
VEE + 0.1
IB
Input bias current
Input offset current
5
1
pA
pA
IOS
Output voltage high (for TLV7011
only)
VOH
VOL
ILKG
VS = 5 V, IO = 3 mA
VS = 5 V, IO = 3 mA
4.7
4.8
120
100
V
Output voltage low
220
mV
pA
Open-drain output leakage current VS = 5 V, VID = +0.1 V (output high), VPULLUP
(TLV7021 only)
=
VCC
CMRR
PSRR
Common-mode rejection ratio
Power supply rejection ratio
VEE < VCM < VCC, VS = 5 V
VS = 1.8 V to 5 V, VCM = VS / 2
VS = 5 V, sourcing
VS = 5 V, sinking
78
78
65
44
5
dB
dB
ISC
ICC
Short-circuit current
Supply current
mA
µA
VS = 1.8 V, no load, VID = –0.1 V (Output Low)
10
6.9 Switching Characteristics (Single)
Typical values are at TA = 25°C, VCC = 5 V, VCM = 2.5 V; CL = 15 pF, input overdrive = 100 mV (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Propagation delay time, high-to-low Midpoint of input to midpoint of output, VOD
(RP = 2.5 kΩ TLV7021 only) 100 mV
=
=
tPHL
tPLH
260
ns
Propagation delay time, low-to-high Midpoint of input to midpoint of output, VOD
310
ns
(RP = 2.5 kΩ TLV7021 only)
Rise time (for TLV7011 only)
Fall time
100 mV
tR
20% to 80%
80% to 20%
5
5
ns
ns
µs
tF
(1)
tON
Power-up time
20
(1) During power on, VS must exceed 1.6 V for tON before the output tracks the input.
Copyright © 2017–2019, Texas Instruments Incorporated
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TLV7011, TLV7021, TLV7012, TLV7022
ZHCSGK4E –SEPTEMBER 2017–REVISED NOVEMBER 2019
www.ti.com.cn
6.10 Electrical Characteristics (Dual)
VS = 1.8 V to 5 V, VCM = VS / 2; minimum and maximum values are at TA = –40°C to +125°C (unless otherwise noted).
Typical values are at TA = 25°C.
PARAMETER
Input Offset Voltage
Hysteresis
TEST CONDITIONS
VS = 1.8 V and 5 V, VCM = VS / 2
VS = 1.8 V and 5 V, VCM = VS / 2
MIN
TYP
±0.1
9
MAX
UNIT
mV
mV
V
VIO
VHYS
VCM
IB
±8
2
15
Common-mode voltage range
Input bias current
Input offset current
VEE
VCC + 0.1
2
1
pA
IOS
pA
Output voltage high (for TLV7012
only)
VOH
VOL
ILKG
VS = 5 V, VEE = 0 V, IO = 3 mA
VS = 5 V, VEE = 0 V, IO = 3 mA
4.65
4.8
250
100
V
Output voltage low
350
mV
pA
Open-drain output leakage
current (TLV7022 only)
VS = 5 V, VID = +0.1 V (output high),
VPULLUP = VCC
CMRR
PSRR
Common-mode rejection ratio
Power supply rejection ratio
VEE < VCM < VCC, VS = 5 V
73
77
dB
dB
VS = 1.8 V to 5 V, VCM = VS / 2
VS = 5 V, sourcing (for TLV7012 only)
VS = 5 V, sinking
29
ISC
ICC
Short-circuit current
mA
µA
33
Supply current / Channel
VS = 1.8 V, no load, VID = –0.1 V (Output Low)
4.7
9
6.11 Switching Characteristics (Dual)
Typical values are at TA = 25°C, VS = 5 V, VCM = VS / 2; CL = 15 pF, input overdrive = 100 mV (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Propagation delay time, high to-
Midpoint of input to midpoint of output,
VOD = 100 mV
tPHL
low (RP = 4.99 kΩ TLV7022
310
ns
(1)
only)
Propagation delay time, low-to high
Midpoint of input to midpoint of output,
VOD = 100 mV
tPLH
(RP = 4.99 kΩ TLV7022
260
ns
(1)
only)
tR
tF
Rise time (TLV7012 only)
Fall time
Measured from 20% to 80%
Measured from 20% to 80%
5
5
ns
ns
During power on, VCC must exceed 1.6V for
200 µs before the output is in correct state.
tON
Power-up time
20
µs
(1) The lower limit for RP is 650 Ω
6.12 Timing Diagrams
tON
VEE
VEE + 1.6V
VCC
VOH/2
VEE
OUT
图 1. Start-Up Time Timing Diagram (IN+ > IN–)
8
版权 © 2017–2019, Texas Instruments Incorporated
TLV7011, TLV7021, TLV7012, TLV7022
www.ti.com.cn
ZHCSGK4E –SEPTEMBER 2017–REVISED NOVEMBER 2019
Timing Diagrams (接下页)
V+
Input
Input
+
Output
VREF + 100 mV
VREF
œ
Vœ
+
VREF
œ
VREF Å 100 mV
Vœ
tpLH
tpHL
V+
80%
80%
Output
50%
20%
50%
20%
Vœ
tR
tF
图 2. Propagation Delay Timing Diagram
版权 © 2017–2019, Texas Instruments Incorporated
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TLV7011, TLV7021, TLV7012, TLV7022
ZHCSGK4E –SEPTEMBER 2017–REVISED NOVEMBER 2019
www.ti.com.cn
6.13 Typical Characteristics
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
0.5
0.5
0.4
0.3
0.2
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
0.4
0.3
0.2
0
20
40
60
80 100 120 140 160 180 200
Input Overdrive (mV)
0
20
40
60
80 100 120 140 160 180 200
Input Overdrive (mV)
TLV7
TLV7
TA = 25°C,
TA = 25°C
图 3. TLV7011 Propagation Delay (L-H) vs. Input Overdrive
图 4. Propagation Delay (H-L) vs. Input Overdrive
0.5
0.5
T = -40èC
T = 25èC
T = 85èC
T = 125èC
T = -40èC
T = 25èC
T = 85èC
T = 125èC
0.4
0.3
0.2
0.4
0.3
0.2
0
0
20
40
60
80 100 120 140 160 180 200
Input Overdrive (mV)
20
40
60
80 100 120 140 160 180 200
Input Overdrive (mV)
TLV7
TLV7
VCC = 5 V
VCC = 5 V
图 5. TLV7011 Propagation Delay (L-H) vs. Input Overdrive
图 6. Propagation Delay (H-L) vs. Input Overdrive
0.5
16
14
12
10
8
T = -40èC
T = 25èC
T = 85èC
T = 125èC
0.4
0.3
0.2
6
4
VCM = VCC / 2
VCM = VCC
VCM = 100 mV
2
0
0
20
40
60
80 100 120 140 160 180 200
Input Overdrive (mV)
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
TLV7
TLV7
Rpull-up = 2.5k
图 7. TLV7021 Propagation Delay (L-H) vs. Input Overdrive
VCC = 1.8 V
图 8. Hysteresis vs. Temperature
10
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Typical Characteristics (接下页)
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
16
16
14
12
10
8
14
12
10
8
6
6
4
4
VCM = VCC / 2
VCM = VCC
VCM = 0
VCM = VCC / 2
VCM = VCC
VCM = 0
2
0
2
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
TLV7
TLV7
VCC = 3.3 V
VCC = 5 V
图 9. Hysteresis vs. Temperature
图 10. Hysteresis vs. Temperature
20
18
16
14
12
10
8
20
18
16
14
12
10
8
-40èC
25èC
85èC
125èC
-40èC
25èC
85èC
125èC
6
6
4
4
2
2
0
0.1
0
0
0.3
0.5
0.7
0.9
VCM (V)
1.1
1.3
1.5
1.7
0.5
1
1.5
VCM (V)
2
2.5
3
3.4
TLV7
TLV7
VCC = 1.8 V
VCC = 3.3 V
图 11. Hysteresis vs. VCM
图 12. Hysteresis vs. VCM
40
35
30
25
20
15
10
5
20
18
16
14
12
10
8
-40èC
25èC
85èC
125èC
6
4
2
0
0
0
3
1
2
3
4
5
4
5
Hysteresis (mV)
6
7
VCM (V)
TLV7
TLV7
VCC = 5 V
Distribution Taken From 10,777 Comparators
图 14. Hysteresis Histogram
图 13. Hysteresis vs. VCM
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Typical Characteristics (接下页)
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
0.7
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VCM = VCC / 2
VCM = VCC
VCM = 0
VCM = VCC / 2
VCM = VCC
VCM = 100 mV
0.6
0.5
0.4
0.3
0.2
0.1
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
TLV7
TLV7
VCC = 3.3 V
VCC = 1.8 V
图 16. Input Offset vs. Temperature
图 15. Input Offset vs. Temperature
0.7
0.6
0.5
0.4
0.3
0.2
0.1
4
3
VCM = VCC / 2
VCM = VCC
VCM = 0
2
1
0
-1
-2
-3
0
-4
-40
-20
0
20
40
60
80
100
120
0.1
0.3
0.5
0.7
0.9
VCM (V)
1.1
1.3
1.5
1.7
Temperature (èC)
TLV7
TLV7
VCC = 5 V
VCC = 1.8 V, 50 devices
图 17. Input Offset vs. Temperature
图 18. Input Offset Voltage vs. VCM
4
3
4
3
2
2
1
1
0
0
-1
-2
-3
-1
-2
-3
-4
-4
0
1
2
3
0
0.5
1
1.5
2
2.5
VCM (V)
3
3.5
4
4.5
5
VCM (V)
TLV7
TLV7
VCC = 3.3 V, 50 devices
图 19. Input Offset Voltage vs. VCM
VCC = 5 V, 50 devices
图 20. Input Offset Voltage vs. VCM
12
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Typical Characteristics (接下页)
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
20
1.8
1.795
1.79
15
10
5
1.785
1.78
1.775
1.77
1.765
1.76
-40èC
25èC
85èC
125èC
1.755
1.75
0
0.1
0.2
IOUT (mA)
0.3
0.4
0.5
-3
-2
-2
-1
0
1
Input Offset (mV)
2
3
4
TLV7
TLV7
VCC = 1.8 V
Distribution Taken From 10,777 Comparators
图 22. TLV7011 Output Voltage High vs. Output Source
图 21. Input Offset Voltage Histogram
Current
5
4.95
4.9
0.05
-40èC
25èC
125èC
0.04
0.03
0.02
0.01
0
4.85
4.8
-4è0C
25èC
85èC
125èC
4.75
0.1
1
5
0.1
0.2
IOUT (mA)
0.3
0.4
0.5
IOUT (mA)
TLV7
TLV7
VCC = 5 V
VCC = 1.8 V
图 23. TLV7011 Output Voltage High vs. Output Source
图 24. Output Voltage Low vs. Output Sink Current
Current
60
50
40
30
20
10
0
0.25
-40èC
25èC
125èC
0.2
0.15
0.1
0.05
0
VCC = 3.5 V
VCC = 5.5 V
0.1
0.2 0.3 0.40.5 0.7
1
2
3
4
5
-60 -40 -20
0
20
40
60
80 100 120 140
IOUT (mA)
Temperature (èC)
TLV7
TLV7
VCC = 5 V
图 25. Output Voltage Low vs. Output Sink Current
VCM = VCC/2
图 26. Output Short-Circuit (Sink) Current vs. Temperature
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Typical Characteristics (接下页)
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
90
60
50
40
30
20
10
0
80
70
60
50
40
30
20
-40èC
25èC
85èC
125èC
VCC = 3.5 V
VCC = 5.5 V
10
0
1.8
2.3
2.8
3.3
3.8
VCC (V)
4.3
4.8
5.3
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (èC)
TLV7
TLV7
VCM = VCC/2
VCM = VCC/2
图 28. Output Short Circuit (Sink) vs. VCC
图 27. TLV7011 Output Short-Circuit (Source) Current vs.
Temperature
90
80
70
60
50
40
30
7
6.5
6
5.5
5
4.5
4
3.5
3
-40èC
25èC
85èC
125èC
20
10
0
VCC = 3.3 V
VCC = 5 V
2.5
2
1.8
2.3
2.8
3.3
3.8
VCC (V)
4.3
4.8
5.3
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (èC)
TLV7
TLV7
VCM = VCC/2
图 29. TLV7011 Output Short Circuit (Source) vs. VCC
VCM = VCC/2
图 30. ICC vs. Temperature
7
7
6.5
6
6.5
6
5.5
5
5.5
5
4.5
4
4.5
4
3.5
3
3.5
3
-40èC
25èC
85èC
125èC
-40èC
25èC
85èC
125èC
2.5
2
2.5
2
0
1
1.5
2
2.5
3
VCC (V)
3.5
4
4.5
5
0.5
1
1.5
VCM (V)
2
2.5
3
TLV7
TLV7
VCM = VCC/2
VCC = 3.3 V
图 31. ICC vs. VCC
图 32. ICC vs. VCM
14
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Typical Characteristics (接下页)
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
10000
1000
100
10
7
6.5
6
5.5
5
4.5
4
1
3.5
-40èC
3
25èC
0.1
85èC
125èC
2.5
2
0.01
0
1
2
3
VCM (V)
4
5
5.5
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
TLV7
TLV7
VCC = 5 V
VCC = 3.3V
图 33. ICC vs. VCM
图 34. Input Bias Current vs. Temperature
100000
10000
1000
100
10000
1000
100
10
10
1
1
10
100
1000
Load Capacitance (pF)
10000
100000
10
100
1000
Load Capacitance (pF)
10000
100000
TLV7
TLV7
VOD = 100mV
图 35. TLV7011 Output Rise Time vs. Load Capacitance
VOD = 100mV
图 36. Output Fall Time vs. Load Capacitance
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7 Detailed Description
7.1 Overview
The TLV701x and TLV702x devices are single-channel, micro-power comparators with push-pull and open-drain
outputs. Operating down to 1.6 V and consuming only 5 µA, the TLV701x and TLV702x are ideally suited for
portable and industrial applications. The comparators are available in leadless and leaded packages to offer
significant board space saving in space-challenged designs.
7.2 Functional Block Diagram
VCC
IN+
IN-
+
OUT
œ
Bias
Power-on-reset
GND
Copyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
The TLV701x (push-pull) and TLV702x (open-drain) devices are micro-power comparators that are capable of
operating at low voltages. The TLV701x and TLV702x feature a rail-to-rail input stage capable of operating up to
100 mV beyond the VCC power supply rail. The comparators also feature a push-pull and open-drain output
stage with internal hysteresis.
7.4 Device Functional Modes
The TLV701x and TLV702x have a Power-on-Reset (POR) circuit. While the power supply (VS) is ramping up or
ramping down, the POR circuitry will be activated.
For the TLV701x, the POR circuit will hold the output low (at VEE) while activated.
For the TLV702x, the POR circuit will keep the output high impedance (logical high) while activated.
When the supply voltage is greater than, or equal to, the minimum supply voltage, the comparator output reflects
the state of the differential input (VID).
7.4.1 Inputs
The TLV701x and TLV702x input common-mode extends from VEE to 100 mV above VCC. The differential input
voltage (VID) can be any voltage within these limits. No phase-inversion of the comparator output will occur when
the input pins exceed VCC and VEE
.
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Device Functional Modes (接下页)
While TI recommends operating the TLV701x and TLV702x within the specified common-mode range, the inputs
are fault tolerant to voltages up to 5.5 V independent of the applied VCC value. Fault tolerant is defined as
maintaining the same high input impedance when VCC is unpowered or within the recommended operating range.
Because the inputs of the TLV701x and TLV702x are fault tolerant, the inputs to the comparator can be any
value between 0 V and 5.5 V while VCC is ramping up. This feature allows any supply and input driven sequence
as long as the input value and supply are within the specified ranges. In this case, no current limiting resistor is
required. This is possible since the VCC is isolated from the inputs such that it maintains its value even when a
higher voltage is applied to the input.
The input bias current is typically 1 pA for input voltages between VCC and VEE. The comparator inputs are
protected from undervoltage by internal diodes connected to VEE. As the input voltage goes under VEE, the
protection diodes become forward biased and begin to conduct causing the input bias current to increase
exponentially. Input bias current typically doubles for 10°C temperature increases.
7.4.2 Internal Hysteresis
The device hysteresis transfer curve is shown in 图 37. This curve is a function of three components: VTH, VOS
,
and VHYST
:
•
•
VTH is the actual set voltage or threshold trip voltage.
VOS is the internal offset voltage between VIN+ and VIN–. This voltage is added to VTH to form the actual trip
point at which the comparator must respond to change output states.
•
VHYST is the internal hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise
(4.2 mV for the TLV7011).
VTH + VOS - (VHYST / 2)
VTH + VOS
VTH + VOS + (VHYST / 2)
图 37. Hysteresis Transfer Curve
7.4.3 Output
The TLV701x feature a push-pull output stage eliminating the need for an external pull-up resistor. On the other
hand, the TLV702x feature an open-drain output stage enabling the output logic levels to be pulled up to an
external source independent of the supply voltage.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV701x and TLV702x are micro-power comparators with reasonable response time. The comparators have
a rail-to-rail input stage that can monitor signals beyond the positive supply rail with integrated hysteresis. When
higher levels of hysteresis are required, positive feedback can be externally added. The push-pull output stage of
the TLV701x is optimal for reduced power budget applications and features no shoot-through current. When level
shifting or wire-ORing of the comparator outputs is needed, the TLV702x with its open-drain output stage is well
suited to meet the system needs. In either case, the wide operating voltage range, low quiescent current, and
micro-package of the TLV701x and TLV702x make these comparators excellent candidates for battery-operated
and portable, handheld designs.
8.1.1 Inverting Comparator With Hysteresis for TLV701x
The inverting comparator with hysteresis requires a three-resistor network that is referenced to the comparator
supply voltage (VCC), as shown in 图 38. When VIN at the inverting input is less than VA, the output voltage is
high (for simplicity, assume VO switches as high as VCC). The three network resistors can be represented as R1
|| R3 in series with R2. 公式 1 defines the high-to-low trip voltage (VA1).
R2
VA1 = VCC
´
(R1 || R3) + R2
(1)
When VIN is greater than VA, the output voltage is low, very close to ground. In this case, the three network
resistors can be presented as R2 || R3 in series with R1. Use 公式 2 to define the low to high trip voltage (VA2).
R2 || R3
VA2 = VCC ´
R1 + (R2 || R3)
(2)
(3)
公式 3 defines the total hysteresis provided by the network.
DVA = VA1 - VA2
+VCC
+5 V
R1
1 MW
VIN
5 V
0 V
RLOAD
VA
VO
100 kW
VA2
1.67 V
VA1
3.33 V
R3
1 MW
VIN
R2
1 MW
VO High
+VCC
VO Low
+VCC
R1
VA1
R2
R3
R1
VA2
R2
R3
Copyright © 2016, Texas Instruments Incorporated
图 38. TLV701x in an Inverting Configuration With Hysteresis
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Application Information (接下页)
8.1.2 Noninverting Comparator With Hysteresis for TLV701x
A noninverting comparator with hysteresis requires a two-resistor network, as shown in 图 39, and a voltage
reference (VREF) at the inverting input. When VIN is low, the output is also low. For the output to switch from low
to high, VIN must rise to VIN1. Use 公式 4 to calculate VIN1
VREF
.
VIN1 = R1 ´
+ VREF
R2
(4)
When VIN is high, the output is also high. For the comparator to switch back to a low state, VIN must drop to VIN2
such that VA is equal to VREF. Use 公式 5 to calculate VIN2
VREF (R1 + R2) - VCC ´ R1
.
VIN2
=
R2
(5)
(6)
The hysteresis of this circuit is the difference between VIN1 and VIN2, as shown in 公式 6.
R1
DVIN = VCC
´
R2
+VCC
+5 V
VREF
VO
+2.5 V
VA
VIN
RLOAD
R1
330 kW
R2
1 MW
VO High
+VCC
VO Low
VIN1
5 V
0 V
R2
R1
VA = VREF
R2
VO
VA = VREF
R1
VIN2
VIN1
1.675 V 3.325 V
VIN
VIN2
Copyright © 2016, Texas Instruments Incorporated
图 39. TLV701x in a Noninverting Configuration With Hysteresis
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8.2 Typical Applications
8.2.1 Window Comparator
Window comparators are commonly used to detect undervoltage and overvoltage conditions. 图 40 shows a
simple window comparator circuit.
3.3 V
RPU
R1
UV_OV
+
Micro-
Controller
œ
Sensor
TLV7021
R2
+
œ
TLV7021
R3
Copyright © 2017, Texas Instruments Incorporated
图 40. Window Comparator
8.2.1.1 Design Requirements
For this design, follow these design requirements:
•
•
•
•
Alert (logic low output) when an input signal is less than 1.1 V
Alert (logic low output) when an input signal is greater than 2.2 V
Alert signal is active low
Operate from a 3.3-V power supply
8.2.1.2 Detailed Design Procedure
Configure the circuit as shown in 图 40. Connect VCC to a 3.3-V power supply and VEE to ground. Make R1, R2
and R3 each 10-MΩ resistors. These three resistors are used to create the positive and negative thresholds for
the window comparator (VTH+ and VTH–). With each resistor being equal, VTH+ is 2.2 V and VTH- is 1.1 V. Large
resistor values such as 10-MΩ are used to minimize power consumption. The sensor output voltage is applied to
the inverting and noninverting inputs of the two TLV702x's. The TLV7021 is used for its open-drain output
configuration. Using the TLV702x allows the two comparator outputs to be Wire-Ored together. The respective
comparator outputs will be low when the sensor is less than 1.1 V or greater than 2.2 V. VOUT will be high when
the sensor is in the range of 1.1 V to 2.2 V.
20
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Typical Applications (接下页)
8.2.1.3 Application Curve
VIN
VTH+ = 2.2 V
VTHœ = 1.1 V
Time (usec)
VOUT
Time (usec)
200
50
100
150
图 41. Window Comparator Results
8.2.2 IR Receiver Analog Front End
A single TLV7011 device can be used to build a complete IR receiver analog front end (AFE). The nanoamp
quiescent current and low input bias current make it possible to be powered with a coin cell battery, which could
last for years.
Vref
470 kꢀ
470 kꢀ
10M ꢀ
R4
3 V
IR LED
R2
R3
U1
+
Output to MCU
(Also to wake-up MCU)
œ
VOUT
C1
10M ꢀ
TLV7011
VIN
R1
0.01 ꢁF
GND
Copyright © 2017, Texas Instruments Incorporated
图 42. IR Receiver Analog Front End Using TLV7011
8.2.2.1 Design Requirements
For this design, follow these design requirements:
•
Use a proper resistor (R1) value to generate an adequate signal amplitude applied to the inverting input of the
comparator.
•
The low input bias current IB (2 pA typical) ensures that a greater value of R1 to be used.
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Typical Applications (接下页)
•
The RC constant value (R2 and C1) must support the targeted data rate (that is, 9,600 bauds) to maintain a
valid tripping threshold.
•
The hysteresis introduced with R3 and R4 helps to avoid spurious output toggles.
8.2.2.2 Detailed Design Procedure
The IR receiver AFE design is highly streamlined and optimized. R1 converts the IR light energy induced current
into voltage and applies to the inverting input of the comparator. Because a reverse biased IR LED is used as
the IR receiver, a higher I/V transimpedance gain is required to boost the amplitude of reduced current. A 10M
resistor is used as R1 to support a 1-V, 100-nA transimpedance gain. This is made possible with the picoamps
Input bias current IB (5pA typical). The RC network of R2 and C1 establishes a reference voltage Vref which tracks
the mean amplitude of the IR signal. The RC constant of R2 and C1 (about 4.7 ms) is chosen for Vref to track the
received IR current fluctuation but not the actual data bit stream. The noninverting input is connected to Vref and
the output over the R3 and R4 resistor network which provides additional hysteresis for improved guard against
spurious toggles.
To reduce the current drain from the coin cell battery, data transmission must be short and infrequent.
8.2.2.3 Application Curve
1.8 V
VIN
1.2 V
4.0 V
VOUT
0.0 V
1.61 V
VREF
1.58 V
0.0
200.0 u
400.0 u
Time
600.0 u
800.0 u
图 43. IR Receiver AFE Waveforms
22
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Typical Applications (接下页)
8.2.3 Square-Wave Oscillator
Square-wave oscillator can be used as low cost timing reference or system supervisory clock source.
图 44. Square-Wave Oscillator
8.2.3.1 Design Requirements
The square-wave period is determined by the RC time constant of the capacitor and resistor. The maximum
frequency is limited by propagation delay of the device and the capacitance load at the output. The low input bias
current allows a lower capacitor value and larger resistor value combination for a given oscillator frequency,
which may help to reduce BOM cost and board space.
8.2.3.2 Detailed Design Procedure
The oscillation frequency is determined by the resistor and capacitor values. The following calculation provides
details of the steps.
图 45. Square-Wave Oscillator Timing Thresholds
First consider the output of Figure 图 44 is high which indicates the inverted input VC is lower than the
noninverting input (VA). This causes the C1 to be charged through R4, and the voltage VC increases until it is
equal to the noninverting input. The value of VA at the point is calculated by 公式 7.
VCCìR2
R2 + R1IIR3
VA1
=
(7)
if R1 = R2= R3, then VA1 = 2 VCC/ 3
版权 © 2017–2019, Texas Instruments Incorporated
23
TLV7011, TLV7021, TLV7012, TLV7022
ZHCSGK4E –SEPTEMBER 2017–REVISED NOVEMBER 2019
www.ti.com.cn
Typical Applications (接下页)
At this time the comparator output trips pulling down the output to the negative rail. The value of VAat this point is
calculated by 公式 8.
VCC(R2IIR3 )
VA2
=
R1+R2IIR3
(8)
if R1 = R2 = R3, then VA2 = VCC/3
The C1 now discharges though the R4, and the voltage VCC decreases until it reaches VA2. At this point, the
output switches back to the starting state. The oscillation period equals to the time duration from for C1 from
2VCC/3 to VCC / 3 then back to 2VCC/3, which is given by R4C1 × ln 2 fro each trip. Therefore, the total time
duration is calculated as 2 R4C1 × ln 2. The oscillation frequency can be obtained by 公式 9:
f = 1/ 2 R4ìC1ìIn2
(9)
8.2.3.3 Application Curve
图 46 shows the simulated results of tan oscillator using the following component values:
•
•
•
•
R1 = R2 = R3 = R4 = 100 kΩ
C1 = 100 pF, CL = 20 pF
V+ = 5 V, V– = GND
Cstray (not shown) from VA TO GND = 10 pF
图 46. Square-Wave Oscillator Output Waveform
24
版权 © 2017–2019, Texas Instruments Incorporated
TLV7011, TLV7021, TLV7012, TLV7022
www.ti.com.cn
ZHCSGK4E –SEPTEMBER 2017–REVISED NOVEMBER 2019
9 Power Supply Recommendations
The TLV701x and TLV702x have a recommended operating voltage range (VS) of 1.6 V to 5.5 / 6.5 V. VS is
defined as VCC – VEE. Therefore, the supply voltages used to create VS can be single-ended or bipolar. For
example, single-ended supply voltages of 5 V and 0 V and bipolar supply voltages of +2.5 V and –2.5 V create
comparable operating voltages for VS. However, when bipolar supply voltages are used, it is important to realize
that the logic low level of the comparator output is referenced to VEE
.
Output capacitive loading and output toggle rate will cause the average supply current to rise over the quiescent
current.
10 Layout
10.1 Layout Guidelines
To reduce PCB fabrication cost and improve reliability, TI recommends using a 4-mil via at the center pad
connected to the ground trace or plane on the bottom layer.
A power-supply bypass capacitor of 100 nF is recommended when supply output impedance is high, supply
traces are long, or when excessive noise is expected on the supply lines. Bypass capacitors are also
recommended when the comparator output drives a long trace or is required to drive a capacitive load. Due to
the fast rising and falling edge rates and high-output sink and source capability of the TLV7011 and TLV7021
output stages, higher than normal quiescent current can be drawn from the power supply. Under this
circumstance, the system would benefit from a bypass capacitor across the supply pins.
10.2 Layout Example
OUT
IN+
Top-Layer
Trace
Bottom-Layer
Trace
4 mil VIA
VCC
IN-
8 mil VIA
Package
Body
Outline
Top-View
0.1 uF
图 47. Layout Example
版权 © 2017–2019, Texas Instruments Incorporated
25
TLV7011, TLV7021, TLV7012, TLV7022
ZHCSGK4E –SEPTEMBER 2017–REVISED NOVEMBER 2019
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 评估模块
我们为您提供了评估模块 (EVM)，可以借此来对使用 TLV70x1 器件系列的电路性能进行初始评估。TLV7011 微功
耗比较器 DIP 适配器评估模块 可在德州仪器 (TI) 网站上的产品文件夹下申请，也可以直接从 TI 网上商店购买。
11.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链
接。
表 1. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
TLV7011
TLV7021
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
26
版权 © 2017–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
1-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV7011DBVR
TLV7011DCKR
TLV7011DCKT
TLV7011DPWR
TLV7012DDFR
TLV7012DGKR
TLV7012DSGR
TLV7021DBVR
TLV7021DCKR
TLV7021DCKT
TLV7021DPWR
TLV7022DDFR
TLV7022DGKR
TLV7022DSGR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SC70
DBV
DCK
DCK
DPW
DDF
DGK
DSG
DBV
DCK
DCK
DPW
DDF
DGK
DSG
5
5
5
5
8
8
8
5
5
5
5
8
8
8
3000 RoHS & Green
3000 RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1IC2
19N
19N
7N
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
SC70
250
RoHS & Green
X2SON
3000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
ACTIVE SOT-23-THIN
NIPDAU
7012
7012
7012
1ID2
19O
19O
7P
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
WSON
SOT-23
SC70
NIPDAUAG | SN
NIPDAU
NIPDAUAG
NIPDAU
SC70
250
RoHS & Green
NIPDAU
X2SON
3000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
NIPDAU
ACTIVE SOT-23-THIN
NIPDAU
7022
7022
7022
ACTIVE
ACTIVE
VSSOP
WSON
NIPDAUAG | SN
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Oct-2022
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV7011DBVR
TLV7011DCKR
TLV7011DCKT
TLV7011DPWR
TLV7012DDFR
SOT-23
SC70
DBV
DCK
DCK
DPW
DDF
5
5
5
5
8
3000
3000
250
180.0
178.0
178.0
178.0
180.0
8.4
9.0
9.0
8.4
8.4
3.23
2.4
3.17
2.5
1.37
1.2
1.2
0.5
1.4
4.0
4.0
4.0
2.0
4.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q2
Q3
SC70
2.4
2.5
X2SON
3000
3000
0.91
3.2
0.91
3.2
SOT-23-
THIN
TLV7012DGKR
TLV7012DGKR
TLV7012DSGR
TLV7021DBVR
TLV7021DCKR
TLV7021DCKT
TLV7021DPWR
TLV7022DDFR
VSSOP
VSSOP
WSON
SOT-23
SC70
DGK
DGK
DSG
DBV
DCK
DCK
DPW
DDF
8
8
8
5
5
5
5
8
2500
2500
3000
3000
3000
250
330.0
330.0
180.0
180.0
178.0
178.0
178.0
180.0
12.4
12.4
8.4
8.4
9.0
9.0
8.4
8.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
4.0
4.0
4.0
4.0
2.0
4.0
12.0
12.0
8.0
8.0
8.0
8.0
8.0
8.0
Q1
Q1
Q2
Q3
Q3
Q3
Q2
Q3
2.3
2.3
1.15
1.37
1.2
3.23
2.4
3.17
2.5
SC70
2.4
2.5
1.2
X2SON
3000
3000
0.91
3.2
0.91
3.2
0.5
SOT-23-
THIN
1.4
TLV7022DGKR
TLV7022DGKR
VSSOP
VSSOP
DGK
DGK
8
8
2500
2500
330.0
330.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV7022DSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV7011DBVR
TLV7011DCKR
TLV7011DCKT
TLV7011DPWR
TLV7012DDFR
TLV7012DGKR
TLV7012DGKR
TLV7012DSGR
TLV7021DBVR
TLV7021DCKR
TLV7021DCKT
TLV7021DPWR
TLV7022DDFR
TLV7022DGKR
TLV7022DGKR
TLV7022DSGR
SOT-23
SC70
DBV
DCK
DCK
DPW
DDF
DGK
DGK
DSG
DBV
DCK
DCK
DPW
DDF
DGK
DGK
DSG
5
5
5
5
8
8
8
8
5
5
5
5
8
8
8
8
3000
3000
250
183.0
190.0
190.0
205.0
210.0
364.0
366.0
210.0
183.0
190.0
190.0
205.0
210.0
366.0
364.0
210.0
183.0
190.0
190.0
200.0
185.0
364.0
364.0
185.0
183.0
190.0
190.0
200.0
185.0
364.0
364.0
185.0
20.0
30.0
30.0
33.0
35.0
27.0
50.0
35.0
20.0
30.0
30.0
33.0
35.0
50.0
27.0
35.0
SC70
X2SON
SOT-23-THIN
VSSOP
VSSOP
WSON
3000
3000
2500
2500
3000
3000
3000
250
SOT-23
SC70
SC70
X2SON
SOT-23-THIN
VSSOP
VSSOP
WSON
3000
3000
2500
2500
3000
Pack Materials-Page 3
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.38
0.22
8X
0.1
C A B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/C 10/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/C 10/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/C 10/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DPW0005A
X2SON - 0.4 mm max height
S
C
A
L
E
1
2
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
0.85
0.75
A
B
PIN 1 INDEX AREA
0.85
0.75
0.4 MAX
C
SEATING PLANE
NOTE 3
(0.1)
0.05
0.00
(0.324)
4X (0.05)
0.25 0.1
2
1
4
5
NOTE 3
2X
3
2X (0.26)
0.48
0.27
0.17
4X
0.239
0.139
0.1
C A B
C
0.288
0.188
3X
0.05
4223102/D 03/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The size and shape of this feature may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.78)
(
0.1)
SYMM
4X (0.42)
VIA
0.05 MIN
ALL AROUND
TYP
1
5
4X (0.22)
SYMM
4X (0.26)
(0.48)
3
2
4
(R0.05) TYP
SOLDER MASK
OPENING, TYP
4X (0.06)
(
0.25)
(0.21) TYP
EXPOSED METAL
CLEARANCE
METAL UNDER
SOLDER MASK
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:60X
4223102/D 03/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.42)
4X (0.06)
5
1
4X (0.22)
SYMM
(
0.24)
4X (0.26)
(0.21)
(0.48)
TYP
SOLDER MASK
EDGE
3
2
4
(R0.05) TYP
SYMM
(0.78)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 3
92% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:100X
4223102/D 03/2022
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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