TLV7022 [TI]
微功耗小型比较器（双路、漏极开路输出）;
| 型号： | TLV7022 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 微功耗小型比较器（双路、漏极开路输出） 比较器 |
| 文件： | 总44页 (文件大小：2376K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV7011, TLV7021, TLV7012, TLV7022
SLVSDM5F –SEPTEMBER 2017–REVISED MARCH 2020
TLV701x and TLV702x Small-Size, Low-Power, Low-Voltage Comparators
The TLV701x and TLV702x offer an excellent speed-
to-power combination with a propagation delay of 260
ns and a quiescent supply current of 5 μA. This
combination of fast response time at micropower
enables power conscious systems to monitor and
respond quickly to fault conditions. With an operating
voltage range of 1.6 V to 6.5 V, these comparators
are compatible with 3-V and 5-V systems.
1 Features
•
Ultra-small packages: X2SON (0.8 × 0.8 mm2) ,
1
WSON (2 × 2 mm2)
•
•
•
•
•
•
•
•
•
Standard packages: SOT23, SC70, VSSOP
Wide supply voltage range of 1.6 V to 6.5 V
Quiescent supply current of 5 µA
Low propagation delay of 260 ns
These comparators also feature no output phase
inversion with overdriven inputs and internal
hysteresis. These features make this family of
comparators well suited for precision voltage
monitoring in harsh, noisy environments where slow-
moving input signals must be converted into clean
digital outputs.
Rail-to-rail common-mode input voltage
Internal hysteresis
Push-pull and open-drain output options
No phase reversal for over driven inputs
–40°C to 125°C Operating ambient temperature
The TLV701x have push-pull output stages capable
of sinking and sourcing milliamps of current when
controlling an LED or driving a capacitive load. The
TLV702x have open-drain output stages that can be
pulled beyond VCC, making it appropriate for level
translators and bipolar to single-ended converters.
2 Applications
•
•
•
•
•
•
•
Mobile phones and tablets
Portable and battery-powered devices
IR receivers
Level translators
Device Information(1)
Threshold detectors and discriminators
Window comparators
PART NUMBERS
PACKAGE (PINS)
X2SON (5)
SC70 (5)
BODY SIZE (NOM)
0.80 mm × 0.80 mm
2.00 mm × 1.25 mm
2.90 mm × 1.60 mm
3 mm × 3 mm
Zero-crossing detectors
TLV7011,
TLV7021
3 Description
SOT-23 (5)
VSSOP (8)
SOT-23 (8)
WSON (8)
The
TLV7011/7021
(single-channel)
and
TLV7012,
TLV7022
TLV7012/7022 (dual-channel) are micro-power
comparators that feature low-voltage operation with
rail-to-rail input capability. These comparators are
available in an ultra-small, leadless package
measuring 0.8 mm × 0.8 mm and standard leaded
packages, making them applicable for space-critical
designs like smartphones and other portable or
battery-powered applications.
2.90 mm x 1.60 mm
2 mm x 2 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
TLV70x1 Family of Low Power Comparators
PART
NUMBERS
OUTPUT
IQ
tPD
TLV701x / 2x Push-pull / Open-drain
TLV703x / 4x Push-pull / Open-drain
5 µA
260 ns
3 µs
335 nA
X2SON Package vs SC70 and US Dime
US dime (18x18x1.35 mm3)
Propagation Delay vs. Overdrive
0.4
Rising Edge
Falling Edge
5-Lead SC70
0.35
0.3
5-Pin X2SON
0.25
0.2
10
20
30
40
50
60
Input Overdrive (mV)
70
80
90
100
TLV7
TA = 25°C, VCC = 5 V, CL = 15 pF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV7011, TLV7021, TLV7012, TLV7022
SLVSDM5F –SEPTEMBER 2017–REVISED MARCH 2020
www.ti.com
Table of Contents
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Applications ................................................ 19
Power Supply Recommendations...................... 24
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings (Single)......................... 5
6.2 Absolute Maximum Ratings (Dual) ........................... 5
6.3 ESD Ratings.............................................................. 5
6.4 Recommended Operating Conditions (Single) ......... 5
6.5 Recommended Operating Conditions (Dual)............ 6
6.6 Thermal Information (Single) .................................... 6
6.7 Thermal Information (Dual) ....................................... 6
6.8 Electrical Characteristics (Single) ............................. 7
6.9 Switching Characteristics (Single) ............................ 7
6.10 Electrical Characteristics (Dual).............................. 8
6.11 Switching Characteristics (Dual) ............................. 8
6.12 Timing Diagrams..................................................... 8
6.13 Typical Characteristics.......................................... 10
Detailed Description ............................................ 15
8
9
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 24
11 Device and Documentation Support ................. 25
11.1 Device Support...................................................... 25
11.2 Related Links ........................................................ 25
11.3 Receiving Notification of Documentation Updates 25
11.4 Community Resources.......................................... 25
11.5 Trademarks........................................................... 25
11.6 Electrostatic Discharge Caution............................ 25
11.7 Glossary................................................................ 25
12 Mechanical, Packaging, and Orderable
7
Information ........................................................... 25
4 Revision History
Changes from Revision E (October 2019) to Revision F
Page
•
•
•
Added SOT-23 (8) and WSON (8) for dual channel options.................................................................................................. 1
Added SOT-23 (8) and WSON (8) Pin Functions and Package drawings for dual channel options ..................................... 4
Added SOT-23 (8) and WSON (8) Thermal Tables for dual channel options........................................................................ 5
Changes from Revision D (February 2019) to Revision E
Page
•
Added dual channel options ................................................................................................................................................... 1
Changes from Revision C (March 2018) to Revision D
Page
•
•
•
Added leaded package option to features.............................................................................................................................. 1
Deleted preview status of SOT23 package............................................................................................................................ 1
Deleted preview status of SOT23 package............................................................................................................................ 3
Changes from Revision B (November 2017) to Revision C
Page
•
Changed the preview SC70 package to production data....................................................................................................... 1
Changes from Revision A (July 2017) to Revision B
Page
•
•
•
•
•
Changed propagation delay from: 200 ns to: 260 ns ............................................................................................................ 1
Added preview SC70 and SOT-23 packages to the data sheet ........................................................................................... 1
Added TLV70x1 Family of Micropower Comparators table per marketing request................................................................ 1
Changed the key graphic title from: Propagation Delay vs. Overdrive (TLV7011) to: Propagation Delay vs. Overdrive ...... 1
Removed (TLV7011 only) text from several Typical Characteristics graphs ....................................................................... 10
2
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Product Folder Links: TLV7011 TLV7021 TLV7012 TLV7022
TLV7011, TLV7021, TLV7012, TLV7022
www.ti.com
SLVSDM5F –SEPTEMBER 2017–REVISED MARCH 2020
•
•
•
•
•
Added Figure 7 .................................................................................................................................................................... 10
Added Figure 10 ................................................................................................................................................................... 10
Removed some Typical Characteristics graphs .................................................................................................................. 13
Added content to the Inputs section..................................................................................................................................... 15
Added the IR Receiver Analog Front End section................................................................................................................ 20
Changes from Original (May 2017) to Revision A
Page
•
Changed device status from ADVANCED INFO to PRODUCTION DATA............................................................................ 1
5 Pin Configuration and Functions
DPW Package
5-Pin X2SON
Top View
OUT
1
5
IN+
3
VEE
VCC
2
4
IN
Not to scale
DBV and DCK Package
5-Pin SOT-23 and SC70
Top View
1
2
3
5
VCC
OUT
VEE
IN+
4
IN-
Pin Functions
PIN
I/O/P(1)
DESCRIPTION
NAME
OUT
VCC
X2SON
SOT-23, SC70
1
2
3
4
5
1
5
2
4
3
O
P
P
I
Output
Positive (highest) power supply
Negative (lowest) power supply
Inverting input
VEE
IN–
IN+
I
Noninverting input
(1) I = Input, O = Output, P = Power
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TLV7011, TLV7021, TLV7012, TLV7022
SLVSDM5F –SEPTEMBER 2017–REVISED MARCH 2020
www.ti.com
TLV7012/22 DGK, DDF Packages
8-Pin VSSOP, SOT-23
Top View
1
2
3
4
8
7
OUTA
VCC
OUTB
INB-
INB+
INA-
INA+
VEE
6
5
TLV7012/22 DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
1
8
7
OUTA
INA-
INA+
VEE
VCC
2
3
4
OUTB
INB-
INB+
Thermal
Pad
6
5
(1) Connect thermal pad to V–.
Pin Functions: TLV7012/22
PIN
I/O
DESCRIPTION
NAME
NO.
2
INA–
INA+
INB–
INB+
OUTA
OUTB
VEE
I
I
Inverting input, channel A
3
Noninverting input, channel A
Inverting input, channel B
6
I
5
I
Noninverting input, channel B
Output, channel A
1
O
O
—
—
7
Output, channel B
4
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
VCC
8
4
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SLVSDM5F –SEPTEMBER 2017–REVISED MARCH 2020
6 Specifications
6.1 Absolute Maximum Ratings (Single)
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Supply voltage (VS = VCC – VEE
)
6
Input pins (IN+, IN–)(2)
VEE – 0.3
6
±10
V
Current into Input pins (IN+, IN–)(2)
Output (OUT)
mA
TLV7011/7012(3)
TLV7021/7022
VEE – 0.3
VEE – 0.3
VCC + 0.3
6
V
Output short-circuit duration(4)
Junction temperature, TJ
Storage temperature, Tstg
10
s
150
°C
°C
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to VEE. Input signals that can swing 0.3V below VEE must be current-limited to 10mA or less.
(3) Output maximum is (VCC + 0.3V) or 6V, whichever is less.
(4) Short-circuit to ground, one comparator per package.
6.2 Absolute Maximum Ratings (Dual)
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
UNIT
V
Supply voltage VS = VCC - VEE
Input pins (IN+, IN-)(2)
7
VEE – 0.3
7
±10
V
Current into Input pins (IN+, IN-)
Output (OUT) (TLV7012)(3)
Output (OUT) (TLV7022)
Output short-circuit duration(4)
Junction temperature, TJ
mA
V
VEE – 0.3
VEE – 0.3
VCC + 0.3
7
V
10
s
150
°C
°C
Storage temperature, Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to VEE. Input signals that can swing 0.3V below VEE must be current-limited to 10mA or less
(3) Output maximum is (VCC + 0.3 V) or 7 V, whichever is less.
(4) Short-circuit to ground, one comparator per package.
6.3 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions (Single)
over operating free-air temperature range (unless otherwise noted)
MIN
1.6
NOM
MAX
5.5
UNIT
V
Supply voltage (VS = VCC – VEE
)
Input Voltage Range
VEE – 0.1
–40
VCC + 0.2
125
V
Ambient temperature, TA
°C
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SLVSDM5F –SEPTEMBER 2017–REVISED MARCH 2020
www.ti.com
6.5 Recommended Operating Conditions (Dual)
over operating free-air temperature range (unless otherwise noted)
MIN
1.6
MAX
6.5
UNIT
V
Supply voltage VS = VCC – VEE
Input voltage range
VCC – 0.1
–40
VEE + 0.2
125
V
Ambient temperature, TA
°C
6.6 Thermal Information (Single)
TLV7011/TLV7021
THERMAL METRIC(1)
DPW (X2SON)
5 PINS
497.5
DBV (SOT23)
5 PINS
306.3
DCK (SC70)
5 PINS
278.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
275.5
228.4
188.6
372.2
166.5
113.2
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
55.5
138.5
82.3
ΨJB
370.3
165.3
112.4
RθJC(bot)
165.1
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.7 Thermal Information (Dual)
TLV7012/TLV7022
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
211.7
DDF (SOT-23)
8 PINS
212.5
DSG (WSON)
8 PINS
106.1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
96.1
127.3
127.3
133.5
129.2
72.5
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
28.3
25.8
16.8
ΨJB
131.7
129.0
72.2
RθJC(bot)
N/A
N/A
47.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
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SLVSDM5F –SEPTEMBER 2017–REVISED MARCH 2020
6.8 Electrical Characteristics (Single)
VS = 1.8 V to 5 V, VCM = VS / 2; minimum and maximum values are at TA = –40°C to +125°C (unless otherwise noted).
Typical values are at TA = 25°C.
PARAMETER
Input offset voltage
Hysteresis
TEST CONDITIONS
VS = 1.8 V and 5 V, VCM = VS / 2
VS = 1.8 V and 5 V, VCM = VS / 2
VS = 2.5 V to 5 V
MIN
TYP
±0.5
4.2
MAX
UNIT
VIO
±8
mV
VHYS
1.2
VEE
14
mV
VCC + 0.1
VCC + 0.1
VCM
Common-mode voltage range
V
VS = 1.8 V to 2.5 V
VEE + 0.1
IB
Input bias current
Input offset current
5
1
pA
pA
IOS
Output voltage high (for TLV7011
only)
VOH
VOL
ILKG
VS = 5 V, IO = 3 mA
VS = 5 V, IO = 3 mA
4.7
4.8
120
100
V
Output voltage low
220
mV
pA
Open-drain output leakage current VS = 5 V, VID = +0.1 V (output high), VPULLUP
(TLV7021 only)
=
VCC
CMRR
PSRR
Common-mode rejection ratio
Power supply rejection ratio
VEE < VCM < VCC, VS = 5 V
VS = 1.8 V to 5 V, VCM = VS / 2
VS = 5 V, sourcing
VS = 5 V, sinking
78
78
65
44
5
dB
dB
ISC
ICC
Short-circuit current
Supply current
mA
µA
VS = 1.8 V, no load, VID = –0.1 V (Output Low)
10
6.9 Switching Characteristics (Single)
Typical values are at TA = 25°C, VCC = 5 V, VCM = 2.5 V; CL = 15 pF, input overdrive = 100 mV (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Propagation delay time, high-to-low Midpoint of input to midpoint of output, VOD
(RP = 2.5 kΩ TLV7021 only) 100 mV
=
=
tPHL
tPLH
260
ns
Propagation delay time, low-to-high Midpoint of input to midpoint of output, VOD
310
ns
(RP = 2.5 kΩ TLV7021 only)
Rise time (for TLV7011 only)
Fall time
100 mV
tR
20% to 80%
80% to 20%
5
5
ns
ns
µs
tF
(1)
tON
Power-up time
20
(1) During power on, VS must exceed 1.6 V for tON before the output tracks the input.
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6.10 Electrical Characteristics (Dual)
VS = 1.8 V to 5 V, VCM = VS / 2; minimum and maximum values are at TA = –40°C to +125°C (unless otherwise noted).
Typical values are at TA = 25°C.
PARAMETER
Input Offset Voltage
Hysteresis
TEST CONDITIONS
VS = 1.8 V and 5 V, VCM = VS / 2
VS = 1.8 V and 5 V, VCM = VS / 2
MIN
TYP
±0.1
7.2
MAX
UNIT
mV
mV
V
VIO
VHYS
VCM
IB
±8
2
15
Common-mode voltage range
Input bias current
Input offset current
VEE
VCC + 0.1
2
1
pA
IOS
pA
Output voltage high (for TLV7012
only)
VOH
VOL
ILKG
VS = 5 V, VEE = 0 V, IO = 3 mA
VS = 5 V, VEE = 0 V, IO = 3 mA
4.65
4.8
250
100
V
Output voltage low
350
mV
pA
Open-drain output leakage
current (TLV7022 only)
VS = 5 V, VID = +0.1 V (output high),
VPULLUP = VCC
CMRR
PSRR
Common-mode rejection ratio
Power supply rejection ratio
VEE < VCM < VCC, VS = 5 V
73
77
dB
dB
VS = 1.8 V to 5 V, VCM = VS / 2
VS = 5 V, sourcing (for TLV7012 only)
VS = 5 V, sinking
29
ISC
ICC
Short-circuit current
mA
µA
33
Supply current / Channel
VS = 1.8 V, no load, VID = –0.1 V (Output Low)
4.7
9
6.11 Switching Characteristics (Dual)
Typical values are at TA = 25°C, VS = 5 V, VCM = VS / 2; CL = 15 pF, input overdrive = 100 mV (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Propagation delay time, high to-
Midpoint of input to midpoint of output,
VOD = 100 mV
tPHL
low (RP = 4.99 kΩ TLV7022
310
ns
(1)
only)
Propagation delay time, low-to high
Midpoint of input to midpoint of output,
VOD = 100 mV
tPLH
(RP = 4.99 kΩ TLV7022
260
ns
(1)
only)
tR
tF
Rise time (TLV7012 only)
Fall time
Measured from 20% to 80%
Measured from 20% to 80%
5
5
ns
ns
During power on, VCC must exceed 1.6V for
20 µs before the output is in a correct state.
tON
Power-up time
20
µs
(1) The lower limit for RP is 650 Ω
6.12 Timing Diagrams
tON
VEE
VEE + 1.6V
VCC
VOH/2
VEE
OUT
Figure 1. Start-Up Time Timing Diagram (IN+ > IN–)
8
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SLVSDM5F –SEPTEMBER 2017–REVISED MARCH 2020
Timing Diagrams (continued)
V+
Input
Input
+
Output
VREF + 100 mV
œ
Vœ
+
VREF
VREF Å 100 mV
Vœ
VREF
œ
tpLH
tpHL
V+
80%
80%
Output
50%
20%
50%
20%
Vœ
tR
tF
Figure 2. Propagation Delay Timing Diagram
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6.13 Typical Characteristics
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
0.7
4
3
VCM = VCC / 2
VCM = VCC
VCM = 0
0.6
0.5
2
1
0.4
0.3
0.2
0.1
0
0
-1
-2
-3
-4
-40
-20
0
20
40
60
80
100
120
0.1
0.3
0.5
0.7
0.9
VCM (V)
1.1
1.3
1.5
1.7
Temperature (èC)
TLV7
TLV7
VCC = 1.8 - 5.0V
Figure 3. Input Offset vs. Temperature
VCC = 1.8 V, 50 devices
Figure 4. Input Offset Voltage vs. VCM
4
4
3
3
2
2
1
1
0
0
-1
-2
-3
-4
-1
-2
-3
-4
0
1
2
3
0
0.5
1
1.5
2
2.5
VCM (V)
3
3.5
4
4.5
5
VCM (V)
TLV7
TLV7
VCC = 3.3 V, 50 devices
VCC = 5 V, 50 devices
Figure 5. Input Offset Voltage vs. VCM
Figure 6. Input Offset Voltage vs. VCM
20
15
10
5
16
14
12
10
8
6
4
VCM = VCC / 2
VCM = VCC
VCM = 0
2
0
0
-40
-20
0
20
40
60
80
100
120
-3
-2
-2
-1
0
1
Input Offset (mV)
2
3
4
Temperature (èC)
TLV7
TLV7
VCC = 1.8V - 5.0V
Figure 8. TLV70x1 Hysteresis vs. Temperature
Distribution Taken From 10,777 Comparators
Figure 7. Input Offset Voltage Histogram
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Typical Characteristics (continued)
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
20
40
35
30
25
20
15
10
5
-40èC
18
25èC
85èC
125èC
16
14
12
10
8
6
4
2
0
0
0
1
2
3
4
5
3
4
5
Hysteresis (mV)
6
7
VCM (V)
TLV7
TLV7
VCC = 5.0V
Distribution Taken From 10,777 Comparators
Figure 9. TLV70x1 Hysteresis vs. VCM
Figure 10. TLV70x1 Hysteresis Histogram
11.2
10.4
9.6
8.8
8
20
18
16
14
12
10
8
-40°C
25°C
85°C
125°C
7.2
6.4
5.6
6
4
VCM = 0V
VCM = VCC/2
VCM = VCC
2
4.8
-50
0
-25
0
25
50
75
Temperature (°C)
100
125
150
0
1
2
3
VCM (V)
4
5
6
VCC = 1.8V - 5.0V
Figure 11. TLV70x2 Hysteresis vs. Temperature
VCC = 5.0V
Figure 12. TLV70x2 Hysteresis vs. VCM
10000
1000
100
10
1.8
1.795
1.79
1.785
1.78
1.775
1.77
1
1.765
1.76
-40èC
25èC
85èC
125èC
0.1
1.755
1.75
0.1
0.01
0.2
IOUT (mA)
0.3
0.4
0.5
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
TLV7
TLV7
VCC = 1.8 V
VCC = 3.3V
Figure 14. TLV701x Output Voltage High vs. Output Source
Current
Figure 13. Input Bias Current vs. Temperature
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Typical Characteristics (continued)
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
5
0.05
0.04
0.03
0.02
0.01
0
-40èC
25èC
125èC
4.95
4.9
4.85
-4è0C
4.8
25èC
85èC
125èC
4.75
0.1
1
5
0.1
0.2
IOUT (mA)
0.3
0.4
0.5
IOUT (mA)
TLV7
TLV7
VCC = 5 V
VCC = 1.8 V
Figure 16. Output Voltage Low vs. Output Sink Current
Figure 15. TLV701x Output Voltage High vs. Output Source
Current
60
0.25
-40èC
25èC
125èC
50
40
30
20
10
0
0.2
0.15
0.1
0.05
0
VCC = 3.5 V
VCC = 5.5 V
0.1
0.2 0.3 0.40.5 0.7
1
2
3
4
5
-60 -40 -20
0
20
40
60
80 100 120 140
IOUT (mA)
Temperature (èC)
TLV7
TLV7
VCC = 5 V
Figure 17. Output Voltage Low vs. Output Sink Current
VCM = VCC/2
Figure 18. Output Short-Circuit (Sink) Current vs.
Temperature
90
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
-40èC
25èC
85èC
125èC
VCC = 3.5 V
VCC = 5.5 V
1.8
2.3
2.8
3.3
3.8
VCC (V)
4.3
4.8
5.3
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (èC)
TLV7
TLV7
VCM = VCC/2
Figure 20. Output Short Circuit (Sink) vs. VCC
VCM = VCC/2
Figure 19. TLV701x Output Short-Circuit (Source) Current
vs. Temperature
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Typical Characteristics (continued)
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
90
7
6.5
6
80
70
60
50
40
30
5.5
5
4.5
4
3.5
3
-40èC
25èC
85èC
125èC
20
10
0
VCC = 3.3 V
VCC = 5 V
2.5
2
1.8
2.3
2.8
3.3
3.8
VCC (V)
4.3
4.8
5.3
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (èC)
TLV7
TLV7
VCM = VCC/2
VCM = VCC/2
Figure 21. TLV701x Output Short Circuit (Source) vs. VCC
Figure 22. ICC vs. Temperature
7
6.5
6
7
6.5
6
5.5
5
5.5
5
4.5
4
4.5
4
3.5
3.5
3
-40èC
-40èC
25èC
85èC
125èC
3
25èC
85èC
125èC
2.5
2.5
2
2
0
1
1.5
2
2.5
3
VCC (V)
3.5
4
4.5
5
1
2
3
VCM (V)
4
5
5.5
TLV7
TLV7
VCM = VCC/2
VCC = 5 V
Figure 23. ICC vs. VCC
Figure 24. ICC vs. VCM
100000
10000
1000
100
10000
1000
100
10
10
1
1
10
100
1000
Load Capacitance (pF)
10000
100000
10
100
1000
Load Capacitance (pF)
10000
100000
TLV7
TLV7
VOD = 100mV
VOD = 100mV
Figure 25. TLV701x Output Rise Time vs. Load Capacitance
Figure 26. Output Fall Time vs. Load Capacitance
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Typical Characteristics (continued)
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
0.5
0.5
0.4
0.3
0.2
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
0.4
0.3
0.2
0
20
40
60
80 100 120 140 160 180 200
Input Overdrive (mV)
0
20
40
60
80 100 120 140 160 180 200
Input Overdrive (mV)
TLV7
TLV7
TA = 25°C,
TA = 25°C
Figure 28. Propagation Delay (H-L) vs. Input Overdrive
Figure 27. TLV701x Propagation Delay (L-H) vs. Input
Overdrive
0.5
0.5
T = -40èC
T = 25èC
T = 85èC
T = 125èC
T = -40èC
T = 25èC
T = 85èC
T = 125èC
0.4
0.3
0.2
0.4
0.3
0.2
0
20
40
60
80 100 120 140 160 180 200
Input Overdrive (mV)
0
20
40
60
80 100 120 140 160 180 200
Input Overdrive (mV)
TLV7
TLV7
VCC = 5 V
VCC = 5 V
Figure 29. TLV701x Propagation Delay (L-H) vs. Input
Overdrive
Figure 30. Propagation Delay (H-L) vs. Input Overdrive
0.5
0.4
0.3
0.2
T = -40èC
T = 25èC
T = 85èC
T = 125èC
0
20
40
60
80 100 120 140 160 180 200
Input Overdrive (mV)
TLV7
Rpull-up = 2.5k
Figure 31. TLV702x Propagation Delay (L-H) vs. Input Overdrive
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7 Detailed Description
7.1 Overview
The TLV701x and TLV702x devices are single-channel, micro-power comparators with push-pull and open-drain
outputs. Operating down to 1.6 V and consuming only 5 µA, the TLV701x and TLV702x are ideally suited for
portable and industrial applications. The comparators are available in leadless and leaded packages to offer
significant board space saving in space-challenged designs.
7.2 Functional Block Diagram
VCC
IN+
IN-
+
OUT
œ
Bias
Power-on-reset
GND
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7.3 Feature Description
The TLV701x (push-pull) and TLV702x (open-drain) devices are micro-power comparators that are capable of
operating at low voltages. The TLV701x and TLV702x feature a rail-to-rail input stage capable of operating up to
100 mV beyond the VCC power supply rail. The comparators also feature a push-pull and open-drain output
stage with internal hysteresis.
7.4 Device Functional Modes
The TLV701x and TLV702x have a Power-on-Reset (POR) circuit. While the power supply (VS) is ramping up or
ramping down, the POR circuitry will be activated.
For the TLV701x, the POR circuit will hold the output low (at VEE) while activated.
For the TLV702x, the POR circuit will keep the output high impedance (logical high) while activated.
When the supply voltage is greater than, or equal to, the minimum supply voltage, the comparator output reflects
the state of the differential input (VID).
7.4.1 Inputs
The TLV701x and TLV702x input common-mode extends from VEE to 100 mV above VCC. The differential input
voltage (VID) can be any voltage within these limits. No phase-inversion of the comparator output will occur when
the input pins exceed VCC and VEE
.
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Device Functional Modes (continued)
While TI recommends operating the TLV701x and TLV702x within the specified common-mode range, the inputs
are fault tolerant to voltages up to 5.5 V independent of the applied VCC value. Fault tolerant is defined as
maintaining the same high input impedance when VCC is unpowered or within the recommended operating range.
Because the inputs of the TLV701x and TLV702x are fault tolerant, the inputs to the comparator can be any
value between 0 V and 5.5 V while VCC is ramping up. This feature allows any supply and input driven sequence
as long as the input value and supply are within the specified ranges. In this case, no current limiting resistor is
required. This is possible since the VCC is isolated from the inputs such that it maintains its value even when a
higher voltage is applied to the input.
The input bias current is typically 1 pA for input voltages between VCC and VEE. The comparator inputs are
protected from undervoltage by internal diodes connected to VEE. As the input voltage goes under VEE, the
protection diodes become forward biased and begin to conduct causing the input bias current to increase
exponentially. Input bias current typically doubles for 10°C temperature increases.
7.4.2 Internal Hysteresis
The device hysteresis transfer curve is shown in Figure 32. This curve is a function of three components: VTH
,
VOS, and VHYST
:
•
•
VTH is the actual set voltage or threshold trip voltage.
VOS is the internal offset voltage between VIN+ and VIN–. This voltage is added to VTH to form the actual trip
point at which the comparator must respond to change output states.
•
VHYST is the internal hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise
(4.2 mV for the TLV7011).
VTH + VOS - (VHYST / 2)
VTH + VOS
VTH + VOS + (VHYST / 2)
Figure 32. Hysteresis Transfer Curve
7.4.3 Output
The TLV701x feature a push-pull output stage eliminating the need for an external pull-up resistor. On the other
hand, the TLV702x feature an open-drain output stage enabling the output logic levels to be pulled up to an
external source independent of the supply voltage.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV701x and TLV702x are micro-power comparators with reasonable response time. The comparators have
a rail-to-rail input stage that can monitor signals beyond the positive supply rail with integrated hysteresis. When
higher levels of hysteresis are required, positive feedback can be externally added. The push-pull output stage of
the TLV701x is optimal for reduced power budget applications and features no shoot-through current. When level
shifting or wire-ORing of the comparator outputs is needed, the TLV702x with its open-drain output stage is well
suited to meet the system needs. In either case, the wide operating voltage range, low quiescent current, and
micro-package of the TLV701x and TLV702x make these comparators excellent candidates for battery-operated
and portable, handheld designs.
8.1.1 Inverting Comparator With Hysteresis for TLV701x
The inverting comparator with hysteresis requires a three-resistor network that is referenced to the comparator
supply voltage (VCC), as shown in Figure 33. When VIN at the inverting input is less than VA, the output voltage is
high (for simplicity, assume VO switches as high as VCC). The three network resistors can be represented as R1
|| R3 in series with R2. Equation 1 defines the high-to-low trip voltage (VA1).
R2
VA1 = VCC
´
(R1 || R3) + R2
(1)
When VIN is greater than VA, the output voltage is low, very close to ground. In this case, the three network
resistors can be presented as R2 || R3 in series with R1. Use Equation 2 to define the low to high trip voltage
(VA2).
R2 || R3
VA2 = VCC
´
R1 + (R2 || R3)
(2)
(3)
Equation 3 defines the total hysteresis provided by the network.
DVA = VA1 - VA2
+VCC
+5 V
R1
1 MW
VIN
5 V
RLOAD
VA
VO
100 kW
VA2
1.67 V
VA1
3.33 V
0 V
R3
1 MW
VIN
R2
1 MW
VO High
+VCC
VO Low
+VCC
R1
VA1
R2
R3
R1
VA2
R2
R3
Copyright © 2016, Texas Instruments Incorporated
Figure 33. TLV701x in an Inverting Configuration With Hysteresis
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Application Information (continued)
8.1.2 Noninverting Comparator With Hysteresis for TLV701x
A noninverting comparator with hysteresis requires a two-resistor network, as shown in Figure 34, and a voltage
reference (VREF) at the inverting input. When VIN is low, the output is also low. For the output to switch from low
to high, VIN must rise to VIN1. Use Equation 4 to calculate VIN1
VREF
.
VIN1 = R1 ´
+ VREF
R2
(4)
When VIN is high, the output is also high. For the comparator to switch back to a low state, VIN must drop to VIN2
such that VA is equal to VREF. Use Equation 5 to calculate VIN2
VREF (R1 + R2) - VCC ´ R1
.
VIN2
=
R2
(5)
(6)
The hysteresis of this circuit is the difference between VIN1 and VIN2, as shown in Equation 6.
R1
DVIN = VCC
´
R2
+VCC
+5 V
VREF
VO
+2.5 V
VA
VIN
RLOAD
R1
330 kW
R2
1 MW
VO High
+VCC
VO Low
VIN1
5 V
0 V
R2
R1
VA = VREF
R2
VO
VA = VREF
R1
VIN2
VIN1
1.675 V 3.325 V
VIN
VIN2
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Figure 34. TLV701x in a Noninverting Configuration With Hysteresis
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8.2 Typical Applications
8.2.1 Window Comparator
Window comparators are commonly used to detect undervoltage and overvoltage conditions. Figure 35 shows a
simple window comparator circuit.
3.3 V
RPU
R1
UV_OV
+
Micro-
Controller
œ
Sensor
TLV7021
R2
+
œ
TLV7021
R3
Copyright © 2017, Texas Instruments Incorporated
Figure 35. Window Comparator
8.2.1.1 Design Requirements
For this design, follow these design requirements:
•
•
•
•
Alert (logic low output) when an input signal is less than 1.1 V
Alert (logic low output) when an input signal is greater than 2.2 V
Alert signal is active low
Operate from a 3.3-V power supply
8.2.1.2 Detailed Design Procedure
Configure the circuit as shown in Figure 35. Connect VCC to a 3.3-V power supply and VEE to ground. Make R1,
R2 and R3 each 10-MΩ resistors. These three resistors are used to create the positive and negative thresholds
for the window comparator (VTH+ and VTH–). With each resistor being equal, VTH+ is 2.2 V and VTH- is 1.1 V. Large
resistor values such as 10-MΩ are used to minimize power consumption. The sensor output voltage is applied to
the inverting and noninverting inputs of the two TLV702x's. The TLV7021 is used for its open-drain output
configuration. Using the TLV702x allows the two comparator outputs to be Wire-Ored together. The respective
comparator outputs will be low when the sensor is less than 1.1 V or greater than 2.2 V. VOUT will be high when
the sensor is in the range of 1.1 V to 2.2 V.
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Typical Applications (continued)
8.2.1.3 Application Curve
VIN
VTH+ = 2.2 V
VTHœ = 1.1 V
Time (usec)
VOUT
Time (usec)
50
100
150
200
Figure 36. Window Comparator Results
8.2.2 IR Receiver Analog Front End
A single TLV7011 device can be used to build a complete IR receiver analog front end (AFE). The nanoamp
quiescent current and low input bias current make it possible to be powered with a coin cell battery, which could
last for years.
Vref
470 kꢀ
470 kꢀ
10M ꢀ
R4
3 V
IR LED
R2
R3
U1
+
Output to MCU
(Also to wake-up MCU)
œ
VOUT
C1
10M ꢀ
TLV7011
VIN
R1
0.01 ꢁF
GND
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Figure 37. IR Receiver Analog Front End Using TLV7011
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Typical Applications (continued)
8.2.2.1 Design Requirements
For this design, follow these design requirements:
•
Use a proper resistor (R1) value to generate an adequate signal amplitude applied to the inverting input of the
comparator.
•
•
The low input bias current IB (2 pA typical) ensures that a greater value of R1 to be used.
The RC constant value (R2 and C1) must support the targeted data rate (that is, 9,600 bauds) to maintain a
valid tripping threshold.
•
The hysteresis introduced with R3 and R4 helps to avoid spurious output toggles.
8.2.2.2 Detailed Design Procedure
The IR receiver AFE design is highly streamlined and optimized. R1 converts the IR light energy induced current
into voltage and applies to the inverting input of the comparator. Because a reverse biased IR LED is used as
the IR receiver, a higher I/V transimpedance gain is required to boost the amplitude of reduced current. A 10M
resistor is used as R1 to support a 1-V, 100-nA transimpedance gain. This is made possible with the picoamps
Input bias current IB (5pA typical). The RC network of R2 and C1 establishes a reference voltage Vref which tracks
the mean amplitude of the IR signal. The RC constant of R2 and C1 (about 4.7 ms) is chosen for Vref to track the
received IR current fluctuation but not the actual data bit stream. The noninverting input is connected to Vref and
the output over the R3 and R4 resistor network which provides additional hysteresis for improved guard against
spurious toggles.
To reduce the current drain from the coin cell battery, data transmission must be short and infrequent.
8.2.2.3 Application Curve
1.8 V
VIN
1.2 V
4.0 V
VOUT
0.0 V
1.61 V
VREF
1.58 V
0.0
200.0 u
400.0 u
Time
600.0 u
800.0 u
Figure 38. IR Receiver AFE Waveforms
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Typical Applications (continued)
8.2.3 Square-Wave Oscillator
Square-wave oscillator can be used as low cost timing reference or system supervisory clock source.
Figure 39. Square-Wave Oscillator
8.2.3.1 Design Requirements
The square-wave period is determined by the RC time constant of the capacitor and resistor. The maximum
frequency is limited by propagation delay of the device and the capacitance load at the output. The low input bias
current allows a lower capacitor value and larger resistor value combination for a given oscillator frequency,
which may help to reduce BOM cost and board space.
8.2.3.2 Detailed Design Procedure
The oscillation frequency is determined by the resistor and capacitor values. The following calculation provides
details of the steps.
Figure 40. Square-Wave Oscillator Timing Thresholds
First consider the output of Figure Figure 39 is high which indicates the inverted input VC is lower than the
noninverting input (VA). This causes the C1 to be charged through R4, and the voltage VC increases until it is
equal to the noninverting input. The value of VA at the point is calculated by Equation 7.
VCCìR2
R2 + R1IIR3
VA1
=
(7)
if R1 = R2= R3, then VA1 = 2 VCC/ 3
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Typical Applications (continued)
At this time the comparator output trips pulling down the output to the negative rail. The value of VAat this point is
calculated by Equation 8.
VCC(R2IIR3 )
VA2
=
R1+R2IIR3
(8)
if R1 = R2 = R3, then VA2 = VCC/3
The C1 now discharges though the R4, and the voltage VCC decreases until it reaches VA2. At this point, the
output switches back to the starting state. The oscillation period equals to the time duration from for C1 from
2VCC/3 to VCC / 3 then back to 2VCC/3, which is given by R4C1 × ln 2 fro each trip. Therefore, the total time
duration is calculated as 2 R4C1 × ln 2. The oscillation frequency can be obtained by Equation 9:
f = 1/ 2 R4ìC1ìIn2
(9)
8.2.3.3 Application Curve
Figure 41 shows the simulated results of tan oscillator using the following component values:
•
•
•
•
R1 = R2 = R3 = R4 = 100 kΩ
C1 = 100 pF, CL = 20 pF
V+ = 5 V, V– = GND
Cstray (not shown) from VA TO GND = 10 pF
Figure 41. Square-Wave Oscillator Output Waveform
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Product Folder Links: TLV7011 TLV7021 TLV7012 TLV7022
TLV7011, TLV7021, TLV7012, TLV7022
SLVSDM5F –SEPTEMBER 2017–REVISED MARCH 2020
www.ti.com
9 Power Supply Recommendations
The TLV701x and TLV702x have a recommended operating voltage range (VS) of 1.6 V to 5.5 / 6.5 V. VS is
defined as VCC – VEE. Therefore, the supply voltages used to create VS can be single-ended or bipolar. For
example, single-ended supply voltages of 5 V and 0 V and bipolar supply voltages of +2.5 V and –2.5 V create
comparable operating voltages for VS. However, when bipolar supply voltages are used, it is important to realize
that the logic low level of the comparator output is referenced to VEE
.
Output capacitive loading and output toggle rate will cause the average supply current to rise over the quiescent
current.
10 Layout
10.1 Layout Guidelines
To reduce PCB fabrication cost and improve reliability, TI recommends using a 4-mil via at the center pad
connected to the ground trace or plane on the bottom layer.
A power-supply bypass capacitor of 100 nF is recommended when supply output impedance is high, supply
traces are long, or when excessive noise is expected on the supply lines. Bypass capacitors are also
recommended when the comparator output drives a long trace or is required to drive a capacitive load. Due to
the fast rising and falling edge rates and high-output sink and source capability of the TLV7011 and TLV7021
output stages, higher than normal quiescent current can be drawn from the power supply. Under this
circumstance, the system would benefit from a bypass capacitor across the supply pins.
10.2 Layout Example
OUT
IN+
Top-Layer
Trace
Bottom-Layer
Trace
4 mil VIA
VCC
IN-
8 mil VIA
Package
Body
Outline
Top-View
0.1 uF
Figure 42. Layout Example
24
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Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TLV7011 TLV7021 TLV7012 TLV7022
TLV7011, TLV7021, TLV7012, TLV7022
www.ti.com
SLVSDM5F –SEPTEMBER 2017–REVISED MARCH 2020
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Module
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TLV70x1
device family. The TLV7011 Micro-Power Comparator Dip Adaptor Evaluation Module can be requested at the
Texas Instruments website through the product folder or purchased directly from the TI eStore.
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
TLV7011
TLV7021
TLV7012
TLV7022
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2017–2020, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Links: TLV7011 TLV7021 TLV7012 TLV7022
PACKAGE OPTION ADDENDUM
www.ti.com
10-Sep-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
3000
3000
250
(1)
(2)
(3)
(4/5)
(6)
TLV7011DBVR
TLV7011DCKR
TLV7011DCKT
TLV7011DPWR
TLV7012DDFR
TLV7012DGKR
TLV7021DBVR
TLV7021DCKR
TLV7021DCKT
TLV7021DPWR
TLV7022DDFR
TLV7022DGKR
ACTIVE
SOT-23
SC70
DBV
5
5
5
5
8
8
5
5
5
5
8
8
Green (RoHS
& no Sb/Br)
NIPDAUAG
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1IC2
19N
19N
7N
ACTIVE
ACTIVE
ACTIVE
DCK
DCK
DPW
DDF
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
SC70
Green (RoHS
& no Sb/Br)
X2SON
3000
3000
2500
3000
3000
250
Green (RoHS
& no Sb/Br)
NIPDAU
ACTIVE SOT-23-THIN
Green (RoHS
& no Sb/Br)
NIPDAU
7012
7012
1ID2
19O
19O
7P
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
SOT-23
SC70
DGK
DBV
Green (RoHS
& no Sb/Br)
NIPDAUAG
NIPDAUAG
NIPDAU
Green (RoHS
& no Sb/Br)
DCK
DCK
DPW
DDF
Green (RoHS
& no Sb/Br)
SC70
Green (RoHS
& no Sb/Br)
NIPDAU
X2SON
3000
3000
2500
Green (RoHS
& no Sb/Br)
NIPDAU
ACTIVE SOT-23-THIN
ACTIVE VSSOP
Green (RoHS
& no Sb/Br)
NIPDAU
7022
7022
DGK
Green (RoHS
& no Sb/Br)
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Sep-2020
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Sep-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV7011DBVR
TLV7011DCKR
TLV7011DCKT
TLV7011DPWR
TLV7012DDFR
SOT-23
SC70
DBV
DCK
DCK
DPW
DDF
5
5
5
5
8
3000
3000
250
180.0
178.0
178.0
178.0
180.0
8.4
9.0
9.0
8.4
8.4
3.23
2.4
3.17
2.5
1.37
1.2
1.2
0.5
1.4
4.0
4.0
4.0
2.0
4.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q2
Q3
SC70
2.4
2.5
X2SON
3000
3000
0.91
3.2
0.91
3.2
SOT-
23-THIN
TLV7012DGKR
TLV7021DBVR
TLV7021DCKR
TLV7021DCKT
TLV7021DPWR
TLV7022DDFR
VSSOP
SOT-23
SC70
DGK
DBV
DCK
DCK
DPW
DDF
8
5
5
5
5
8
2500
3000
3000
250
330.0
180.0
178.0
178.0
178.0
180.0
12.4
8.4
9.0
9.0
8.4
8.4
5.3
3.23
2.4
3.4
3.17
2.5
1.4
1.37
1.2
1.2
0.5
1.4
8.0
4.0
4.0
4.0
2.0
4.0
12.0
8.0
8.0
8.0
8.0
8.0
Q1
Q3
Q3
Q3
Q2
Q3
SC70
2.4
2.5
X2SON
3000
3000
0.91
3.2
0.91
3.2
SOT-
23-THIN
TLV7022DGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Sep-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV7011DBVR
TLV7011DCKR
TLV7011DCKT
TLV7011DPWR
TLV7012DDFR
TLV7012DGKR
TLV7021DBVR
TLV7021DCKR
TLV7021DCKT
TLV7021DPWR
TLV7022DDFR
TLV7022DGKR
SOT-23
SC70
DBV
DCK
DCK
DPW
DDF
DGK
DBV
DCK
DCK
DPW
DDF
DGK
5
5
5
5
8
8
5
5
5
5
8
8
3000
3000
250
183.0
190.0
190.0
205.0
210.0
364.0
183.0
190.0
190.0
205.0
210.0
364.0
183.0
190.0
190.0
200.0
185.0
364.0
183.0
190.0
190.0
200.0
185.0
364.0
20.0
30.0
30.0
33.0
35.0
27.0
20.0
30.0
30.0
33.0
35.0
27.0
SC70
X2SON
SOT-23-THIN
VSSOP
SOT-23
SC70
3000
3000
2500
3000
3000
250
SC70
X2SON
SOT-23-THIN
VSSOP
3000
3000
2500
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DPW0005A
X2SON - 0.4 mm max height
S
C
A
L
E
1
2
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
0.85
0.75
A
B
PIN 1 INDEX AREA
0.85
0.75
0.4 MAX
C
SEATING PLANE
NOTE 3
(0.1)
0.05
0.00
(0.25)
4X (0.05)
0.25 0.1
2
1
4
5
NOTE 3
2X
0.48
3
2X (0.26)
0.27
0.17
4X
0.27
0.17
0.1 C A B
0.05 C
(0.06)
3X
0.32
0.23
4223102/B 09/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The size and shape of this feature may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.78)
(
0.1)
SYMM
4X (0.42)
VIA
0.05 MIN
ALL AROUND
TYP
1
5
4X (0.22)
SYMM
4X (0.26)
(0.48)
3
2
4
(R0.05) TYP
SOLDER MASK
OPENING, TYP
4X (0.06)
(
0.25)
(0.21) TYP
EXPOSED METAL
CLEARANCE
METAL UNDER
SOLDER MASK
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:60X
4223102/B 09/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.42)
4X (0.06)
5
1
4X (0.22)
SYMM
(
0.24)
4X (0.26)
(0.21)
(0.48)
TYP
SOLDER MASK
EDGE
3
2
4
(R0.05) TYP
SYMM
(0.78)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
92% PRINTED SOLDER COVERAGE BY AREA
SCALE:100X
4223102/B 09/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.4
0.2
8X
0.1
C A
B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/B 11/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/B 11/2015
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/B 11/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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