TLV7031-Q1_V02 [TI]
TLV703x-Q1 and TLV704x-Q1 Rail-to-Rail, Low-Power Comparators;
| 型号： | TLV7031-Q1_V02 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TLV703x-Q1 and TLV704x-Q1 Rail-to-Rail, Low-Power Comparators |
| 文件： | 总42页 (文件大小：2261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV7031-Q1, TLV7041-Q1, TLV7032-Q1, TLV7042-Q1, TLV7034-Q1, TLV7044-Q1
SNOSDA5C – MAY 2020 – REVISED OCTOBER 2021
TLV703x-Q1 and TLV704x-Q1 Rail-to-Rail, Low-Power Comparators
1 Features
3 Description
•
•
Qualified for automotive applications
AEC-Q100 qualified with the following results:
– Device temperature grade 1: –40°C to 125°C
ambient operating temperature range
– Device HBM ESD classification level 2
– Device CDM ESD classification level C5
Wide supply voltage range of 1.6 V to 6.5 V
Quiescent supply current of 315 nA
Low propagation delay of 3 µs
The TLV703x-Q1/TLV704x-Q1 are low-voltage,
nanopower comparators with rail-to-rail inputs. These
comparators are applicable for space-critical and
power conscious designs like infotainment, telematics,
and head unit applications.
The TLV703x-Q1 and TLV704x-Q1 offer an excellent
combination of power and speed. The benefit of
fast response time at nanopower enables power-
conscious systems to monitor and respond quickly to
fault conditions. With an operating voltage range of
1.6 V to 6.5 V, these comparators are compatible with
1.8 V, 3 V, and 5 V systems.
•
•
•
•
•
•
Internal hysteresis of 6.5 mV
Rail-to-rail common-mode input voltage
Internal Power-On-Reset provides a known startup
condition
The TLV703x-Q1 and TLV704x-Q1 also ensure no
output phase inversion with overdriven inputs and
internal hysteresis, so engineers can use this family of
comparators for precision voltage monitoring in harsh,
noisy environments where slow-moving input signals
must be converted into clean digital outputs.
•
•
•
•
•
No phase reversal for overdriven inputs
Push-pull output (TLV703x-Q1)
Open-drain output (TLV704x-Q1)
–40°C to 125°C Operating temperature
Functional Safety Capable
– Documentation available to aid functional safety
system design (TLV70x1-Q1)
The TLV703x-Q1 have a push-pull output stage
capable of sinking and sourcing milliamps of current.
The TLV704x-Q1 have an open-drain output stage
– Documentation available to aid functional safety
system design (TLV70x2-Q1)
that can be pulled beyond VCC
.
2 Applications
Device Information
•
•
•
•
•
Telematics eCall
Automotive head unit
Instrument cluster
Audio amplifier
On-board (OBC) & wireless chargers
PART NUMBERS PACKAGE (PINS) (1) BODY SIZE (NOM)
SC70 (5)
2.00 mm × 1.25 mm
2.90 mm × 1.60 mm
3.00 mm x 3.00 mm
TLV7031-Q1,
TLV7041-Q1
SOT-23 (5)
VSSOP (8)
TLV7032-Q1,
TLV7042-Q1
SOT-23 (8)
(Preview)
2.90 mm x 1.60 mm
4.40 mm x 5.00 mm
TLV7034-Q1,
TLV7044-Q1
TSSOP (14)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
900
7
Temp = -40°C
Temp = 25°C
Temp = 125°C
Temp -40°C
Temp 25°C
Temp 85°C
800
6
5
4
3
2
1
Temp 125°C
700
600
500
400
300
200
1
1.5
2
2.5
3
3.5
VCC (V)
4
4.5
5
5.5
6
Iq_v
0
100
200
VOD (mV)
300
400
500
tlv7
ICC vs. VCC
Propagation Delay vs. Input Overdrive
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV7031-Q1, TLV7041-Q1, TLV7032-Q1, TLV7042-Q1, TLV7034-Q1, TLV7044-Q1
SNOSDA5C – MAY 2020 – REVISED OCTOBER 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions: TLV7032/42...............................................4
5.1 Pin Functions: TLV7034/44.........................................5
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings ....................................... 6
6.2 ESD Ratings .............................................................. 6
6.3 Recommended Operating Conditions ........................6
6.4 Thermal Information (Single) ..................................... 6
6.5 Thermal Information (Dual) ........................................7
6.6 Thermal Information (Quad) .......................................7
6.7 Electrical Characteristics ............................................8
6.8 Switching Characteristics ...........................................8
6.9 Electrical Characteristics (Dual) .................................9
6.10 Switching Characteristics (Dual) ..............................9
6.11 Electrical Characteristics (Quad) ............................10
6.12 Switching Characteristics (Quad) ...........................10
6.13 Timing Diagrams..................................................... 11
6.14 Typical Characteristics............................................12
7 Detailed Description......................................................16
7.1 Overview...................................................................16
7.2 Functional Block Diagram.........................................16
7.3 Feature Description...................................................16
7.4 Device Functional Modes..........................................16
8 Application and Implementation..................................18
8.1 Application Information............................................. 18
8.2 Typical Applications.................................................. 21
9 Power Supply Recommendations................................26
10 Layout...........................................................................27
10.1 Layout Guidelines................................................... 27
10.2 Layout Example...................................................... 27
11 Device and Documentation Support..........................28
11.1 Device Support........................................................28
11.2 Receiving Notification of Documentation Updates..28
11.3 Support Resources................................................. 28
11.4 Trademarks............................................................. 28
11.5 Electrostatic Discharge Caution..............................28
11.6 Glossary..................................................................28
12 Mechanical, Packaging, and Orderable
Information.................................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (February 2021) to Revision C (October 2021)
Page
•
Added link for new FIT Rate Report to the Features section..............................................................................1
Changes from Revision A (October 2020) to Revision B (February 2021)
Page
•
Added Dual and Quad package options throughout ..........................................................................................1
Changes from Revision * (May 2020) to Revision A (October 2020)
Page
•
•
Updated the numbering format for tables, figures, and cross-references throughout the document..................1
APL to RTM release............................................................................................................................................1
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SNOSDA5C – MAY 2020 – REVISED OCTOBER 2021
5 Pin Configuration and Functions
OUT
VEE
IN+
1
2
3
5
4
VCC
IN-
Figure 5-1. DBV, DCK Packages
5-Pin SOT-23, SC70
Top View
Table 5-1. Pin Functions
PIN
I/O (1)
DESCRIPTION
SOT-23, SC70
NAME
OUT
VCC
1
5
2
4
3
O
P
P
I
Output
Positive (highest) power supply
Negative (lowest) power supply
Inverting input
VEE
IN–
IN+
I
Noninverting input
(1) I = Input, O = Output, P = Power
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Pin Functions: TLV7032/42
1
2
3
4
8
7
OUTA
INA-
INA+
VEE
VCC
OUTB
INB-
INB+
6
5
Figure 5-2. TLV7032/42 DGK, DDF Packages
8-Pin VSSOP, SOT-23
Top View
Table 5-2. Pin Functions: TLV7032/42
PIN
I/O
DESCRIPTION
NAME
INA–
INA+
INB–
INB+
OUTA
OUTB
VEE
NO.
2
I
I
Inverting input, channel A
Noninverting input, channel A
Inverting input, channel B
Noninverting input, channel B
Output, channel A
3
6
I
5
I
1
O
O
—
—
7
Output, channel B
4
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
VCC
8
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5.1 Pin Functions: TLV7034/44
OUT A
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT D
œIN D
+IN D
VEE
œIN A
+IN A
VCC
+IN B
œIN B
OUT B
+IN C
œIN C
OUT C
8
Not to scale
Figure 5-3. TLV7034/44 PW Packages
14-Pin TSSOP
Top View
Table 5-3. Pin Functions: TLV7034/44
PIN
I/O
DESCRIPTION
NAME
–IN1 A
TSSOP
2
3
I
I
Inverting input, channel A
Noninverting input, channel A
Inverting input, channel B
Noninverting input, channel B
Inverting input, channel C
Noninverting input, channel C
Inverting input, channel D
Noninverting input, channel D
No internal connection
+IN A
–IN B
+IN B
–IN C
+IN C
–IN D
+IN D
NC
6
I
5
I
9
I
10
13
12
—
1
I
I
I
—
O
O
O
O
—
—
OUT A
OUT B
OUT C
OUT D
VEE
Output, channel A
7
Output, channel B
8
Output, channel C
14
11
4
Output, channel D
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
VCC
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
UNIT
V
Supply voltage VS = VCC – VEE
Input pins (IN+, IN–) (2)
7
VEE – 0.3
VEE – 0.3
VEE – 0.3
7
V
Output (OUT) (push-pull)(3)
Output (OUT) (open-drain)
Output short-circuit duration(4)
Junction temperature, TJ
Storage temperature, Tstg
VCC + 0.3
V
7
10
V
s
150
150
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Input terminals are diode-clamped to VEE. Input signals that can swing 0.3V below VEE must be current-limited to 10mA or less
(3) Output maximum is (VCC + 0.3 V) or 7 V, whichever is less.
(4) Short-circuit to ground, one comparator per package.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Electrostatic
discharge
V(ESD)
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.6
MAX
6.5
UNIT
V
Supply voltage VS = VCC – VEE
Input voltage range
VEE – 0.1
–40
VCC + 0.1
125
V
Ambient temperature, TA
°C
6.4 Thermal Information (Single)
TLV7031/TLV7041
THERMAL METRIC (1)
DBV (SOT-23)
DCK (SC70)
UNIT
5 PINS
297.2
224.7
200.1
141.2
198.9
N/A
5 PINS
278.8
186.6
113.2
82.3
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJB
112.4
N/A
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Thermal Information (Dual)
TLV7032/TLV7042
THERMAL METRIC (1)
DGK (VSSOP)
8 PINS
211.7
DDF (SOT-23)
8 PINS
212.5
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
96.1
127.3
133.5
129.2
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
28.3
25.8
ΨJB
131.7
129.0
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information (Quad)
TLV7034/44
THERMAL METRIC (1)
RTE (QFN)
16 PINS
65.4
PW (TSSOP)
14 PINS
131.0
60.5
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
70.2
40.5
74.1
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
5.6
12.6
ΨJB
40.5
73.5
RθJC(bot)
24.1
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.7 Electrical Characteristics
VS = 1.8 V to 5 V, VCM = VS / 2; minimum and maximum values are at TA = –40°C to +125°C (unless otherwise noted).
Typical values are at TA = 25°C.
PARAMETER
Input Offset Voltage
Hysteresis
TEST CONDITIONS
VS = 1.8 V and 5 V, VCM = VS / 2
MIN
TYP
±0.1
6.5
MAX
±8
UNIT
mV
mV
V
VIO
VHYS
VCM
IB
VS = 1.8 V and 5 V, VCM = VS / 2, TA = 25℃
2
17
Common-mode voltage range
Input bias current
Input offset current
VEE
VCC + 0.1
2
1
pA
IOS
pA
Output voltage high (push-pull
only)
VOH
VOL
ILKG
VS = 5 V, VEE = 0 V, IO = 3 mA
VS = 5 V, VEE = 0 V, IO = 3 mA
4.65
4.8
250
100
V
Output voltage low
350
mV
pA
Output leakage
current (open-drain only)
VS = 5 V, VID = +0.1 V (Output High),
VPULLUP = VCC
CMRR
PSRR
Common-mode rejection ratio
Power supply rejection ratio
VEE < VCM < VCC, VS = 5 V
73
77
dB
dB
VS = 1.8 V to 5 V, VCM = VS / 2
VS = 5 V, sourcing (push-pull only)
VS = 5 V, sinking
35
ISC
ICC
Short-circuit current
mA
nA
40
Supply current / Channel
VS = 1.8 V, no load, VID = –0.1 V (Output Low)
390
900
6.8 Switching Characteristics
Typical values are at TA = 25°C, VS = 5 V, VCM = VS / 2; CL = 15 pF, input overdrive = 100 mV (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Propagation delay time, high to-
low (RP = 4.99 kΩ open-drain
only)
Midpoint of input to midpoint of output,
VOD = 100 mV
tPHL
3
µs
Propagation delay time, low-to high
(RP = 4.99 kΩ open-drain
only)
Midpoint of input to midpoint of output,
VOD = 100 mV
tPLH
3
µs
tR
tF
Rise time (push-pull only)
Fall time
Measured from 20% to 80%
Measured from 20% to 80%
4.5
4.5
ns
ns
During power on, VCC must exceed 1.6V for
200 µs before the output will reflect the input..
tON
Power-up time
200
µs
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6.9 Electrical Characteristics (Dual)
VS = 1.8 V to 5 V, VCM = VS / 2; minimum and maximum values are at TA = –40°C to +125°C (unless otherwise noted).
Typical values are at TA = 25°C.
PARAMETER
Input Offset Voltage
Hysteresis
TEST CONDITIONS
VS = 1.8 V and 5 V, VCM = VS / 2
VS = 1.8 V and 5 V, VCM = VS / 2
MIN
TYP
±0.1
10
MAX
±8
UNIT
mV
mV
V
VIO
VHYS
VCM
IB
3
25
Common-mode voltage range
Input bias current
Input offset current
VEE
VCC + 0.1
2
1
pA
IOS
pA
Output voltage high (push-pull
only)
VOH
VOL
ILKG
VS = 5 V, VEE = 0 V, IO = 3 mA
VS = 5 V, VEE = 0 V, IO = 3 mA
4.65
4.8
250
100
V
Output voltage low
350
mV
pA
Output leakage
current (open-drain only)
VS = 5 V, VID = +0.1 V (output high),
VPULLUP = VCC
CMRR
PSRR
Common-mode rejection ratio
Power supply rejection ratio
VEE < VCM < VCC, VS = 5 V
73
77
dB
dB
VS = 1.8 V to 5 V, VCM = VS / 2
VS = 5 V, sourcing (push-pull only)
VS = 5 V, sinking
29
ISC
ICC
Short-circuit current
mA
nA
33
Supply current / Channel
VS = 1.8 V, no load, VID = –0.1 V (Output Low)
315
750
6.10 Switching Characteristics (Dual)
Typical values are at TA = 25°C, VS = 5 V, VCM = VS / 2; CL = 15 pF, input overdrive = 100 mV (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Propagation delay time, high to-
low (RP = 4.99 kΩ open-drain
only) (1)
Midpoint of input to midpoint of output,
VOD = 100 mV
tPHL
3
µs
Propagation delay time, low-to high
(RP = 4.99 kΩ open-drain
only) (1)
Midpoint of input to midpoint of output,
VOD = 100 mV
tPLH
3
µs
tR
tF
Rise time (push-pull only)
Fall time
Measured from 20% to 80%
Measured from 20% to 80%
4.5
4.5
ns
ns
During power on, VCC must exceed 1.6V for
200 µs before the output will reflect the input..
tON
Power-up time
200
µs
(1) The lower limit for RP is 650 Ω
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6.11 Electrical Characteristics (Quad)
VS = 1.8 V to 5 V, VCM = VS / 2; minimum and maximum values are at TA = –40°C to +125°C (unless otherwise noted).
Typical values are at TA = 25°C.
PARAMETER
Input Offset Voltage
Hysteresis
TEST CONDITIONS
VS = 1.8 V and 5 V, VCM = VS / 2
VS = 1.8 V and 5 V, VCM = VS / 2
MIN
TYP
±0.1
10
MAX
±8
UNIT
mV
mV
V
VIO
VHYS
VCM
IB
3
25
Common-mode voltage range
Input bias current
Input offset current
VEE
VCC + 0.1
2
1
pA
IOS
pA
Output voltage high (push-pull
only)
VOH
VOL
ILKG
VS = 5 V, VEE = 0 V, IO = 3 mA
VS = 5 V, VEE = 0 V, IO = 3 mA
4.65
4.8
250
100
V
Output voltage low
350
mV
pA
Output leakage
current (open-drain only)
VS = 5 V, VID = +0.1 V (output high),
VPULLUP = VCC
CMRR
PSRR
Common-mode rejection ratio
Power supply rejection ratio
VEE < VCM < VCC, VS = 5 V
73
77
dB
dB
VS = 1.8 V to 5 V, VCM = VS / 2
VS = 5 V, sourcing (push-pull only)
VS = 5 V, sinking
29
ISC
ICC
Short-circuit current
mA
nA
33
Supply current / Channel
VS = 1.8 V, no load, VID = –0.1 V (Output Low)
315
750
6.12 Switching Characteristics (Quad)
Typical values are at TA = 25°C, VS = 5 V, VCM = VS / 2; CL = 15 pF, input overdrive = 100 mV (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Propagation delay time, high to-
low (RP = 4.99 kΩ open-drain
only) (1)
Midpoint of input to midpoint of output,
VOD = 100 mV
tPHL
3
µs
Propagation delay time, low-to high
(RP = 4.99 kΩ open-drain
only) (1)
Midpoint of input to midpoint of output,
VOD = 100 mV
tPLH
3
µs
tR
tF
Rise time (push-pull only)
Fall time
Measured from 20% to 80%
Measured from 20% to 80%
4.5
4.5
ns
ns
During power on, VCC must exceed 1.6V for tON
before the output will reflect the input..
tON
Power-up time
400
µs
(1) The lower limit for RP is 650 Ω
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6.13 Timing Diagrams
tON
VEE
VEE + 1.6V
VCC
VOH/2
VEE
OUT
Figure 6-1. Start-Up Time Timing Diagram (IN+ > IN–)
Figure 6-2. Propagation Delay Timing Diagram
Note
The propagation delays tpLH and tpHL include the contribution of input offset and hysteresis.
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6.14 Typical Characteristics
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VCM = VCC /2
VCM = VCC
VCM = 0
VCM = VCC /2
VCM = VCC
VCM = 0
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
vio_
vio_
VCC = 1.8 V
VCC = 3.3 V
Figure 6-4. Input Offset vs Temperature
Figure 6-3. Input Offset vs Temperature
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Temp -40°C
Temp 25°C
Temp 125°C
VCM = VCC /2
VCM = VCC
VCM = 0
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
0
0.2 0.4 0.6 0.8
1
VCM (V)
1.2 1.4 1.6 1.8
2
vio_
vio_
VCC = 5 V
Figure 6-5. Input Offset vs Temperature
VCC = 1.8 V
Figure 6-6. Input Offset Voltage vs VCM
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Temp -40°C
Temp 25°C
Temp 125°C
Temp -40°C
Temp 25°C
Temp 125°C
0
0.5
1
1.5
VCM (V)
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
VCM (V)
3
3.5
4
4.5
5
vio_
vio_
VCC = 3.3 V
Figure 6-7. Input Offset Voltage vs VCM
VCC = 5 V
Figure 6-8. Input Offset Voltage vs VCM
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6.14 Typical Characteristics (continued)
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
10
9
10
9
8
7
6
5
4
3
2
1
8
7
6
5
4
3
VCM = VCC /2
VCM = VCC
VCM = 0
Temp -40°C
Temp 25°C
Temp 125°C
2
1
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
0
0.5
1
VCM (V)
1.5
2
hyst
hyst
VCC = 1.8 V to 5 V
Figure 6-9. Hysteresis vs Temperature
TLV70x1
VCC = 1.8 V
TLV70x1
Figure 6-10. Hysteresis vs VCM
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
Temp -40°C
Temp 25°C
Temp 125°C
Temp -40°C
Temp 25°C
Temp 125°C
2
1
0
0
1
2
VCM (V)
3
4
1
2
3
4
5
VCM (V)
hyst
hyst
VCC = 3.3 V
TLV70x1
VCC = 5 V
TLV70x1
Figure 6-11. Hysteresis vs VCM
Figure 6-12. Hysteresis vs VCM
1.795
1.79
1000
100
10
1.785
1.78
1.775
1.77
1
1.765
1.76
Temp -40°C
Temp 25°C
Temp 85°C
Temp 125°C
0.1
0.01
1.755
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
0.1
0.15
0.2
0.25
Output Source Current (mA)
0.3
0.35
0.4
0.45
0.5
voh_
tlv7
A.
VCC = 5 V
VCC = 1.8 V
TLV703x
Figure 6-13. Input Bias Current vs Temperature
Figure 6-14. Output Voltage High vs Output Source Current
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6.14 Typical Characteristics (continued)
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
5
4.98
4.96
4.94
4.92
4.9
0.1
0.08
0.07
0.06
0.05
0.04
0.03
4.88
4.86
4.84
4.82
4.8
0.02
Temp -40°C
Temp 25°C
Temp 85°C
Temp 125°C
Temp -40°C
Temp 25°C
Temp 125°C
4.78
0.01
0
0.5
1
1.5
2
2.5
3
3.5
Output Source Current (mA)
4
4.5
5
0.1
0.2 0.3
Output Sink Current (mA)
0.4
0.5
voh_
vol_
VCC = 5 V
TLV703x
VCC = 1.8 V
Figure 6-15. Output Voltage High vs Output Source Current
Figure 6-16. Output Voltage Low vs Output Sink Current
0.5
50
VCC=3.5V
VCC=5.5V
0.3
0.2
40
30
20
10
0.1
0.07
0.05
0.03
0.02
Temp -40°C
Temp 25°C
Temp 125°C
0.01
0.007
0.005
0.1
0.2 0.3 0.40.5 0.7 1
Output Sink Current (mA)
2
3
4 5
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
vol_
nisc
VCC = 5 V
VCM = VCC / 2
Figure 6-17. Output Voltage Low vs Output Sink Current
Figure 6-18. Output Short-Circuit (Sink) Current vs Temperature
50
50
Vcc=3.5V
Vcc=5.5V
40
30
20
40
30
20
10
10
Temp -40°C
Temp 25°C
Temp 125°C
0
-40
-20
0
20
40
Temperature ( °C)
60
80
100 120 140
1
1.5
2
2.5
3
3.5 4
VCC(V)
4.5
5
5.5 6 6.5
pisc
nisc
VCM = VCC / 2
Figure 6-20. Output Short Circuit (Sink) vs VCC
VCM = VCC / 2
TLV703x
Figure 6-19. Output Short-Circuit (Source) Current vs
Temperature
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6.14 Typical Characteristics (continued)
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
50
45
40
35
30
25
20
15
800
700
600
500
400
300
200
10
Temp -40C
Temp 25C
Temp 125C
VCC = 1.8V
VCC = 3.3V
VCC = 5.0V
5
0
1
1.5
2
2.5
3
3.5 4
Vcc (V)
4.5
5
5.5
6
6.5
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Iq_v
pisc
VCM = VCC / 2
TLV70x2
VCM = VCC / 2
Figure 6-21. Output Short Circuit (Source) vs VCC
900
TLV703x
Figure 6-22. ICC vs Temperature
20000
10000
5000
Fall Time
Rise Time
Temp = -40°C
Temp = 25°C
Temp = 125°C
800
700
600
500
400
300
200
2000
1000
500
200
100
50
20
10
5
2
10 2030 50 100 200 5001000
Load Capacitance (pF)
10000
100000
1
1.5
2
2.5
3
3.5
VCC (V)
4
4.5
5
5.5
6
Iq_v
tlv7
VOD = 100 mV
TLV703x Rise only
VCM = VCC / 2
TLV70x2
Figure 6-24. Rise/Fall Time vs Load Capacitance
Figure 6-23. ICC vs VCC
7
6
5
4
3
2
1
7
6
5
4
3
2
1
Temp -40°C
Temp 25°C
Temp 85°C
Temp 125°C
Temp -40°C
Temp 25°C
Temp 85°C
Temp 125°C
0
100
200
300
400
500
0
100
200
300
400
500
VOD (mV)
VOD (mV)
tlv7
tlv7
VCC = 3.3 V to 5 V
TLV703x
VCC = 3.3 V to 5 V
Figure 6-25. Propagation Delay (L-H) vs Input Overdrive
Figure 6-26. Propagation Delay (H-L) vs Input Overdrive
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7 Detailed Description
7.1 Overview
The TLV703x-Q1 and TLV704x-Q1 devices are single-channel, nano-power comparators with push-pull and
open-drain outputs. Operating from 1.6 V to 6.5 V and consuming only 315 nA, the TLV703x-Q1 and TLV704x-
Q1 are designed for portable and industrial applications.
7.2 Functional Block Diagram
VCC
IN+
+
OUT
-
IN-
Power-on-reset
Bias
7.3 Feature Description
The TLV703x-Q1 and TLV704x-Q1 comparators are nanopower comparators that are capable of operating at
low voltages. The TLV703x-Q1 and TLV704x-Q1 feature a rail-to-rail input stage capable of operating up to 100
mV beyond the VCC power supply rail. The TLV703x-Q1 (push-pull) and TLV704x-Q1 (open-drain) also feature
internal hysteresis.
7.4 Device Functional Modes
The TLV703x-Q1 and TLV704x-Q1 have a power-on-reset (POR) circuit. While the power supply (VS) is less
than the minimum supply voltage, either upon ramp-up or ramp-down, the POR circuitry is activated.
For the TLV703x-Q1, the POR circuit holds the output low (at VEE) while activated.
For the TLV704x-Q1, the POR circuit keeps the output high impedance (logical high) while activated.
When the supply voltage is greater than, or equal to, the minimum supply voltage, the comparator output reflects
the state of the differential input (VID).
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7.4.1 Inputs
The TLV703x-Q1 and TLV704x-Q1 input common-mode extends from VEE to 100 mV above VCC. The differential
input voltage (VID) can be any voltage within these limits. No phase inversion of the comparator output occurs
when the input pins exceed VCC and VEE
.
The input of TLV703x-Q1 and TLV704x-Q1 is fault tolerant. It maintains the same high input impedance when
VCC is unpowered or ramping up. The input can be safely driven up to the specified maximum voltage (7 V) with
VCC = 0 V or any value up to the maximum specified. The VCC is isolated from the input such that it maintains its
value even when a higher voltage is applied to the input.
The input bias current is typically 1 pA for input voltages between VCC and VEE. The comparator inputs are
protected from voltages below VEE by internal diodes connected to VEE. As the input voltage goes under VEE
,
the protection diodes become forward biased and begin to conduct causing the input bias current to increase
exponentially. Input bias current typically doubles every 10°C temperature increases.
7.4.2 Internal Hysteresis
The device hysteresis transfer curve is shown in Figure 7-1. This curve is a function of three components: VTH
,
VOS, and VHYST
:
•
•
VTH is the actual set voltage or threshold trip voltage.
VOS is the internal offset voltage between VIN+ and VIN–. This voltage is added to VTH to form the actual trip
point at which the comparator must respond to change output states.
•
VHYST is the internal hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise
(7 mV for both TLV703x-Q1 and TLV704x-Q1).
VTH + VOS - (VHYST / 2)
VTH + VOS
VTH + VOS + (VHYST / 2)
Figure 7-1. Hysteresis Transfer Curve
7.4.3 Output
The TLV703x-Q1 features a push-pull output stage eliminating the need for an external pullup resistor. On the
other hand, the TLV704x-Q1 features an open-drain output stage enabling the output logic levels to be pulled up
to an external source up to 6.5 V independent of the supply voltage.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TLV703x-Q1 and TLV704x-Q1 are nano-power comparators with reasonable response time. The
comparators have a rail-to-rail input stage that can monitor signals beyond the positive supply rail with integrated
hysteresis. When higher levels of hysteresis are required, positive feedback can be externally added. The push-
pull output stage of the TLV703x-Q1 is optimal for reduced power budget applications and features no shoot-
through current. When level shifting or wire-ORing of the comparator outputs is needed, the TLV704x-Q1 with
its open-drain output stage is well suited to meet the system needs. In either case, the wide operating voltage
range, low quiescent current, and small size of the TLV703x-Q1 and TLV704x-Q1 make these comparators
excellent candidates for battery-operated and portable, handheld designs.
8.1.1 Inverting Comparator With Hysteresis for TLV703x-Q1
The inverting comparator with hysteresis requires a three-resistor network that is referenced to the comparator
supply voltage (VCC), as shown in Figure 8-1. When VIN at the inverting input is less than VA, the output voltage
is high (for simplicity, assume VO switches as high as VCC). The three network resistors can be represented as
R1 || R3 in series with R2. Equation 1 defines the high-to-low trip voltage (VA1).
R2
VA1 = VCC
´
(R1 || R3) + R2
(1)
When VIN is greater than VA, the output voltage is low, very close to ground. In this case, the three network
resistors can be presented as R2 || R3 in series with R1. Use Equation 2 to define the low to high trip voltage
(VA2).
R2 || R3
VA2 = VCC
´
R1 + (R2 || R3)
(2)
(3)
Equation 3 defines the total hysteresis provided by the network.
DVA = VA1 - VA2
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+VCC
+5 V
R1
1 MW
VIN
5 V
RLOAD
VA
VO
100 kW
VA2
1.67 V
VA1
3.33 V
0 V
R3
1 MW
VIN
R2
1 MW
VO High
+VCC
VO Low
+VCC
R1
VA1
R2
R3
R1
VA2
R2
R3
Copyright © 2016, Texas Instruments Incorporated
Figure 8-1. TLV703x-Q1 in an Inverting Configuration With Hysteresis
8.1.2 Noninverting Comparator With Hysteresis for TLV703x-Q1
A noninverting comparator with hysteresis requires a two-resistor network, as shown in Figure 8-2, and a voltage
reference (VREF) at the inverting input. When VIN is low, the output is also low. For the output to switch from low
to high, VIN must rise to VIN1. Use Equation 4 to calculate VIN1
.
VREF
VIN1 = R1 ´
+ VREF
R2
(4)
When VIN is high, the output is also high. For the comparator to switch back to a low state, VIN must drop to VIN2
such that VA is equal to VREF. Use Equation 5 to calculate VIN2
.
VREF (R1 + R2) - VCC ´ R1
VIN2
=
R2
(5)
(6)
The hysteresis of this circuit is the difference between VIN1 and VIN2, as shown in Equation 6.
R1
DVIN = VCC
´
R2
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+VCC
+5 V
VREF
VO
+2.5 V
VA
VIN
RLOAD
R1
330 kW
R2
1 MW
VO High
+VCC
VO Low
VIN1
5 V
0 V
R2
R1
VA = VREF
R2
VO
VA = VREF
R1
VIN2
VIN1
1.675 V 3.325 V
VIN
VIN2
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Figure 8-2. TLV703x-Q1 in a Noninverting Configuration With Hysteresis
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8.2 Typical Applications
8.2.1 Window Comparator
Window comparators are commonly used to detect undervoltage and overvoltage conditions. Figure 8-3 shows a
simple window comparator circuit.
3.3V
RPU
R1
UV_OV
+
Micro-
Controller
Sensor
R2
+
R3
Figure 8-3. TLV704x-Q1-Based Window Comparator
8.2.1.1 Design Requirements
For this design, follow these design requirements:
•
•
•
•
Alert (logic low output) when an input signal is less than 1.1 V
Alert (logic low output) when an input signal is greater than 2.2 V
Alert signal is active low
Operate from a 3.3-V power supply
8.2.1.2 Detailed Design Procedure
Configure the circuit as shown in Figure 8-3. Connect VCC to a 3.3-V power supply and VEE to ground. Make R1,
R2, and R3 each 10-MΩ resistors. These three resistors are used to create the positive and negative thresholds
for the window comparator (VTH+ and VTH–). With each resistor being equal, VTH+ is 2.2 V and VTH- is 1.1 V.
Large resistor values such as 10 MΩ are used to minimize power consumption. The sensor output voltage is
applied to the inverting and noninverting inputs of the two TLV704x-Q1 devices. The TLV704x-Q1 is used for
its open-drain output configuration. Using the TLV704x-Q1 allows the two comparator outputs to be wire-ored
together. The respective comparator outputs are low when the sensor is less than 1.1 V or greater than 2.2 V.
VOUT is high when the sensor is in the range of 1.1 V to 2.2 V.
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8.2.1.3 Application Curve
VIN
VTH+ = 2.2 V
VTHœ = 1.1 V
Time (usec)
VOUT
Time (usec)
50
100
150
200
Figure 8-4. Window Comparator Results
8.2.2 IR Receiver Analog Front End
A single TLV703x-Q1 device can be used to build a complete IR receiver analog front end (AFE). The nanoamp
quiescent current and low input bias current make it possible to be powered with a coin cell battery, which could
last for years.
Vref
470 kꢀ
470 kꢀ
10M ꢀ
R4
3 V
IR LED
R2
R3
U1
+
Output to MCU
(Also to wake-up MCU)
œ
VOUT
C1
10M ꢀ
TLV7031
VIN
R1
0.01 ꢁF
GND
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Figure 8-5. IR Receiver Analog Front End Using TLV703x-Q1
8.2.2.1 Design Requirements
For this design, follow these design requirements:
•
Use a proper resistor (R1) value to generate an adequate signal amplitude applied to the inverting input of the
comparator.
•
•
The low input bias current IB (2 pA typical) ensures that a greater value of R1 to be used.
The RC constant value (R2 and C1) must support the targeted data rate (that is, 9,600 bauds) in order to
maintain a valid tripping threshold.
•
The hysteresis introduced with R3 and R4 helps to avoid spurious output toggles.
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SNOSDA5C – MAY 2020 – REVISED OCTOBER 2021
8.2.2.2 Detailed Design Procedure
The IR receiver AFE design is highly streamlined and optimized. R1 converts the IR light energy induced current
into voltage and applies to the inverting input of the comparator. The RC network of R2 and C1 establishes
a reference voltage Vref, which tracks the mean amplitude of the IR signal. The noninverting input is directly
connected to Vref through R3. R3 and R4 are used to produce a hysteresis to keep transitions free of spurious
toggles. To reduce the current drain from the coin cell battery, data transmission must be short and infrequent.
More technical details are provided in the TI TechNote Low Power Comparator for Signal Processing and
Wake-Up Circuit in Smart Meters (SNVA808).
8.2.2.3 Application Curve
1.8 V
VIN
1.2 V
4.0 V
VOUT
0.0 V
1.61 V
VREF
1.58 V
0.0
200.0 u
400.0 u
Time
600.0 u
800.0 u
Figure 8-6. IR Receiver AFE Waveforms
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8.2.3 Square-Wave Oscillator
A square-wave oscillator can be used as low-cost timing reference or system supervisory clock source.
Figure 8-7. Square-Wave Oscillator
8.2.3.1 Design Requirements
The square-wave period is determined by the RC time constant of the capacitor and resistor. The maximum
frequency is limited by the propagation delay of the device and the capacitance load at the output. The low input
bias current allows a lower capacitor value and larger resistor value combination for a given oscillator frequency,
which may help reduce BOM cost and board space.
8.2.3.2 Detailed Design Procedure
The oscillation frequency is determined by the resistor and capacitor values. The following section provides
details to calculate these component values.
Figure 8-8. Square-Wave Oscillator Timing Thresholds
First consider the output of figure Figure 8-7 is high, which indicates the inverted input VC is lower than the
noninverting input (VA). This causes the C1 to be charged through R4, and the voltage VC increases until it is
equal to the noninverting input. The value of VA at the point is calculated by Equation 7.
VCCìR2
R2 + R1IIR3
VA1
=
(7)
If R1 = R2= R3, then VA1 = 2 VCC/ 3
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SNOSDA5C – MAY 2020 – REVISED OCTOBER 2021
At this time the comparator output trips pulling down the output to the negative rail. The value of VA at this point
is calculated by Equation 8.
VCC(R2IIR3 )
VA2
=
R1+R2IIR3
(8)
If R1 = R2 = R3, then VA2 = VCC/3
The C1 now discharges though the R4, and the voltage VCC decreases until it reaches VA2. At this point, the
output switches back to the starting state. The oscillation period equals the time duration from 2 VCC / 3 to
VCC / 3 then back to 2 VCC / 3, which is given by R4C1 × ln2 for each trip. Therefore, the total time duration is
calculated as 2 R4C1 × ln2. The oscillation frequency can be obtained by Equation 9:
f = 1/ 2 R4ìC1ìIn2
(9)
8.2.3.3 Application Curve
Figure 8-9 shows the simulated results of an oscillator using the following component values:
•
•
•
•
R1 = R2 = R3 = R4 = 100 kΩ
C1 = 100 pF, CL = 20 pF
V+ = 5 V, V– = GND
Cstray (not shown) from VA to GND = 10 pF
Figure 8-9. Square-Wave Oscillator Output Waveform
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SNOSDA5C – MAY 2020 – REVISED OCTOBER 2021
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9 Power Supply Recommendations
The TLV703x-Q1 and TLV704x-Q1 have a recommended operating voltage range (VS) of 1.6 V to 6.5 V. VS is
defined as VCC – VEE. Therefore, the supply voltages used to create VS can be single-ended or bipolar. For
example, single-ended supply voltages of 5 V and 0 V and bipolar supply voltages of +2.5 V and –2.5 V create
comparable operating voltages for VS. However, when bipolar supply voltages are used, it is important to realize
that the logic low level of the comparator output is referenced to VEE
.
Output capacitive loading and output toggle rate will cause the average supply current to rise over the quiescent
current.
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SNOSDA5C – MAY 2020 – REVISED OCTOBER 2021
10 Layout
10.1 Layout Guidelines
Figure 10-1 shows the typical connections for the TLV7031-Q1. To minimize supply noise, power supplies
must be capacitively decoupled by a 0.1-µF ceramic capacitor in parallel with a 10-µF electrolytic capacitor.
Comparators are very sensitive to input noise. Proper grounding (the use of a ground plane) helps to maintain
the specified performance of the TLV70x1-Q1 family.
For best results, maintain the following layout guidelines:
1. Use a printed-circuit board (PCB) with a good, unbroken low-inductance ground plane.
2. Place a decoupling capacitor (0.1-µF ceramic, surface-mount capacitor) as close as possible to VCC
.
3. On the inputs and the output, keep lead lengths as short as possible to avoid unwanted parasitic feedback
around the comparator. Keep inputs away from the output.
4. Solder the device directly to the PCB rather than using a socket.
5. For slow-moving input signals, take care to prevent parasitic feedback. A small capacitor (1000 pF or less)
placed between the inputs can help eliminate oscillations in the transition region. This capacitor causes
some degradation to propagation delay when the impedance is low. The top-side ground plane runs between
the output and inputs.
6. The ground pin ground trace runs under the device up to the bypass capacitor, shielding the inputs from the
outputs.
10.2 Layout Example
VEE
VOUT
VEE
IN+
VCC
IN-
Figure 10-1. TLV7031-Q1 Layout Example
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SNOSDA5C – MAY 2020 – REVISED OCTOBER 2021
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Module
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TLV703x-
Q1, TLV704x-Q1 device family. The DIP Adapter EVM can be requested at the Texas Instruments website
through the product folder or purchased directly from the TI eStore.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Nov-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV7031QDBVRQ1
TLV7031QDCKRQ1
TLV7032QDGKRQ1
TLV7034QPWRQ1
TLV7041QDBVRQ1
TLV7041QDCKRQ1
TLV7042QDGKRQ1
TLV7044QPWRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SC70
DBV
DCK
DGK
PW
5
5
3000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
2000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
7031
1GP
7032
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
VSSOP
TSSOP
SOT-23
SC70
8
14
5
7034Q
7041
DBV
DCK
DGK
PW
5
1GQ
VSSOP
TSSOP
8
7042
14
7044Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Nov-2021
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV7031-Q1, TLV7032-Q1, TLV7034-Q1, TLV7041-Q1, TLV7042-Q1, TLV7044-Q1 :
Catalog : TLV7031, TLV7032, TLV7034, TLV7041, TLV7042, TLV7044
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Nov-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV7031QDBVRQ1
TLV7031QDCKRQ1
TLV7032QDGKRQ1
TLV7034QPWRQ1
TLV7041QDBVRQ1
TLV7041QDCKRQ1
TLV7042QDGKRQ1
TLV7044QPWRQ1
SOT-23
SC70
DBV
DCK
DGK
PW
5
5
3000
3000
2500
2000
3000
3000
2500
2000
178.0
178.0
330.0
330.0
178.0
178.0
330.0
330.0
9.0
9.0
3.3
2.4
5.3
6.9
3.3
2.4
5.3
6.9
3.2
2.5
3.4
5.6
3.2
2.5
3.4
5.6
1.4
1.2
1.4
1.6
1.4
1.2
1.4
1.6
4.0
4.0
8.0
8.0
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q1
Q1
Q3
Q3
Q1
Q1
VSSOP
TSSOP
SOT-23
SC70
8
12.4
12.4
9.0
12.0
12.0
8.0
14
5
DBV
DCK
DGK
PW
5
9.0
8.0
VSSOP
TSSOP
8
12.4
12.4
12.0
12.0
14
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Nov-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV7031QDBVRQ1
TLV7031QDCKRQ1
TLV7032QDGKRQ1
TLV7034QPWRQ1
TLV7041QDBVRQ1
TLV7041QDCKRQ1
TLV7042QDGKRQ1
TLV7044QPWRQ1
SOT-23
SC70
DBV
DCK
DGK
PW
5
5
3000
3000
2500
2000
3000
3000
2500
2000
180.0
190.0
366.0
853.0
180.0
190.0
366.0
853.0
180.0
190.0
364.0
449.0
180.0
190.0
364.0
449.0
18.0
30.0
50.0
35.0
18.0
30.0
50.0
35.0
VSSOP
TSSOP
SOT-23
SC70
8
14
5
DBV
DCK
DGK
PW
5
VSSOP
TSSOP
8
14
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/F 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
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EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/F 06/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/F 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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