TLV7034 [TI]
TLV703x and TLV704x Small-Size, Nanopower, Low-Voltage Comparators;
| 型号： | TLV7034 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TLV703x and TLV704x Small-Size, Nanopower, Low-Voltage Comparators |
| 文件： | 总51页 (文件大小：2494K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV7031, TLV7032, TLV7041, TLV7042, TLV7034, TLV7044
SLVSE13F –SEPTEMBER 2017–REVISED JUNE 2020
TLV703x and TLV704x Small-Size, Nanopower, Low-Voltage Comparators
The TLV703x and TLV704x offer an excellent
combination of speed and power, with a propagation
delay of 3 μs and a quiescent supply current of 315
nA. The benefit of fast response time at nanoPower
enables power-conscious systems to monitor and
respond quickly to fault conditions. With an operating
voltage range of 1.6 V to 6.5 V, these comparators
are compatible with 3-V and 5-V systems.
1 Features
1
•
•
Ultra-small X2SON, WSON, WQFN packages
Tiny SOT-23, SC70, VSSOP, and TSSOP
packages
•
•
•
•
•
•
•
•
•
Wide supply voltage range of 1.6 V to 6.5 V
Quiescent supply current of 315 nA
Low propagation delay of 3 µs
The TLV703x and TLV704x also ensure no output
phase inversion with overdriven inputs and internal
hysteresis, so engineers can use this family of
comparators for precision voltage monitoring in harsh,
noisy environments where slow-moving input signals
must be converted into clean digital outputs.
Rail-to-rail common-mode input voltage
Internal hysteresis
Push-pull output (TLV703x)
Open-drain output (TLV704x)
No phase reversal for overdriven inputs
–40°C to 125°C Operating temperature
The TLV703x has a push-pull output stage capable of
sinking and sourcing milliamps of current when
controlling an LED or driving a capacitive load. The
TLV704x has an open-drain output stage that can be
pulled beyond VCC, making it appropriate for level
translators and bipolar to single-ended converters.
2 Applications
•
•
•
•
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Mobile phones and tablets
Headsets/headphones & earbuds
PC & notebooks
Device Information(1)
Gas detector
PART NUMBERS
PACKAGE (PINS)
BODY SIZE (NOM)
0.80 mm × 0.80 mm
2.00 mm × 1.25 mm
2.90 mm × 1.60 mm
3.00 mm x 3.00 mm
2.90 mm x 1.60 mm
2.00 mm x 2.00 mm
3.00 mm x 3.00 mm
4.40 mm x 5.00 mm
Smoke & heat detector
Motion detector
X2SON (5)
TLV7031, TLV7041 SC70 (5)
SOT-23 (5)
Gas meter
VSSOP (8)
Servo drive position sensor
TLV7032, TLV7042 SOT-23 (8)
WSON (8)
3 Description
The TLV7031/TLV7041 (single-channel), TLV7032/42
(dual-channel), and TLV7034/44 (quad-channel) are
low-voltage, nanoPower comparators. These devices
are available in an ultra-small, leadless packages as
well as standard 5-pin SC70, SOT-23, VSSOP, and
TSSOP packages, making them applicable for space-
critical designs like smartphones, smart meters, and
other portable or battery-powered applications.
WQFN (16)
TSSOP (14)
TLV7034,
TLV7044(2)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) QUAD option is for preview only.
X2SON Package vs SC70 and US Dime
US dime (18x18x1.35 mm3)
ICC vs. Supply Voltage
0.6
0.5
0.4
0.3
0.2
5-Lead SC70
5-Pin X2SON
Temp -40°C
Temp 25°C
Temp 125°C
0.1
0
1.5
2.5
3.5
4.5
5.5
6.5
VCC (V)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV7031, TLV7032, TLV7041, TLV7042, TLV7034, TLV7044
SLVSE13F –SEPTEMBER 2017–REVISED JUNE 2020
www.ti.com
Table of Contents
7.1 Overview ................................................................. 18
7.2 Functional Block Diagram ....................................... 18
7.3 Feature Description................................................. 18
7.4 Device Functional Modes........................................ 18
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Applications ................................................ 22
Power Supply Recommendations...................... 29
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 7
6.1 Absolute Maximum Ratings ...................................... 7
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information (Single) .................................... 7
6.5 Thermal Information (Dual) ....................................... 8
6.6 Thermal Information (Quad)...................................... 8
6.7 Electrical Characteristics (Single) ............................. 9
6.8 Switching Characteristics (Single) ............................ 9
6.9 Electrical Characteristics (Dual).............................. 10
6.10 Switching Characteristics (Dual) ........................... 10
6.11 Electrical Characteristics (Quad) .......................... 11
6.12 Switching Characteristics (Quad).......................... 11
6.13 Timing Diagrams................................................... 12
6.14 Typical Characteristics.......................................... 13
Detailed Description ............................................ 18
8
9
10 Layout................................................................... 29
10.1 Layout Guidelines ................................................. 29
10.2 Layout Example .................................................... 29
11 Device and Documentation Support ................. 30
11.1 Device Support...................................................... 30
11.2 Documentation Support ........................................ 30
11.3 Related Links ........................................................ 30
11.4 Receiving Notification of Documentation Updates 30
11.5 Community Resources.......................................... 30
11.6 Trademarks........................................................... 30
11.7 Electrostatic Discharge Caution............................ 30
11.8 Glossary................................................................ 31
12 Mechanical, Packaging, and Orderable
7
Information ........................................................... 31
4 Revision History
Changes from Revision E (June 2019) to Revision F
Page
•
•
•
•
Added quad channel versions ................................................................................................................................................ 1
Added SOT-23 (8) and WSON (8) for dual channel options.................................................................................................. 1
Added QUAD package options............................................................................................................................................... 1
Added TSSOP and RTE pinout information to Pin Configuration and Functions section ..................................................... 6
Changes from Revision D (April 2019) to Revision E
Page
•
•
•
Changed VOH min from 4.7V to 4.65V for all package options in EC Table (Single) ........................................................... 7
Changed VOL max from 300mV to 350mV for all package options in EC Table (Single)..................................................... 7
Deleted separate rows for VOH & VOL for DBV package options only in EC Table (Single) ............................................... 7
Changes from Revision C (March 2019) to Revision D
Page
•
Added separate rows for VOH & VOL for DBV package options in EC Table (Single) ......................................................... 7
Changes from Revision B (May 2018) to Revision C
Page
•
•
•
•
•
Added dual channel versions in VSSOP package ................................................................................................................. 1
Changed TLV7031 to TLV703x and TLV7041 to TLV704x throughout the document ......................................................... 1
Added dual channel versions ................................................................................................................................................. 1
Added Device Information dual channel versions in VSSOP package .................................................................................. 1
Deleted The SOT-23 package is in preview only ................................................................................................................... 1
2
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Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: TLV7031 TLV7032 TLV7041 TLV7042 TLV7034 TLV7044
TLV7031, TLV7032, TLV7041, TLV7042, TLV7034, TLV7044
www.ti.com
SLVSE13F –SEPTEMBER 2017–REVISED JUNE 2020
Changes from Revision A (January 2018) to Revision B
Page
•
Changed the preview SC70 package to production data....................................................................................................... 1
Changes from Original (September 2017) to Revision A
Page
•
Changed data sheet title from: TLV7031/TLV7041 Small-Size, nanoPower, Low-Voltage Comparators to: TLV7031
and TLV7041 Small Size, nanopower, Low-Voltage Comparators ....................................................................................... 1
Added Internal Hysteresis bullet to Features ........................................................................................................................ 1
Specified which device has push-pull output and open-drain output options in Features ..................................................... 1
Removed (TLV7031) from key graphic title because the graph covers both the TLV7031 and TLV7041 devices ............... 1
Added X2SON tablenote to Pin Functions table ................................................................................................................... 4
Changed Figure 2................................................................................................................................................................. 12
Added note to the Timing Diagrams section ........................................................................................................................ 12
Smoothed Propagation Delay plots in Figure 31 through ................................................................................................... 13
Changed vertical labels on Figure 20, Figure 21, Figure 17, and Figure 30........................................................................ 15
Changed Functional Block Diagram..................................................................................................................................... 18
•
•
•
•
•
•
•
•
•
•
Changed text 'the TLV7041 features an open-drain output stage enabling the output logic levels to be pulled up to
an external source up to 7 V' to 'the TLV7041 features an open-drain output stage enabling the output logic levels to
be pulled up to an external source up to 6.5 V'.................................................................................................................... 19
•
•
•
Changed Figure 36............................................................................................................................................................... 22
Added note to the Layout Example section.......................................................................................................................... 29
Added Documentation Support section ............................................................................................................................... 30
Copyright © 2017–2020, Texas Instruments Incorporated
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Product Folder Links: TLV7031 TLV7032 TLV7041 TLV7042 TLV7034 TLV7044
TLV7031, TLV7032, TLV7041, TLV7042, TLV7034, TLV7044
SLVSE13F –SEPTEMBER 2017–REVISED JUNE 2020
www.ti.com
5 Pin Configuration and Functions
DPW Package
5-Pin X2SON
Top View
OUT
1
5
IN+
3
VEE
VCC
2
4
IN
Not to scale
DBV and DCK Package
5-Pin SOT-23 and SC70
Top View
OUT
VEE
IN+
1
2
3
5
VCC
4
IN-
Pin Functions
PIN
I/O(1)
DESCRIPTION
X2SON(2)
SOT-23, SC70
NAME
OUT
VCC
1
2
3
4
5
1
5
2
4
3
O
P
P
I
Output
Positive (highest) power supply
Negative (lowest) power supply
Inverting input
VEE
IN–
IN+
I
Noninverting input
(1) I = Input, O = Output, P = Power
(2) The application report Designing and Manufacturing With TI's X2SON Packages (SCEA055) provides more details on the optimal PCB
designs.
4
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Product Folder Links: TLV7031 TLV7032 TLV7041 TLV7042 TLV7034 TLV7044
TLV7031, TLV7032, TLV7041, TLV7042, TLV7034, TLV7044
www.ti.com
SLVSE13F –SEPTEMBER 2017–REVISED JUNE 2020
TLV7032/42 DGK, DDF Packages
8-Pin VSSOP, SOT-23
Top View
1
2
3
4
8
7
OUTA
INA-
INA+
VEE
VCC
OUTB
INB-
INB+
6
5
TLV7032/42 DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
1
8
7
OUTA
INA-
INA+
VEE
VCC
2
3
4
OUTB
INB-
INB+
Thermal
Pad
6
5
(1) Connect thermal pad to V–.
Pin Functions: TLV7032/42
PIN
I/O
DESCRIPTION
NAME
INA–
INA+
INB–
INB+
OUTA
OUTB
VEE
NO.
2
I
I
Inverting input, channel A
3
Noninverting input, channel A
Inverting input, channel B
6
I
5
I
Noninverting input, channel B
Output, channel A
1
O
O
—
—
7
Output, channel B
4
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
VCC
8
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TLV7031, TLV7032, TLV7041, TLV7042, TLV7034, TLV7044
SLVSE13F –SEPTEMBER 2017–REVISED JUNE 2020
www.ti.com
TLV7034/44 PW Packages
14-Pin TSSOP
TLV7034/44 RTE Package
16-Pin WQFN With Exposed Thermal Pad
Top View
Top View
OUT A
œIN A
+IN A
VCC
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT D
œIN D
+IN D
VEE
+IN A
VCC
NC
1
2
3
4
12
11
10
9
+IN D
+IN B
œIN B
OUT B
+IN C
œIN C
OUT C
VEE
NC
Thermal
Pad
8
+IN B
+IN C
Not to scale
(TOP view,
not to scale)
(1) Connect thermal pad to V–.
Pin Functions: TLV7034/44
PIN
I/O
DESCRIPTION
NAME
TSSOP
WQFN
–IN1 A
2
3
16
1
I
I
Inverting input, channel A
Noninverting input, channel A
Inverting input, channel B
Noninverting input, channel B
Inverting input, channel C
Noninverting input, channel C
Inverting input, channel D
Noninverting input, channel D
No internal connection
Output, channel A
+IN A
–IN B
+IN B
–IN C
+IN C
–IN D
+IN D
NC
6
5
I
5
4
I
9
8
I
10
13
12
—
1
9
I
13
12
3, 10
15
6
I
I
—
O
O
O
O
—
—
OUT A
OUT B
OUT C
OUT D
VEE
7
Output, channel B
8
7
Output, channel C
14
11
4
14
11
2
Output, channel D
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
VCC
6
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Product Folder Links: TLV7031 TLV7032 TLV7041 TLV7042 TLV7034 TLV7044
TLV7031, TLV7032, TLV7041, TLV7042, TLV7034, TLV7044
www.ti.com
SLVSE13F –SEPTEMBER 2017–REVISED JUNE 2020
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
UNIT
V
Supply voltage VS = VCC - VEE
Input pins (IN+, IN-)(2)
7
VEE – 0.3
7
±10
V
Current into Input pins (IN+, IN-)
Output (OUT) (TLV703x)(3)
Output (OUT) (TLV704x)
Output short-circuit duration(4)
Junction temperature, TJ
mA
V
VEE – 0.3
VEE – 0.3
VCC + 0.3
7
V
10
s
150
°C
°C
Storage temperature, Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to VEE. Input signals that can swing 0.3V below VEE must be current-limited to 10mA or less
(3) Output maximum is (VCC + 0.3 V) or 7 V, whichever is less.
(4) Short-circuit to ground, one comparator per package.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
6.5
UNIT
Supply voltage VS = VCC – VEE
Input voltage range
1.6
VEE – 0.1
–40
V
V
VCC + 0.1
125
Ambient temperature, TA
°C
6.4 Thermal Information (Single)
TLV7031/TLV7041
THERMAL METRIC(1)
DPW (X2SON)
5 PINS
533.2
DBV (SOT-23)
5 PINS
297.2
DCK (SC70)
5 PINS
278.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
302.7
224.7
186.6
408.3
200.1
113.2
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
71.5
141.2
82.3
ΨJB
405.9
198.9
112.4
RθJC(bot)
188.3
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Thermal Information (Dual)
TLV7032/TLV7042
DDF (SOT-23)
8 PINS
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
211.7
DSG (WSON)
8 PINS
106.1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
212.5
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
96.1
127.3
127.3
133.5
129.2
72.5
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
28.3
25.8
16.8
ΨJB
131.7
129.0
72.2
RθJC(bot)
N/A
N/A
47.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information (Quad)
TLV7034/44
THERMAL METRIC(1)
RTE (QFN)
16 PINS
PW (TSSOP)
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8
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SLVSE13F –SEPTEMBER 2017–REVISED JUNE 2020
6.7 Electrical Characteristics (Single)
VS = 1.8 V to 5 V, VCM = VS / 2; minimum and maximum values are at TA = –40°C to +125°C (unless otherwise noted).
Typical values are at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIO
Input Offset Voltage
VS = 1.8 V and 5 V, VCM = VS / 2
±0.1
±8
mV
VS = 1.8 V and 5 V, VCM = VS / 2,
TA = 25°C
VHYS
Hysteresis
2
7
17
mV
VCM
IB
Common-mode voltage range
Input bias current
VEE
VCC + 0.1
V
2
1
pA
pA
IOS
Input offset current
Output voltage high
(for TLV7031 only)
VOH
VOL
ILKG
VS = 5 V, VEE = 0 V, IO = 3 mA
VS = 5 V, VEE = 0 V, IO = 3 mA
4.65
4.8
250
100
V
Output voltage low
350
mV
pA
Open-drain output leakage
current (TLV7041 only)
VS = 5 V, VID = +0.1 V (output high),
VPULLUP = VCC
CMRR
PSRR
Common-mode rejection ratio
Power supply rejection ratio
VEE < VCM < VCC, VS = 5 V
VS = 1.8 V to 5 V, VCM = VS / 2
VS = 5 V, sourcing
73
77
29
33
dB
dB
ISC
Short-circuit current
Supply current
mA
nA
VS = 5 V, sinking
VS = 1.8 V, no load, VID = –0.1 V (Output
Low)
ICC
335
900
6.8 Switching Characteristics (Single)
Typical values are at TA = 25°C, VS = 5 V, VCM = VS / 2; CL = 15 pF, input overdrive = 100 mV (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Propagation delay time, high to-
low (RP = 2.5 kΩ TLV7041
only)
Midpoint of input to midpoint of output,
VOD = 100 mV
tPHL
3
µs
Propagation delay time, low-to high
(RP = 2.5 kΩ TLV7041
only)
Midpoint of input to midpoint of output,
VOD = 100 mV
tPLH
3
µs
tR
tF
Rise time (TLV7031 only)
Fall time
Measured from 10% to 90%
Measured from 10% to 90%
4.5
4.5
ns
ns
During power on, VCC must exceed 1.6V for
200 µs before the output will reflect the input.
tON
Power-up time
200
µs
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6.9 Electrical Characteristics (Dual)
VS = 1.8 V to 5 V, VCM = VS / 2; minimum and maximum values are at TA = –40°C to +125°C (unless otherwise noted).
Typical values are at TA = 25°C.
PARAMETER
Input Offset Voltage
Hysteresis
TEST CONDITIONS
VS = 1.8 V and 5 V, VCM = VS / 2
VS = 1.8 V and 5 V, VCM = VS / 2
MIN
TYP
±0.1
10
MAX
UNIT
mV
mV
V
VIO
VHYS
VCM
IB
±8
3
25
Common-mode voltage range
Input bias current
Input offset current
VEE
VCC + 0.1
2
1
pA
IOS
pA
Output voltage high (for TLV7032
only)
VOH
VOL
ILKG
VS = 5 V, VEE = 0 V, IO = 3 mA
VS = 5 V, VEE = 0 V, IO = 3 mA
4.65
4.8
250
100
V
Output voltage low
350
mV
pA
Open-drain output leakage
current (TLV7042 only)
VS = 5 V, VID = +0.1 V (output high),
VPULLUP = VCC
CMRR
PSRR
Common-mode rejection ratio
Power supply rejection ratio
VEE < VCM < VCC, VS = 5 V
73
77
dB
dB
VS = 1.8 V to 5 V, VCM = VS / 2
VS = 5 V, sourcing (for TLV7032 only)
VS = 5 V, sinking
29
ISC
ICC
Short-circuit current
mA
nA
33
Supply current / Channel
VS = 1.8 V, no load, VID = –0.1 V (Output Low)
315
750
6.10 Switching Characteristics (Dual)
Typical values are at TA = 25°C, VS = 5 V, VCM = VS / 2; CL = 15 pF, input overdrive = 100 mV (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Propagation delay time, high to-
Midpoint of input to midpoint of output,
VOD = 100 mV
tPHL
low (RP = 4.99 kΩ TLV7042
3
µs
(1)
only)
Propagation delay time, low-to high
Midpoint of input to midpoint of output,
VOD = 100 mV
tPLH
(RP = 4.99 kΩ TLV7042
3
µs
(1)
only)
tR
tF
Rise time (TLV7032 only)
Fall time
Measured from 20% to 80%
Measured from 20% to 80%
4.5
4.5
ns
ns
During power on, VCC must exceed 1.6V for
tON before the output will reflect the input..
tON
Power-up time
200
µs
(1) The lower limit for RP is 650 Ω
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6.11 Electrical Characteristics (Quad)
VS = 1.8 V to 5 V, VCM = VS / 2; minimum and maximum values are at TA = –40°C to +125°C (unless otherwise noted).
Typical values are at TA = 25°C.
PARAMETER
Input Offset Voltage
Hysteresis
TEST CONDITIONS
VS = 1.8 V and 5 V, VCM = VS / 2
VS = 1.8 V and 5 V, VCM = VS / 2
MIN
TYP
±0.1
10
MAX
UNIT
mV
mV
V
VIO
VHYS
VCM
IB
±8
3
25
Common-mode voltage range
Input bias current
Input offset current
VEE
VCC + 0.1
2
1
pA
IOS
pA
Output voltage high (for TLV7034
only)
VOH
VOL
ILKG
VS = 5 V, VEE = 0 V, IO = 3 mA
VS = 5 V, VEE = 0 V, IO = 3 mA
4.65
4.8
250
100
V
Output voltage low
350
mV
pA
Open-drain output leakage
current (TLV7044 only)
VS = 5 V, VID = +0.1 V (output high),
VPULLUP = VCC
CMRR
PSRR
Common-mode rejection ratio
Power supply rejection ratio
VEE < VCM < VCC, VS = 5 V
73
77
dB
dB
VS = 1.8 V to 5 V, VCM = VS / 2
VS = 5 V, sourcing (for TLV7034 only)
VS = 5 V, sinking
29
ISC
ICC
Short-circuit current
mA
nA
33
Supply current / Channel
VS = 1.8 V, no load, VID = –0.1 V (Output Low)
315
750
6.12 Switching Characteristics (Quad)
Typical values are at TA = 25°C, VS = 5 V, VCM = VS / 2; CL = 15 pF, input overdrive = 100 mV (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Propagation delay time, high to-
Midpoint of input to midpoint of output,
VOD = 100 mV
tPHL
low (RP = 4.99 kΩ TLV7044
3
µs
(1)
only)
Propagation delay time, low-to high
Midpoint of input to midpoint of output,
VOD = 100 mV
tPLH
(RP = 4.99 kΩ TLV7044
3
µs
(1)
only)
tR
tF
Rise time (TLV7034 only)
Fall time
Measured from 20% to 80%
Measured from 20% to 80%
4.5
4.5
ns
ns
During power on, VCC must exceed 1.6V for tON
before the output will reflect the input..
tON
Power-up time
400
µs
(1) The lower limit for RP is 650 Ω
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6.13 Timing Diagrams
tON
VEE
VEE + 1.6V
VCC
VOH/2
VEE
OUT
Figure 1. Start-Up Time Timing Diagram (IN+ > IN–)
Figure 2. Propagation Delay Timing Diagram
NOTE
The propagation delays tpLH and tpHL include the contribution of input offset and hysteresis.
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6.14 Typical Characteristics
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
0.7
0.7
VCM = VCC /2
VCM = VCC
VCM = 0
VCM = VCC /2
VCM = VCC
VCM = 0
0.6
0.5
0.6
0.5
0.4
0.3
0.2
0.1
0
0.4
0.3
0.2
0.1
0
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
vio_
vio_
VCC = 1.8 V
VCC = 3.3 V
Figure 3. Input Offset vs Temperature
Figure 4. Input Offset vs Temperature
0.7
0.6
0.5
0.4
0.3
0.2
0.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Temp -40°C
Temp 25°C
Temp 125°C
VCM = VCC /2
VCM = VCC
VCM = 0
0
-40
0
0
-20
0
20
40 60
Temperature (°C)
80
100 120 140
0.2 0.4 0.6 0.8
1
VCM (V)
1.2 1.4 1.6 1.8
2
vio_
vio_
VCC = 5 V
VCC = 1.8 V
Figure 5. Input Offset vs Temperature
Figure 6. Input Offset Voltage vs VCM
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Temp -40°C
Temp 25°C
Temp 125°C
Temp -40°C
Temp 25°C
Temp 125°C
0
0
0
0
0.5
1
1.5
VCM (V)
2
2.5
3
3.5
0.5
1
1.5
2
2.5
VCM (V)
3
3.5
4
4.5
5
vio_
vio_
VCC = 3.3 V
VCC = 5 V
Figure 7. Input Offset Voltage vs VCM
Figure 8. Input Offset Voltage vs VCM
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Typical Characteristics (continued)
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
10
10
9
8
7
6
5
4
3
2
1
9
8
7
6
5
4
3
VCM = VCC /2
VCM = VCC
VCM = 0
Temp -40°C
Temp 25°C
Temp 125°C
2
1
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
0
0.5
1
VCM (V)
1.5
2
hyst
hyst
VCC = 1.8 V to 5 V
Figure 9. Hysteresis vs Temperature
TLV70x1
VCC = 1.8 V
TLV70x1
Figure 10. Hysteresis vs VCM
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
Temp -40°C
Temp 25°C
Temp 125°C
Temp -40°C
Temp 25°C
Temp 125°C
2
1
0
0
1
2
VCM (V)
3
4
1
2
3
4
5
VCM (V)
hyst
hyst
VCC = 3.3 V
TLV70x1
VCC = 5 V
TLV70x1
Figure 11. Hysteresis vs VCM
Figure 12. Hysteresis vs VCM
14.5
14
18
16
14
12
10
8
13.5
13
12.5
12
11.5
11
10.5
10
VCM = VCC/2
VCM = VCC
VCM = 0
9.5
9
Temp -40°C
Temp 25°C
Temp 125°C
8.5
-40
6
-0.5
-20
0
20
40 60
Temperature (°C)
80
100 120 140
0
0.5
1
1.5
2
VCM (V)
VCC = 1.8 V to 5 V
Figure 13. Hysteresis vs Temperature
TLV70x2
VCC = 1.8 V
TLV70x2
Figure 14. Hysteresis vs VCM
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Typical Characteristics (continued)
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
16
15
14
13
12
11
10
9
14
12
10
8
8
Temp -40°C
Temp 25°C
Temp 125°C
Temp -40°C
Temp 25°C
Temp 125°C
7
6
-0.5
6
-0.5
0.5
1.5
VCM (V)
2.5
3.5
0.5
1.5
2.5
VCM (V)
3.5
4.5
5.5
VCC = 3.3 V
TLV70x2
VCC = 5 V
TLV70x2
Figure 15. Hysteresis vs VCM
Figure 16. Hysteresis vs VCM
1.795
1.79
1000
100
10
1.785
1.78
1.775
1.77
1
1.765
1.76
Temp -40°C
Temp 25°C
Temp 85°C
Temp 125°C
0.1
0.01
-40
1.755
-20
0
20
40 60
Temperature (°C)
80
100 120 140
0.1
0.15
0.2
0.25
0.3
0.35
Output Source Current (mA)
0.4
0.45
0.5
voh_
tlv7
VCC = 5 V
VCC = 1.8 V
TLV703x
Figure 17. Input Bias Current vs Temperature
Figure 18. Output Voltage High vs Output Source Current
0.1
5
4.98
4.96
4.94
4.92
4.9
0.08
0.07
0.06
0.05
0.04
0.03
4.88
4.86
4.84
4.82
4.8
0.02
Temp -40°C
Temp 25°C
Temp 85°C
Temp 125°C
Temp -40°C
Temp 25°C
Temp 125°C
4.78
0
0.01
0.5
1
1.5
Output Source Current (mA)
2
2.5
3
3.5
4
4.5
5
0.1
0.2 0.3
Output Sink Current (mA)
0.4 0.5
voh_
vol_
VCC = 5 V
TLV703x
VCC = 1.8 V
Figure 19. Output Voltage High vs Output Source Current
Figure 20. Output Voltage Low vs Output Sink Current
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Typical Characteristics (continued)
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
0.5
50
40
30
20
10
VCC=3.5V
VCC=5.5V
0.3
0.2
0.1
0.07
0.05
0.03
0.02
Temp -40°C
Temp 25°C
Temp 125°C
0.01
0.007
0.005
0.1
0.2 0.3 0.40.5 0.7 1
Output Sink Current (mA)
2
3
4
5
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
vol_
nisc
VCM = VCC / 2
VCC = 5 V
Figure 21. Output Voltage Low vs Output Sink Current
Figure 22. Output Short-Circuit (Sink) Current vs
Temperature
50
40
30
20
10
0
50
Vcc=3.5V
Vcc=5.5V
40
30
20
10
Temp -40°C
Temp 25°C
Temp 125°C
-40
-20
0
20
40
60
Temperature ( °C)
80
100 120 140
1
1.5
2
2.5
3
3.5 4
VCC(V)
4.5
5
5.5
6
6.5
pisc
nisc
VCM = VCC / 2
VCM = VCC / 2
TLV703x
Figure 24. Output Short Circuit (Sink) vs VCC
Figure 23. Output Short-Circuit (Source) Current vs
Temperature
50
45
40
35
30
25
20
15
10
5
0.6
0.5
0.4
0.3
0.2
Temp -40C
Temp 25C
Temp 125C
VCC = 1V
VCC = 3V
VCC = 5V
0
1
1.5
2
2.5
3
3.5 4
Vcc (V)
4.5
5
5.5
6
6.5
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
pisc
icc_
VCM = VCC / 2
TLV703x
VCM = VCC / 2
TLV70x1
Figure 25. Output Short Circuit (Source) vs VCC
Figure 26. ICC vs Temperature
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Typical Characteristics (continued)
TA = 25°C, VCC = 5 V, VEE = 0 V, VCM = VCC/2, CL = 15 pF
0.6
0.6
0.5
0.4
0.3
0.5
0.4
0.3
0.2
Temp -40°C
Temp 25°C
Temp 125°C
0.1
0
VCC = 1.8V
VCC = 3.3V
VCC = 5.0V
0.2
-40
1
2
3
4
5
6
-20
0
20
40 60
Temperature (°C)
80
100 120 140
VCC (V)
icc_
VCM = VCC / 2
TLV70x1
VCM = VCC / 2
TLV70x2
Figure 27. ICC vs VCC
Figure 28. ICC vs Temperature
0.6
0.5
0.4
0.3
0.2
0.1
20000
10000
5000
Fall Time
Rise Time
2000
1000
500
200
100
50
20
10
5
Temp -40°C
Temp 25°C
Temp 125°C
2
0
10 2030 50 100 200 5001000
Load Capacitance (pF)
10000
100000
1.5
2.5
3.5
4.5
5.5
6.5
TLV70x2
VCC (V)
tlv7
VOD = 100 mV
TLV703x Rise only
VCM = VCC / 2
Figure 30. Rise/Fall Time vs Load Capacitance
Figure 29. ICC vs VCC
7
6
5
4
3
2
7
6
5
4
3
2
1
Temp -40°C
Temp 25°C
Temp 85°C
Temp 125°C
Temp -40°C
Temp 25°C
Temp 85°C
Temp 125°C
1
0
100
200
300
400
500
0
100
200
300
400
500
VOD (mV)
VOD (mV)
tlv7
tlv7
VCC = 3.3 V to 5 V
TLV703x
VCC = 3.3 V to 5 V
Figure 31. Propagation Delay (L-H) vs Input Overdrive
Figure 32. Propagation Delay (H-L) vs Input Overdrive
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7 Detailed Description
7.1 Overview
The TLV703x and TLV704x are nano-power comparators with push-pull and open-drain outputs. Operating from
1.6 V to 6.5 V and consuming only 315 nA, the TLV703x and TLV704x are designed for portable and industrial
applications. The TLV703x and TLV704x are available in a variety of leadless and leaded packages to offer
significant board space saving in space-challenged designs.
7.2 Functional Block Diagram
VCC
IN+
+
OUT
-
IN-
Power-on-reset
Bias
7.3 Feature Description
The TLV703x and TLV704x devices are nanoPower comparators that are capable of operating at low voltages.
The TLV703x and TLV704x feature a rail-to-rail input stage capable of operating up to 100 mV beyond the VCC
power supply rail. The TLV703x (push-pull) and TLV704x (open-drain) also feature internal hysteresis.
7.4 Device Functional Modes
The TLV703x and TLV704x have a power-on-reset (POR) circuit. While the power supply (VS) is less than the
minimum supply voltage, either upon ramp-up or ramp-down, the POR circuitry is activated.
For the TLV703x, the POR circuit holds the output low (at VEE) while activated.
For the TLV704x, the POR circuit keeps the output high impedance (logical high) while activated.
When the supply voltage is greater than, or equal to, the minimum supply voltage, the comparator output reflects
the state of the differential input (VID).
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Device Functional Modes (continued)
7.4.1 Inputs
The TLV703x and TLV704x input common-mode extends from VEE to 100 mV above VCC. The differential input
voltage (VID) can be any voltage within these limits. No phase inversion of the comparator output occurs when
the input pins exceed VCC and VEE
.
The input of TLV703x and TLV704x is fault tolerant. It maintains the same high input impedance when VCC is
unpowered or ramping up. The input can be safely driven up to the specified maximum voltage (7 V) with VCC
=
0 V or any value up to the maximum specified. The VCC is isolated from the input such that it maintains its value
even when a higher voltage is applied to the input.
The input bias current is typically 1 pA for input voltages between VCC and VEE. The comparator inputs are
protected from voltages below VEE by internal diodes connected to VEE. As the input voltage goes under VEE, the
protection diodes become forward biased and begin to conduct causing the input bias current to increase
exponentially. Input bias current typically doubles every 10°C temperature increases.
7.4.2 Internal Hysteresis
The device hysteresis transfer curve is shown in Figure 33. This curve is a function of three components: VTH
,
VOS, and VHYST
:
•
•
VTH is the actual set voltage or threshold trip voltage.
VOS is the internal offset voltage between VIN+ and VIN–. This voltage is added to VTH to form the actual trip
point at which the comparator must respond to change output states.
•
VHYST is the internal hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise
(7 mV for both TLV703x and TLV704x).
VTH + VOS - (VHYST / 2)
VTH + VOS
VTH + VOS + (VHYST / 2)
Figure 33. Hysteresis Transfer Curve
7.4.3 Output
The TLV703x features a push-pull output stage eliminating the need for an external pullup resistor. On the other
hand, the TLV704x features an open-drain output stage enabling the output logic levels to be pulled up to an
external source up to 6.5 V independent of the supply voltage.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV703x and TLV704x are nano-power comparators with reasonable response time. The comparators have
a rail-to-rail input stage that can monitor signals beyond the positive supply rail with integrated hysteresis. When
higher levels of hysteresis are required, positive feedback can be externally added. The push-pull output stage of
the TLV703x is optimal for reduced power budget applications and features no shoot-through current. When level
shifting or wire-ORing of the comparator outputs is needed, the TLV704x with its open-drain output stage is well
suited to meet the system needs. In either case, the wide operating voltage range, low quiescent current, and
small size of the TLV703x and TLV704x make these comparators excellent candidates for battery-operated and
portable, handheld designs.
8.1.1 Inverting Comparator With Hysteresis for TLV703x
The inverting comparator with hysteresis requires a three-resistor network that is referenced to the comparator
supply voltage (VCC), as shown in Figure 34. When VIN at the inverting input is less than VA, the output voltage is
high (for simplicity, assume VO switches as high as VCC). The three network resistors can be represented as R1
|| R3 in series with R2. Equation 1 defines the high-to-low trip voltage (VA1).
R2
VA1 = VCC
´
(R1 || R3) + R2
(1)
When VIN is greater than VA, the output voltage is low, very close to ground. In this case, the three network
resistors can be presented as R2 || R3 in series with R1. Use Equation 2 to define the low to high trip voltage
(VA2).
R2 || R3
VA2 = VCC
´
R1 + (R2 || R3)
(2)
(3)
Equation 3 defines the total hysteresis provided by the network.
DVA = VA1 - VA2
+VCC
+5 V
R1
1 MW
VIN
5 V
RLOAD
VA
VO
100 kW
VA2
1.67 V
VA1
3.33 V
0 V
R3
1 MW
VIN
R2
1 MW
VO High
+VCC
VO Low
+VCC
R1
VA1
R2
R3
R1
VA2
R2
R3
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Figure 34. TLV703x in an Inverting Configuration With Hysteresis
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Application Information (continued)
8.1.2 Noninverting Comparator With Hysteresis for TLV703x
A noninverting comparator with hysteresis requires a two-resistor network, as shown in Figure 35, and a voltage
reference (VREF) at the inverting input. When VIN is low, the output is also low. For the output to switch from low
to high, VIN must rise to VIN1. Use Equation 4 to calculate VIN1
VREF
.
VIN1 = R1 ´
+ VREF
R2
(4)
When VIN is high, the output is also high. For the comparator to switch back to a low state, VIN must drop to VIN2
such that VA is equal to VREF. Use Equation 5 to calculate VIN2
VREF (R1 + R2) - VCC ´ R1
.
VIN2
=
R2
(5)
(6)
The hysteresis of this circuit is the difference between VIN1 and VIN2, as shown in Equation 6.
R1
DVIN = VCC
´
R2
+VCC
+5 V
VREF
VO
+2.5 V
VA
VIN
RLOAD
R1
330 kW
R2
1 MW
VO High
+VCC
VO Low
VIN1
5 V
0 V
R2
R1
VA = VREF
R2
VO
VA = VREF
R1
VIN2
VIN1
1.675 V 3.325 V
VIN
VIN2
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Figure 35. TLV703x in a Noninverting Configuration With Hysteresis
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8.2 Typical Applications
8.2.1 Window Comparator
Window comparators are commonly used to detect undervoltage and overvoltage conditions. Figure 36 shows a
simple window comparator circuit.
3.3V
RPU
R1
UV_OV
+
Micro-
Controller
Sensor
R2
+
R3
Figure 36. TLV704x-Based Window Comparator
8.2.1.1 Design Requirements
For this design, follow these design requirements:
•
•
•
•
Alert (logic low output) when an input signal is less than 1.1 V
Alert (logic low output) when an input signal is greater than 2.2 V
Alert signal is active low
Operate from a 3.3-V power supply
8.2.1.2 Detailed Design Procedure
Configure the circuit as shown in Figure 36. Connect VCC to a 3.3-V power supply and VEE to ground. Make R1,
R2, and R3 each 10-MΩ resistors. These three resistors are used to create the positive and negative thresholds
for the window comparator (VTH+ and VTH–). With each resistor being equal, VTH+ is 2.2 V and VTH- is 1.1 V. Large
resistor values such as 10 MΩ are used to minimize power consumption. The sensor output voltage is applied to
the inverting and noninverting inputs of the two TLV704x devices. The TLV704x is used for its open-drain output
configuration. Using the TLV704x allows the two comparator outputs to be wire-ored together. The respective
comparator outputs are low when the sensor is less than 1.1 V or greater than 2.2 V. VOUT is high when the
sensor is in the range of 1.1 V to 2.2 V.
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SLVSE13F –SEPTEMBER 2017–REVISED JUNE 2020
Typical Applications (continued)
8.2.1.3 Application Curve
VIN
VTH+ = 2.2 V
VTHœ = 1.1 V
Time (usec)
VOUT
Time (usec)
50
100
150
200
Figure 37. Window Comparator Results
8.2.2 IR Receiver Analog Front End
A single TLV703x device can be used to build a complete IR receiver analog front end (AFE). The nanoamp
quiescent current and low input bias current make it possible to be powered with a coin cell battery, which could
last for years.
Vref
470 kꢀ
470 kꢀ
10M ꢀ
R4
3 V
IR LED
R2
R3
U1
+
Output to MCU
(Also to wake-up MCU)
œ
VOUT
C1
10M ꢀ
TLV7031
VIN
R1
0.01 ꢁF
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 38. IR Receiver Analog Front End Using TLV703x
8.2.2.1 Design Requirements
For this design, follow these design requirements:
•
Use a proper resistor (R1) value to generate an adequate signal amplitude applied to the inverting input of the
comparator.
•
•
The low input bias current IB (2 pA typical) ensures that a greater value of R1 to be used.
The RC constant value (R2 and C1) must support the targeted data rate (that is, 9,600 bauds) in order to
maintain a valid tripping threshold.
•
The hysteresis introduced with R3 and R4 helps to avoid spurious output toggles.
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Typical Applications (continued)
8.2.2.2 Detailed Design Procedure
The IR receiver AFE design is highly streamlined and optimized. R1 converts the IR light energy induced current
into voltage and applies to the inverting input of the comparator. The RC network of R2 and C1 establishes a
reference voltage Vref, which tracks the mean amplitude of the IR signal. The noninverting input is directly
connected to Vref through R3. R3 and R4 are used to produce a hysteresis to keep transitions free of spurious
toggles. To reduce the current drain from the coin cell battery, data transmission must be short and infrequent.
More technical details are provided in the TI TechNote Low Power Comparator for Signal Processing and Wake-
Up Circuit in Smart Meters (SNVA808).
8.2.2.3 Application Curve
1.8 V
VIN
1.2 V
4.0 V
VOUT
0.0 V
1.61 V
VREF
1.58 V
0.0
200.0 u
400.0 u
Time
600.0 u
800.0 u
Figure 39. IR Receiver AFE Waveforms
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SLVSE13F –SEPTEMBER 2017–REVISED JUNE 2020
Typical Applications (continued)
8.2.3 Square-Wave Oscillator
A square-wave oscillator can be used as low-cost timing reference or system supervisory clock source.
Figure 40. Square-Wave Oscillator
8.2.3.1 Design Requirements
The square-wave period is determined by the RC time constant of the capacitor and resistor. The maximum
frequency is limited by the propagation delay of the device and the capacitance load at the output. The low input
bias current allows a lower capacitor value and larger resistor value combination for a given oscillator frequency,
which may help reduce BOM cost and board space.
8.2.3.2 Detailed Design Procedure
The oscillation frequency is determined by the resistor and capacitor values. The following section provides
details to calculate these component values.
Figure 41. Square-Wave Oscillator Timing Thresholds
First consider the output of figure Figure 40 is high, which indicates the inverted input VC is lower than the
noninverting input (VA). This causes the C1 to be charged through R4, and the voltage VC increases until it is
equal to the noninverting input. The value of VA at the point is calculated by Equation 7.
VCCìR2
R2 + R1IIR3
VA1
=
(7)
If R1 = R2= R3, then VA1 = 2 VCC/ 3
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Typical Applications (continued)
At this time the comparator output trips pulling down the output to the negative rail. The value of VA at this point
is calculated by Equation 8.
VCC(R2IIR3 )
VA2
=
R1+R2IIR3
If R1 = R2 = R3, then VA2 = VCC/3
The C1 now discharges though the R4, and the voltage VCC decreases until it reaches VA2. At this point, the
(8)
output switches back to the starting state. The oscillation period equals the time duration from 2 VCC / 3 to VCC
/
3 then back to 2 VCC / 3, which is given by R4C1 × ln2 for each trip. Therefore, the total time duration is
calculated as 2 R4C1 × ln2. The oscillation frequency can be obtained by Equation 9:
f = 1/ 2 R4ìC1ìIn2
(9)
8.2.3.3 Application Curve
Figure 42 shows the simulated results of an oscillator using the following component values:
•
•
•
•
R1 = R2 = R3 = R4 = 100 kΩ
C1 = 100 pF, CL = 20 pF
V+ = 5 V, V– = GND
Cstray (not shown) from VA to GND = 10 pF
Figure 42. Square-Wave Oscillator Output Waveform
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SLVSE13F –SEPTEMBER 2017–REVISED JUNE 2020
Typical Applications (continued)
8.2.4 Quadrature Rotary Encoder
A quadrature encoder for rotary motors/shafts utilizing a Tunneling Magnetoresitance (TMR) Rotation Sensor can
track the position of the motor shaft even when power is turned off, while the TLV7032 provides additional
hysteresis to prevent unwanted output toggling between quadrants. The TLV7032 can be used with other
sensing techniques as well, such as optical, capacitive, or inductive.
Figure 43. Quadrant Encoder Detector
8.2.4.1 Design Requirements
TMR Rotation Sensors general have two digital, binary outputs that are 90 degrees out of phase. The TLV7032
can be used to provide additional hysteresis to ensure there isn't any unwanted toggling of the output when the
sensors are between the transition points of two quadrants. The TLV7032 already provides 10mV of typical
internal hysteresis. By dividing down the output voltage from the rotation sensor using a voltage divider, the
internal hysteresis will be scaled up by the same voltage divider ratio.
Figure 44. Voltage Divider Equation
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Typical Applications (continued)
8.2.4.2 Detailed Design Procedure
First, choose a target range of hysteresis to achieve. For this design example, 50mV of hysteresis will be the
target. Since the TLV7032 already has 10mV (typ) of internal hysteresis, the voltage output from the TMR
Rotation Sensor should be scaled down by a factor of 5. This way, the 10mV of internal hysteresis gets scaled
up by a factor of 5, resulting in 50mV of hysteresis. The minimum output HIGH level for the TMR Rotation
Sensor used in Figure 47 is 5.25 V. Since 5.25V will be the minimum output high value, it can be used to
substitute VIN from the Voltage Divider Equation in Figure 48. Since the voltage from the TMR rotation sensor
needs to be scaled down by a factor of 5, the equation in Figure 48 can be rewritten as:
The above equation can be solved for using standard resistor values, where R1 = 100kΩ, and R2 = 24.9kΩ. The
minimum voltage seen at the noninverting pins of the comparator when the output is HIGH will be 1.05V. To
make the device transition at 50% output high level, the inverting pins of the TLV7032 should be tied to a 0.525V
reference.
8.2.4.3 Application Curve
Figure 49 shows the TLV7032 achieving approximately 50mV of hysteresis using the following component
values:
•
•
•
R1 = 100kΩ
R2 = 24.9kΩ
VREF (IN-) = 0.525V
Figure 45. DC Input Voltage Sweep
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SLVSE13F –SEPTEMBER 2017–REVISED JUNE 2020
9 Power Supply Recommendations
The TLV703x and TLV704x have a recommended operating voltage range (VS) of 1.6 V to 6.5 V. VS is defined
as VCC – VEE. Therefore, the supply voltages used to create VS can be single-ended or bipolar. For example,
single-ended supply voltages of 5 V and 0 V and bipolar supply voltages of +2.5 V and –2.5 V create comparable
operating voltages for VS. However, when bipolar supply voltages are used, it is important to realize that the logic
low level of the comparator output is referenced to VEE
.
Output capacitive loading and output toggle rate will cause the average supply current to rise over the quiescent
current.
10 Layout
10.1 Layout Guidelines
To reduce PCB fabrication cost and improve reliability, TI recommends using a 4-mil via at the center pad
connected to the ground trace or plane on the bottom layer.
TI recommends a power-supply bypass capacitor of 100 nF when supply output impedance is high, supply traces
are long, or when excessive noise is expected on the supply lines. Bypass capacitors are also recommended
when the comparator output drives a long trace or is required to drive a capacitive load. Due to the fast rising
and falling edge rates and high-output sink and source capability of the TLV703x and TLV704x output stages,
higher than normal quiescent current can be drawn from the power supply. Under this circumstance, the system
would benefit from a bypass capacitor across the supply pins.
10.2 Layout Example
Figure 46. Layout Example
The application report Designing and Manufacturing With TI's X2SON Packages (SCEA055) helps PCB
designers to achieve optimal designs.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Module
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TLV70x1
device family. The TLV7011 Micro-Power Comparator Dip Adaptor Evaluation Module can be requested at the
Texas Instruments website through the product folder or purchased directly from the TI eStore.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
•
•
Designing and Manufacturing With TI's X2SON Packages (SCEA055)
Low Power Comparator for Signal Processing and Wake-Up Circuit in Smart Meters (SNVA808)
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
TLV7031
TLV7032
TLV7041
TLV7042
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.6 Trademarks
E2E is a trademark of Texas Instruments.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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SLVSE13F –SEPTEMBER 2017–REVISED JUNE 2020
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Sep-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTLV7034PWR
PTLV7044PWR
TLV7031DBVR
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
SOT-23
PW
PW
14
14
5
2000
2000
3000
TBD
TBD
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
Call TI
DBV
Green (RoHS
& no Sb/Br)
NIPDAUAG
Level-1-260C-UNLIM
1IE2
19P
19P
7K
TLV7031DCKR
TLV7031DCKT
TLV7031DPWR
TLV7032DDFR
TLV7032DGKR
ACTIVE
ACTIVE
ACTIVE
SC70
SC70
DCK
DCK
DPW
DDF
DGK
5
5
5
8
8
3000
250
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Green (RoHS
& no Sb/Br)
X2SON
3000
3000
2500
Green (RoHS
& no Sb/Br)
NIPDAU
ACTIVE SOT-23-THIN
Green (RoHS
& no Sb/Br)
NIPDAU
22KF
7032
ACTIVE
VSSOP
Green (RoHS
& no Sb/Br)
NIPDAUAG
TLV7034PWR
TLV7041DBVR
PREVIEW
ACTIVE
TSSOP
SOT-23
PW
14
5
2000
3000
TBD
Call TI
Call TI
-40 to 125
-40 to 125
DBV
Green (RoHS
& no Sb/Br)
NIPDAUAG
Level-1-260C-UNLIM
1IF2
19Q
19Q
7L
TLV7041DCKR
TLV7041DCKT
TLV7041DPWR
TLV7042DDFR
TLV7042DGKR
TLV7044PWR
ACTIVE
ACTIVE
ACTIVE
SC70
SC70
DCK
DCK
DPW
DDF
DGK
PW
5
5
3000
250
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAUAG
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Green (RoHS
& no Sb/Br)
X2SON
5
3000
3000
2500
2000
Green (RoHS
& no Sb/Br)
ACTIVE SOT-23-THIN
8
Green (RoHS
& no Sb/Br)
22LF
7042
ACTIVE
VSSOP
TSSOP
8
Green (RoHS
& no Sb/Br)
PREVIEW
14
TBD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Sep-2020
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV7031, TLV7041 :
Automotive: TLV7031-Q1, TLV7041-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Aug-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV7031DBVR
TLV7031DCKR
TLV7031DCKT
TLV7031DPWR
TLV7032DDFR
SOT-23
SC70
DBV
DCK
DCK
DPW
DDF
5
5
5
5
8
3000
3000
250
180.0
178.0
178.0
178.0
180.0
8.4
9.0
9.0
8.4
8.4
3.23
2.4
3.17
2.5
1.37
1.2
1.2
0.5
1.4
4.0
4.0
4.0
2.0
4.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q2
Q3
SC70
2.4
2.5
X2SON
3000
3000
0.91
3.2
0.91
3.2
SOT-
23-THIN
TLV7032DGKR
TLV7041DBVR
TLV7041DCKR
TLV7041DCKT
TLV7041DPWR
TLV7042DDFR
VSSOP
SOT-23
SC70
DGK
DBV
DCK
DCK
DPW
DDF
8
5
5
5
5
8
2500
3000
3000
250
330.0
180.0
178.0
178.0
178.0
180.0
12.4
8.4
9.0
9.0
8.4
8.4
5.3
3.23
2.4
3.4
3.17
2.5
1.4
1.37
1.2
1.2
0.5
1.4
8.0
4.0
4.0
4.0
2.0
4.0
12.0
8.0
8.0
8.0
8.0
8.0
Q1
Q3
Q3
Q3
Q2
Q3
SC70
2.4
2.5
X2SON
3000
3000
0.91
3.2
0.91
3.2
SOT-
23-THIN
TLV7042DGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Aug-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV7031DBVR
TLV7031DCKR
TLV7031DCKT
TLV7031DPWR
TLV7032DDFR
TLV7032DGKR
TLV7041DBVR
TLV7041DCKR
TLV7041DCKT
TLV7041DPWR
TLV7042DDFR
TLV7042DGKR
SOT-23
SC70
DBV
DCK
DCK
DPW
DDF
DGK
DBV
DCK
DCK
DPW
DDF
DGK
5
5
5
5
8
8
5
5
5
5
8
8
3000
3000
250
183.0
190.0
190.0
205.0
210.0
364.0
183.0
190.0
190.0
205.0
210.0
364.0
183.0
190.0
190.0
200.0
185.0
364.0
183.0
190.0
190.0
200.0
185.0
364.0
20.0
30.0
30.0
33.0
35.0
27.0
20.0
30.0
30.0
33.0
35.0
27.0
SC70
X2SON
SOT-23-THIN
VSSOP
SOT-23
SC70
3000
3000
2500
3000
3000
250
SC70
X2SON
SOT-23-THIN
VSSOP
3000
3000
2500
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DPW0005A
X2SON - 0.4 mm max height
S
C
A
L
E
1
2
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
0.85
0.75
A
B
PIN 1 INDEX AREA
0.85
0.75
0.4 MAX
C
SEATING PLANE
NOTE 3
(0.1)
0.05
0.00
(0.25)
4X (0.05)
0.25 0.1
2
1
4
5
NOTE 3
2X
0.48
3
2X (0.26)
0.27
0.17
4X
0.27
0.17
0.1 C A B
0.05 C
(0.06)
3X
0.32
0.23
4223102/B 09/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The size and shape of this feature may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.78)
(
0.1)
SYMM
4X (0.42)
VIA
0.05 MIN
ALL AROUND
TYP
1
5
4X (0.22)
SYMM
4X (0.26)
(0.48)
3
2
4
(R0.05) TYP
SOLDER MASK
OPENING, TYP
4X (0.06)
(
0.25)
(0.21) TYP
EXPOSED METAL
CLEARANCE
METAL UNDER
SOLDER MASK
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:60X
4223102/B 09/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.42)
4X (0.06)
5
1
4X (0.22)
SYMM
(
0.24)
4X (0.26)
(0.21)
(0.48)
TYP
SOLDER MASK
EDGE
3
2
4
(R0.05) TYP
SYMM
(0.78)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
92% PRINTED SOLDER COVERAGE BY AREA
SCALE:100X
4223102/B 09/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.4
0.2
8X
0.1
C A
B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/B 11/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/B 11/2015
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/B 11/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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