TLV7103318QDSERQ1 [TI]
具有使能功能的汽车类、200mA、高 PSRR、双通道低压降稳压器 | DSE | 6 | -40 to 125;
| 型号： | TLV7103318QDSERQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有使能功能的汽车类、200mA、高 PSRR、双通道低压降稳压器 | DSE | 6 | -40 to 125 光电二极管 输出元件 稳压器 调节器 |
| 文件： | 总27页 (文件大小：2159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV7103318-Q1
TLV7101828-Q1
www.ti.com
SBVS202A –MARCH 2013–REVISED MARCH 2013
Dual, 200-mA, Low-IQ
Low-Dropout Regulator for Portable Devices
Check for Samples: TLV7103318-Q1 , TLV7101828-Q1
1
FEATURES
APPLICATIONS
•
•
Qualified for Automotive Applications
•
•
•
Automotive Applications
AEC-Q100 Qualified With the Following
Results:
Wireless Handsets, Smart Phones, PDAs
MP3 Players and Other Handheld Products
–
Device Temperature Grade 1: –40°C to
125°C Ambient Operating Temperature
Range
DESCRIPTION
The TLV7103318-Q1 and TLV7101828-Q1 family of
dual, low-dropout (LDO) linear regulators are low
quiescent current devices with excellent line and load
transient performance. These LDOs are designed for
power-sensitive applications. These devices provide
a typical accuracy of 2% over temperature.
–
–
Device HBM ESD Classification Level H2
Device CDM ESD Classification Level C4B
•
Very Low Dropout:
–
–
–
150 mV at IOUT = 200 mA and VOUT = 2.8 V
75 mV at IOUT = 100 mA and VOUT = 2.8 V
40 mV at IOUT = 50 mA and VOUT = 2.8 V
The TLV7103318-Q1 and TLV7101828-Q1 family are
available in a 1,5-mm × 1,5-mm SON-6 package, and
are ideal for handheld applications.
TLV7103318-Q1
TLV7101828-Q1
•
•
•
2% Accuracy Over Temperature
Low IQ of 35 μA per Regulator
1,5-mm ´ 1,5-mm SON-6
(TOP VIEW)
Multiple Fixed-Output Voltage Combinations
Possible from 1.2 V to 4.8 V
EN1
IN
1
2
3
6
5
4
OUT1
OUT2
GND
•
•
•
•
High PSRR: 70 dB at 1kHz
Stable With Effective Capacitance of 0.1 μF(1)
EN2
Overcurrent and Thermal Protection
Dedicated VREF for Each Output Minimizes
Crosstalk
Figure 1. Typical Application Circuit
•
(1)
Available in 1.5mm × 1.5mm SON-6 Package
VIN
VOUT1
IN
OUT1
OUT2
See the Input and Output Capacitor Requirements in the
Application Information section
VOUT2
COUT2
EN1
EN2
COUT1
ON
ON
CIN
1mF
Ceramic
1mF
OFF
OFF
GND
Ceramic
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TLV7103318-Q1
TLV7101828-Q1
SBVS202A –MARCH 2013–REVISED MARCH 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DEVICE DETAILS
(1)
PRODUCT
VOUT
TLV710xxyyqwwwz
XX is nominal output voltage of channel 1 (for example 18 = 1.8 V).
YY is nominal output voltage of channel 2 (for example 28 = 2.8V).
Q is optional. Use "U" for devices with EN pin pull-up resistor, and "D" for devices with EN
pin pull-down resistor.
WWW is package designator.
Z is package quantity. Use "R" for reel (3000 pieces), and "T" for tape (250 pieces).
(1) Output voltages from 1.2V to 4.8V in 50mV increments are available through the use of innovative factory OTP programming; minimum
order quantities may apply. Contact factory for details and availability.
ORDERING INFORMATION(1)
ORDERABLE PART NUMBER
TLV7103318QDSERQ1
TA
PACKAGE(2)
TOP-SIDE MARKING
ZD
CP
–40°C to 125°C
WSON-DSE Reel of 3000
TLV7101828QDSERQ1
(1) For the most-current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS(1)
At TA = –40°C to 125°C (unless otherwise noted).
VALUE
MIN
–0.3
–0.3
–0.3
MAX
UNIT
V
IN
6
VIN 0.3
6
Voltage(2)
EN
V
OUT
OUT
V
Current
Internally limited
Indefinite
–40
A
Output short-circuit duration
s
Operating ambient, TA
125
150
150
2
°C
°C
°C
kV
Temperature
Junction, TJ
Storage, Tstg
–55
Human-Body Model (HBM) AEC-Q100 Classification Level H2
Electrostatic Discharge (ESD) rating
Charged-Device Model (CDM) AEC-Q100 Classification Level
C4B
750
V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages with respect to ground.
2
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SBVS202A –MARCH 2013–REVISED MARCH 2013
THERMAL INFORMATION
TLV7103318-Q1, TLV7101828-Q1
THERMAL METRIC(1)
DSE
6 PINS
190.5
94.9
UNIT
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJCtop
θJB
149.3
6.4
ψJT
ψJB
152.8
N/A
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
At TA = –40°C to 125ºC, VIN = VOUT(TYP) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA, VEN1 = VEN2 = 0.9 V, and COUT1
=
COUT2 = 1 μF, unless otherwise noted.
TLV710xxx8-Q1
PARAMETER
Input voltage range
Output voltage range
DC output accuracy
Line regulation
TEST CONDITIONS
MIN
2
TYP
MAX
5.5
4.8
2
UNIT
V
VIN
VO
1.2
–2
V
VOUT
–40°C ≤ TA ≤ 125°C
%
ΔVO/ΔVIN
ΔVO/ΔIOUT
VOUT(NOM) + 0.5 V ≤ VIN
0 mA ≤ IOUT ≤ 200 mA
≤
1
5
5
mV
mV
Load regulation
15
VIN = 0.98 V × VOUT(NOM), IOUT = 200 mA,
2V ≤ VOUT < 2.4V
200
175
150
140
285
250
215
mV
mV
mV
mV
VIN = 0.98 V × VOUT(NOM), IOUT = 200 mA,
2.4 V ≤ VOUT < 2.8 V
VDO
Dropout voltage
VIN = 0.98 V × VOUT(NOM), IOUT = 200 mA,
2.8 V ≤ VOUT < 3.3 V
VIN = 0.98 V × VOUT(NOM), IOUT = 200 mA,
3.3 V ≤ VOUT ≤ 4.8 V
200
550
ICL
Output current limit
Quiescent current
VOUT = 0.9V × VOUT(NOM)
VEN1 = high, VEN2 = low, IOUT1 = 0 mA
VEN1 = low, VEN2 = high, IOUT2 = 0 mA
VEN1 = high, VEN2 = high, IOUT = 0 mA
IOUT1 = IOUT2 = 200mA
220
350
35
mA
μA
μA
µA
µA
μA
dB
dB
dB
dB
dB
IQ
35
70
110
4
IGND
Ground pin current
Shutdown current
360
2.5
80
ISHUTDOWN
VEN1,2 ≤ 0.4 V, 2 V ≤ VIN ≤ 4.5 V
f = 10 Hz
f = 100 Hz
75
PSRR
Power-supply rejection ratio
VOUT = 1.8 V
f = 1k Hz
70
f = 10 kHz
f = 100 kHz
70
50
VN
Output noise voltage
Startup time(1)
BW = 100 Hz to 100 kHz, VOUT = 1.8 V
48
μVRMS
μs
tSTR
COUT = 1 μF, IOUT = 200 mA
100
(1) Startup time = time from EN assertion to 0.98 x VOUT(NOM)
.
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SBVS202A –MARCH 2013–REVISED MARCH 2013
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RECOMMENDED OPERATING CONDITIONS (continued)
At TA = –40°C to 125ºC, VIN = VOUT(TYP) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA, VEN1 = VEN2 = 0.9 V, and COUT1
=
COUT2 = 1 μF, unless otherwise noted.
TLV710xxx8-Q1
PARAMETER
TEST CONDITIONS
MIN
0.9
0
TYP
MAX
VIN
UNIT
V
VHI
Enable high (enabled)
Enable low (shutdown)
VLO
0.4
V
TLV7103318-Q1, TLV7101828-Q1
0.04
6
μA
μA
V
IEN
Enable pin current, enabled
TLV710-D
VIN rising
UVLO
TA
Undervoltage lockout
1.9
Operating ambient temperature
–40
125
°C
°C
°C
Shutdown, temperature increasing
Reset, temperature decreasing
165
145
TSD
Thermal shutdown temperature
4
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TLV7103318-Q1
TLV7101828-Q1
www.ti.com
SBVS202A –MARCH 2013–REVISED MARCH 2013
FUNCTIONAL BLOCK DIAGRAM
120W
Bandgap
TLV710-D
only
UVLO
Current
Limit
Thermal
Shutdown
OUT1
OUT2
Enable
and
EN1
EN2
Power
Control
Logic
150kW
Thermal
Shutdown
Current
Limit
IN
UVLO
TLV710-D
only
Bandgap
120W
GND
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SBVS202A –MARCH 2013–REVISED MARCH 2013
www.ti.com
PIN CONFIGURATION
DSE PACKAGE
1.5mm x 1.5mm SON-6
(TOP VIEW)
EN1
IN
1
2
3
6
5
4
OUT1
OUT2
GND
EN2
PIN DESCRIPTIONS
NAME
PIN NO.
DESCRIPTION
Enable pin for regulator 1. Driving EN1 over 0.9V turns on regulator 1. Driving EN below 0.4V puts regulator
1 into shutdown mode.
EN1
1
Input pin. A small capacitor is needed from this pin to ground to assure stability. See Input and Output
Capacitor Requirements in the Application Information section for more details.
IN
2
Enable pin for regulator 2. Driving EN2 over 0.9V turns on regulator 2. Driving EN2 below 0.4V puts
regulator2 into shutdown mode.
EN2
3
4
GND
Ground pin.
Regulated output voltage pin. A small 1μF ceramic capacitor is needed from this pin to ground to assure
stability. See Input and Output Capacitor Requirements in the Application Information section for more
details.
OUT2
OUT1
5
6
Regulated output voltage pin. A small 1μF ceramic capacitor is needed from this pin to ground to assure
stability. See Input and Output Capacitor Requirements in the Application Information section for more
details.
6
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TLV7103318-Q1
TLV7101828-Q1
www.ti.com
SBVS202A –MARCH 2013–REVISED MARCH 2013
TYPICAL CHARACTERISTICS
Over operating temperature range of TA = –40°C to 125°C, VEN1 = VEN2 = VIN, CIN = 1 μF, COUT1 = 1 μF, and COUT2 = 1 μF, unless otherwise
noted. Typical values are at TA = 25°C.
LINE REGULATION: VOUT1
(TLV7101828-Q1)
LINE REGULATION: VOUT2
(TLV7101828-Q1)
1.90
1.88
1.86
1.84
1.82
1.80
1.78
1.76
1.74
1.72
1.70
2.90
2.88
2.86
2.84
2.82
2.80
2.78
2.76
2.74
2.72
2.70
IOUT1 = 10mA
IOUT2 = 10mA
IOUT1 = 10mA
IOUT2 = 10mA
+125°C
+85°C
+25°C
-40°C
+125°C
+85°C
+25°C
-40°C
2.1
2.6
3.1
3.6
4.1
4.6
5.1
5.6
3.1
3.6
4.1
4.6
5.1
5.6
VIN (V)
VIN (V)
Figure 2.
Figure 3.
LINE REGULATION: VOUT1
(TLV7101828-Q1)
LINE REGULATION: VOUT2
(TLV7101828-Q1)
1.90
1.88
1.86
1.84
1.82
1.80
1.78
1.76
1.74
1.72
1.70
2.90
2.88
2.86
2.84
2.82
2.80
2.78
2.76
2.74
2.72
2.70
IOUT1 = 200mA
IOUT2 = 0mA
IOUT1 = 0mA
IOUT2 = 200mA
+125°C
+85°C
+25°C
-40°C
+125°C
+85°C
+25°C
-40°C
2.1
2.6
3.1
3.6
4.1
4.6
5.1
5.6
3.1
3.6
4.1
4.6
5.1
5.6
VIN (V)
VIN (V)
Figure 4.
Figure 5.
LINE REGULATION: VOUT1
(TLV7103333)
LINE REGULATION: VOUT2
(TLV7103333)
3.40
3.38
3.36
3.34
3.32
3.30
3.28
3.26
3.24
3.22
3.20
3.40
3.38
3.36
3.34
3.32
3.30
3.28
3.26
3.24
3.22
3.20
IOUT1 = 10mA
IOUT2 = 10mA
IOUT1 = 10mA
IOUT2 = 10mA
+125°C
+85°C
+25°C
-40°C
+125°C
+85°C
+25°C
-40°C
3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
VIN (V)
3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
VIN (V)
Figure 6.
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
Over operating temperature range of TA = –40°C to 125°C, VEN1 = VEN2 = VIN, CIN = 1 μF, COUT1 = 1 μF, and COUT2 = 1 μF,
unless otherwise noted. Typical values are at TA = 25°C.
LINE REGULATION: VOUT1
LINE REGULATION: VOUT2
(TLV7103333)
(TLV7103333)
3.40
3.38
3.36
3.34
3.32
3.30
3.28
3.26
3.24
3.22
3.20
3.40
3.38
3.36
3.34
3.32
3.30
3.28
3.26
3.24
3.22
3.20
IOUT1 = 200mA
IOUT1 = 0mA
IOUT2 = 0mA
IOUT2 = 200mA
+125°C
+85°C
+25°C
-40°C
+125°C
+85°C
+25°C
-40°C
3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
VIN (V)
3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
VIN (V)
Figure 8.
Figure 9.
LOAD REGULATION: VOUT1
(TLV7101828-Q1)
LOAD REGULATION: VOUT2
(TLV7101828-Q1)
1.90
1.88
1.86
1.84
1.82
1.80
1.78
1.76
1.74
1.72
1.70
2.90
2.88
2.86
2.84
2.82
2.80
2.78
2.76
2.74
2.72
2.70
VIN = 3.3V
VIN = 3.3V
+125°C
+85°C
+25°C
-40°C
+125°C
+85°C
+25°C
-40°C
0
20
40
60
80 100 120 140 160 180 200
IOUT (mA)
0
20
40
60
80 100 120 140 160 180 200
IOUT (mA)
Figure 10.
Figure 11.
LOAD REGULATION: VOUT1
(TLV7103333)
LOAD REGULATION: VOUT2
(TLV7103333)
3.40
3.38
3.36
3.34
3.32
3.30
3.28
3.26
3.24
3.22
3.20
3.40
3.38
3.36
3.34
3.32
3.30
3.28
3.26
3.24
3.22
3.20
VIN = 3.8V
VIN = 3.8V
+125°C
+85°C
+25°C
-40°C
+125°C
+85°C
+25°C
-40°C
0
20
40
60
80 100 120 140 160 180 200
IOUT (mA)
0
20
40
60
80 100 120 140 160 180 200
IOUT (mA)
Figure 12.
Figure 13.
8
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SBVS202A –MARCH 2013–REVISED MARCH 2013
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range of TA = –40°C to 125°C, VEN1 = VEN2 = VIN, CIN = 1 μF, COUT1 = 1 μF, and COUT2 = 1 μF,
unless otherwise noted. Typical values are at TA = 25°C.
DROPOUT VOLTAGE
versus INPUT VOLTAGE
DROPOUT VOLTAGE
versus INPUT VOLTAGE
70
60
50
40
30
20
10
0
120
100
80
60
40
20
0
VOUT1 = VOUT2 = 4.8V
VOUT1 = VOUT2 = 4.8V
IOUT = 50mA
IOUT = 100mA
+125°C
+85°C
+25°C
-40°C
+125°C
+85°C
+25°C
-40°C
2.0
2.4
2.8
3.2
3.6
4.0
4.4
4.8
2.0
2.4
2.8
3.2
3.6
4.0
4.4
4.8
VIN (V)
VIN (V)
Figure 14.
Figure 15.
DROPOUT VOLTAGE
versus INPUT VOLTAGE
DROPOUT VOLTAGE
versus INPUT VOLTAGE
180
160
140
120
100
80
250
200
150
100
50
VOUT1 = VOUT2 = 4.8V
IOUT = 200mA
VOUT1 = VOUT2 = 4.8V
IOUT = 150mA
60
+125°C
+85°C
+25°C
-40°C
+125°C
+85°C
+25°C
-40°C
40
20
0
0
2.0
2.4
2.8
3.2
3.6
4.0
4.4
4.8
2.0
2.4
2.8
3.2
3.6
4.0
4.4
4.8
VIN (V)
VIN (V)
Figure 16.
Figure 17.
DROPOUT VOLTAGE versus OUTPUT CURRENT:
DROPOUT VOLTAGE versus OUTPUT CURRENT: VOUT2
VOUT1/VOUT2
(TLV7101828-Q1)
(TLV7103333)
200
180
160
140
120
100
80
180
160
140
120
100
80
60
60
+125°C
+125°C
+85°C
+25°C
-40°C
40
+85°C
+25°C
-40°C
40
20
0
20
0
0
20
40
60
80 100 120 140 160 180 200
IOUT (mA)
0
20
40
60
80 100 120 140 160 180 200
IOUT (mA)
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
Over operating temperature range of TA = –40°C to 125°C, VEN1 = VEN2 = VIN, CIN = 1 μF, COUT1 = 1 μF, and COUT2 = 1 μF,
unless otherwise noted. Typical values are at TA = 25°C.
OUTPUT VOLTAGE versus TEMPERATURE: VOUT1
OUTPUT VOLTAGE versus TEMPERATURE: VOUT2
(TLV7101828-Q1)
(TLV7101828-Q1)
1.90
1.88
1.86
1.84
1.82
1.80
1.78
1.76
1.74
1.72
1.70
2.90
2.88
2.86
2.84
2.82
2.80
2.78
2.76
2.74
2.72
2.70
VIN = 3.3V
VIN = 3.3V
10mA
10mA
150mA
200mA
150mA
200mA
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Junction Temperature (°C)
Figure 20.
Figure 21.
OUTPUT VOLTAGE versus TEMPERATURE: VOUT1
(TLV7103333)
OUTPUT VOLTAGE versus TEMPERATURE: VOUT2
(TLV7103333)
3.40
3.38
3.36
3.34
3.32
3.30
3.28
3.26
3.24
3.22
3.20
3.40
3.38
3.36
3.34
3.32
3.30
3.28
3.26
3.24
3.22
3.20
VIN = 3.8V
VIN = 3.8V
10mA
10mA
150mA
200mA
150mA
200mA
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
Junction Temperature (°C)
Figure 22.
Figure 23.
GROUND PIN CURRENT versus INPUT VOLTAGE: IQ1
(TLV7101828)
GROUND PIN CURRENT versus INPUT VOLTAGE: IQ2
(TLV7101828)
50
50
VIN = 3.3V
45
40
35
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
+125°C
+85°C
+25°C
-40°C
+125°C
+85°C
+25°C
-40°C
0
0
2.1
2.6
3.1
3.6
4.1
4.6
5.1
5.6
3.1
3.6
4.1
4.6
5.1
5.6
VIN (V)
VIN (V)
Figure 24.
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
Over operating temperature range of TA = –40°C to 125°C, VEN1 = VEN2 = VIN, CIN = 1 μF, COUT1 = 1 μF, and COUT2 = 1 μF,
unless otherwise noted. Typical values are at TA = 25°C.
GROUND PIN CURRENT versus INPUT VOLTAGE: IQ1
GROUND PIN CURRENT versus INPUT VOLTAGE: IQ2
(TLV7103333)
(TLV7103333)
50
50
45
40
35
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
+125°C
+85°C
+25°C
-40°C
+125°C
+85°C
+25°C
-40°C
0
0
3.6
4.0
4.4
4.8
5.2
5.6
3.6
4.0
4.4
4.8
5.2
5.6
VIN (V)
VIN (V)
Figure 26.
Figure 27.
GROUND PIN CURRENT versus LOAD: IQ1
(TLV7101828)
GROUND PIN CURRENT versus LOAD: IQ2
(TLV7103333)
350
300
250
200
150
100
50
350
300
250
200
150
100
50
VIN = 3.3V
VIN = 3.8V
+125°C
+85°C
+25°C
-40°C
+125°C
+85°C
+25°C
-40°C
0
0
0
20
40
60
80 100 120 140 160 180 200
IOUT (mA)
0
20
40
60
80 100 120 140 160 180 200
IOUT (mA)
Figure 28.
Figure 29.
SHUTDOWN CURRENT versus INPUT VOLTAGE
(TLV7101828)
SHUTDOWN CURRENT versus INPUT VOLTAGE
(TLV7103333)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
5
+125°C
+85°C
+25°C
-40°C
+125°C
+85°C
+25°C
-40°C
0
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
VIN (V)
Figure 30.
Figure 31.
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TYPICAL CHARACTERISTICS (continued)
Over operating temperature range of TA = –40°C to 125°C, VEN1 = VEN2 = VIN, CIN = 1 μF, COUT1 = 1 μF, and COUT2 = 1 μF,
unless otherwise noted. Typical values are at TA = 25°C.
CURRENT LIMIT versus INPUT VOLTAGE: ICL1
CURRENT LIMIT versus INPUT VOLTAGE: ICL2
(TLV7101828)
(TLV7101828)
500
480
460
440
420
400
380
360
340
320
300
500
480
460
440
420
400
380
360
340
320
300
+125°C
+85°C
+25°C
-40°C
+125°C
+85°C
+25°C
-40°C
2.1
2.6
3.1
3.6
4.1
4.6
5.1
5.6
3.1
3.6
4.1
4.6
5.1
5.6
VIN (V)
VIN (V)
Figure 32.
Figure 33.
CURRENT LIMIT versus INPUT VOLTAGE: ICL1
(TLV7103333)
CURRENT LIMIT versus INPUT VOLTAGE: ICL2
(TLV7103333)
500
480
460
440
420
400
380
360
340
320
300
500
480
460
440
420
400
380
360
340
320
300
+125°C
+85°C
+25°C
-40°C
+125°C
+85°C
+25°C
-40°C
3.6
4.0
4.4
4.8
5.2
5.6
3.6
4.0
4.4
4.8
5.2
5.6
VIN (V)
VIN (V)
Figure 34.
Figure 35.
POWER-SUPPLY RIPPLE REJECTION versus FREQUENCY
(TLV7101828)
100
POWER-SUPPLY RIPPLE REJECTION versus FREQUENCY
(TLV7103333)
100
IOUT2 = 30mA
IOUT1 = 30mA
IOUT1 = 30mA
VIN = 3.8V
90
90
80
70
60
50
40
30
20
10
0
VIN = 3.3V
IOUT2 = 30mA
VOUT = 2.8V
VOUT = 3.3V
80
70
60
50
40
30
20
10
0
IOUT2 = 150mA
IOUT2 = 150mA
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 36.
Figure 37.
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TYPICAL CHARACTERISTICS (continued)
Over operating temperature range of TA = –40°C to 125°C, VEN1 = VEN2 = VIN, CIN = 1 μF, COUT1 = 1 μF, and COUT2 = 1 μF,
unless otherwise noted. Typical values are at TA = 25°C.
OUTPUT SPECTRAL NOISE DENSITY
versus FREQUENCY (TLV7101828)
OUTPUT SPECTRAL NOISE DENSITY
versus FREQUENCY (TLV7103333)
10
1
10
1
VIN = 3.3V
VIN = 3.8V
VOUT2 = 2.8V
IOUT2 = 30mA
VOUT2 = 3.3V
IOUT2 = 30mA
0.1
0.1
0.01
0.001
0.01
0.001
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 38.
Figure 39.
LINE TRANSIENT RESPONSE
VOUT1 = 1.2 V, VOUT2 = 1.2 V
LINE TRANSIENT RESPONSE
VOUT1 = 1.2V, VOUT2 = 1.2V
Slew Rate = 1V/ms
Slew Rate = 1V/ms
3.0V
5.5V
IOUT = 30mA
IOUT = 30mA
1V/div
VIN
VIN
VOUT1
VOUT2
2.0V
2V/div
2.0V
5mV/div
VOUT1
5mV/div
5mV/div
5mV/div
VOUT2
Time (200ms/div)
Time (200ms/div)
Figure 40.
Figure 41.
LINE TRANSIENT RESPONSE
VOUT1 = 1.8V, VOUT2 = 2.8V
LINE TRANSIENT RESPONSE
VOUT1 = 1.8V, VOUT2 = 2.8V
5.5V
Slew Rate = 1V/ms
Slew Rate = 1V/ms
IOUT = 30mA
IOUT = 30mA
4.3V
3.3V
VIN
1V/div
VIN
1V/div
3.3V
5mV/div
VOUT1
5mV/div
5mV/div
VOUT1
VOUT2
VOUT2
5mV/div
Time (200ms/div)
Time (200ms/div)
Figure 42.
Figure 43.
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TYPICAL CHARACTERISTICS (continued)
Over operating temperature range of TA = –40°C to 125°C, VEN1 = VEN2 = VIN, CIN = 1 μF, COUT1 = 1 μF, and COUT2 = 1 μF,
unless otherwise noted. Typical values are at TA = 25°C.
LINE TRANSIENT RESPONSE
VOUT1 = 4.8V, VOUT2 = 4.8V
Slew Rate = 1V/ms
IOUT = 30mA
5.5V
5.3V
1V/div
VIN
VOUT1
5mV/div
5mV/div
VOUT2
Time (200ms/div)
Figure 44.
LOAD TRANSIENT RESPONSE AND CROSSTALK
VOUT1 = 1.2V, VOUT2 = 1.2V
LOAD TRANSIENT RESPONSE AND CROSSTALK
VOUT1 = 1.2V, VOUT2 = 1.2V
Slew Rate = 1V/ms
Slew Rate = 1V/ms
200mA
VIN = 2.0V
VIN = 2.0V
200mA
100mA/div
50mV/div
50mA
IOUT1
VOUT1
VOUT2
IOUT1
VOUT1
VOUT2
100mA/div
50mV/div
0mA
10mV/div
10mV/div
Time (50ms/div)
Time (50ms/div)
Figure 45.
Figure 46.
LOAD TRANSIENT RESPONSE AND CROSSTALK
VOUT1 = 1.8V, VOUT2 = 2.8V
LOAD TRANSIENT RESPONSE AND CROSSTALK
VOUT1 = 1.8V, VOUT2 = 2.8V
200mA
Slew Rate = 1V/ms
Slew Rate = 1V/ms
200mA
VIN = 3.3V
VIN = 3.3V
100mA/div
20mV/div
IOUT2
50mA
100mA/div
50mV/div
IOUT2
0mA
VOUT1
VOUT2
VOUT2
50mV/div
VOUT1
5mV/div
Time (50ms/div)
Time (50ms/div)
Figure 47.
Figure 48.
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SBVS202A –MARCH 2013–REVISED MARCH 2013
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range of TA = –40°C to 125°C, VEN1 = VEN2 = VIN, CIN = 1 μF, COUT1 = 1 μF, and COUT2 = 1 μF,
unless otherwise noted. Typical values are at TA = 25°C.
LOAD TRANSIENT RESPONSE AND CROSSTALK
LOAD TRANSIENT RESPONSE AND CROSSTALK
VOUT1 = 4.8V, VOUT2 = 4.8V
VOUT1 = 4.8V, VOUT2 = 4.8V
Slew Rate = 1V/ms
Slew Rate = 1V/ms
200mA
VIN = 5.3V
VIN = 5.3V
200mA
IOUT1
VOUT1
VOUT2
IOUT1
100mA/div
50mV/div
50mA/div
50mV/div
0mA
50mA
VOUT1
VOUT2
5mV/div
5mV/div
Time (50ms/div)
Time (50ms/div)
Figure 49.
Figure 50.
VIN RAMP UP, RAMP DOWN RESPONSE
VOUT1 = 1.2V, VOUT2 = 1.2V
VIN RAMP UP, RAMP DOWN RESPONSE
VOUT1 = 1.8V, VOUT2 = 2.8V
IOUT = 30mA
IOUT = 30mA
VIN/VEN
VIN/VEN
VOUT2
VOUT1
1V/div
1V/div
VOUT1/VOUT2
Time (200ms/div)
Time (200ms/div)
Figure 51.
Figure 52.
VIN RAMP UP, RAMP DOWN RESPONSE
VOUT1 = 4.8V, VOUT2 = 4.8V
IOUT = 30mA
VIN/VEN
VOUT1/VOUT2
1V/div
Time (200ms/div)
Figure 53.
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APPLICATION INFORMATION
IMPROVE PSRR AND NOISE PERFORMANCE
The TLV7103318-Q1 and TLV7101828-Q1 devices
belong to a new family of next-generation, value LDO
regulators. These devices consume low quiescent
current and deliver excellent line and load transient
performance. These features, combined with low
Input and output capacitors should be placed as
close to the device pins as possible. To improve ac
performance such as PSRR, output noise, and
transient response, it is recommended that the board
be designed with separate ground planes for VIN and
VOUT, with the ground plane connected only at the
GND pin of the device. In addition, the ground
connection for the output capacitor should be
connected directly to the GND pin of the device. High
ESR capacitors may degrade PSRR.
noise, very good PSRR with little (VIN to VOUT
)
headroom, make these devices ideal for RF portable
applications. This family of LDO regulators offers
current limit and thermal protection, and is specified
from –40°C to 125°C.
INPUT AND OUTPUT CAPACITOR
REQUIREMENTS
INTERNAL CURRENT LIMIT
1.0μF X5R- and X7R-type ceramic capacitors are
recommended because they have minimal variation
in value and equivalent series resistance (ESR) over
temperature.
The TLV7103318-Q1 and TLV7101828-Q1 internal
current limits help protect the regulator during fault
conditions. During current limit, the output sources a
fixed amount of current that is largely independent of
output voltage. In such a case, the output voltage is
However, the TLV7103318-Q1 and TLV7101828-Q1
are designed to be stable with an effective
capacitance of 0.1 μF or larger at the output. Thus,
the device would also be stable with capacitors of
other dielectrics, as long as the effective capacitance
under operating bias voltage and temperature is
greater than 0.1 μF. This effective capacitance refers
to the capacitance that the device sees under
operating bias voltage and temperature conditions
(that is, the capacitance after taking bias voltage and
temperature derating into consideration.)
not regulated, and is VOUT = ILIMIT × RLOAD
.
The PMOS pass transistor dissipates (VIN – VOUT) ×
ILIMIT until thermal shutdown is triggered and the
device is turned off. As the device cools down, it is
turned on by the internal thermal shutdown circuit. If
the fault condition continues, the device cycles
between current limit and thermal shutdown. See the
Thermal Information section for more details. The
PMOS pass element in the TLV7103318-Q1 and
TLV7101828-Q1 has a built-in body diode that
conducts current when the voltage at OUT exceeds
the voltage at IN. This current is not limited, so if
extended reverse voltage operation is anticipated,
external limiting to 5% of rated output current is
recommended.
In addition to allowing the use of cost-effective
dielectrics, these devices also enable using smaller
footprint capacitors that have a higher derating in
size-constrained applications.
Note that using a 0.1-μF rating capacitor at the output
of the LDO regulator does not ensure stability
because the effective capacitance under operating
conditions would be less than 0.1 μF. The maximum
ESR should be less than 200 mΩ.
SHUTDOWN
The enable pin (EN) is active high. The device is
enabled when EN pin goes above 0.9V. This
relatively lower value of voltage needed to turn the
LDO regulator on can be used to enable the device
with the GPIO of recent processors whose GPIO
voltage is lower than traditional microcontrollers.
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1μF to 1.0μF low ESR capacitor across the IN
and GND pins of the regulator. This capacitor
counteracts reactive input sources and improves
transient response, noise rejection, and ripple
rejection. A higher-value capacitor may be necessary
if large, fast-rise-time load transients are anticipated,
or if the device is not located near the power source.
If source impedance is more than 2Ω, a 0.1μF input
capacitor may be necessary to ensure stability.
The device is turned off when the EN pin is held at
less than 0.4 V. When shutdown capability is not
required, the EN pin can be connected to the IN pin.
DROPOUT VOLTAGE
The TLV7103318-Q1 and TLV7101828-Q1 use a
PMOS pass transistor to achieve low dropout. When
(VIN – VOUT) is less than the dropout voltage (VDO),
the PMOS pass device is in the linear region of
operation and the input-to-output resistance is the
RDS(ON) of the PMOS pass element. VDO scales
approximately with the output current because the
PMOS device behaves as a resistor in dropout.
BOARD LAYOUT RECOMMENDATIONS TO
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As with any linear regulator, PSRR and transient
response are degraded as (VIN – VOUT) approaches
dropout.
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
35°C above the maximum expected ambient
condition of the particular application. This
configuration produces
temperature of 125°C at the highest expected
ambient temperature and worst-case load.
a
worst-case junction
TRANSIENT RESPONSE
As with any regulator, increasing the size of the
output capacitor reduces over/undershoot magnitude
but increases duration of the transient response.
The internal protection circuitry of the TLV7103318-
Q1 and TLV7101828-Q1 has been designed to
protect against overload conditions. It was not
intended to replace proper heatsinking. Continuously
running the TLV710-Q1 into thermal shutdown
degrades device reliability.
The TLV7103318-Q1 and TLV7101828-Q1 each
have a dedicated VREF. Consequently, crosstalk from
one channel to the other as a result of transients is
close to 0V.
UNDERVOLTAGE LOCKOUT (UVLO)
POWER DISSIPATION
The TLV7103318-Q1and TLV7101828-Q1 use an
undervoltage lockout circuit to keep the output shut
off until the internal circuitry is operating properly.
The ability to remove heat from a die is different for
each
package
type,
presenting
different
considerations in the printed circuit board (PCB)
layout. The PCB area around the device that is free
of other components moves the heat from the device
to the ambient air.
THERMAL INFORMATION
Thermal protection disables the output when the
junction temperature rises to approximately 165°C,
allowing the device to cool. When the junction
temperature cools to approximately 145°C, the output
circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage as a result of
overheating.
Performance data for the TLV710-Q1 evaluation
module (EVM) are shown in Table 1. The EVM is a 2-
layer board with 2 ounces of copper per side. The
dimension and layout are shown in Figure 54 and
Figure 55. Using heavier copper increases the
effectiveness of removing heat from the device. The
addition of plated through-holes in the heat-
dissipating layer also improves the heatsink
effectiveness. Power dissipation depends on input
voltage and load conditions.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to 125°C maximum. To
estimate the margin of safety in a complete design
Power dissipation (PD) is equal to the product of the
output current and the voltage drop across the output
pass element, as shown in Equation 1:
PD = (VIN – VOUT) × IOUT
(1)
(including
heatsink),
increase
the
ambient
temperature until the thermal protection is triggered;
PACKAGE MOUNTING
Solder pad footprint recommendations for the
TLV7103318-Q1 and TLV7101828-Q1 are available
from the Texas Instruments Web site at www.ti.com.
The recommended land pattern for the DSE (SON-6)
package is shown in .
Table 1. TLV7103318-Q1 and TLV7101828-Q1 EVM Dissipation Ratings
PACKAGE
RθJA
170°C/W
TA < 25°C
585 mW
TA = 85°C
235 mW
TA = 125°C
DSE
mW
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33mm
27mm
Figure 54. Top Layer
33mm
27mm
Figure 55. Bottom Layer
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV7101828QDSERQ1
TLV7103318QDSERQ1
ACTIVE
ACTIVE
WSON
WSON
DSE
DSE
6
6
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
CP
ZD
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
OTHER QUALIFIED VERSIONS OF TLV710-Q1 :
Catalog: TLV710
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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5-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV7101828QDSERQ1 WSON
TLV7103318QDSERQ1 WSON
DSE
DSE
6
6
3000
3000
179.0
179.0
8.4
8.4
1.8
1.8
1.8
1.8
1.0
1.0
4.0
4.0
8.0
8.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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5-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV7101828QDSERQ1
TLV7103318QDSERQ1
WSON
WSON
DSE
DSE
6
6
3000
3000
200.0
200.0
183.0
183.0
25.0
25.0
Pack Materials-Page 2
PACKAGE OUTLINE
DSE0006A
WSON - 0.8 mm max height
SCALE 6.000
PLASTIC SMALL OUTLINE - NO LEAD
1.55
1.45
A
B
1.55
1.45
PIN 1 INDEX AREA
0.8 MAX
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
0.6
0.4
5X
3
4
2X 1
4X 0.5
6
1
0.3
6X
0.7
0.5
0.2
0.1
0.05
PIN 1 ID
C A B
C
4220552/A 04/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
DSE0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
PKG
(0.8)
5X (0.7)
1
6
6X (0.25)
SYMM
4X 0.5
4
3
(R0.05) TYP
(1.6)
LAND PATTERN EXAMPLE
SCALE:40X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
PADS 4-6
NON SOLDER MASK
DEFINED
PADS 1-3
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220552/A 04/2021
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
DSE0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
PKG
5X (0.7)
(0.8)
6X (0.25)
1
6
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:40X
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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