TLV733285PDQNR [TI]
具有使能功能的 300mA、低 IQ、低压降无电容稳压器 | DQN | 4 | -40 to 125;型号: | TLV733285PDQNR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有使能功能的 300mA、低 IQ、低压降无电容稳压器 | DQN | 4 | -40 to 125 稳压器 |
文件: | 总38页 (文件大小:1201K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TLV733P
ZHCSD13C –OCTOBER 2014–REVISED JULY 2019
采用 1mm × 1mm X2SON 封装的 TLV733P 无电容器、300mA、低压降
稳压器
1 特性
3 说明
1
•
•
•
•
输入电压范围:1.4V 至 5.5V
TLV733 系列低压降线性稳压器 (LDO) 尺寸超小且静
态电流较低,可提供 300mA 的拉电流,并且线路和负
载瞬态性能出色。此系列器件可提供典型值为 1% 的
精度。
有无电容器均可实现稳定运行
折返过流保护
封装:
–
–
1.0mm × 1.0mm X2SON (4)
SOT-23 (5)
TLV733 系列采用现代无电容架构设计,无需使用输入
或输出电容即可确保运行稳定。移除输出电容有助于减
小解决方案的尺寸,并且可以消除启动时的浪涌电流。
不过,TLV733 系列在使用陶瓷输出电容时也可以稳定
运行。使用输出电容时,TLV733 还可以在器件上电和
使能期间提供折返电流控制。此功能对于电池供电类器
件尤为重要。
•
•
•
•
超低压降:300mA (3.3 VOUT) 时为 125mV
精度:典型值 1%,最大值 1.4%
低 IQ:34µA
可提供固定输出电压:
1.0V 至 3.3V
•
•
高电源抑制比 (PSRR):1kHz 频率时为 50dB
TLV733 提供了有源下拉电路,当被禁用时可以使输出
负载快速放电。
有源输出放电
2 应用
TLV733 系列采用标准的 DBV (SOT-23) 和 DQN
(X2SON) 封装。
•
•
•
•
•
•
平板电脑
智能手机
器件信息(1)
笔记本和台式计算机
便携式工业和消费类产品
无线局域网 (WLAN) 和其他 PC 附加卡
摄像机模块
器件型号
TLV733P
封装
SOT-23 (5)
X2SON (4)
封装尺寸(标称值)
2.90mm × 1.60mm
1.00mm x 1.00mm
(1) 要了解所有可用封装,请参见数据表末尾的封装选项附录。
典型应用电路
压降电压与输出电流间的关系
180
VOUT = 3.3 V
VOUT = 1.8 V
IN
OUT
GND
160
140
120
100
80
TLV733
COUT
CIN
EN
Optional
Optional
ON
OFF
60
40
20
0
0
30
60
90 120 150 180 210 240 270 300
IOUT (mA)
D020
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SBVS235
TLV733P
ZHCSD13C –OCTOBER 2014–REVISED JULY 2019
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 15
8
9
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Applications ............................................... 18
Power Supply Recommendations...................... 20
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Examples................................................... 20
11 器件和文档支持 ..................................................... 21
11.1 器件支持 ............................................................... 21
11.2 文档支持................................................................ 21
11.3 接收文档更新通知 ................................................. 21
11.4 社区资源................................................................ 21
11.5 商标....................................................................... 21
11.6 静电放电警告......................................................... 21
11.7 Glossary................................................................ 22
12 机械、封装和可订购信息....................................... 23
7
4 修订历史记录
Changes from Revision B (November 2015) to Revision C
Page
•
•
•
•
•
•
Changed description of EN pin from 0.9 V to VEN(HI) and from 0.35 V to VEN(LO) .................................................................. 4
Deleted typical specifications from VEN(HI) and VEN(LO) parameters ....................................................................................... 6
Added maximum specification to ILIM parameter ................................................................................................................... 6
Changed Shutdown and Output Enable title from Shutdown and changed first paragraph................................................. 14
Added DBV package to last paragraph of Power Dissipation section.................................................................................. 17
已添加 向器件命名规则 表中添加了 (3) ................................................................................................................................ 21
Changes from Revision A (December 2014) to Revision B
Page
•
•
•
•
•
•
•
•
已将低压降特性要点的值从 122mV 改为 125mV,以匹配电气特性中的值............................................................................ 1
已更改首页曲线图中的 VOUT 标签........................................................................................................................................... 1
Changed min junction temperature value from –55 to –40 in Absolute Maximum Ratings table .......................................... 5
Changed max junction temperature value from 160 to 150 in Absolute Maximum Ratings table ........................................ 5
Changed max storage temperature value from 150 to 160 in Absolute Maximum Ratings table.......................................... 5
Added test condition to line regulation parameter in Electrical Characteristics table............................................................. 6
Changed unit for line regulation parameter from mV/V to mV ............................................................................................... 6
Added test condition to load regulation parameter in Electrical Characteristics table .......................................................... 6
Changes from Original (October 2014) to Revision A
Page
•
•
•
•
•
•
•
已更改数据表首页的标题信息,以反映器件系列而非各个器件............................................................................................... 1
已将输入电压范围 特性 更改为列表中的第一个要点............................................................................................................... 1
已更改 首页的典型应用电路;修正了可选电容标识中的错误 ................................................................................................. 1
Changed format of I/O column contents and order of packages in Pin Functions table ....................................................... 4
Moved storage temperature range specification to Absolute Maximum Ratings table ......................................................... 5
Changed Handling Ratings table title to ESD Ratings, updated table format ........................................................................ 5
Added new first row to the VDO parameter in the Electrical Characteristics table.................................................................. 6
2
Copyright © 2014–2019, Texas Instruments Incorporated
TLV733P
www.ti.com.cn
ZHCSD13C –OCTOBER 2014–REVISED JULY 2019
•
•
•
Changed condition text for Figure 34 .................................................................................................................................. 17
已添加 评估模块小节 ............................................................................................................................................................ 21
已删除 相关链接部分 ............................................................................................................................................................ 21
Copyright © 2014–2019, Texas Instruments Incorporated
3
TLV733P
ZHCSD13C –OCTOBER 2014–REVISED JULY 2019
www.ti.com.cn
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
DQN Package
4-Pin 1-mm × 1-mm X2SON
Top View
IN
4
EN
3
IN
GND
EN
1
2
3
5
4
OUT
NC
1
2
OUT
GND
Pin Functions
PIN
NO.
NAME
EN
DQN
3
DBV
I/O
DESCRIPTION
Enable pin. Drive EN greater than VEN(HI) to turn on the regulator.
Drive EN less than VEN(LO) to put the LDO into shutdown mode.
3
2
1
4
I
GND
IN
2
—
I
Ground pin
Input pin. A small capacitor is recommended from this pin to ground.
See the Input and Output Capacitor Selection section for more details.
4
NC
N/A
—
No internal connection
Regulated output voltage pin. For best transient response, use a small 1-μF
ceramic capacitor from this pin to ground.
OUT
1
5
O
See the Input and Output Capacitor Selection section for more details.
The thermal pad is electrically connected to the GND node.
Connect to the GND plane for improved thermal performance.
Thermal pad
—
—
4
Copyright © 2014–2019, Texas Instruments Incorporated
TLV733P
www.ti.com.cn
ZHCSD13C –OCTOBER 2014–REVISED JULY 2019
6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted); all voltages are with respect to GND(1)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
V
VIN
6.0
Voltage
VEN
VOUT
IOUT
VIN + 0.3
3.6
Current
Internally limited
A
Output short-circuit duration
Indefinite
150
Operating junction, TJ
Storage, Tstg
–40
–65
Temperature
°C
160
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
1.4
1.0
0
NOM
MAX
5.5
UNIT
Input range, VIN
V
V
Output range, VOUT
Output current, IOUT
Enable range, VEN
Junction temperature, TJ
3.3
300
VIN
mA
V
0
–40
125
°C
6.4 Thermal Information
TLV733P
THERMAL METRIC(1)
DQN (X2SON)
4 PINS
218.6
DBV (SOT-23)
UNIT
5 PINS
228.4
151.5
55.8
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
164.8
164.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
5.6
31.4
ψJB
163.9
54.8
RθJC(bot)
131.4
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2014–2019, Texas Instruments Incorporated
5
TLV733P
ZHCSD13C –OCTOBER 2014–REVISED JULY 2019
www.ti.com.cn
6.5 Electrical Characteristics
At operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted). All typical values at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
1.4
TYP
MAX
5.5
UNIT
VIN
Input voltage
V
TJ = 25°C
–1%
1%
DC output accuracy
Undervoltage lockout
–40°C ≤ TJ ≤ +125°C
VIN rising
–1.4%
1.4%
1.4
1.3
1.25
1
UVLO
V
VIN falling
ΔVO(ΔVI) Line regulation
ΔVO(ΔIO) Load regulation
ΔVI = VIN(nom) to VIN(nom) + 1
mV
mV
DQN package
16
ΔIO = 1 mA to
300 mA
DBV package
25
VOUT = 1.1 V, –40°C ≤ TJ ≤ 85°C
1.2 V ≤ VOUT < 1.5 V, –40°C ≤ TJ ≤ 85°C
1.5 V ≤ VOUT < 1.8 V, –40°C ≤ TJ ≤ 85°C
1.8 V ≤ VOUT < 2.5 V, –40°C ≤ TJ ≤ 85°C
2.5 V ≤ VOUT < 3.3 V, –40°C ≤ TJ ≤ 85°C
VOUT = 3.3 V, –40°C ≤ TJ ≤ 85°C
1.2 V ≤ VOUT < 1.5 V, –40°C ≤ TJ ≤ 125°C
1.5 V ≤ VOUT < 1.8 V, –40°C ≤ TJ ≤ 125°C
1.8 V ≤ VOUT < 2.5 V, –40°C ≤ TJ ≤ 125°C
2.5 V ≤ VOUT < 3.3 V, –40°C ≤ TJ ≤ 125°C
VOUT = 3.3 V, –40°C ≤ TJ ≤ 125°C
460
420
370
270
260
220
450
400
300
290
270
60
VOUT = 0.98 ×
VOUT(nom),
IOUT = 300 mA
VDO
Dropout voltage(1)
125
mV
125
34
IGND
Ground pin current
Shutdown current
IOUT = 0 mA
µA
µA
ISHDN
V
EN ≤ 0.35 V, 2.0 V ≤ VIN ≤ 5.5 V, TJ = 25°C
0.1
68
1
f = 100 Hz
f = 10 kHz
f = 100 kHz
Power-supply
rejection ratio
VOUT = 1.8 V,
IOUT = 300 mA
PSRR
35
dB
28
Vn
Output noise voltage
BW = 10 Hz to 100 kHz, VOUT = 1.8 V, IOUT = 10 mA
120
µVRMS
V
EN pin high voltage
(enabled)
VEN(HI)
0.9
EN pin low voltage
(disabled)
VEN(LO)
IEN
0.35
V
EN pin current
VEN = 5.5 V
0.01
250
µA
Time from EN assertion to 98% × VOUT(nom), VOUT = 1.0
V, IOUT = 0 mA
tSTR
Startup time
µs
Time from EN assertion to 98% × VOUT(nom), VOUT = 3.3
V, IOUT = 0 mA
800
120
Pull-down resistor
Output current limit
VIN = 2.3 V
Ω
ILIM
IOS
360
700
mA
VOUT shorted to GND, VOUT = 1.0 V
VOUT shorted to GND, VOUT = 3.3 V
Shutdown, temperature increasing
Reset, temperature decreasing
150
170
160
140
Short-circuit current
limit
mA
°C
Tsd
Thermal shutdown
(1) Dropout voltage for the TLV73310P is not valid at room temperature. The device engages undervoltage lockout (VIN < UVLOFALL) before
the dropout condition is met.
6
Copyright © 2014–2019, Texas Instruments Incorporated
TLV733P
www.ti.com.cn
ZHCSD13C –OCTOBER 2014–REVISED JULY 2019
6.6 Typical Characteristics
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
1.03
1.02
1.01
1
1.004
1
TJ = -40 èC
TJ = 0 èC
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
TJ = -40 èC
TJ = 0 èC
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
0.996
0.992
0.988
0.984
0.98
0.99
0.98
0.97
0.96
0.976
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Current (mA)
Current (mA)
D001
D005
TLV73310PDBV
TLV73310PDQN
Figure 1. 1.0-V Load Regulation vs IOUT and Temperature
Figure 2. 1.0-V Load Regulation vs IOUT and Temperature
1.816
1.8
TJ = -40 èC
TJ = 0 èC
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
TJ = -40 èC
TJ = 0 èC
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
1.808
1.8
1.797
1.794
1.791
1.788
1.785
1.782
1.779
1.792
1.784
1.776
1.768
1.76
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Current (mA)
Current (mA)
D002
D006
TLV73318PDBV
TLV73318PDQN
Figure 3. 1.8-V Load Regulation vs IO and Temperature
Figure 4. 1.8-V Load Regulation vs IOUT and Temperature
3.345
3.32
TJ = -40 èC
TJ = 0 èC
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
TJ = -40 èC
TJ = 0 èC
3.33
3.315
3.3
3.312
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
3.304
3.296
3.288
3.28
3.285
3.27
3.255
3.24
3.272
3.264
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Current (mA)
Current (mA)
D003
D007
TLV73333PDBV
TLV73333PDQN
Figure 6. 3.3-V Load Regulation vs IOUT and Temperature
Figure 5. 3.3-V Load Regulation vs IOUT and Temperature
Copyright © 2014–2019, Texas Instruments Incorporated
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TLV733P
ZHCSD13C –OCTOBER 2014–REVISED JULY 2019
www.ti.com.cn
Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
400
350
300
250
200
150
100
50
390
360
330
300
270
240
210
180
150
120
90
TJ = -40 èC
TJ = 0 èC
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
TJ = -40 èC
TJ = 0 èC
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
60
0
30
60
90 120 150 180 210 240 270 300
0
30
60
90 120 150 180 210 240 270 300
Current (mA)
Current (mA)
D024
D025
TLV73312PDBV
TLV73312PDQN
Figure 7. 1.2-V Dropout Voltage vs IOUT and Temperature
Figure 8. 1.2-V Dropout Voltage vs IOUT and Temperature
275
300
TJ = -40 èC
TJ = -40 èC
TJ = 0 èC
250
TJ = 0 èC
250
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
TJ = 25 èC
225
200
175
150
125
100
75
TJ = 85 èC
TJ = 125 èC
200
150
100
50
50
25
0
0
0
30
60
90 120 150 180 210 240 270 300
0
30
60
90 120 150 180 210 240 270 300
Current (mA)
Current (mA)
D008
D010
TLV73318PDBV
TLV73318PDQN
Figure 9. 1.8-V Dropout Voltage vs IOUT and Temperature
Figure 10. 1.8-V Dropout Voltage vs IOUT and Temperature
300
300
TJ = -40 èC
TJ = 0 èC
TJ = -40 èC
TJ = 0 èC
250
250
TJ = 25 èC
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
TJ = 85 èC
TJ = 125 èC
200
200
150
100
50
150
100
50
0
0
0
30
60
90 120 150 180 210 240 270 300
Current (mA)
0
30
60
90 120 150 180 210 240 270 300
Current (mA)
D009
D011
TLV73333PDBV
Figure 11. 3.3-V Dropout Voltage vs IOUT and Temperature
TLV73333PDQN
Figure 12. 3.3-V Dropout Voltage vs IOUT and Temperature
8
Copyright © 2014–2019, Texas Instruments Incorporated
TLV733P
www.ti.com.cn
ZHCSD13C –OCTOBER 2014–REVISED JULY 2019
Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
1.816
1.814
1.812
1.81
70
65
60
55
50
45
40
35
30
25
TJ = -40èC
TJ = 0èC
TJ = 25èC
TJ = 85èC
TJ = 125èC
TJ = -40èC
TJ = 0èC
TJ = 25èC
TJ = 85èC
TJ = 125èC
1.808
1.806
1.804
1.802
1.8
1.798
1.796
2
2.5
3
3.5
VIN (V)
4
4.5
5
5.5
0
30
60
90 120 150 180 210 240 270 300
IOUT (mA)
D019
D012
TLV73318PDBV
Figure 13. 1.8-V Regulation vs VIN (Line Regulation) and
Temperature
Figure 14. Ground Pin Current vs IOUT and Temperature
40
100
TJ = 25èC
TJ = -40èC
TJ = 0èC
35
TJ = 25èC
TJ = 85èC
TJ = 125èC
30
25
20
15
10
5
10
1
0.1
0.01
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
0
1
2
3
4
5
6
VIN (V)
VIN (V)
D013
D015
IOUT = 0 mA
Figure 15. Ground Pin Current vs VIN
Figure 16. Shutdown Current vs VIN and Temperature
1
0.675
VEN(LO)
VEN(HI)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.65
0.625
0.6
0.575
0.55
0.525
0.5
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
0.475
0.45
0.425
150 200 250 300 350 400 450 500 550 600 650 700
Output Current (mA)
-40
-20
0
20
40
TJ (èC)
60
80
100 120 140
D023
D014
TLV73310PDBV
Figure 17. Enable Threshold vs Temperature
Figure 18. 1.0-V Foldback Current Limit vs
IOUT and Temperature
Copyright © 2014–2019, Texas Instruments Incorporated
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ZHCSD13C –OCTOBER 2014–REVISED JULY 2019
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
2
1.75
1.5
1.25
1
3.5
3
2.5
2
1.5
1
0.75
0.5
0.25
0
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
0.5
0
150
200
250
300 350
Output Current (mA)
400
450
500
150
200
250
300 350
Output Current (mA)
400
450
500
D021
D022
TLV73318PDBV
TLV73333PDBV
Figure 19. 1.8-V Foldback Current Limit vs
IOUT and Temperature
Figure 20. 3.3-V Foldback Current Limit vs
IOUT and Temperature
80
70
60
50
40
30
20
10
0
10
1
No Output Capacitor
1-mF Output Capacitor
VOUT = 1 V
VOUT = 1.8 V
VOUT = 3.3 V
0.1
0.01
0.005
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
D017
D016
TLV73318PDQN, IOUT = 300 mA
IOUT = 300 mA
Figure 21. Power-Supply Rejection Ratio vs Frequency
Figure 22. Output Spectral Noise Density
VIN (2 V/div)
VIN (2 V/div)
VOUT (1 V/div,
AC Coupled)
VOUT (1 V/div,
AC Coupled)
Time (20 µs/div)
Time (20 µs/div)
TLV73318PDBV, IOUT = 10 mA, 1-µF output capacitor
TLV73318PDBV, IOUT = 300 mA, 1-µF output capacitor
Figure 23. Line Transient
Figure 24. Line Transient
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
VOUT (200 mV/div,
AC Coupled)
VOUT (200 mV/div,
AC Coupled)
ILOAD (100 mA/div)
ILOAD (100 mA/div)
Time (20 µs/div)
Time (20 µs/div)
TLV73310PDBV, VIN = 2.0 V, 1-µF output capacitor, output
current slew rate = 0.25 A/µs
TLV73310PDBV, VIN = 2.0 V, no output capacitor, output current
slew rate = 0.25 A/µs
Figure 25. 1.0-V, 50-mA to 300-mA Load Transient
Figure 26. 1.0 V, 50-mA to 300-mA Load Transient
VOUT (100 mV/div,
AC Coupled)
VOUT (100 mV/div,
AC coupled)
ILOAD (100 mA/div)
ILOAD (200 mA/div)
Time (50 µs/div)
Time (20 µs/div)
TLV73333PDBV, VIN = 3.8 V,1-µF output capacitor, output current
slew rate = 0.25 A/µs
TLV73333PDBV, VIN = 3.8 V, no output capacitor, output current
slew rate = 0.25 A/µs
Figure 27. 3.3 V, 50-mA to 300-mA Load Transient
Figure 28. 3.3 V, 50-mA to 300-mA Load Transient
VEN (500 mV/div)
VIN (1 V/div)
VOUT (1 V/div)
ILOAD (200 mA/div)
VOUT (500 mV/div)
Time (100 µs/div)
Time (100 µs/div)
TLV73318PDBV, RL = 6.2 Ω, 1-µF output capacitor
TLV73318PDBV, RL = 6.2 Ω, VEN = VIN, 1-µF output capacitor
Figure 30. Startup with EN
Figure 29. VIN Power-Up and Power-Down
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
VOUT (500 mV/div)
VEN (500 mV/div)
VOUT (500 mV/div)
ILOAD (200 mA/div)
Time (100 µs/div)
Time (100 µs/div)
TLV73318PDBV, 1-µF output capacitor
TLV73318PDBV, IOUT = 300 mA, 1-µF output capacitor
Figure 32. Foldback Current Limit Response
Figure 31. Shutdown Response with Enable
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7 Detailed Description
7.1 Overview
The TLV733 belongs to a new family of next-generation, low-dropout regulators (LDOs). These devices consume
low quiescent current and deliver excellent line and load transient performance. These characteristics, combined
with low noise, good PSRR with low dropout voltage, make this family of devices ideal for portable consumer
applications.
This family of regulators offers foldback current limit, shutdown, and thermal protection. The operating junction
temperature for this family of devices is –40°C to 125°C.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
Thermal
Shutdown
UVLO
120 W
Bandgap
EN
Logic
TLV733
GND
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7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
The TLV733 uses an undervoltage lockout (UVLO) circuit that disables the output until the input voltage is
greater than the rising UVLO voltage, UVLORISE. This circuit ensures that the device does not exhibit any
unpredictable behavior when the supply voltage is lower than the operational range of the internal circuitry.
During UVLO disable, the output is connected to ground with a 120-Ω pulldown resistor.
7.3.2 Shutdown and Output Enable
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(HI). Turn off the device
by forcing the EN pin to drop below VEN(LO). If shutdown capability is not required, connect EN to IN. There is no
internal pulldown resistor connected to the EN pin.
The TLV733 has an internal pulldown MOSFET that connects a 120-Ω resistor to ground when the device is
disabled. The discharge time after disabling depends on the output capacitance (COUT) and the load resistance
(RL) in parallel with the 120-Ω pulldown resistor. The time constant is calculated in Equation 1:
120 · RL
t =
· COUT
120 + RL
(1)
7.3.3 Internal Foldback Current Limit
The TLV733 has an internal foldback current limit that protects the regulator during fault conditions. The current
allowed through the device is reduced as the output voltage falls. When the output is shorted, the LDO supplies a
typical current of 150 mA. The output voltage is not regulated when the device is in current limit. In this condition,
the output voltage is the product of the regulated current and the load resistance. When the device output is
shorted, the PMOS pass transistor dissipates power [(VIN – VOUT) × IOS] until thermal shutdown is triggered and
the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on.
If the fault condition continues, the device cycles between current limit and thermal shutdown. See the Thermal
Information table for more details.
The foldback current-limit circuit limits the current allowed through the device to current levels lower than the
minimum current limit at nominal VOUT current limit (ILIM) during startup. See Figure 18 to Figure 20 for typical
foldback current limit values. If the output is loaded by a constant-current load during startup, or if the output
voltage is negative when the device is enabled, then the load current demanded by the load may exceed the
foldback current limit and the device may not rise to the full output voltage. For constant-current loads, disable
the output load until the TLV733 has fully risen to its nominal output voltage.
The TLV733 PMOS pass element has an intrinsic body diode that conducts current when the voltage at the OUT
pin exceeds the voltage at the IN pin. Do not force the output voltage to exceed the input voltage because
excessively high current may flow through the body diode.
7.3.4 Thermal Shutdown
Thermal shutdown protection disables the output when the junction temperature rises to approximately 160°C.
Disabling the device eliminates the power dissipated by the device, allowing the device to cool. When the
junction temperature cools to approximately 140°C, the output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off.
This cycling limits regulator dissipation, protecting it from damage as a result of overheating.
Activating the thermal shutdown feature usually indicates excessive power dissipation as a result of the product
of the (VIN –VOUT) voltage and the load current. For reliable operation, limit junction temperature to 125°C
maximum. To estimate the margin of safety in a complete design, increase the ambient temperature until the
thermal protection is triggered; use worst-case loads and signal conditions.
The TLV733 internal protection circuitry protects against overload conditions but is not intended to be activated in
normal operation. Continuously running the TLV733 into thermal shutdown degrades device reliability.
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7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
•
The input voltage has previously exceeded the UVLO rising voltage and has not decreased below the UVLO
falling threshold.
•
•
The input voltage is greater than the nominal output voltage added to the dropout voltage.
The enable voltage has previously exceeded the enable rising threshold voltage and not decreased below the
enable falling threshold.
•
•
The output current is less than the current limit.
The device junction temperature is less than the thermal shutdown temperature.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this condition, the output
voltage is the same the input voltage minus the dropout voltage. The transient performance of the device is
significantly degraded because the pass device is in a triode state and no longer controls the current through the
LDO. Line or load transients in dropout may result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
•
•
The input voltage is less than the UVLO falling voltage, or has not yet exceeded the UVLO rising threshold.
The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
•
The device junction temperature is greater than the thermal shutdown temperature.
When the device is disabled, the active pulldown resistor discharges the output.
Table 1 shows the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
VIN > VOUT(nom) + VDO
and VIN > UVLORISE
Normal mode
Dropout mode
VEN > VEN(HI)
VEN > VEN(HI)
IOUT < ILIM
IOUT < ILIM
TJ < 160°C
TJ < 160°C
UVLORISE < VIN < VOUT(nom) + VDO
Disabled mode
(any true condition
disables the device)
VIN < UVLOFALL
VEN < VEN(LO)
—
TJ > 160°C
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input and Output Capacitor Selection
The TLV733 uses an advanced internal control loop to obtain stable operation both with and without the use of
input or output capacitors. Dynamic performance is improved with the use of an output capacitor, and may be
improved with an input capacitor. An output capacitance of 0.1 μF or larger generally provides good dynamic
response. Use X5R- and X7R-type ceramic capacitors because these capacitors have minimal variation in value
and equivalent series resistance (ESR) over temperature.
Although an input capacitor is not required for stability, increased output impedance from the input supply may
compromise the performance of the TLV733. Good analog design practice is to connect a 0.1-µF to 1-µF
capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response,
input ripple, and PSRR. Use an input capacitor if the source impedance is greater than 0.5 Ω. Use a higher-value
capacitor if large, fast, rise-time load transients are anticipated, or if the device is located several inches from the
input power source.
Figure 33 shows the transient performance improvements with an external 1-µF capacitor on the output versus
no output capacitor. The data in this figure are taken with an increasing load step from 50 mA to 300 mA, and the
peak output voltage deviation (load transient response) is measured. For low output current slew rates,
(< 0.1 A/µs), the transient performance of the device is similar with or without an output capacitor. As the current
slew rate is increased, the peak voltage deviation is significantly increased. For loads that exhibit fast current
slew rates above 0.1 A/µs, use an output capacitor. For best performance, the maximum recommended output
capacitance is 100 µF.
35
1-mF COUT
COUT Removed
30
25
20
15
10
5
0
0.01
0.1
1
Output Load Transient Slew Rate (A/ms)
D027
TLV73333PDBV, output current stepped from 50 mA to 300 mA, output voltage change measured at positive dI/dt
Figure 33. Output Voltage Deviation vs Load Step Slew Rate
Some applications benefit from the removal of the output capacitor. In addition to space and cost savings, the
removal of the output capacitor lowers inrush current as a result of eliminating the required current flow into the
output capacitor upon startup. In these cases, take care to ensure that the load is tolerant of the additional output
voltage deviations.
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Application Information (continued)
8.1.2 Dropout Voltage
The TLV733 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device
behaves like a resistor in dropout mode. As with any linear regulator, PSRR and transient response degrade as
(VIN – VOUT) approaches dropout operation. See Figure 7 to Figure 12 for typical dropout values.
8.1.3 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to ambient air. Performance data for JEDEC high-K boards are given in the Thermal
Information table. Using heavier copper increases the effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating layers also improves heatsink effectiveness.
Power dissipation (PD) depends on input voltage and load conditions. PD is equal to the product of the output
current and voltage drop across the output pass element, as shown in Equation 2.
PD = (VIN – VOUT) × IOUT
(2)
Figure 34 shows the maximum ambient temperature versus the power dissipation of the TLV733 in the DQN and
DBV packages. This figure assumes the device is soldered on JEDEC standard high-K layout with no airflow
over the board. Actual board thermal impedances vary widely. If the application requires high power dissipation,
having a thorough understanding of the board temperature and thermal impedances is helpful to make sure the
TLV733 does not operate continuously above a junction temperature of 125°C.
125
TLV733 DQN, High-K Layout
TLV733 DBV, High-K Layout
120
115
110
105
100
95
90
85
80
75
70
65
60
55
0
0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 0.3
Power Dissipation (W)
D028
TLV733, high-K layout
Figure 34. Maximum Ambient Temperature vs Device Power Dissipation
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8.2 Typical Applications
8.2.1 DC-DC Converter Post Regulation
VOUT
VOUT
1.8 V
1.5 V
IN
OUT
GND
CIN
1 µF
COUT
1 µF
DC-DC
Converter
TLV733
Load
EN
ON
OFF
Figure 35. DC-DC Converter Post Regulation
8.2.1.1 Design Requirements
Table 2. Design Parameters
PARAMETER
Input voltage
Output voltage
Output current
DESIGN REQUIREMENT
1.8 V, ±5%
1.5 V, ±1%
200-mA dc, 300-mA peak
Output voltage transient deviation
Maximum ambient temperature
< 10%, 1-A/µs load step from 50 mA to 200 mA
85°C
8.2.1.2 Design Considerations
Input and output capacitors are required to achieve the output voltage transient requirements. Capacitance
values of 1 µF are selected to give the maximum output capacitance in a small, low-cost package.
Figure 7 shows the 1.2-V option dropout voltage. Given that dropout voltages are higher for lower output-voltage
options, and given that the 1.2-V option dropout voltage is typically less than 300 mV at 125°C, then the 1.5-V
option dropout voltage is typically less than 300 mV at 125°C.
Verify that the maximum junction temperature is not exceeded by referring to Figure 34.
8.2.1.3 Application Curve
VIN (500 mV/div)
VOUT (500 mV/div)
IOUT (100 mA/div)
Time (50 µs/div)
Figure 36. 1.8-V to 1.5-V Regulation at 300 mA
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8.2.2 Capacitor-Free Operation from Battery Input Supply
IN
OUT
GND
TLV733
VBAT
Load
EN
Figure 37. Capacitor-Free Operation from Battery Input Supply
8.2.2.1 Design Requirements
Table 3. Design Parameters
PARAMETER
Input voltage
DESIGN REQUIREMENT
3.0 V to 1.8 V (two 1.5-V batteries)
1.0 V, ±1%
Output voltage
Input current
200 mA, maximum
100-mA dc
Output load
Maximum ambient temperature
70°C
8.2.2.2 Design Considerations
An input capacitor is not required for this design because of the low impedance connection directly to the battery.
No output capacitor allows for the minimal possible inrush current during startup, ensuring the 200-mA maximum
input current is not exceeded.
Verify that the maximum junction temperature is not exceeded by referring to Figure 34.
8.2.2.3 Application Curve
VIN (1 V/div)
VOUT (500 mV/div)
IIN (100 mA/div)
Time (50 µs/div)
Figure 38. No Inrush Startup, 3.0-V to 1.0-V Regulation
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9 Power Supply Recommendations
Connect a low output impedance power supply directly to the IN pin of the TLV733. Inductive impedances
between the input supply and the IN pin can create significant voltage excursions at the IN pin during startup or
load transient events. If inductive impedances are unavoidable, use an input capacitor.
10 Layout
10.1 Layout Guidelines
•
•
•
•
Place input and output capacitors as close to the device as possible.
Use copper planes for device connections, in order to optimize thermal performance.
Place thermal vias around the device to distribute the heat.
Do not place a thermal via directly beneath the thermal pad of the DQN package. A via can wick solder or
solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder
joint on the thermal pad.
10.2 Layout Examples
VOUT
VIN
TLV733
1
4
3
COUT
*
CIN*
2
GND PLANE
Represents via used for
application specific connections
*not required
Figure 39. Layout Example for the DQN Package
VOUT
VIN
5
1
CIN*
COUT
*
2
3
4
GND PLANE
Represents via used for
application specific connections
*not required
Figure 40. Layout Example for the DBV Package
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11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 评估模块
评估模块 (EVM) 可与 TLV733 配套使用,帮助评估初始电路性能。TLV73312PEVM-643 评估模块(和相关的用户
指南)可在德州仪器 (TI) 网站上的产品文件夹中获取,也可直接从 TI 网上商店购买。
11.1.2 器件命名规则
表 4. 器件命名规则(1)(2)
产品
VOUT
xx(x) 为标称输出电压。对于分辨率为 100mV 的输出电压,订货编号中使用两位数字;否则,使用三位数
字(例如,28 = 2.8V;125 = 1.25V)。
P 表示有源输出放电功能。TLV733 系列的所有成员在被禁用时都可以使输出进行有源放电。
yyy 为封装标识符。
TLV733xx(x)Pyyyz(3)
z 为封装数量。R 表示卷(3000 片),T 表示带(250 片)。
(3) 表示替代卷带方向。3 表示引脚 1 位于第 3 象限中。请参阅“封装材料信息”附录,获取更多信息。
(1) 要获得最新的封装和订货信息,请参阅本文档末尾的封装选项附录,或者访问器件产品文件夹(www.ti.com.cn)。
(2) 可提供 1.0V 至 3.3V 范围内的输出电压(以 50mV 为单位增量)。更多详细信息及可用性,请联系制造商。
11.2 文档支持
11.2.1 相关文档ꢀ
德州仪器 (TI),《TLV73312PDQN-643 评估模块》 用户指南
11.3 接收文档更新通知
要接收文档更新通知,请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册,即可每周接收产
品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
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11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
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PACKAGE OUTLINE
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
4215302/D 06/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
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EXAMPLE BOARD LAYOUT
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
4215302/D 06/2016
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
6. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.
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ZHCSD13C –OCTOBER 2014–REVISED JULY 2019
www.ti.com.cn
EXAMPLE STENCIL DESIGN
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
4215302/D 06/2016
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
26
版权 © 2014–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV73310PDBVR
TLV73310PDBVT
TLV73310PDQNR
TLV73310PDQNT
TLV73311PDBVR
TLV73311PDBVT
TLV73311PDQNR
TLV73311PDQNT
TLV73312PDBVR
TLV73312PDBVT
TLV73312PDQNR
TLV73312PDQNR3
TLV73312PDQNT
TLV73315PDBVR
TLV73315PDBVT
TLV73315PDQNR
TLV73315PDQNR3
TLV73315PDQNT
TLV73318PDBVR
TLV73318PDBVT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
X2SON
SOT-23
SOT-23
DBV
DBV
DQN
DQN
DBV
DBV
DQN
DQN
DBV
DBV
DQN
DQN
DQN
DBV
DBV
DQN
DQN
DQN
DBV
DBV
5
5
4
4
5
5
4
4
5
5
4
4
4
5
5
4
4
4
5
5
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
VCCQ
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU | SN
NIPDAU
VCCQ
FG
NIPDAU
FG
NIPDAU | SN
NIPDAU | SN
NIPDAU
ZBLW
ZBLW
GR
NIPDAU
GR
NIPDAU | SN
NIPDAU | SN
NIPDAU
VCDQ
VCDQ
FI
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
FI
250
3000 RoHS & Green
250 RoHS & Green
RoHS & Green
NIPDAU
FI
NIPDAU | SN
NIPDAU | SN
NIPDAU
VCFQ
VCFQ
FJ
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
FJ
250
RoHS & Green
NIPDAU
FJ
3000 RoHS & Green
NIPDAU | SN
NIPDAU | SN
VCGQ
VCGQ
250
RoHS & Green
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jan-2023
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV73318PDQNR
TLV73318PDQNR3
TLV73318PDQNT
TLV73325PDBVR
TLV73325PDBVT
TLV73325PDQNR
TLV73325PDQNT
TLV733285PDBVR
TLV733285PDBVT
TLV733285PDQNR
TLV733285PDQNT
TLV73328PDBVR
TLV73328PDBVT
TLV73328PDQNR
TLV73328PDQNR3
TLV73328PDQNT
TLV73330PDBVR
TLV73330PDBVT
TLV73330PDQNR
TLV73330PDQNT
TLV73333PDBVR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
X2SON
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
SOT-23
DQN
DQN
DQN
DBV
DBV
DQN
DQN
DBV
DBV
DQN
DQN
DBV
DBV
DQN
DQN
DQN
DBV
DBV
DQN
DQN
DBV
4
4
4
5
5
4
4
5
5
4
4
5
5
4
4
4
5
5
4
4
5
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
FK
FK
FK
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
250
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
RoHS & Green
NIPDAU | SN
NIPDAU | SN
NIPDAU
VCHQ
VCHQ
FL
NIPDAU
FL
NIPDAU | SN
NIPDAU | SN
NIPDAU
ZDRW
ZDRW
GZ
NIPDAU
GZ
NIPDAU | SN
NIPDAU | SN
NIPDAU
ZDQW
ZDQW
GY
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
GY
250
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
RoHS & Green
NIPDAU
GY
NIPDAU | SN
NIPDAU | SN
NIPDAU
ZDMW
ZDMW
GW
NIPDAU
GW
NIPDAU | SN
VCIQ
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jan-2023
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV73333PDBVT
TLV73333PDQNR
TLV73333PDQNT
ACTIVE
ACTIVE
ACTIVE
SOT-23
X2SON
X2SON
DBV
DQN
DQN
5
4
4
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
VCIQ
FM
Samples
Samples
Samples
3000 RoHS & Green
250 RoHS & Green
NIPDAU
NIPDAU
FM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jan-2023
OTHER QUALIFIED VERSIONS OF TLV733P :
Automotive : TLV733P-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV73310PDBVR
TLV73310PDBVT
TLV73310PDQNR
TLV73310PDQNT
TLV73311PDBVR
TLV73311PDBVT
TLV73311PDQNR
TLV73311PDQNT
TLV73312PDBVR
TLV73312PDBVT
TLV73312PDQNR
TLV73312PDQNR3
TLV73312PDQNT
TLV73315PDBVR
TLV73315PDBVT
TLV73315PDQNR
SOT-23
SOT-23
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
X2SON
SOT-23
SOT-23
X2SON
DBV
DBV
DQN
DQN
DBV
DBV
DQN
DQN
DBV
DBV
DQN
DQN
DQN
DBV
DBV
DQN
5
5
4
4
5
5
4
4
5
5
4
4
4
5
5
4
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
9.5
9.5
8.4
8.4
9.5
9.5
8.4
8.4
8.4
9.5
9.5
8.4
8.4
9.5
3.2
3.2
3.2
3.2
1.4
1.4
0.5
0.5
1.4
1.4
0.5
0.5
1.4
1.4
0.5
0.5
0.5
1.4
1.4
0.5
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q2
Q2
Q3
Q3
Q2
Q2
Q3
Q3
Q2
Q3
Q2
Q3
Q3
Q2
3000
250
1.16
1.16
3.2
1.16
1.16
3.2
3000
250
3.2
3.2
3000
250
1.16
1.16
3.2
1.16
1.16
3.2
3000
250
3.2
3.2
3000
3000
250
1.16
1.16
1.16
3.2
1.16
1.16
1.16
3.2
3000
250
3.2
3.2
3000
1.16
1.16
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV73315PDQNR3
TLV73315PDQNT
TLV73318PDBVR
TLV73318PDBVT
TLV73318PDQNR
TLV73318PDQNR3
TLV73318PDQNT
TLV73325PDBVR
TLV73325PDBVT
TLV73325PDQNR
TLV73325PDQNT
TLV733285PDBVR
TLV733285PDBVT
TLV733285PDQNR
TLV733285PDQNT
TLV73328PDBVR
TLV73328PDBVT
TLV73328PDQNR
TLV73328PDQNR3
TLV73328PDQNT
TLV73330PDBVR
TLV73330PDBVT
TLV73330PDQNR
TLV73330PDQNT
TLV73333PDBVR
TLV73333PDBVT
TLV73333PDQNR
TLV73333PDQNT
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
DQN
DQN
DBV
DBV
DQN
DQN
DQN
DBV
DBV
DQN
DQN
DBV
DBV
DQN
DQN
DBV
DBV
DQN
DQN
DQN
DBV
DBV
DQN
DQN
DBV
DBV
DQN
DQN
4
4
5
5
4
4
4
5
5
4
4
5
5
4
4
5
5
4
4
4
5
5
4
4
5
5
4
4
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
9.5
9.5
8.4
8.4
9.5
9.5
9.5
8.4
8.4
9.5
9.5
8.4
8.4
9.5
9.5
8.4
8.4
9.5
9.5
9.5
8.4
8.4
9.5
9.5
8.4
8.4
9.5
9.5
1.16
1.16
3.2
1.16
1.16
3.2
0.5
0.5
1.4
1.4
0.5
0.5
0.5
1.4
1.4
0.5
0.5
1.4
1.4
0.5
0.5
1.4
1.4
0.5
0.5
0.5
1.4
1.4
0.5
0.5
1.4
1.4
0.5
0.5
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q2
Q3
Q3
Q2
Q3
Q2
Q3
Q3
Q2
Q2
Q3
Q3
Q2
Q2
Q3
Q3
Q2
Q3
Q2
Q3
Q3
Q2
Q2
Q3
Q3
Q2
Q2
3000
250
3.2
3.2
3000
3000
250
1.16
1.16
1.16
3.2
1.16
1.16
1.16
3.2
3000
250
3.2
3.2
3000
250
1.16
1.16
3.2
1.16
1.16
3.2
3000
250
3.2
3.2
3000
250
1.16
1.16
3.2
1.16
1.16
3.2
3000
250
3.2
3.2
3000
3000
250
1.16
1.16
1.16
3.2
1.16
1.16
1.16
3.2
3000
250
3.2
3.2
3000
250
1.16
1.16
3.2
1.16
1.16
3.2
3000
250
3.2
3.2
3000
250
1.16
1.16
1.16
1.16
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV73310PDBVR
TLV73310PDBVT
TLV73310PDQNR
TLV73310PDQNT
TLV73311PDBVR
TLV73311PDBVT
TLV73311PDQNR
TLV73311PDQNT
TLV73312PDBVR
TLV73312PDBVT
TLV73312PDQNR
TLV73312PDQNR3
TLV73312PDQNT
TLV73315PDBVR
TLV73315PDBVT
TLV73315PDQNR
TLV73315PDQNR3
TLV73315PDQNT
SOT-23
SOT-23
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
X2SON
DBV
DBV
DQN
DQN
DBV
DBV
DQN
DQN
DBV
DBV
DQN
DQN
DQN
DBV
DBV
DQN
DQN
DQN
5
5
4
4
5
5
4
4
5
5
4
4
4
5
5
4
4
4
3000
250
210.0
210.0
184.0
184.0
210.0
210.0
184.0
184.0
210.0
210.0
210.0
184.0
184.0
210.0
210.0
184.0
184.0
184.0
185.0
185.0
184.0
184.0
185.0
185.0
184.0
184.0
185.0
185.0
185.0
184.0
184.0
185.0
185.0
184.0
184.0
184.0
35.0
35.0
19.0
19.0
35.0
35.0
19.0
19.0
35.0
35.0
35.0
19.0
19.0
35.0
35.0
19.0
19.0
19.0
3000
250
3000
250
3000
250
3000
250
3000
3000
250
3000
250
3000
3000
250
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2023
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV73318PDBVR
TLV73318PDBVT
TLV73318PDQNR
TLV73318PDQNR3
TLV73318PDQNT
TLV73325PDBVR
TLV73325PDBVT
TLV73325PDQNR
TLV73325PDQNT
TLV733285PDBVR
TLV733285PDBVT
TLV733285PDQNR
TLV733285PDQNT
TLV73328PDBVR
TLV73328PDBVT
TLV73328PDQNR
TLV73328PDQNR3
TLV73328PDQNT
TLV73330PDBVR
TLV73330PDBVT
TLV73330PDQNR
TLV73330PDQNT
TLV73333PDBVR
TLV73333PDBVT
TLV73333PDQNR
TLV73333PDQNT
SOT-23
SOT-23
X2SON
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
DBV
DBV
DQN
DQN
DQN
DBV
DBV
DQN
DQN
DBV
DBV
DQN
DQN
DBV
DBV
DQN
DQN
DQN
DBV
DBV
DQN
DQN
DBV
DBV
DQN
DQN
5
5
4
4
4
5
5
4
4
5
5
4
4
5
5
4
4
4
5
5
4
4
5
5
4
4
3000
250
210.0
210.0
184.0
184.0
184.0
210.0
210.0
184.0
184.0
210.0
210.0
184.0
184.0
210.0
210.0
184.0
184.0
184.0
210.0
210.0
184.0
184.0
210.0
210.0
184.0
184.0
185.0
185.0
184.0
184.0
184.0
185.0
185.0
184.0
184.0
185.0
185.0
184.0
184.0
185.0
185.0
184.0
184.0
184.0
185.0
185.0
184.0
184.0
185.0
185.0
184.0
184.0
35.0
35.0
19.0
19.0
19.0
35.0
35.0
19.0
19.0
35.0
35.0
19.0
19.0
35.0
35.0
19.0
19.0
19.0
35.0
35.0
19.0
19.0
35.0
35.0
19.0
19.0
3000
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 4
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
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EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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