TLV740P_V01 [TI]
TLV740P 300-mA, Low-Dropout Regulator With Foldback Current Limit;
| 型号： | TLV740P_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TLV740P 300-mA, Low-Dropout Regulator With Foldback Current Limit |
| 文件： | 总31页 (文件大小：2429K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV740P
SBVS401A – JUNE 2020 – REVISED DECEMBER 2020
TLV740P 300-mA, Low-Dropout Regulator
With Foldback Current Limit
1 Features
3 Description
•
•
Foldback overcurrent protection
Packages:
– 1-mm × 1-mm, 4-pin X2SON
– 5-pin SOT-23
Very low dropout: 460 mV at 300 mA
Accuracy: 1%
The TLV740P low-dropout (LDO) linear regulator is a
low quiescent current LDO with excellent line and load
transient performance designed for power-sensitive
applications. This device provides a typical accuracy
of 1%.
•
•
•
•
•
The TLV740P also provides inrush current control
during device power up and enabling. The TLV740P
limits the input current to the defined current limit to
avoid large currents from flowing from the input power
source. This functionality is especially important in
battery-operated devices.
Low IQ: 50 µA
Input voltage range: 1.4 V to 5.5 V
Available in fixed-output voltages:
1 V to 3.3 V
High PSRR: 65 dB at 1 kHz
Active output discharge
•
•
The TLV740P is available in standard DQN and DBV
packages. The TLV740P also provides an active
pulldown circuit to quickly discharge output loads.
2 Applications
Device Information (1)
•
•
•
•
•
Portable media players
Standard notebook PCs
Streaming media players
Home printers
DEVICE NAME
TLV740P
PACKAGE
SOT-23 (5)
X2SON (4)
BODY SIZE
2.90 mm × 1.60 mm
1.00 mm × 1.00 mm
STB and DVR
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
0.6
TJ
-40èC
0èC
25èC
85èC
IN
OUT
GND
TLV740P
COUT
CIN
0.4
0.2
0
EN
ON
OFF
Typical Application Circuit
0
30
60
90 120 150 180 210 240 270 300
Output Current (mA)
Dropout Voltage vs Output Current (3.3 VOUT
)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV740P
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SBVS401A – JUNE 2020 – REVISED DECEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................6
7 Detailed Description......................................................11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................11
7.4 Device Functional Modes..........................................14
8 Application and Implementation..................................15
8.1 Application Information............................................. 15
8.2 Typical Application.................................................... 20
8.3 What to Do and What Not to Do............................... 21
9 Power Supply Recommendations................................21
10 Layout...........................................................................22
10.1 Layout Guidelines................................................... 22
10.2 Layout Examples.................................................... 22
11 Device and Documentation Support..........................23
11.1 Device Support........................................................23
11.2 Documentation Support.......................................... 23
11.3 Receiving Notification of Documentation Updates..23
11.4 Support Resources................................................. 23
11.5 Trademarks............................................................. 23
11.6 Electrostatic Discharge Caution..............................23
11.7 Glossary..................................................................23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (June 2020) to Revision A (December 2020)
Page
•
Changed status of DQN package from preview to production data....................................................................1
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5 Pin Configuration and Functions
OUT
1
4
IN
IN
GND
EN
1
2
3
5
OUT
Thermal Pad
4
NC
GND
2
3
EN
Not to scale
Not to scale
Figure 5-1. DQN Package, 4-Pin X2SON, Top View
Figure 5-2. DBV Package, 5-Pin SOT-23, Top View
Table 5-1. Pin Functions
PIN
NO.
SOT-23
I/O
DESCRIPTION
NAME
X2SON
Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low
disables the device. Do not float this pin. If not used, connect EN to IN.
EN
3
2
3
2
I
GND
IN
—
Ground pin. This pin must be connected to ground on the board.
Input pin. For best transient response and to minimize input impedance, use the
recommended value or larger ceramic capacitor from IN to ground; see the Recommended
Operating Conditions table. Place the input capacitor as close to the input of the device as
possible.
4
—
1
1
4
I
No connect pin. This pin is not internally connected. Connect to ground for best thermal
performance or leave floating.
NC
—
O
—
Regulated output pin. A 1-µF or greater effective capacitance is required from OUT to ground
for stability. see the Recommended Operating Conditions table. For best transient response,
use a 1-µF or larger ceramic capacitor from OUT to ground. Place the output capacitor as
close to output of the device as possible.
OUT
5
The thermal pad is electrically connected to the GND pin. Connect the thermal pad to a large-
area GND plane for improved thermal performance.
Thermal pad
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
6.0
UNIT
VIN
Voltage
VEN
VIN(2)
V
VOUT
–0.3 VIN + 0.3 or 3.6(3)
Operating junction, TJ
Storage, Tstg
–55
–55
125
150
Temperature
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Maximum is VIN or smaller.
(3) Maximum is VIN + 0.3 V or 3.6 V, whichever is smaller.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.4
0
NOM
MAX
5.5
UNIT
V
VIN
Input voltage
VOUT
VEN
IOUT
CIN
Output voltage
VIN + 0.3
V
(1)
Enable voltage
0
VIN
V
Output current
0
300
mA
μF
μF
kHz
°C
Input capacitor
1
COUT
fEN
Output capacitor(2)
Enable toggle frequency
Junction temperature
1
100
10
TJ
–40
85
(1) VEN is VIN or smaller.
(2) Effective output capacitance of 0.5 µF minimum required for stability.
6.4 Thermal Information
TLV740P
THERMAL METRIC(1)
DQN (X2SON)
4 PINS
224.3
DBV (SOT-23-5)
5 PINS
216
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
161.5
123.2
164.6
88.2
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
10.9
62.2
ψJB
164.0
87.8
RθJC(bot)
154.8
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at operating temperature range (TJ = +25°C), VIN = VOUT(NOM) + 2.1 V, IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 μF,
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
%
Output accuracy
1 V ≤ VOUT ≤ 3.3 V
–1
1
Maximum output current(1)
300
mA
Output voltage temperature
coefficient
IOUT = 0.1 mA, –40°C ≤ TJ ≤ +85°C
0.0017
%/℃
Line regulation
Load regulation
VOUT(NOM) + 0.5 V ≤ VIN ≤ 5.5 V
1 mA ≤ IOUT ≤ 300 mA
VOUT = 0.95 x
1
5
mV
mV
10
30
VOUT(nom)
1 V ≤ VOUT < 1.8 V, IOUT = 300 mA
1200
700
1300
800
VOUT = 0.95 x
VOUT(nom)
VDO
Dropout voltage
1.8 V ≤ VOUT < 2.1 V, IOUT = 300 mA
2.1 V ≤ VOUT ≤ 3.3 V, IOUT = 300 mA
mV
VOUT = 0.95 x
VOUT(nom)
460
500
IGND
Ground current
IOUT = 0 mA
50
0.1
67
80
1
µA
µA
ISHDN
Shutdown current
VEN ≤ 0.4 V, 3.1 V ≤ VIN ≤ 5.5 V, –40°C ≤ TJ ≤ +85°C
f = 100 Hz
VIN = 5.4 V,
PSRR
Power-supply rejection ratio
VOUT = 3.3 V,
IOUT = 150 mA
f = 10 kHz
f = 1 MHz
45
dB
32
Vn
Output noise voltage
Startup time(2)
BW = 100 Hz to 100 kHz, VOUT = 1.0 V, IOUT = 1 mA
COUT = 1 µF, IOUT = 300 mA
65
µVRMS
µs
tSTR
VHI
100
EN pin high voltage (enabled)
EN pin low voltage (disabled)
Enable pin current
1.0
0
VIN
0.4
V
–40°C ≤ TJ ≤ +85°C
VLO
V
IEN
EN = 5.5 V, –40°C ≤ TJ ≤ +85°C
VIN = 5.5 V, VEN = 0 V
10
nA
Ω
RPULLDOWN
ICL
Pulldown resistance
Output current limit
120
360
mA
mA
ISC
Short circuit current limit
VOUT = 0 V
40
TSD(shutdown) Thermal shutdown temperature Shutdown, temperature increasing
Thermal shutdown reset
158
°C
TSD(reset)
Reset, temperature decreasing
140
temperature
(1) Maximum output current is affected by the PCB layout, metal trace width, number of layers, ambient temperatrue and other
environmental factors. Thermal limitations of the system must be carefully considered.
(2) Startup time = time from EN assertion to 0.95 × VOUT(NOM)
.
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6.6 Typical Characteristics
over operating temperature range (TJ = –40°C to 85°C), VIN = VOUT(nom) + 2.1 V, IOUT = 1 mA, VEN = VIN, and CIN = COUT
1 µF (unless otherwise noted); typical values are at TJ = 25°C
=
10
5
18
14
10
6
TJ
-40èC
0èC
TJ
-40èC
0èC
25èC
85èC
25èC
85èC
2
0
-2
-6
-5
-10
-14
-18
-10
3.3 3.55 3.8 4.05 4.3 4.55 4.8 5.05 5.3 5.5
Input Voltage (V)
0
30
60
90 120 150 180 210 240 270 300
Output Current (mA)
Figure 6-1. Line Regulation vs VIN
Figure 6-2. Load Regulation vs IOUT
1.8
0.6
0.4
0.2
0
TJ
-40èC
0èC
TJ
25èC
85èC
-40èC
0èC
25èC
85èC
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
30
60
90 120 150 180 210 240 270 300
Output Current (mA)
0
30
60
90 120 150 180 210 240 270 300
Output Current (mA)
VOUT = 1.0 V
VOUT = 3.3 V
Figure 6-3. Dropout Voltage vs IOUT
Figure 6-4. Dropout Voltage vs IOUT
5
4.5
4
2.4
2
TJ
-40èC
0èC
TJ
-40èC
0èC
25èC
85èC
25èC
85èC
3.5
3
1.6
1.2
0.8
0.4
0
2.5
2
1.5
1
0.5
1.5
2
2.5
3
Input Voltage (V)
3.5
4
4.5
5
5.5
3
3.25 3.5 3.75
4 4.25 4.5 4.75
Input Voltage (V)
5
5.25 5.5
VOUT = 1.0 V
VOUT = 3.3 V
Figure 6-6. Dropout Voltage vs VIN
Figure 6-5. Dropout Voltage vs VIN
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6.6 Typical Characteristics (continued)
over operating temperature range (TJ = –40°C to 85°C), VIN = VOUT(nom) + 2.1 V, IOUT = 1 mA, VEN = VIN, and CIN = COUT
=
1 µF (unless otherwise noted); typical values are at TJ = 25°C
1.4
2.7
2.25
1.8
TJ
-40èC
0èC
TJ
-40èC
0èC
25èC
85èC
25èC
85èC
1.2
1
0.8
0.6
0.4
0.2
0
1.35
0.9
0.45
0
0
100
200
300
Output Current (mA)
400
500
600
0
100
200
300
Output Current (mA)
400
500
600
VOUT = 1.0 V
VOUT = 1.8 V
Figure 6-7. Foldback Current Limit vs IOUT
Figure 6-8. Foldback Current Limit vs IOUT
4.8
4.2
3.6
3
100
80
60
40
20
0
TJ
-40èC
0èC
TJ
0èC
25èC
85èC
-40èC
25èC
85èC
2.4
1.8
1.2
0.6
0
0
100
200
300
Output Current (mA)
400
500
600
0
0.5
1
1.5
2
2.5
Input Voltage (V)
3
3.5
4
4.5
5
5.5
VOUT = 3.3 V
VOUT = 3.3 V, IOUT = 0 mA
Figure 6-9. Foldback Current Limit vs IOUT
Figure 6-10. IGND vs VIN
140
120
100
80
0.95
0.9
VEN(LOW)
VEN(HIGH)
0.85
0.8
60
0.75
0.7
TJ
-40èC
0èC
25èC
85èC
40
20
0.65
0.6
0
0
30
60
90 120 150 180 210 240 270 300
Output Current (mA)
-60
-35
-10
15
40
65
90
115 140 160
Temperature (èC)
VOUT = 3.3 V
VIN = 5.5 V
Figure 6-11. IGND vs IOUT
Figure 6-12. EN High and Low Threshold vs Temperature
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6.6 Typical Characteristics (continued)
over operating temperature range (TJ = –40°C to 85°C), VIN = VOUT(nom) + 2.1 V, IOUT = 1 mA, VEN = VIN, and CIN = COUT
1 µF (unless otherwise noted); typical values are at TJ = 25°C
=
1.4
1.375
1.35
120
110
100
90
80
70
60
50
40
30
20
10
0
VUVLO(HIGH)
VUVLO(LOW)
IOUT
150 mA
1 mA
300 mA
1.325
1.3
1.275
1.25
-60
-35
-10
15
40
65
90
115 140 160
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
Temperature (èC)
CIN = open, VOUT = 1.0 V
Figure 6-13. UVLO Rising and Falling Threshold vs Temperature
Figure 6-14. PSRR vs Frequency and IOUT
120
120
110
100
90
80
70
60
50
40
30
20
10
0
IOUT
1 mA
IOUT
150 mA
110
300 mA
1 mA
300 mA
100
90
80
70
60
50
40
30
20
10
0
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
CIN = open, VOUT = 1.8 V
Figure 6-15. PSRR vs Frequency and IOUT
CIN = open, VOUT = 3.3 V
Figure 6-16. PSRR vs Frequency and IOUT
10
5.5
70
60
50
40
30
20
10
0
VOUT, VRMS
5
5
4.5
4
1.0 V, 64.7 mVRMS
1.8 V, 75.9 mVRMS
3.3 V, 111.8 mVRMS
2
1
3.5
3
0.5
VIN
VEN
VOUT
0.2
0.1
2.5
2
0.05
1.5
1
-10
-20
-30
-40
0.02
0.01
0.5
0
0.005
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
0
50 100 150 200 250 300 350 400 450 500
Time (ms)
VIN = 3.9 V to 4.9 V, slew rate = 1 V/µs, VEN = 1 V, IOUT = 1 mA
Figure 6-17. Output Noise vs Frequency and VOUT
Figure 6-18. Line Transient
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6.6 Typical Characteristics (continued)
over operating temperature range (TJ = –40°C to 85°C), VIN = VOUT(nom) + 2.1 V, IOUT = 1 mA, VEN = VIN, and CIN = COUT
1 µF (unless otherwise noted); typical values are at TJ = 25°C
=
6
5
4
3
2
1
0
150
100
50
6
5
4
3
2
1
0
150
100
50
VIN
VEN
VOUT
VIN
VEN
VOUT
0
0
-50
-100
-150
-50
-100
-150
0
20
40
60
80
100
0
20
40
60
80
100
Time (ms)
Time (ms)
VIN = 3.9 V to 4.9 V, slew rate = 1 V/µs, VEN = 1 V,
IOUT = 150 mA
VIN = 3.9 V to 4.9 V, slew rate = 1 V/µs, VEN = 1 V,
IOUT = 300 mA
Figure 6-19. Line Transient
Figure 6-20. Line Transient
100
900
750
600
450
300
150
0
50
750
600
450
300
150
0
VOUT
IOUT
VOUT
IOUT
50
0
-50
0
-50
-100
-150
-200
-100
-150
-200
0
50 100 150 200 250 300 350 400 450 500
Time (ms)
0
5
10
15
20
25
Time (ms)
30
35
40
45
50
VIN = 3.9 V, VEN = 1 V, IOUT = 1 mA to 150 mA,
slew rate = 1 A/µs
VIN = 3.9 V, VEN = 1 V, IOUT = 1 mA to 150 mA,
slew rate = 1 A/µs, rising edge
Figure 6-21. Load Transient
Figure 6-22. Load Transient
200
100
0
1400
1200
1000
800
600
400
200
0
100
900
750
600
450
300
150
0
VOUT
IOUT
VOUT
IOUT
0
-100
-200
-300
-400
-500
-100
-200
-300
-400
-500
0
50 100 150 200 250 300 350 400 450 500
Time (ms)
0
5
10
15
20
25
Time (ms)
30
35
40
45
50
VIN = 3.9 V, VEN = 1 V, IOUT = 1 mA to 300 mA,
slew rate = 1 A/µs
VIN = 3.9 V, VEN = 1 V, IOUT = 1 mA to 300 mA,
slew rate = 1 A/µs, rising edge
Figure 6-23. Load Transient
Figure 6-24. Load Transient
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6.6 Typical Characteristics (continued)
over operating temperature range (TJ = –40°C to 85°C), VIN = VOUT(nom) + 2.1 V, IOUT = 1 mA, VEN = VIN, and CIN = COUT
1 µF (unless otherwise noted); typical values are at TJ = 25°C
=
7.5
6.5
5.5
4.5
3.5
2.5
1.5
0.5
-0.5
200
150
100
50
7.5
6.5
5.5
4.5
3.5
2.5
1.5
0.5
-0.5
VIN
VEN
VOUT
IIN
VIN
VEN
VOUT
0
-50
-100
-150
-200
0
200
400
600
800
1000
1200
1400
0
1000
2000
3000
4000
5000
Time (ms)
Time (ms)
VIN = 5.5 V, CIN = open, IOUT = open
VIN = 0 V to 5.5 V to 0 V, IOUT = 150 mA
Figure 6-25. Start-Up With EN, Inrush Current
Figure 6-26. Start-Up and Shutdown
7.5
6.5
5.5
4.5
3.5
2.5
1.5
0.5
VIN
VEN
VOUT
-0.5
0
200
400
Time (ms)
600
800
VIN = 5.5 V, VEN = 1 V to 0 V, IOUT = open
Figure 6-27. Shutdown Response With Enable
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7 Detailed Description
7.1 Overview
The TLV740P is a cost-effective low-dropout (LDO) regulator that consumes low quiescent current and delivers
excellent line and load transient performance. These characteristics make the device ideal for a wide range of
portable applications.
This LDO offers foldback current limit, output enable, active discharge, undervoltage lockout (UVLO), and
thermal protection.
7.2 Functional Block Diagram
Current
Limit
IN
OUT
Bandgap
120 Ω
UVLO
Internal
Controller
Thermal
Shutdown
GND
EN
7.3 Feature Description
7.3.1 Foldback Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a
brickwall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with the
output voltage above VFOLDBACK, the brickwall scheme limits the output current to the current limit (ICL). When
the voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the output
voltage approaches GND. When the output is shorted, the device supplies a typical current called the short-
circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.
For this device, VFOLDBACK = 0.95 V × VOUT(NOM)
.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brickwall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. When the device output is shorted and the output
is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered,
the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on.
If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For
more information on current limits, see the Know Your Limits application report.
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Figure 7-1 shows a diagram of the foldback current limit.
VOUT
Brickwall
VOUT(NOM)
VFOLDBACK
Foldback
0 V
IOUT
IRATED
0 mA
ISC
ICL
Figure 7-1. Foldback Current Limit
7.3.2 Output Enable
The enable pin (EN) is active high. Enable the device by forcing the voltage of the enable pin to exceed the
minimum EN pin high-level input voltage (see the Electrical Characteristics table). Turn off the device by forcing
the voltage of the enable pin to drop below the maximum EN pin low-level input voltage (see the Electrical
Characteristics table). If shutdown capability is not required, connect EN to IN.
This device has an internal pulldown circuit that activates when the device is disabled to actively discharge the
output voltage.
7.3.3 Active Discharge
The device has an internal pulldown MOSFET that connects an RPULLDOWN resistor to ground when the device is
disabled to actively discharge the output voltage. The active discharge circuit is activated by the enable pin.
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current
flow can cause damage to the device. Limit reverse current to no more than 5% of the device rated current for a
short period of time.
7.3.4 Undervoltage Lockout (UVLO) Operation
The UVLO circuit ensures that the device stays disabled before its input supply reaches the minimum
operational voltage range, and ensures that the device shuts down when the input supply collapses. Figure 7-2
illustrates the UVLO circuit response to various input voltage events. The diagram can be separated into the
following parts:
•
•
•
Region A: The device does not start until the input reaches the UVLO rising threshold.
Region B: Normal operation, regulating device.
Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The
output may fall out of regulation but the device remains enabled.
Region D: Normal operation, regulating device.
•
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•
Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the
output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising
threshold is reached by the input voltage and a normal start-up follows.
•
•
Region F: Normal operation followed by the input falling to the UVLO falling threshold.
Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The
output falls because of the load and active discharge circuit.
UVLO Rising Threshold
UVLO Hysteresis
VIN
C
VOUT
tAt
tBt
tDt
tEt
tFt
tGt
Figure 7-2. Typical UVLO Operation
7.3.5 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. The following equation calculates the RDS(ON) of the device.
VDO
RDS(ON)
=
IRATED
(1)
7.3.6 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).
The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when
thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can be high
from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output
capacitors. Under some conditions, the thermal shutdown protection disables the device before startup
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed its operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
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7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
The Device Functional Mode Comparison table shows the conditions that lead to the different modes of
operation. See the Electrical Characteristics table for parameter values.
Table 7-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal operation
Dropout operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
VIN(min) < VIN < VOUT(nom) + VDO
VEN > VEN(HI)
VEN > VEN(HI)
IOUT < IOUT(max)
IOUT < IOUT(max)
TJ < TSD(shutdown)
TJ < TSD(shutdown)
Disabled
(any true condition
disables the device)
VIN < VUVLO
VEN < VEN(LOW)
Not applicable
TJ > TSD(shutdown)
7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The output current is less than the current limit (IOUT < ICL)
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD
)
•
The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased
to less than the enable falling threshold
7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO
,
directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN
pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned
off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal
discharge circuit from the output to ground.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and
are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and
temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input
and output capacitors recommended in the Recommended Operating Conditions table account for an effective
capacitance of approximately 50% of the nominal value.
8.1.2 Input and Output Capacitor Requirements
The device requires an input capacitor of 1.0 µF or larger, as specified in the Recommended Operating
Conditions table for stability. A higher value capacitor may be necessary if large, fast rise-time load or line
transients are anticipated or if the device is located several inches from the input power source.
The device also requires an output capacitor of 1.0 µF or larger, as specified in the Recommended Operating
Conditions table for stability. Dynamic performance of the device is improved by using a higher capacitor than
the minimum output capacitor.
8.1.3 Dropout Voltage
The device uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(on) of the PMOS pass element. VDO scales approximately with output current because the PMOS device
behaves like a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as
(VIN – VOUT) approaches dropout.
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8.1.4 Exiting Dropout
Some applications have transients that place the LDO into dropout, such as slower ramps on VIN during start-up.
As with other LDOs, the output can overshoot on recovery from these conditions. A ramping input supply causes
an LDO to overshoot on start-up, as shown in Figure 8-1, when the slew rate and voltage levels are in the
correct range. Use an enable signal to delay the LDO startup to avoid VOUT overshoot resulting from dropout
exit. The enable signal can be set high after VIN is greater than VOUT(nom)
.
Input Voltage
Response time for
LDO to get back into
regulation.
Load current discharges
output voltage.
VIN = VOUT(nom) + VDO
Output Voltage
Dropout
VOUT = VIN - VDO
Output Voltage in
normal regulation.
Time
Figure 8-1. Start-Up Into Dropout
Line transients out of dropout can also cause overshoot on the output of the regulator. These overshoots are
caused by the error amplifier having to drive the gate capacitance of the pass element and bring the gate back to
the correct voltage for proper regulation. Figure 8-2 illustrates what is happening internally with the gate voltage
and how overshoot can be caused during operation. When the LDO is placed in dropout, the gate voltage (VGS
)
is pulled all the way down to ground to give the pass device the lowest on-resistance as possible. However, if a
line transient occurs when the device is in dropout, the loop is not in regulation and can cause the output to
overshoot until the loop responds and the output current pulls the output voltage back down into regulation. If
these transients are not acceptable, then continue to add input capacitance in the system until the transient is
slow enough to reduce the overshoot.
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Transient response
time of the LDO
Input Voltage
Load current
discharges
output
voltage
Output Voltage
VDO
Output Voltage in
normal regulation
Dropout
VOUT = VIN - VDO
VGS voltage
(pass device
fully off)
Input Voltage
VGS voltage for
normal operation
VGS voltage for
normal operation
Gate Voltage
VGS voltage in
dropout (pass device
fully on)
Time
Figure 8-2. Line Transients From Dropout
8.1.5 Transient Response
As with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude but
increases the duration of the transient response.
8.1.6 Reverse Current
As with most LDOs, excessive reverse current can damage this device.
Reverse current flows through the body diode on the pass element instead of the normal conducting channel. At
high magnitudes, this current flow degrades the long-term reliability of the device, as a result of one of the
following conditions:
•
•
•
Degradation caused by electromigration
Excessive heat dissipation
Potential for a latch-up condition
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Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT > VIN + 0.3 V:
•
•
•
If the device has a large COUT and the input supply collapses with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply
If reverse current flow is expected in the application, external protection must be used to protect the device.
Figure 8-3 shows one approach of protecting the device.
Schottky Diode
Internal Body Diode
IN
OUT
Device
COUT
CIN
GND
Figure 8-3. Example Circuit for Reverse Current Protection Using a Schottky Diode
8.1.7 Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. Use Equation 2 to approximate PD:
PD = (VIN – VOUT) × IOUT
(2)
Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system
voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low
dropout of the TLV740P allows for maximum efficiency across a wide range of output voltages.
The main heat conduction path for the device is through the thermal pad on the DQN package. As such, the
thermal pad must be soldered to a copper pad area under the device. This pad area contains an array of plated
vias that conduct heat to any inner plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
According to Equation 3, power dissipation and junction temperature are most often related by the junction-to-
ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient
air (TA). Equation 4 rearranges Equation 3 for output current.
TJ = TA + (RθJA × PD)
(3)
(4)
IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)]
Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
planes. The RθJA recorded in the Recommended Operating Conditions table is determined by the JEDEC
standard, PCB, and copper-spreading area, and is only used as a relative measure of package thermal
performance. For a well-designed thermal layout, RθJA is actually the sum of the X2SON package junction-to-
case (bottom) thermal resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper.
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8.1.7.1 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are used in accordance with Equation 5 and are given in the Recommended Operating Conditions table.
ΨJT : TJ = TT + ΨJT × PD and ΨJB : TJ = TB + ΨJB × PD
(5)
where:
•
•
•
PD is the power dissipated as explained in Equation 2
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
8.1.7.2 Recommended Area for Continuous Operation
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input
voltage. The recommended area for continuous operation for a linear regulator is given in Figure 8-4 and can be
separated into the following parts:
•
•
•
Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a
given output current level. See the Dropout Voltage section for more details.
The rated output currents limits the maximum recommended output current level. Exceeding this rating
causes the device to fall out of specification.
The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating
causes the device to fall out of specification and reduces long-term reliability.
– The shape of the slope is given by Equation 4. The slope is nonlinear because the maximum rated
junction temperature of the LDO is controlled by the power dissipation across the LDO; thus when VIN
VOUT increases the output current must decrease.
–
•
The rated input voltage range governs both the minimum and maximum of VIN – VOUT.
Figure 8-4 shows the recommended area of operation for this device on a JEDEC-standard high-K board with a
RθJA as given in the Recommended Operating Conditions table.
Output current limited
by dropout
Rated output
current
Output current limited by thermals
Limited by
minimum VIN
Limited by
maximum VIN
VIN œ VOUT (V)
Figure 8-4. Region Description of Continuous Operation Regime
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8.2 Typical Application
VIN
VOUT
IN
OUT
IN
OUT
CIN
COUT
COUT
DC/DC
Converter
TLV740P
GND GND
EN
GND
GND
VEN
GND
GND
Figure 8-5. Operation From a DC/DC Converter
8.2.1 Design Requirements
Table 8-1 summarizes the design requirement for this application.
Table 8-1. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
Output voltage
Output load
3.9 V
1.8 V
30 mA
1 µF
Output Capacitor
8.2.2 Detailed Design Procedure
For this design example, the 1.8-V output voltage device is selected. The device is powered by DC/DC converter
connected to a battery. A 2.1-V headroom between VIN and VOUT is used to keep the device within the dropout
voltage specification and to ensure the device stays in regulation under all load conditions for this design.
8.2.3 Application Curves
5.5
5
70
60
50
40
30
20
10
0
5.5
5
120
100
80
4.5
4
4.5
4
60
3.5
3
3.5
3
40
VIN
VEN
VOUT
VIN
VEN
VOUT
20
2.5
2
2.5
2
0
-20
-40
-60
-80
1.5
1
-10
-20
-30
-40
1.5
1
0.5
0
0.5
0
50 100 150 200 250 300 350 400 450 500
Time (ms)
0
20
40
60
80
100
Time (ms)
Figure 8-6. VIN Line Transient, IOUT = 1 mA
Figure 8-7. VIN Line Transient, IOUT = 30 mA
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8.3 What to Do and What Not to Do
Place at least one 1-µF ceramic capacitor as close as possible to the OUT pin of the regulator for best transient
performance.
Place at least one 1-µF capacitor as close as possible to the IN pin for best transient performance.
Do not place the output capacitor more than 10 mm away from the regulator.
Do not exceed the absolute maximum ratings.
Do not continuously operate the device in current limit or near thermal shutdown.
9 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 1.4 V to 5.5 V. The input supply must
be well regulated and free of spurious noise. To ensure that the output voltage is well regulated and dynamic
performance is optimum, the input supply must be at least VOUT(nom) + 2.1 V. TI requires using a 1 µF or greater
input capacitor to reduce the impedance of the input supply, especially during transients.
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10 Layout
10.1 Layout Guidelines
•
•
•
•
Place input and output capacitors as close to the device as possible.
Use copper planes for device connections, in order to optimize thermal performance.
Place thermal vias around the device to distribute the heat.
Only place tented thermal vias directly beneath the thermal pad of the DQN package. An untented via can
wick solder or solder paste away from the thermal pad joint during the soldering process, leading to a
compromised solder joint on the thermal pad.
10.2 Layout Examples
OUT
IN
VOUT
VIN
COUT
PAD
CIN
EN
GND
GND PLANE
Represents via used for
application-specific connections
Figure 10-1. Layout Example for the DQN Package
VIN
VOUT
OUT
IN
CIN
COUT
GND
EN
NC
GND PLANE
Represents via used for
application-specific connections
Figure 10-2. Layout Example for the DBV Package
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Device Nomenclature
Table 11-1. Ordering Information (1) (2)
PRODUCT
VO
XX(X) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used
in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 175 = 1.75 V).
P is optional; devices with P have an LDO regulator with an active output discharge.
YYY is the package designator.
TLV740xx(x)Pyyyz
Z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
(2) Output voltages from 1.0 V to 3.3 V in 50-mV increments are available. Contact the factory for details and availability.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
•
Texas Instruments, Universal Low-Dropout (LDO) Linear Voltage Regulator MultiPkgLDOEVM-823 Evaluation
Module user's guide
•
Texas Instruments, Using New Thermal Metrics application report
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV74010PDBVR
TLV74010PDQNR
ACTIVE
SOT-23
X2SON
DBV
DQN
5
4
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Call TI
-40 to 125
-40 to 125
74010
74018
74033
PREVIEW
3000 RoHS (In work)
& Non-Green
Call TI
Call TI
TLV74012PDQNR
PREVIEW
X2SON
DQN
4
3000 RoHS (In work)
& Non-Green
Call TI
-40 to 125
TLV74018PDBVR
TLV74018PDQNR
ACTIVE
SOT-23
X2SON
DBV
DQN
5
4
3000 RoHS & Green
NIPDAU
Call TI
Level-1-260C-UNLIM
Call TI
-40 to 125
-40 to 125
PREVIEW
3000 RoHS (In work)
& Non-Green
TLV74028PDQNR
PREVIEW
X2SON
DQN
4
3000 RoHS (In work)
& Non-Green
Call TI
Call TI
-40 to 125
TLV74033PDBVR
TLV74033PDQNR
ACTIVE
SOT-23
X2SON
DBV
DQN
5
4
3000 RoHS & Green
NIPDAU
Call TI
Level-1-260C-UNLIM
Call TI
-40 to 125
-40 to 125
PREVIEW
3000 RoHS (In work)
& Non-Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Dec-2020
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Dec-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV74010PDBVR
TLV74018PDBVR
TLV74033PDBVR
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
5
5
5
3000
3000
3000
180.0
180.0
180.0
8.4
8.4
8.4
3.2
3.2
3.2
3.2
3.2
3.2
1.4
1.4
1.4
4.0
4.0
4.0
8.0
8.0
8.0
Q3
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Dec-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV74010PDBVR
TLV74018PDBVR
TLV74033PDBVR
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
5
5
5
3000
3000
3000
210.0
210.0
210.0
185.0
185.0
185.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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