TLV74212PDQNR [TI]
200mA、低 IQ、低压降稳压器 | DQN | 4 | -40 to 125;
| 型号： | TLV74212PDQNR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 200mA、低 IQ、低压降稳压器 | DQN | 4 | -40 to 125 稳压器 |
| 文件： | 总31页 (文件大小：1233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV742P
ZHCSGP8 –SEPTEMBER 2017
TLV742P 200mA 小尺寸低压降线性稳压器
1 特性
3 说明
1
•
•
输入电压范围：2V 至 5.5V
TLV742P 系列低压降线性稳压器 (LDO) 经过优化，能
够通过支持宽输出电压范围提供出色的性能。这些
LDO 可将单节锂离子电池的输入至输出电压直接调节
为低至 0.85V。如果此器件用于对直流/直流转换器输
出进行后期调节，则其在 1MHz 下的 55dB 高 PSRR
可抑制纹波，从而提供低噪声且良好调节的稳定
可提供 0.85V 至 5V 范围（以 50mV 为增量）内的
固定输出电压组合(1)
•
•
典型精度为 0.5%
高 PSRR：
–
1MHz 时为 55dB
•
•
•
•
•
启用时的 IQ：25µA
禁用时的 IQ：1µA
有源输出放电
VOUT
。
TLV742P 具备有源输出放电特性，有助于在系统处于
禁用状态、待机模式或睡眠模式时确保输出保持低电
平。此外，该器件的过流保护功能可在输出短路的情况
下保护器件，并且其热关断功能可防止过热。
热关断保护和过流保护
封装：
–
1mm × 1mm DQN (X2SON)
TLV742P 系列稳压器采用 1mm × 1mm X2SON 封
装，因此可最大限度减少 PCB 面积。
2 应用
•
•
•
•
•
销售终端
器件信息(1)
摄像头和机器视觉模块
游戏和玩具
器件型号
TLV742P
封装
X2SON (4)
封装尺寸（标称值）
1.00mm x 1.00mm
楼宇自动化和视频监控
电视和机顶盒
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
典型应用电路
VIN
VOUT
IN
OUT
1 µF
Ceramic
CIN
COUT
TLV742P
GND
On
EN
Off
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBVS323
TLV742P
ZHCSGP8 –SEPTEMBER 2017
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
8
9
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application .................................................. 15
8.3 Do's and Don'ts....................................................... 18
Power Supply Recommendations...................... 19
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagrams ..................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 14
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 20
10.3 Thermal Considerations........................................ 20
10.4 Power Dissipation ................................................. 20
11 器件和文档支持 ..................................................... 21
11.1 器件支持 ............................................................... 21
11.2 接收文档更新通知 ................................................. 21
11.3 社区资源................................................................ 21
11.4 商标....................................................................... 21
11.5 静电放电警告......................................................... 21
11.6 Glossary................................................................ 21
12 机械、封装和可订购信息....................................... 22
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2017 年 9 月
*
初始发行版。
2
Copyright © 2017, Texas Instruments Incorporated
TLV742P
www.ti.com.cn
ZHCSGP8 –SEPTEMBER 2017
5 Pin Configuration and Functions
DQN Package
4-Pin X2SON With Exposed Thermal Pad
Top View
IN
4
EN
3
Thermal
Pad
1
2
OUT
GND
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the
regulator into shutdown mode.
For TLV742P, output voltage is discharged through an internal 120-Ω resistor when device is
shut down.
EN
3
I
GND
IN
2
4
—
I
Ground pin
Input pin. For good transient performance, place a small 1-µF ceramic capacitor from this pin to
ground. See Input and Output Capacitor Requirements for more details.
Regulated output voltage pin. A small 1-μF ceramic capacitor is required from this pin to ground
to ensure stability. See Input and Output Capacitor Requirements for more details.
OUT
1
O
Thermal
pad
The thermal pad is electrically connected to the GND node. Connect to the GND plane for
improved thermal performance.
—
—
Copyright © 2017, Texas Instruments Incorporated
3
TLV742P
ZHCSGP8 –SEPTEMBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
IN
6
6
6
V
V
V
Voltage(2)
EN
OUT
OUT
Current (source)
Internally limited
Indefinite
Output short-circuit duration
Operating junction, TJ
Storage, Tstg
–55
–55
150
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to GND pin.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM) QSS 009-105 (JESD22-A114A)(1)
Charged device model (CDM) QSS 009-147 (JESD22-C101B.01)(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
2
NOM
MAX
UNIT
VIN
IOUT
TJ
Input voltage
5.5
200
125
V
Output current
0
mA
°C
Operating junction temperature range
–40
6.4 Thermal Information
TLV742P
THERMAL METRIC(1)
DQN (X2SON)
4 PINS
180.4
152
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
117.2
5.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
117
RθJC(bot)
99.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2017, Texas Instruments Incorporated
TLV742P
www.ti.com.cn
ZHCSGP8 –SEPTEMBER 2017
6.5 Electrical Characteristics
at VIN = VOUT(NOM) + 0.5 V or 2 V (whichever is greater); IOUT = 1 mA, VEN = VIN, COUT = 0.47 μF, and TJ = –40°C to +85°C.
Typical values are at TJ = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input voltage
range
VIN
2
5.5
V
Output voltage
range
0.85
5
V
VOUT
0.5%
DC output
accuracy
V
OUT ≥ 0.85 V
–1.5%
1.5%
5
ΔVO(ΔVI)
ΔVO(ΔIO)
Line regulation
Load regulation
1
10
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
0 mA ≤ IOUT ≤ 150 mA
20
IOUT = 30 mA
IOUT = 150 mA
IOUT = 30 mA
IOUT = 150 mA
IOUT = 30 mA
IOUT = 150 mA
IOUT = 30 mA
IOUT = 150 mA
65
2 V < VOUT ≤ 2.4 V
2.4 V < VOUT ≤ 2.8 V
2.8 V < VOUT ≤ 3.3 V
3.3 V < VOUT ≤ 5 V
325
50
360
300
270
250
45
V(DO)
Dropout voltage
VIN = 0.98 × VOUT(NOM)
220
40
200
250
450
Output current
limit
ICL
VOUT = 0.9 × VOUT(NOM)
240
300
mA
Ground pin
current
I(GND)
IOUT = 0 mA
VEN = 5.5 V
25
0.01
1
50
µA
µA
µA
I(EN)
EN pin current
VEN ≤ 0.4 V
2 V ≤ VIN ≤ 4.5 V
ISHUTDOWN
Shutdown current
EN pin low-level
input voltage
(disable device)
VIL(EN)
0
0.4
VIN
V
V
EN pin high-level
input voltage
VIH(EN)
0.9
(enable device)
f = 100 Hz
f = 10 kHz
f = 1 MHz
70
55
55
VIN = 3.3 V
VOUT = 2.8 V
IOUT = 30 mA
Power-supply
rejection ratio
PSRR
dB
BW = 100 Hz to 100 kHz,
VIN = 2.3 V
VOUT = 1.8 V
Output noise
voltage
Vn
45
µVRMS
IOUT = 10 mA
COUT = 1 µF
IOUT = 150 mA
tSTR
Startup time(1)
Pulldown
100
120
µs
RPULLDOWN resistance
(TLV742P only)
Ω
Operating
junction
TJ
–40
125
°C
temperature
(1) Start-up time = time from EN assertion to 0.98 × VOUT
.
版权 © 2017, Texas Instruments Incorporated
5
TLV742P
ZHCSGP8 –SEPTEMBER 2017
www.ti.com.cn
6.6 Typical Characteristics
at TJ = –40°C to +85°C, VIN = VOUT(NOM) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA, VEN = VIN, and COUT = 1 µF
Typical values are at TJ = 25°C, (unless otherwise noted)
1.3
1.28
1.26
1.24
1.22
1.2
2.9
2.88
2.86
2.84
2.82
2.8
1.18
1.16
1.14
1.12
1.1
2.78
2.76
2.74
2.72
2.7
85°C
25°C
-40°C
85°C
25°C
-40°C
0
2
2
20
40
60
80 100 120 140 160 180 200
Output Current (mA)
0
20
40
60
80 100 120 140 160 180 200
Output Current (mA)
VOUT = 1.2 V
VOUT = 2.8 V
图 1. Load Regulation
图 2. Load Regulation
1.3
1.28
1.26
1.24
1.22
1.2
2.9
2.88
2.86
2.84
2.82
2.8
1.18
1.16
1.14
1.12
1.1
2.78
2.76
2.74
2.72
2.7
85°C
25°C
-40°C
85°C
25°C
-40°C
2.5
3
3.5
4
4.5
5
5.5
3.1
3.7
4.3
4.9
5.5
Input Voltage (V)
Input Voltage (V)
VOUT = 1.2 V, IOUT = 10 mA
VOUT = 2.8 V, IOUT = 10 mA
图 3. Line Regulation
图 4. Line Regulation
1.3
1.28
1.26
1.24
1.22
1.2
2.9
2.88
2.86
2.84
2.82
2.8
1.18
1.16
1.14
1.12
1.1
2.78
2.76
2.74
2.72
2.7
85°C
25°C
-40°C
85°C
25°C
-40°C
2.5
3
3.5
4
4.5
5
5.5
3.1
3.7
4.3
4.9
5.5
Input Voltage (V)
Input Voltage (V)
VOUT = 1.2 V, IOUT = 150 mA
VOUT = 2.8 V, IOUT = 150 mA
图 5. Line Regulation
图 6. Line Regulation
6
版权 © 2017, Texas Instruments Incorporated
TLV742P
www.ti.com.cn
ZHCSGP8 –SEPTEMBER 2017
Typical Characteristics (接下页)
at TJ = –40°C to +85°C, VIN = VOUT(NOM) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA, VEN = VIN, and COUT = 1 µF
Typical values are at TJ = 25°C, (unless otherwise noted)
1.3
1.28
1.26
1.24
1.22
1.2
2.9
2.88
2.86
2.84
2.82
2.8
1.18
1.16
1.14
1.12
1.1
2.78
2.76
2.74
2.72
2.7
IOUT = 10 mA
IOUT = 150 mA
IOUT = 10 mA
IOUT = 150 mA
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
VOUT = 1.2 V
VOUT = 2.8 V
图 7. Output Voltage vs Temperature
图 8. Output Voltage vs Temperature
400
350
300
250
200
150
100
50
600
500
400
300
200
100
0
85°C
25°C
-40°C
85°C
25°C
-40°C
0
2
2.5
3
3.5
4
4.5
5
2
2.5
3
3.5
4
4.5
5
Input Voltage (V)
Input Voltage (V)
IOUT = 150 mA
图 9. Dropout Voltage vs Input Voltage
IOUT = 200 mA
图 10. Dropout Voltage vs Input Voltage
35
30
25
20
15
10
5
350
300
250
200
150
100
50
85°C
85°C
25°C
-40°C
25°C
-40°C
0
0
2
2.5
3
3.5
4
4.5
5
5.5
0
20
40
60
80 100 120 140 160 180 200
Output Current (mA)
Input Voltage (V)
VOUT = 1.2 V, IOUT = 0 mA
图 12. Ground Pin Current vs Input Voltage
VOUT = 2.8 V
图 11. Dropout Voltage vs Output Current
版权 © 2017, Texas Instruments Incorporated
7
TLV742P
ZHCSGP8 –SEPTEMBER 2017
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Typical Characteristics (接下页)
at TJ = –40°C to +85°C, VIN = VOUT(NOM) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA, VEN = VIN, and COUT = 1 µF
Typical values are at TJ = 25°C, (unless otherwise noted)
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
85°C
25°C
-40°C
0
0
3.1
-40
0
3.7
4.3
4.9
5.5
-40
-15
10
35
60
85
Input Voltage (V)
Temperature (°C)
VOUT = 2.8 V, IOUT = 0 mA
图 13. Ground Pin Current vs Input Voltage
VOUT = 1.2 V, IOUT = 0 mA
图 14. Ground Pin Current vs Temperature
40
35
30
25
20
15
10
5
1200
1000
800
600
400
200
0
85°C
25°C
-40°C
0
-15
10
35
60
85
0
20
40
60
80 100 120 140 160 180 200
Output Current (mA)
Temperature (°C)
VOUT = 2.8 V, IOUT = 0 mA
图 15. Ground Pin Current vs Temperature
VOUT = 1.2 V
图 16. Ground Pin Current vs Output Current
1200
1000
800
600
400
200
0
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
85°C
85°C
25°C
-40°C
25°C
-40°C
20
40
60
80 100 120 140 160 180 200
Output Current (mA)
2
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
VOUT = 2.8 V
图 17. Ground Pin Current vs Output Current
VOUT = 1.2 V
图 18. Shutdown Current vs Input Voltage
8
版权 © 2017, Texas Instruments Incorporated
TLV742P
www.ti.com.cn
ZHCSGP8 –SEPTEMBER 2017
Typical Characteristics (接下页)
at TJ = –40°C to +85°C, VIN = VOUT(NOM) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA, VEN = VIN, and COUT = 1 µF
Typical values are at TJ = 25°C, (unless otherwise noted)
450
425
400
375
350
325
300
275
250
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
85°C
25°C
-40°C
25°C
-40°C
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
Input Voltage (V)
VOUT = 1.2 V
VOUT = 2.8 V
图 20. Current Limit vs Input Voltage
图 19. Shutdown Current vs Input Voltage
450
425
400
375
350
325
300
275
250
90
80
70
60
50
40
30
20
10
0
25°C
-40°C
IOUT = 30 mA
IOUT = 150 mA
3.1
3.7
4.3
4.9
5.5
10
100
1k
10k
100k
1M
10M
Input Voltage (V)
Frequency (Hz)
VOUT = 2.8 V
VOUT = 1.2 V
图 22. Power-Supply Ripple Rejection vs Frequency
图 21. Current Limit vs Input Voltage
90
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
IOUT = 30 mA
IOUT = 150 mA
1 kHz
1 MHz
10
100
1k
10k
100k
1M
10M
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Frequency (Hz)
Input Voltage (V)
VOUT = 2.8 V
图 23. Power-Supply Ripple Rejection vs Frequency
VOUT = 2.8 V, IOUT = 30 mA
图 24. Power-Supply Ripple Rejection vs Input Voltage
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ZHCSGP8 –SEPTEMBER 2017
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Typical Characteristics (接下页)
at TJ = –40°C to +85°C, VIN = VOUT(NOM) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA, VEN = VIN, and COUT = 1 µF
Typical values are at TJ = 25°C, (unless otherwise noted)
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
1 kHz
1 kHz
1 MHz
1 MHz
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.6
3.7
3.8
3.9
4
4.1
4.2
4.3
Input Voltage (V)
Input Voltage (V)
VOUT = 2.8 V, IOUT = 150 mA
VOUT = 3.3 V, IOUT = 30 mA
图 25. Power-Supply Ripple Rejection vs Input Voltage
图 26. Power-Supply Ripple Rejection vs Input Voltage
70
100
5 V
2.8 V
60
50
40
30
20
10
1
1.2 V
0.1
0.01
0.001
10
0
1 kHz
1 MHz
3.6
3.7
3.8
3.9
4
4.1
4.2
4.3
10
100
1k
10k
100k
1M
10M
Input Voltage (V)
Frequency (Hz)
VOUT = 3.3 V, IOUT = 150 mA
图 27. Power-Supply Ripple Rejection vs Input Voltage
图 28. Output Spectral Noise Density vs Frequency
150 mA
150 mA
IOUT
IOUT
50 mA
1 mA
VOUT
VOUT
Time (100 ms/div)
Time (100 ms/div)
VOUT = 1.2 V
VOUT = 1.2 V
图 30. Load Transient Response
图 29. Load Transient Response
10
版权 © 2017, Texas Instruments Incorporated
TLV742P
www.ti.com.cn
ZHCSGP8 –SEPTEMBER 2017
Typical Characteristics (接下页)
at TJ = –40°C to +85°C, VIN = VOUT(NOM) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA, VEN = VIN, and COUT = 1 µF
Typical values are at TJ = 25°C, (unless otherwise noted)
100 mA
150 mA
IOUT
50 mA
IOUT
1 mA
VOUT
VOUT
Time (100 ms/div)
Time (100 ms/div)
VOUT = 2.8 V
VOUT = 2.8 V
图 31. Load Transient Response
图 32. Load Transient Response
VIN
VIN
VOUT
VOUT
Time (100 ms/div)
Time (100 ms/div)
VOUT = 1.2 V, IOUT = 150 mA
VOUT = 1.2 V, IOUT = 200 mA
图 33. Line Transient Response
图 34. Line Transient Response
VIN
VIN
VOUT
VOUT
Time (100 ms/div)
Time (100 ms/div)
VOUT = 1.2 V, IOUT = 150 mA
VOUT = 1.2 V, IOUT = 200 mA
图 35. Line Transient Response
图 36. Line Transient Response
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ZHCSGP8 –SEPTEMBER 2017
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Typical Characteristics (接下页)
at TJ = –40°C to +85°C, VIN = VOUT(NOM) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA, VEN = VIN, and COUT = 1 µF
Typical values are at TJ = 25°C, (unless otherwise noted)
VIN
VIN
VOUT
VOUT
Time (100 ms/div)
Time (100 ms/div)
VOUT = 2.8 V, IOUT = 150 mA
VOUT = 2.8 V, IOUT = 200 mA
图 37. Line Transient Response
图 38. Line Transient Response
VIN
VI
VOUT
VO
Time (100 ms/div)
Time (100 ms/div)
VOUT = 2.8 V, IOUT = 200 mA
VOUT = 2.8 V, IOUT = 200 mA
图 39. Line Transient Response
图 40. Line Transient Response
VIN
VIN
VOUT
VOUT
Time (100 ms/div)
Time (100 ms/div)
VOUT = 1.2 V, IOUT = 30 mA
VOUT = 2.8 V, IOUT = 30 mA
图 41. VIN Ramp Up, Ramp Down Response
图 42. VIN Ramp Up, Ramp Down Response
12
版权 © 2017, Texas Instruments Incorporated
TLV742P
www.ti.com.cn
ZHCSGP8 –SEPTEMBER 2017
7 Detailed Description
7.1 Overview
The TLV742P device belongs to a family of LDOs. This device consumes low quiescent current and delivers
excellent line and load transient performance. These characteristics [combined with low noise and very good
PSRR with little (VIN – VOUT) headroom] make this device ideal for portable RF applications.
7.2 Functional Block Diagrams
IN
OUT
Current
Limit
Thermal
Shutdown
120 W
Band Gap
EN
LOGIC
TLV742P
GND
Copyright © 2017, Texas Instruments Incorporated
图 43. TLV742P Block Diagram
7.3 Feature Description
This LDO regulator offers current limit and thermal protection. The operating junction temperature of this device
is –40°C to +125°C.
7.3.1 Internal Current Limit
The internal current limit helps to protect the regulator during fault conditions. During current limit, the output
sources a fixed amount of current that is largely independent of the output voltage. In such a case, the output
voltage is not regulated, and is VOUT = ICL × RL. The PMOS pass transistor dissipates (VIN – VOUT) × ILIMIT until
thermal shutdown is triggered and the device turns off. When the device cools, the internal thermal shutdown
circuit turns the device back on. If the fault condition continues, the device cycles between current limit and
thermal shutdown; see Thermal Information for more details.
The PMOS pass element has a built-in body diode that conducts current when the voltage at OUT exceeds the
voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting
to 5% of the rated output current is recommended.
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13
TLV742P
ZHCSGP8 –SEPTEMBER 2017
www.ti.com.cn
Feature Description (接下页)
7.3.2 Shutdown
The enable pin (EN) is active high. The device is enabled when voltage at the EN pin goes above 0.9 V. The
device is turned off when the EN pin is held at less than 0.4 V. When shutdown capability is not required, EN can
be connected to the IN pin.
The TLV742P version has internal active pulldown circuitry that discharges the output with a time constant as
given by 公式 1:
(120 · RL)
t =
· COUT
(120 + RL)
where:
•
•
RL = Load resistance
COUT = Output capacitor
(1)
7.4 Device Functional Modes
The TLV742P series is specified over the recommended operating conditions (see Recommended Operating
Conditions). The specifications may not be met when exposed to conditions outside of the recommended
operating range.
To turn on the regulator, the EN pin must be driven over 0.9 V. Driving the EN pin below 0.4 V causes the
regulator to enter shutdown mode.
In shutdown, the current consumption of the device typically reduces to 1 µA.
14
版权 © 2017, Texas Instruments Incorporated
TLV742P
www.ti.com.cn
ZHCSGP8 –SEPTEMBER 2017
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV742P is a LDO with low quiescent current that delivers excellent line and load transient performance.
This LDO regulator offers current limit and thermal protection. The operating junction temperature of this device
series is –40°C to +125°C.
8.2 Typical Application
VIN
VOUT
IN
OUT
1 µF
Ceramic
CIN
COUT
TLV742P
GND
On
EN
Off
Copyright © 2017, Texas Instruments Incorporated
图 44. Typical Application Circuit
8.2.1 Design Requirements
Provide an input supply with adequate headroom to meet minimum VIN requirements (as listed in 表 1),
compensate for the GND pin current, and to power the load.
表 1. Design Parameters
PARAMETER
Input voltage
Output voltage
Output current
DESIGN REQUIREMENT
1.8 V to 3.6 V
1.2 V
100 mA
版权 © 2017, Texas Instruments Incorporated
15
TLV742P
ZHCSGP8 –SEPTEMBER 2017
www.ti.com.cn
8.2.2 Detailed Design Procedure
8.2.2.1 Input and Output Capacitor Requirements
Generally, 1-µF X5R- and X7R-type ceramic capacitors are recommended because these capacitors have
minimal variation in value and equivalent series resistance (ESR) over temperature.
However, the TLV742P is designed to be stable with an effective capacitance of 0.1 µF or larger at the output.
As a result, the device is stable with capacitors of other dielectric types if the effective capacitance under
operating bias voltage and temperature is greater than 0.1 µF. This effective capacitance refers to the
capacitance that the LDO detects under operating bias voltage and temperature conditions; that is, the
capacitance after taking bias voltage and temperature derating into consideration. In addition to using less
expensive dielectrics, this stability with 0.1-µF effective capacitance enables the use of smaller footprint
capacitors that have higher derating in size- and space-constrained applications.
Using a 0.1-µF rated capacitor at the output of the LDO does not ensure stability because the effective
capacitance under the specified operating conditions is less than 0.1 µF. Maximum ESR must be less than
200 mΩ.
Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-µF to
1-µF, low ESR capacitor across the IN pin and GND pin of the regulator. This capacitor counteracts reactive
input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor
may be required if large, fast rise-time load transients are anticipated, or if the device is not located close to the
power source. If source impedance is more than 2-Ω, a 0.1-µF input capacitor may be required to ensure
stability.
8.2.2.2 Dropout Voltage
The TLV742P series of LDOs use a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less
than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output
resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the
PMOS device functions similar to a resistor in dropout.
PSRR and transient response degrade when (VIN – VOUT) approaches dropout.
8.2.2.3 Transient Response
Increasing the size of the output capacitor reduces overshoot and undershoot magnitude but increases the
duration of the transient response.
16
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TLV742P
www.ti.com.cn
ZHCSGP8 –SEPTEMBER 2017
8.2.3 Application Curves
90
80
70
60
50
40
30
20
10
0
100
10
5 V
2.8 V
1.2 V
1
0.1
0.01
0.001
IOUT = 30 mA
IOUT = 150 mA
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
VOUT = 1.2 V
图 45. Power-Supply Ripple Rejection vs Frequency
图 46. Output Spectral Noise Density vs Frequency
150 mA
IOUT
1 mA
VIN
VOUT
VOUT
Time (100 ms/div)
Time (100 ms/div)
VOUT = 1.2 V
VOUT = 1.2 V, IOUT = 150 mA
图 47. Load Transient Response
图 48. Line Transient Response
VIN
VIN
VOUT
VOUT
Time (100 ms/div)
Time (100 ms/div)
VOUT = 1.2 V, IOUT = 200 mA
VOUT = 1.2 V, IOUT = 150 mA
图 49. Line Transient Response
图 50. Line Transient Response
版权 © 2017, Texas Instruments Incorporated
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TLV742P
ZHCSGP8 –SEPTEMBER 2017
www.ti.com.cn
VIN
VIN
VOUT
VOUT
Time (100 ms/div)
Time (100 ms/div)
VOUT = 1.2 V, IOUT = 200 mA
VOUT = 1.2 V, IOUT = 30 mA
图 52. VIN Ramp Up, Ramp Down Response
图 51. Line Transient Response
8.3 Do's and Don'ts
Place at least one 1-µF ceramic capacitor as close as possible to the OUT pin of the regulator.
Do not place the output capacitor more than 10 mm away from the regulator.
Connect a 1-µF low equivalent series resistance (ESR) capacitor across the IN pin and GND input of the
regulator for improved transient performance.
Do not exceed the absolute maximum ratings.
18
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TLV742P
www.ti.com.cn
ZHCSGP8 –SEPTEMBER 2017
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2 V and 5.5 V. The input voltage
range provides adequate headroom for the device to have a regulated output. This input supply must be well-
regulated (see 图 33 through 图 40). If the input supply is noisy, additional input capacitors with low ESR help
improve the output noise performance.
10 Layout
10.1 Layout Guidelines
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
Place input and output capacitors as close to the device pins as possible. To improve ac performance (such as
PSRR, output noise, and transient response), TI recommends that the board be designed with separate ground
planes for VIN and VOUT, with the ground plane connected only at the GND pin of the device, as shown in 图 53.
Connect the ground connection for the output capacitor directly to the GND pin of the device. High ESR
capacitors can degrade PSRR performance.
10.1.2 Package Mounting
Solder pad footprint recommendations are available from the TI website at www.ti.com. The recommended land
pattern for the DQN (X2SON-4) package is provided in the 机械、封装和可订购信息 section.
版权 © 2017, Texas Instruments Incorporated
19
TLV742P
ZHCSGP8 –SEPTEMBER 2017
www.ti.com.cn
10.2 Layout Example
VOUT
VIN
1
4
3
COUT
CIN
2
GND PLANE
Represents via used for
application specific connections
Copyright © 2017, Texas Instruments Incorporated
图 53. Recommended Layout Example
10.3 Thermal Considerations
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is enables
again. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits the dissipation of the regulator, which protects the regulator from
damage as a result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat sink. For reliable operation, limit junction temperature to 125°C (maximum). To estimate the margin of safety
in a complete design (including heat sink), increase the ambient temperature until the thermal protection is
triggered; use worst-case loads and signal conditions.
For good reliability, thermal protection triggers at least 35°C above the maximum expected ambient condition of
the particular application. This configuration produces a worst-case junction temperature of 125°C at the highest
expected ambient temperature and worst-case load.
The internal protection circuitry of the LDO is designed to protect against overload conditions. This circuitry is not
intended to replace proper heat sinking. Continuously running the LDO into thermal shutdown degrades device
reliability.
10.4 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed-circuit-board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to the ambient air.
Performance data for JEDEC low- and high-K boards are shown in Thermal Information. Using heavier copper
increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-
dissipating layers improves heat sink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of
the output current and the voltage drop across the output pass element, as shown in 公式 2.
PD = (VIN - VOUT) ´ IOUT
(2)
20
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TLV742P
www.ti.com.cn
ZHCSGP8 –SEPTEMBER 2017
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 评估模块
我们提供了一款评估模块 (EVM)，可与 TLV742P 配套使用，帮助评估初始电路性能。 TLV70728EVM-612 详细介
绍了 TLV70728EVM-612 的设计套件和评估模块。
可通过德州仪器 (TI) 网站上的 TLV742P 产品文件夹申请获取该 EVM，也可以直接从 TI 网上商店购买。
11.1.2 器件命名规则
订购信息(1)
(2)
产品
VOUT
XX(X) 是标称输出电压。对于分辨率为 100mV 的输出电压，订货编号中使用两位数字；否则，使用三位数字
（例如，18 = 1.8V，285 = 2.85V）。
TLV742xx(x)Pyyyz
P 为可选项；P 表示器件具有一个带有源输出放电功能的 LDO 稳压器。
YYY 为封装标识符。
Z 为封装数量。R 表示卷（3000 片），T 表示带（250 片）。
(1) 要获得最新的封装和订货信息，请参阅本文档末尾的封装选项附录，或者访问器件产品文件夹，此文件夹位于www.ti.com.cn内。
(2) 可提供 0.85V 至 5V 范围内的输出电压（以 50mV 为单位增量）。请与厂方联系以了解详细信息和可用性。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2017, Texas Instruments Incorporated
21
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ZHCSGP8 –SEPTEMBER 2017
www.ti.com.cn
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。
22
版权 © 2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV74211PDQNR
TLV74212PDQNR
TLV74215PDQNR
TLV74218PDQNR
TLV74225PDQNR
TLV74227PDQNR
TLV74228PDQNR
TLV74229PDQNR
TLV74230PDQNR
TLV74233PDQNR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
4
4
4
4
4
4
4
4
4
4
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
8H
8G
8F
8E
CS
8D
8C
8B
CT
7Z
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV74211PDQNR
TLV74212PDQNR
TLV74215PDQNR
TLV74218PDQNR
TLV74225PDQNR
TLV74227PDQNR
TLV74228PDQNR
TLV74229PDQNR
TLV74230PDQNR
TLV74233PDQNR
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
4
4
4
4
4
4
4
4
4
4
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
1.16
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV74211PDQNR
TLV74212PDQNR
TLV74215PDQNR
TLV74218PDQNR
TLV74225PDQNR
TLV74227PDQNR
TLV74228PDQNR
TLV74229PDQNR
TLV74230PDQNR
TLV74233PDQNR
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
X2SON
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
DQN
4
4
4
4
4
4
4
4
4
4
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
A
B
1
1.05
0.95
PIN 1
INDEX AREA
C
0.4 MAX
SEATING PLANE
0.08
NOTE 6
+0.12
-0.1
0.05
0.00
0.48
(0.05) TYP
NOTE 6
2
1
3
EXPOSED
THERMAL PAD
5
2X 0.65
(0.07) TYP
NOTE 5
4
0.28
PIN 1 ID
(OPTIONAL)
NOTE 4
4X
0.15
(0.11)
0.3
0.2
0.1
C A B
0.05
C
0.30
0.15
3X
4215302/E 12/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
5. Shape of exposed side leads may differ.
6. Number and location of exposed tie bars may vary.
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EXAMPLE BOARD LAYOUT
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
(0.86)
SYMM
SEE DETAIL
4X
4X (0.36)
(0.03)
4
4X (0.21)
1
5
SYMM
(0.65)
4X (0.18)
2
3
(
0.48)
(0.22) TYP
EXPOSED METAL
CLEARANCE
LAND PATTERN EXAMPLE
SCALE: 40X
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAIL
4215302/E 12/2016
NOTES: (continued)
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
8. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
SYMM
4X (0.4)
4X (0.03)
4
1
4X (0.21)
5
SYMM
(0.65)
SOLDER MASK
EDGE
4X (0.22)
2
3
(
0.45)
4X (0.235)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1mm THICK STENCIL
EXPOSED PAD
88% PRINTED SOLDER COVERAGE BY AREA
SCALE: 60X
4215302/E 12/2016
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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