TLV74325PDQNR [TI]
具有使能功能的 300mA、低 IQ、低压降稳压器 | DQN | 4 | -40 to 125;
| 型号： | TLV74325PDQNR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有使能功能的 300mA、低 IQ、低压降稳压器 | DQN | 4 | -40 to 125 稳压器 |
| 文件： | 总38页 (文件大小：1691K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV743P
SBVS310C –JULY 2017–REVISED JUNE 2019
TLV743P 300-mA, Low-Dropout Regulator
1 Features
3 Description
The TLV743P low-dropout linear regulator (LDO) is
an ultra-small, low quiescent current LDO that
sources 300 mA with good line and load transient
performance. The device provides a typical accuracy
of 1%.
1
•
•
Input Voltage Range: 1.4 V to 5.5 V
Stable Operation With 1-µF Ceramic Output
Capacitor
•
•
Foldback Overcurrent Protection
Packages:
The TLV743P is designed to be stable with a small
output capacitor with a value of 1 µF. The TLV743P
device provides foldback current control during device
power up and enabling. This functionality is especially
important in battery-operated devices.
–
–
SOT-23 (5)
X2SON (4)
•
•
•
•
Very Low Dropout: 125 mV at 300 mA (3.3 VOUT
Accuracy: 1% (Typical), 1.4% (Maximum)
Low IQ: 34 µA
)
The TLV743P provides an active pulldown circuit to
quickly discharge output loads when the device is
disabled.
Available in Fixed-Output Voltages:
1 V to 3.3 V
The TLV743P is available in standard DBV (SOT-23)
and DQN (X2SON) packages.
•
•
High PSRR: 50 dB at 1 kHz
Active Output Discharge
Device Information(1)
PART NUMBER
PACKAGE
SOT-23 (5)
X2SON (4)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
1.00 mm × 1.00 mm
2 Applications
•
•
•
•
•
•
Tablets
TLV743P
Smartphones
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Notebook and Desktop Computers
Portable Industrial and Consumer Products
WLAN and Other PC Add-On Cards
Camera Modules
Typical Application Circuit
Dropout Voltage vs Output Current
180
VOUT = 3.3 V
VOUT = 1.8 V
IN
OUT
160
140
120
100
80
TLV743P
COUT
CIN
EN
GND
Optional
ON
OFF
60
40
20
0
0
30
60
90 120 150 180 210 240 270 300
IOUT (mA)
D020
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV743P
SBVS310C –JULY 2017–REVISED JUNE 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Typical Characteristics.............................................. 8
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application .................................................. 18
Power Supply Recommendations...................... 19
9
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Examples................................................... 19
11 Device and Documentation Support ................. 20
11.1 Device Support .................................................... 20
11.2 Documentation Support ........................................ 20
11.3 Receiving Notification of Documentation Updates 20
11.4 Community Resources.......................................... 20
11.5 Trademarks........................................................... 21
11.6 Electrostatic Discharge Caution............................ 21
11.7 Glossary................................................................ 21
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
Changes from Revision B (March 2018) to Revision C
Page
•
•
•
•
•
•
•
•
•
•
•
•
Changed description of EN pin in Pin Functions table........................................................................................................... 4
Deleted typical specification from VEN(HI) and VEN(LO) parameters ......................................................................................... 6
Added maximum specification to ILIM parameter ................................................................................................................... 7
Added condition to 1-V Load Regulation vs IOUT and Temperature figure ............................................................................. 8
Added condition to 1.8-V Load Regulation vs IOUT and Temperature figure .......................................................................... 8
Added condition to 3.3-V Load Regulation vs IOUT and Temperature figure ......................................................................... 8
Added condition to 1.2-V Dropout Voltage vs IOUT and Temperature figure ......................................................................... 9
Added condition to 1.8-V Dropout Voltage vs IOUT and Temperature figure ......................................................................... 9
Added condition to 3.3-V Dropout Voltage vs IOUT and Temperature figure ......................................................................... 9
Added and Output Enable to title and changed first paragraph of Shutdown and Output Enable section .......................... 14
Added DBV package to Maximum Ambient Temperature vs Device Power Dissipation figure and text reference............. 17
Added (3) to Device Nomenclature table ............................................................................................................................. 20
Changes from Revision A (January 2018) to Revision B
Page
•
Changed X2SON package from preview to production data (active) .................................................................................... 1
Changes from Original (July 2017) to Revision A
Page
•
•
•
•
•
•
•
•
Added X2SON package to Features list ................................................................................................................................ 1
Added DQN (X2SON) package to Description section ......................................................................................................... 1
Added X2SON package to Device Information table ............................................................................................................. 1
Added DQN (X2SON) package pinout drawing and pin functions table to Pin Configuration and Functions section .......... 4
Deleted thermal pad from DBV pinout drawing and Pin Functions table .............................................................................. 4
Changed format of I/O column contents and order of packages in Pin Functions table ....................................................... 4
Added DQN (X2SON) thermal information to Thermal Information table ............................................................................. 5
Changed condition text for Figure 31 .................................................................................................................................. 17
2
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SBVS310C –JULY 2017–REVISED JUNE 2019
•
Added X2SON layout example image to Layout Examples section .................................................................................... 19
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SBVS310C –JULY 2017–REVISED JUNE 2019
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5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
IN
GND
EN
1
2
3
5
4
OUT
NC
Not to scale
DQN Package
4-Pin X2SON With Exposed Thermal Pad
Top View
OUT
GND
1
4
3
IN
Thermal Pad
2
EN
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
EN
SOT-23
X2SON
Enable pin. Drive EN greater than VEN(LO) to turn on the regulator.
Drive EN less than VEN(LO) to put the LDO into shutdown mode.
3
2
1
4
3
2
4
I
GND
IN
—
I
Ground pin
Input pin. A small capacitor is recommended from this pin to ground.
See Input and Output Capacitor Selection for more details.
NC
—
No internal connection
Regulated output voltage pin. For best transient response, use a small 1-μF ceramic
capacitor from this pin to ground.
OUT
5
1
O
See Input and Output Capacitor Selection for more details.
The thermal pad is electrically connected to the GND node.
Connect to the GND plane for improved thermal performance.
Thermal pad
—
Thermal pad
—
4
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SBVS310C –JULY 2017–REVISED JUNE 2019
6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted); all voltages are with respect to GND(1)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
V
VIN
6
Voltage
VEN
VOUT
IOUT
VIN + 0.3
3.6
Current
Internally limited
Indefinite
A
Output short-circuit duration
Operating junction, TJ
Storage, Tstg
–40
–65
150
160
Temperature
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.4
1
NOM
MAX
5.5
UNIT
VIN
Input range
V
V
VOUT
IOUT
VEN
TJ
Output range
3.3
Output current
Enable range
Junction temperature
0
300
VIN
mA
V
0
–40
125
°C
6.4 Thermal Information
TLV743P
THERMAL METRIC(1)
DBV (SOT-23)
5 PINS
228.4
DQN (X2SON)
4 PINS
218.6
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
151.5
164.8
55.8
164.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
31.4
5.6
ψJB
54.8
163.9
RθJC(bot)
N/A
131.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted). All typical values at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
1.4
TYP
MAX
5.5
UNIT
VIN
Input voltage
V
TJ = 25°C
–1%
1%
DC output accuracy
–40°C ≤ TJ ≤ 125°C
VIN rising
–1.4%
1.4%
1.4
1.3
1.25
1
Undervoltage
lockout
UVLO
V
VIN falling
ΔVO(ΔVI) Line regulation
ΔVO(ΔIO) Load regulation
ΔVI = VIN(nom) to VIN(nom) + 1
mV
mV
16
ΔIO = 1 mA to 300 mA DBV package
25
VOUT = 1.1 V
–40°C ≤ TJ ≤ 85°C
480
420
370
270
260
220
450
400
300
290
1.2 V ≤ VOUT < 1.5 V
–40°C ≤ TJ ≤ 85°C
1.5 V ≤ VOUT < 1.8 V
–40°C ≤ TJ ≤ 85°C
1.8 V ≤ VOUT < 2.5 V
–40°C ≤ TJ ≤ 85°C
2.5 V ≤ VOUT < 3.3 V
–40°C ≤ TJ ≤ 85°C
VOUT = 0.98 × VOUT(nom) VOUT = 3.3 V
IOUT = 300 mA –40°C ≤ TJ ≤ 85°C
VDO
Dropout voltage(1)
125
mV
1.2 V ≤ VOUT < 1.5 V
–40°C ≤ TJ ≤ 125°C
1.5 V ≤ VOUT < 1.8 V
–40°C ≤ TJ ≤ 125°C
1.8 V ≤ VOUT < 2.5 V
–40°C ≤ TJ ≤ 125°C
2.5 V ≤ VOUT < 3.3 V
–40°C ≤ TJ ≤ 125°C
VOUT = 3.3 V
–40°C ≤ TJ ≤ 125°C
125
34
270
60
IGND
Ground pin current
Shutdown current
IOUT = 0 mA
EN ≤ 0.35 V
2 V ≤ VIN ≤ 5.5 V
µA
µA
V
ISHDN
0.1
1
TJ = 25°C
f = 100 Hz
f = 10 kHz
f = 100 kHz
68
35
28
Power-supply
rejection ratio
VOUT = 1.8 V
IOUT = 300 mA
PSRR
dB
Bandwidth = 10 Hz to 100 kHz
Vn
Output noise voltage VOUT = 1.8 V
IOUT = 10 mA
120
µVRMS
EN pin high voltage
(enabled)
VEN(HI)
0.9
V
EN pin low voltage
(disabled)
VEN(LO)
IEN
0.35
V
EN pin current
VEN = 5.5 V
0.01
µA
(1) Dropout voltage for the TLV743P is not valid at room temperature. The device engages undervoltage lockout (VIN < UVLOFALL) before
the dropout condition is met.
6
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SBVS310C –JULY 2017–REVISED JUNE 2019
Electrical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted). All typical values at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Time from EN assertion to 98% × VOUT(nom)
VOUT = 1 V
IOUT = 0 mA
250
tSTR
Startup time
µs
Time from EN assertion to 98% × VOUT(nom)
VOUT = 3.3 V
IOUT = 0 mA
800
120
Pulldown resistor
VIN = 2.3 V
Ω
ILIM
Output current limit
360
700
mA
VOUT shorted to GND
VOUT = 1 V
150
170
Short-circuit current
limit
IOS
mA
°C
VOUT shorted to GND
VOUT = 3.3 V
Shutdown, temperature increasing
Reset, temperature decreasing
160
140
Tsd
Thermal shutdown
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6.6 Typical Characteristics
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
1.03
1.02
1.01
1
1.004
1
TJ = -40 èC
TJ = 0 èC
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
TJ = -40 èC
TJ = 0 èC
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
0.996
0.992
0.988
0.984
0.98
0.99
0.98
0.97
0.96
0.976
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Current (mA)
Current (mA)
D001
D005
TLV74310PDBV
TLV74310PDQN
Figure 1. 1-V Load Regulation vs IOUT and Temperature
Figure 2. 1-V Load Regulation vs IOUT and Temperature
1.816
1.8
TJ = -40 èC
TJ = 0 èC
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
TJ = -40 èC
TJ = 0 èC
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
1.808
1.8
1.797
1.794
1.791
1.788
1.785
1.782
1.779
1.792
1.784
1.776
1.768
1.76
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Current (mA)
Current (mA)
D002
D006
TLV74318PDBV
TLV74318PDQN
Figure 3. 1.8-V Load Regulation vs IO and Temperature
Figure 4. 1.8-V Load Regulation vs IOUT and Temperature
3.345
3.32
TJ = -40 èC
TJ = 0 èC
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
TJ = -40 èC
TJ = 0 èC
3.33
3.315
3.3
3.312
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
3.304
3.296
3.288
3.28
3.285
3.27
3.255
3.24
3.272
3.264
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Current (mA)
Current (mA)
D003
D007
TLV74333PDBV
TLV74333PDQN
Figure 5. 3.3-V Load Regulation vs IOUT and Temperature
Figure 6. 3.3-V Load Regulation vs IOUT and Temperature
8
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SBVS310C –JULY 2017–REVISED JUNE 2019
Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
400
350
300
250
200
150
100
50
390
360
330
300
270
240
210
180
150
120
90
TJ = -40 èC
TJ = 0 èC
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
TJ = -40 èC
TJ = 0 èC
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
60
0
30
60
90 120 150 180 210 240 270 300
0
30
60
90 120 150 180 210 240 270 300
Current (mA)
Current (mA)
D024
D025
TLV74312PDBV
TLV74312PDQN
Figure 7. 1.2-V Dropout Voltage vs IOUT and Temperature
Figure 8. 1.2-V Dropout Voltage vs IOUT and Temperature
275
300
TJ = -40 èC
TJ = -40 èC
TJ = 0 èC
250
TJ = 0 èC
250
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
TJ = 25 èC
225
200
175
150
125
100
75
TJ = 85 èC
TJ = 125 èC
200
150
100
50
50
25
0
0
0
30
60
90 120 150 180 210 240 270 300
0
30
60
90 120 150 180 210 240 270 300
Current (mA)
Current (mA)
D008
D010
TLV74318PDBV
TLV74318PDQN
Figure 9. 1.8-V Dropout Voltage vs IOUT and Temperature
Figure 10. 1.8-V Dropout Voltage vs IOUT and Temperature
300
300
TJ = -40 èC
TJ = 0 èC
TJ = -40 èC
TJ = 0 èC
250
250
TJ = 25 èC
TJ = 25 èC
TJ = 85 èC
TJ = 125 èC
TJ = 85 èC
TJ = 125 èC
200
200
150
100
50
150
100
50
0
0
0
30
60
90 120 150 180 210 240 270 300
Current (mA)
0
30
60
90 120 150 180 210 240 270 300
Current (mA)
D009
D011
TLV74333PDBV
TLV74333PDQN
Figure 11. 3.3-V Dropout Voltage vs IOUT and Temperature
Figure 12. 3.3-V Dropout Voltage vs IOUT and Temperature
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
1.816
1.814
1.812
1.81
70
65
60
55
50
45
40
35
30
25
TJ = -40èC
TJ = 0èC
TJ = 25èC
TJ = 85èC
TJ = 125èC
TJ = -40èC
TJ = 0èC
TJ = 25èC
TJ = 85èC
TJ = 125èC
1.808
1.806
1.804
1.802
1.8
1.798
1.796
2
2.5
3
3.5
VIN (V)
4
4.5
5
5.5
0
30
60
90 120 150 180 210 240 270 300
IOUT (mA)
D019
D012
TLV74318PDBV
Figure 13. 1.8-V Regulation vs VIN (Line Regulation) and
Temperature
Figure 14. Ground Pin Current vs IOUT and Temperature
40
100
TJ = 25èC
TJ = -40èC
TJ = 0èC
35
TJ = 25èC
TJ = 85èC
TJ = 125èC
30
25
20
15
10
5
10
1
0.1
0.01
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
0
1
2
3
4
5
6
VIN (V)
VIN (V)
D013
D015
IOUT = 0 mA
Figure 15. Ground Pin Current vs VIN
Figure 16. Shutdown Current vs VIN and Temperature
1
0.675
VEN(LO)
VEN(HI)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.65
0.625
0.6
0.575
0.55
0.525
0.5
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
0.475
0.45
0.425
150 200 250 300 350 400 450 500 550 600 650 700
Output Current (mA)
-40
-20
0
20
40
TJ (èC)
60
80
100 120 140
D023
D014
TLV74310PDBV
Figure 17. Enable Threshold vs Temperature
Figure 18. 1-V Foldback Current Limit vs
IOUT and Temperature
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SBVS310C –JULY 2017–REVISED JUNE 2019
Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
2
1.75
1.5
1.25
1
3.5
3
2.5
2
1.5
1
0.75
0.5
0.25
0
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
0.5
0
150
200
250
300 350
Output Current (mA)
400
450
500
150
200
250
300 350
Output Current (mA)
400
450
500
D021
D022
TLV74318PDBV
TLV74333PDBV
Figure 19. 1.8-V Foldback Current Limit vs
IOUT and Temperature
Figure 20. 3.3-V Foldback Current Limit vs
IOUT and Temperature
80
70
60
50
40
30
20
10
0
10
1
1-µF Output Capacitor
VOUT = 1 V
VOUT = 1.8 V
VOUT = 3.3 V
0.1
0.01
0.005
10
100
1k 10k
Frequency (Hz)
100k
1M
10
100
1k
10k
100k
1M
Frequency (Hz)
D017
D016
IOUT = 300 mA
IOUT = 300 mA
Figure 21. Power-Supply Rejection Ratio vs Frequency
Figure 22. Output Spectral Noise Density
VIN (2 V/div)
VIN (2 V/div)
VOUT (1 V/div,
AC Coupled)
VOUT (1 V/div,
AC Coupled)
Time (20 µs/div)
Time (20 µs/div)
TLV74318PDBV
IOUT = 300 mA
1-µF output
capacitor
TLV74318PDBV, IOUT = 10 mA, 1-µF output capacitor
Figure 23. Line Transient
Figure 24. Line Transient
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
VOUT (100 mV/div,
AC Coupled)
VOUT (200 mV/div,
AC Coupled)
ILOAD (100 mA/div)
ILOAD (100 mA/div)
Time (20 µs/div)
Time (20 µs/div)
TLV74310
PDBV
VIN = 2 V, 1-µF output capacitor,
output current slew rate = 0.25 A/µs
TLV74333PDBV, VIN = 3.8 V,1-µF output capacitor, output current
slew rate = 0.25 A/µs
Figure 25. 1-V, 50-mA to 300-mA Load Transient
Figure 26. 3.3 V, 50-mA to 300-mA Load Transient
VEN (500 mV/div)
VIN (1 V/div)
VOUT (1 V/div)
ILOAD (200 mA/div)
VOUT (500 mV/div)
Time (100 µs/div)
Time (100 µs/div)
TLV74318PDBV, RL = 6.2 Ω, 1-µF output capacitor
TLV74318PDBV, RL = 6.2 Ω, VEN = VIN, 1-µF output capacitor
Figure 28. Startup with EN
Figure 27. VIN Power-Up and Power-Down
VOUT (500 mV/div)
VEN (500 mV/div)
VOUT (500 mV/div)
ILOAD (200 mA/div)
Time (100 µs/div)
Time (100 µs/div)
TLV74318PDBV, 1-µF output capacitor
TLV74318PDBV, IOUT = 300 mA, 1-µF output capacitor
Figure 30. Foldback Current Limit Response
Figure 29. Shutdown Response With Enable
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7 Detailed Description
7.1 Overview
The TLV743P device belongs to a new family of next-generation, low-dropout regulators (LDOs). This device
consumes low quiescent current and delivers excellent line and load transient performance. These
characteristics, combined with low noise, good PSRR with low-dropout voltage, make this device well-suited for
portable consumer applications.
This regulator offers foldback current limit, shutdown, and thermal protection. The operating junction temperature
for this device is –40°C to +125°C.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
Thermal
Shutdown
UVLO
120 W
Bandgap
EN
Logic
TLV743P
GND
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7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
The TLV743P device uses an undervoltage lockout (UVLO) circuit that disables the output until the input voltage
is greater than the rising UVLO voltage, UVLORISE. This circuit makes certain that the device does not exhibit any
unpredictable behavior when the supply voltage is lower than the operational range of the internal circuitry.
During UVLO disable, the output connects to ground with a 120-Ω pulldown resistor.
7.3.2 Shutdown and Output Enable
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(HI). Turn off the device
by forcing the EN pin to drop below VEN(LO). If shutdown capability is not required, connect EN to IN. There is no
internal pulldown resistor connected to the EN pin.
The TLV743P device has an internal pulldown MOSFET that connects a 120-Ω resistor to ground when the
device is disabled. The discharge time after disabling depends on the output capacitance (COUT) and the load
resistance (RL) in parallel with the 120-Ω pulldown resistor. The time constant is calculated in Equation 1:
120ì RL
t =
ì COUT
120 + RL
(1)
7.3.3 Internal Foldback Current Limit
The TLV743P device has an internal foldback current limit that protects the regulator during fault conditions. The
current allowed through the device is reduced as the output voltage falls. When the output is shorted, the LDO
supplies a typical current of 150 mA. The output voltage is not regulated when the device is in current limit. In
this condition, the output voltage is the product of the regulated current and the load resistance. When the device
output is shorted, the PMOS pass transistor dissipates power [(VIN – VOUT) × IOS] until thermal shutdown is
triggered and the device turns off. After the device cools down, the internal thermal shutdown circuit turns the
device back on. If the fault condition continues, the device cycles between current limit and thermal shutdown.
See Thermal Information for more details.
The foldback current limit circuit limits the current allowed through the device to current levels lower than the
minimum current limit at nominal VOUT current limit (ILIM) during startup. See Figure 18 to Figure 20 for typical
foldback current limit values. If the output is loaded by a constant-current load during startup, or if the output
voltage is negative when the device is enabled, then the required load current by the load may exceed the
foldback current limit and the device may not rise to the full output voltage. For constant current loads, disable
the output load until the TLV743P has risen to the nominal output voltage.
The TLV743P PMOS pass element has an intrinsic body diode that conducts current when the voltage at the
OUT pin exceeds the voltage at the IN pin. Do not force the output voltage to exceed the input voltage because
excessively high current may flow through the body diode.
7.3.4 Thermal Shutdown
Thermal shutdown protection disables the output when the junction temperature rises to approximately 160°C.
Disabling the device eliminates power dissipated by the device, which allows the device to cool. When the
junction temperature cools to approximately 140°C, the output circuitry is enabled again. Depending on power
dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off.
This cycling limits regulator dissipation, which protects the device from damage as a result of overheating.
Activating the thermal shutdown feature usually indicates excessive power dissipation as a result of the product
of the (VIN – VOUT) voltage and the load current. For reliable operation, limit junction temperature to 125°C
maximum. To estimate the margin of safety in a complete design, increase the ambient temperature until the
thermal protection is triggered; use worst-case loads and signal conditions.
The TLV743P internal protection circuitry protects against overload conditions, but is not intended to be active in
normal operation. Continuously running the TLV743P device into thermal shutdown degrades device reliability.
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7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
•
The input voltage has previously exceeded the UVLO rising voltage and has not decreased below the UVLO
falling threshold.
•
•
The input voltage is greater than the nominal output voltage added to the dropout voltage.
The enable voltage has previously exceeded the enable rising threshold voltage and not decreased below the
enable falling threshold.
•
•
The output current is less than the current limit.
The device junction temperature is less than the thermal shutdown temperature.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this condition, the output
voltage is the same the input voltage minus the dropout voltage. The transient performance of the device is
significantly degraded because the pass device is in a triode state and no longer controls the current through the
LDO. Line or load transients in dropout may result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
•
•
The input voltage is less than the UVLO falling voltage, or has not yet exceeded the UVLO rising threshold.
The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
•
The device junction temperature is greater than the thermal shutdown temperature.
When the device is disabled, the active pulldown resistor discharges the output.
Table 1 lists the conditions that result in different operating modes.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
VIN > VOUT(nom) + VDO
and VIN > UVLORISE
Normal mode
Dropout mode
VEN > VEN(HI)
VEN > VEN(HI)
IOUT < ILIM
IOUT < ILIM
TJ < 160°C
TJ < 160°C
UVLORISE < VIN < VOUT(nom) + VDO
Disabled mode
(any true condition
disables the device)
VIN < UVLOFALL
VEN < VEN(LO)
—
TJ > 160°C
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input and Output Capacitor Selection
The TLV743P device uses an advanced internal control loop to obtain stable operation with the use of input or
output capacitors. An output capacitance of 1 μF or larger generally provides good dynamic response. Use X5R-
and X7R-type ceramic capacitors because these capacitors have minimal variation in value and equivalent series
resistance (ESR) over temperature.
Although an input capacitor is not required for stability, increased output impedance from the input supply may
compromise the performance of the TLV743P. Good analog design practice is to connect a 0.1-µF to 1-µF
capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response,
input ripple, and PSRR. Use an input capacitor if the source impedance is greater than 0.5 Ω. Use a higher-value
capacitor if large, fast, rise-time load transients are expected, or if the device is located several inches from the
input power source.
8.1.2 Dropout Voltage
The TLV743P device uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the
dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output
resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the
PMOS device behaves like a resistor in dropout mode. As with any linear regulator, PSRR and transient
response degrade as (VIN – VOUT) approaches dropout operation. See Figure 7 to Figure 12 for typical dropout
values.
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Application Information (continued)
8.1.3 Power Dissipation
The ability to remove heat from the die is different for each package type and presents different considerations in
the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to ambient air. Performance data for JEDEC high-K boards are shown in Thermal
Information. Using heavier copper increases the effectiveness in removing heat from the device. The addition of
plated through-holes to heat-dissipating layers also improves heat sink effectiveness.
Power dissipation (PD) depends on input voltage and load conditions. PD is equal to the product of the output
current and voltage drop across the output pass element, as shown in Equation 2.
P = VIN œ VOUT ì I
D
OUT
(2)
Figure 31 shows the maximum ambient temperature versus the power dissipation of the TLV743P device in the
DQN and DBV packages. This figure assumes the device is soldered on JEDEC standard high-K layout with no
airflow over the board. Actual board thermal impedances vary widely. If the application requires high power
dissipation, it is helpful to have a thorough understanding of the board temperature and thermal impedances to
make certain that the TLV743P device does not operate continuously above a junction temperature of 125°C.
125
TLV743P DQN, High-K Layout
TLV743P DBV, High-K Layout
120
115
110
105
100
95
90
85
80
75
70
65
60
55
0
0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 0.3
Power Dissipation (W)
D028
TLV743P, high-K layout
Figure 31. Maximum Ambient Temperature vs Device Power Dissipation
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8.2 Typical Application
VOUT
VOUT
1.8 V
1.5 V
IN
OUT
GND
CIN
1 µF
COUT
1 µF
DC-DC
Converter
TLV743P
Load
EN
ON
OFF
Figure 32. DC/DC Converter Post Regulation
8.2.1 Design Requirements
Table 2. Design Parameters
PARAMETER
Input voltage
Output voltage
Output current
DESIGN REQUIREMENT
1.8 V, ±5%
1.5 V, ±1%
200-mA DC, 300-mA peak
< 10%, 1-A/µs load step from 50 mA to 200 mA
85°C
Output voltage transient deviation
Maximum ambient temperature
8.2.2 Detailed Design Procedure
Input and output capacitors are required to achieve the output voltage transient requirements. Capacitance
values of 1 µF are selected to give the maximum output capacitance in a small, low-cost package.
Figure 7 shows the 1.2-V option dropout voltage. Given that dropout voltages are higher for lower output-voltage
options, and given that the 1.2-V option dropout voltage is typically less than 300 mV at 125°C, then the 1.5-V
option dropout voltage is typically less than 300 mV at 125°C.
See Figure 31 to verify that the maximum junction temperature is not exceeded.
8.2.3 Application Curve
VIN (500 mV/div)
VOUT (500 mV/div)
IOUT (100 mA/div)
Time (50 µs/div)
Figure 33. 1.8-V to 1.5-V Regulation at 300 mA
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9 Power Supply Recommendations
Connect a low-output impedance power supply directly to the IN pin of the TLV743P device. Inductive
impedances between the input supply and the IN pin can create significant voltage excursions at the IN pin
during startup or load transient events. If inductive impedances are unavoidable, use an input capacitor.
10 Layout
10.1 Layout Guidelines
•
•
•
Place input and output capacitors as close as possible to the device.
Use copper planes for device connections to optimize thermal performance.
Place thermal vias around the device to distribute heat.
10.2 Layout Examples
VOUT
VIN
5
1
CIN*
COUT
*
2
3
4
GND PLANE
Represents via used for
application specific connections
*not required
Figure 34. Layout Example: DBV Package
VOUT
VIN
TLV741P
IN
OUT
(1)
COUT
(1)
CIN
EN
GND
GND PLANE
Represents via used for
application-specific connections
(1) Not required.
Figure 35. X2SON Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Module
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TLV743P
device. The TLV73312PEVM-643 evaluation module (and related user guide) can be requested at the Texas
Instruments website through the product folders or purchased directly from the TI eStore.
11.1.2 Device Nomenclature
Table 3. Device Nomenclature(1)(2)
PRODUCT
VOUT
xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used
in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V).
P indicates an active output discharge feature. All members of the TLV743 family will actively discharge
the output when the device is disabled.
TLV743Pxx(x)Pyyyz(3)
yyy is the package designator.
z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
(3) indicates an alternative tape and reel orientation. 3 indicates that pin 1 is in quadrant 3. See the
Package Materials Information addendum for more information.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
(2) Output voltages from 1 V to 3.3 V in 50-mV increments are available. Contact the factory for details and availability.
11.2 Documentation Support
11.2.1 Related Documentation
TLV73312PDQN-643 Evaluation Module User Guide (SBVU024)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
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11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
4215302/D 06/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
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EXAMPLE BOARD LAYOUT
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
4215302/D 06/2016
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
6. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
4215302/D 06/2016
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
DBV
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DQN
DBV
DQN
DBV
DQN
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV743105PDBVR
TLV74310PDBVR
TLV74310PDQNR
TLV74311PDBVR
TLV74311PDQNR
TLV74312PDBVR
TLV74312PDQNR
TLV74315PDBVR
TLV74315PDQNR
TLV74318PDBVR
TLV74318PDQNR
TLV74318PDQNR3
TLV74325PDBVR
TLV74325PDQNR
TLV743285PDBVR
TLV743285PDQNR
ACTIVE
SOT-23
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
X2SON
SOT-23
X2SON
SOT-23
X2SON
5
5
4
5
4
5
4
5
4
5
4
4
5
4
5
4
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1NGT
1CCT
8U
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Green (RoHS
& no Sb/Br)
SN
NIPDAU
SN
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
1DAT
8W
Green (RoHS
& no Sb/Br)
NIPDAU
SN
Green (RoHS
& no Sb/Br)
1DBT
8X
Green (RoHS
& no Sb/Br)
NIPDAU
SN
Green (RoHS
& no Sb/Br)
1DCT
8Z
Green (RoHS
& no Sb/Br)
NIPDAU
SN
Green (RoHS
& no Sb/Br)
1D7T
9A
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
SN
Green (RoHS
& no Sb/Br)
9A
Green (RoHS
& no Sb/Br)
1DDT
9B
Green (RoHS
& no Sb/Br)
NIPDAU
SN
Green (RoHS
& no Sb/Br)
1DET
9C
Green (RoHS
& no Sb/Br)
NIPDAU
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV74328PDBVR
TLV74328PDQNR
TLV74328PDQNR1
TLV74330PDBVR
TLV74330PDQNR
TLV74333PDBVR
TLV74333PDQNR
ACTIVE
SOT-23
X2SON
X2SON
SOT-23
X2SON
SOT-23
X2SON
DBV
5
4
4
5
4
5
4
3000
3000
3000
3000
3000
3000
3000
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1DFT
9D
ACTIVE
PREVIEW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DQN
DQN
DBV
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
SN
Green (RoHS
& no Sb/Br)
9D
Green (RoHS
& no Sb/Br)
1DGT
9E
DQN
DBV
Green (RoHS
& no Sb/Br)
NIPDAU
SN
Green (RoHS
& no Sb/Br)
1CBT
9F
DQN
Green (RoHS
& no Sb/Br)
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Aug-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV743105PDBVR
TLV74310PDBVR
TLV74310PDQNR
TLV74311PDBVR
TLV74311PDQNR
TLV74312PDBVR
TLV74312PDQNR
TLV74315PDBVR
TLV74315PDQNR
TLV74318PDBVR
TLV74318PDQNR
TLV74325PDBVR
TLV74325PDQNR
TLV743285PDBVR
TLV743285PDQNR
TLV74328PDBVR
TLV74328PDQNR
TLV74330PDBVR
SOT-23
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
DBV
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
5
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
178.0
178.0
180.0
178.0
180.0
178.0
180.0
178.0
180.0
178.0
180.0
178.0
180.0
178.0
180.0
178.0
180.0
178.0
9.0
9.0
8.4
9.0
8.4
9.0
8.4
9.0
8.4
9.0
8.4
9.0
8.4
9.0
8.4
9.0
8.4
9.0
3.3
3.3
3.2
3.2
1.4
1.4
4.0
4.0
2.0
4.0
2.0
4.0
2.0
4.0
2.0
4.0
2.0
4.0
2.0
4.0
2.0
4.0
2.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q2
Q3
Q2
Q3
Q2
Q3
Q2
Q3
Q2
Q3
Q2
Q3
Q2
Q3
Q2
Q3
1.16
3.3
1.16
3.2
0.53
1.4
1.16
3.3
1.16
3.2
0.53
1.4
1.16
3.3
1.16
3.2
0.53
1.4
1.16
3.3
1.16
3.2
0.53
1.4
1.16
3.3
1.16
3.2
0.53
1.4
1.16
3.3
1.16
3.2
0.53
1.4
1.16
3.3
1.16
3.2
0.53
1.4
1.16
3.3
1.16
3.2
0.53
1.4
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Aug-2019
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV74330PDQNR
TLV74333PDBVR
TLV74333PDQNR
X2SON
SOT-23
X2SON
DQN
DBV
DQN
4
5
4
3000
3000
3000
180.0
178.0
180.0
8.4
9.0
8.4
1.16
3.3
1.16
3.2
0.53
1.4
2.0
4.0
2.0
8.0
8.0
8.0
Q2
Q3
Q2
1.16
1.16
0.53
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV743105PDBVR
TLV74310PDBVR
TLV74310PDQNR
TLV74311PDBVR
TLV74311PDQNR
TLV74312PDBVR
TLV74312PDQNR
TLV74315PDBVR
TLV74315PDQNR
TLV74318PDBVR
TLV74318PDQNR
TLV74325PDBVR
TLV74325PDQNR
TLV743285PDBVR
SOT-23
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
DBV
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
5
5
4
5
4
5
4
5
4
5
4
5
4
5
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
180.0
180.0
203.2
180.0
203.2
180.0
203.2
180.0
203.2
180.0
203.2
180.0
203.2
180.0
180.0
180.0
196.8
180.0
196.8
180.0
196.8
180.0
196.8
180.0
196.8
180.0
196.8
180.0
18.0
18.0
33.3
18.0
33.3
18.0
33.3
18.0
33.3
18.0
33.3
18.0
33.3
18.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Aug-2019
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV743285PDQNR
TLV74328PDBVR
TLV74328PDQNR
TLV74330PDBVR
TLV74330PDQNR
TLV74333PDBVR
TLV74333PDQNR
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
DQN
DBV
DQN
DBV
DQN
DBV
DQN
4
5
4
5
4
5
4
3000
3000
3000
3000
3000
3000
3000
203.2
180.0
203.2
180.0
203.2
180.0
203.2
196.8
180.0
196.8
180.0
196.8
180.0
196.8
33.3
18.0
33.3
18.0
33.3
18.0
33.3
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
A
B
1
1.05
0.95
PIN 1
INDEX AREA
C
0.4 MAX
SEATING PLANE
0.08
NOTE 6
+0.12
-0.1
0.05
0.00
0.48
(0.05) TYP
NOTE 6
2
1
3
EXPOSED
THERMAL PAD
5
2X 0.65
(0.07) TYP
NOTE 5
4
0.28
PIN 1 ID
(OPTIONAL)
NOTE 4
4X
0.15
(0.11)
0.3
0.2
0.1
C A B
0.05
C
0.30
0.15
3X
4215302/E 12/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
5. Shape of exposed side leads may differ.
6. Number and location of exposed tie bars may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
(0.86)
SYMM
SEE DETAIL
4X
4X (0.36)
(0.03)
4
4X (0.21)
1
5
SYMM
(0.65)
4X (0.18)
2
3
(
0.48)
(0.22) TYP
EXPOSED METAL
CLEARANCE
LAND PATTERN EXAMPLE
SCALE: 40X
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAIL
4215302/E 12/2016
NOTES: (continued)
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
8. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
SYMM
4X (0.4)
4X (0.03)
4
1
4X (0.21)
5
SYMM
(0.65)
SOLDER MASK
EDGE
4X (0.22)
2
3
(
0.45)
4X (0.235)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1mm THICK STENCIL
EXPOSED PAD
88% PRINTED SOLDER COVERAGE BY AREA
SCALE: 60X
4215302/E 12/2016
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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