TLV75201PDSQR [TI]

1A、低 IQ、高 PSRR、可调节、双通道低压降 (LDO) 稳压器 | DSQ | 10 | -40 to 125;


型号：	TLV75201PDSQR
厂家：	TEXAS INSTRUMENTS
描述：	1A、低 IQ、高 PSRR、可调节、双通道低压降 (LDO) 稳压器 \| DSQ \| 10 \| -40 to 125 光电二极管输出元件稳压器调节器
文件：	总31页 (文件大小：2837K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TLV752

ZHCSKJ0A –DECEMBER 2019–REVISED MARCH 2020

采用小尺寸封装的 TLV752 双通道 1A 高精度可调节 LDO

1 特性

3 说明

•

输入电压范围：1.5V 至 6.0V

可调节输出电压：

0.55V 至 5.5V

极低压降：

TLV752 是一款双通道、可调节的 1A 低压降 (LDO) 稳

压器。该器件采用小型 10 引脚 2mm × 2mm WSON

封装，具有 25µA 的静态电流，同时提供快速的线路和

负载瞬态响应。该 TLV752 具有 225mV 的低压降，有

助于提高总功效。

•

–

1A 电流时为 225mV（最大值）(3.3V_OUT)

高输出精度:

TLV752 具有宽输入和输出电压范围以及出色的输出电

流能力，当用于小型印刷电路板 (PCB) 上时，可帮助

支持各类应用，如传感器电源、辅助电源轨和具有更

低内核电压的现代微控制器。

–

过温条件下的最大值为 1.5%

•

I_Q：25µA（典型值）

内置软启动功能，具有单调 V_OUT上升

封装：

TLV752 可与小型陶瓷输出电容器搭配使用，从而减小

整体解决方案尺寸。精密带隙和误差放大器在整个温度

范围内具有高精度，最大值为 1.5%。该器件包括集成

的热关断、电流限制、有源输出放电和欠压锁定

(UVLO) 功能。TLV752 的内部过流保护限制功能可在

发生短路事件时减少热耗散。

–

2mm × 2mm 10 引脚 WSON (DSQ)

•

有源输出放电

2 应用

•

微服务器和塔式服务器

门窗传感器

便携式销售终端 (EPOS)

可穿戴健身和活动监测仪

扫描仪

器件信息⁽¹⁾

器件型号

TLV752

封装

封装尺寸（标称值）

WSON (10)

2.00mm × 2.00mm

Wi-Fi 接入点

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

通信模块

典型应用

V_IN

V_OUT

INx

OUTx

C_IN

R₁

R₂

C_OUT

TLV752P

GND

FBx

V_EN

ENx

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBVS383

TLV752

ZHCSKJ0A –DECEMBER 2019–REVISED MARCH 2020

www.ti.com.cn

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information ................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 6

Detailed Description ............................................ 13

7.1 Overview ................................................................. 13

7.2 Functional Block Diagram ....................................... 13

7.3 Feature Description................................................. 13

7.4 Device Functional Modes........................................ 15

Application and Implementation ........................ 16

8.1 Application Information............................................ 16

8.2 Typical Application ................................................. 20

Power Supply Recommendations...................... 22

10 Layout................................................................... 22

10.1 Layout Guidelines ................................................. 22

10.2 Layout Example .................................................... 22

11 器件和文档支持 ..................................................... 23

11.1 器件支持................................................................ 23

11.2 文档支持................................................................ 23

11.3 接收文档更新通知 ................................................. 23

11.4 社区资源................................................................ 23

11.5 商标....................................................................... 23

11.6 静电放电警告......................................................... 23

11.7 Glossary................................................................ 23

12 机械、封装和可订购信息....................................... 23

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (December 2019) to Revision A

Page

•

Changed pins 5, 6, 8, 9, and 10 in Pin Configuration and Functions section ........................................................................ 3

TLV752

www.ti.com.cn

ZHCSKJ0A –DECEMBER 2019–REVISED MARCH 2020

5 Pin Configuration and Functions

DSQ Package

10-Pin Adjustable WSON

Top View

FB1

GND

EN1

GND

EN2

OUT1

IN1

Thermal

Pad

OUT2

FB2

IN2

Not to scale

Pin Functions

I/O

DESCRIPTION

NAME

NO.

Enable pin. Drive EN1 greater than V_EN1(HI)to turn on the regulator.

Drive EN1 less than V_EN1(LO)to put the low-dropout (LDO) regulator into shutdown mode.

EN1

Input

—

Enable pin. Drive EN2 greater than V_EN1(HI)to turn on the regulator.

Drive EN2 less than V_EN2(LO)to put the LDO into shutdown mode.

EN2

FB1

This pin is used as an input to the control loop error amplifier and is used to set the

output voltage of the LDO.

This pin is used as an input to the control loop error amplifier and is used to set the

output voltage of the LDO.

FB2

—

GND

2, 4

Ground pin

Input pin. For best transient response and to minimize input impedance, use the

recommended value or larger ceramic capacitor from IN to ground; see the

Recommended Operating Conditions table and the Input and Output Capacitor Selection

section. Place the input capacitor as close to the output of the device as possible.

IN1

IN2

Input

Input pin. For best transient response and to minimize input impedance, use the

recommended value or larger ceramic capacitor from IN to ground; see the

Recommended Operating Conditions table and the Input and Output Capacitor Selection

section. Place the input capacitor as close to the output of the device as possible.

Regulated output voltage pin. A capacitor is required from OUT to ground for stability.

For best transient response, use the nominal recommended value or larger ceramic

capacitor from OUT to ground; see the Recommended Operating Conditions table and

the Input and Output Capacitor Selection section. Place the output capacitor as close to

output of the device as possible.

OUT1

Output

Regulated output voltage pin. A capacitor is required from OUT to ground for stability.

For best transient response, use the nominal recommended value or larger ceramic

capacitor from OUT to ground; see the Recommended Operating Conditions table and

the Input and Output Capacitor Selection section. Place the output capacitor as close to

output of the device as possible.

OUT2

Output

—

Thermal pad

Pad

Connect the thermal pad to a large area GND plane for improved thermal performance.

TLV752

ZHCSKJ0A –DECEMBER 2019–REVISED MARCH 2020

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–40

MAX

6.5

UNIT

Supply voltage, V_IN

Enable voltage, V_EN;

6.5

Feedback Voltage, V_FB

Output voltage, V_OUT

2.0

V_IN+ 0.3⁽²⁾

Operating junction temperature, T_J

Storage temperature, T_stg

150

°C

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The absolute maximum rating is V_IN+ 0.3 V or 6.0 V, whichever is smaller

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.5

0.55

NOM

MAX

6.0

5.5

UNIT

V_IN

Input voltage

V_OUT

I_OUT

C_IN

Output voltage

Output current

Input capacitor

Output capacitor⁽¹⁾

μF

C_OUT

V_EN

f_EN

220

6.0

Enable voltage

Enable toggle frequency

Junction temperature

kHz

°C

T_J

–40

125

(1) Minimun derated capacitance of 0.47 μF is required for stability

6.4 Thermal Information

TLV752

THERMAL METRIC⁽¹⁾

DSQ (WSON)

10 PINS

74.6

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

90.5

39.7

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

3.8

ψ_JB

39.7

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

TLV752

www.ti.com.cn

ZHCSKJ0A –DECEMBER 2019–REVISED MARCH 2020

6.5 Electrical Characteristics

at operating temperature range (T_J= –40°C to 125°C), V_IN= V_OUT(NOM)+ 0.5 V or 1.5 V (whichever is greater), I_OUT= 1 mA,

V_EN= V_IN, and C_IN= C_OUT= 1 μF, unless otherwise noted. All typical values at T_J= 25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_FBx

Feedback voltage

T_J= 25°C

0.55

–0.5%

–1.5%

0.5%

1.5%

Output accuracy⁽¹⁾

–40°C ≤ T_J≤ +125°C; V_OUT(NOM)+ 0.5 V⁽²⁾≤ V_IN≤ 6.0 V

V_OUT(NOM)+ 0.5 V⁽²⁾≤ V_IN≤ 6.0 V

0.1 mA ≤ I_OUT≤ 1 A, V_IN= V_OUT+ 0.5 V⁽³⁾

Line regulation

Load regulation

0.03

V/A

T_J= 25°C

I_GND

Ground current

I_OUT= 0 mA

_EN≤ 0.3 V, 1.5 V ≤ V_IN≤ 6.0 V

µA

–40°C ≤ T_J≤ +125°C

I_SHDN

I_FB

Shutdown current

0.1

µA

Feedback pin current

0.01

0.1

V_OUT= V_OUT(NOM)

0.2 V, V_OUT< 1.5 V

1.22

1.54

670

1.83

850

V_IN= 2.0 V for V_OUT< 1.0 V,

otherwise V_IN= V_OUT(NOM)+ 1.0 V

I_CL

Output current limit

V_OUT= 0.9 x V_OUT(NOM),

V_OUT≥ 1.5 V

V_IN= 2.0 V for V_OUT< 1.0 V,

otherwise V_IN= V_OUT(NOM)+ 1.0 V

I_SC

Short-circuit current limit

V_OUT= 0 V

0.65 V ≤ V_OUT< 0.8 V

0.8 V ≤ V_OUT< 0.9 V

0.9 V ≤ V_OUT< 1.0 V

1.0 V ≤ V_OUT< 1.2 V

1.2 V ≤ V_OUT< 1.5 V

1.5 V ≤ V_OUT< 1.8 V

1.8 V ≤ V_OUT< 2.5 V

2.5 V ≤ V_OUT< 3.3 V

3.3 V ≤ V_OUT≤ 5.5 V

f = 1 kHz

896

765

700

600

464

332

264

193

161

1050

920

850

750

585

440

360

270

225

I_OUT= 1 A,

–40°C ≤ T_J≤ +125°C,

V_OUT= 0.95 × V_OUT(NOM)

V_DO

Dropout voltage

V_IN= V_OUT(NOM)+ 1 V,

I_OUT= 50 mA

PSRR

Power-supply rejection ratio

f = 100 kHz

f = 1 MHz

V_n

Output noise voltage

Undervoltage lockout

BW = 10 Hz to 100 kHz, V_OUT= 0.9 V

µV_RMS

V_INrising

V_INfalling

1.21

1.17

1.33

1.29

1.47

1.42

V_UVLO

Undervoltage lockout

hysteresis

V_{UVLO, HYST}

V_INhysteresis

t_STR

Startup time

From EN low-to-high transition to V_OUT= V_OUT(NOM)x 95%

500

700

0.3

µs

V_ENx(HI)

V_ENx(LO)

I_ENx

EN pin high voltage

EN pin low voltage

Enable pin current

Pulldown resistance

1.0

V_IN= V_EN= 6.0 V

R_PULLDOWN

V_IN= 6.0 V

Shutdown, temperature increasing

Reset, temperature decreasing

170

155

T_SD

Thermal shutdown

°C

(1) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.

(2) V_IN= 1.5 V for V_OUT< 1.0 V.

(3) V_IN= 2 V for V_OUT< 1.5 V.

TLV752

ZHCSKJ0A –DECEMBER 2019–REVISED MARCH 2020

www.ti.com.cn

6.6 Typical Characteristics

at operating temperature range T_J= 25°C, V_IN= V_OUT(NOM)+ 0.5 V or 1.5 V (whichever is greater), I_OUT= 1 mA, V_EN= V_IN, and

C_IN= C_OUT= 1 μF (unless otherwise noted)

0.6

0.45

0.3

0.6

0.45

0.3

0.15

-0.15

-0.3

-0.45

-0.6

-0.15

-0.3

-0.45

-0.6

T_J

œ20èC

0èC

T_J

œ20èC

0èC

œ50èC

œ40èC

25èC

85èC

125èC

150èC

œ50èC

œ40èC

25èC

85èC

125èC

150èC

3.8

4.2 4.4 4.6 4.8

Input Voltage (V)

5.2 5.4 5.6 5.8

1.5

2.5

3.5

4.5

5.5

Input Voltage (V)

V_OUT= 0.55 V, I_OUT= 1 mA

V_OUT= 3.3 V, I_OUT= 1 mA

图 1. 3.3-V Line Regulation vs V_IN

图 2. 0.55-V Line Regulation vs V_IN

320

280

240

200

160

120

0.3

0.2

0.1

T_J

œ20èC

0èC

œ50èC

œ40èC

25èC

85èC

125èC

150èC

-0.1

-0.2

-0.3

T_J

œ20èC

0èC

œ50èC

œ40èC

25èC

85èC

125èC

150èC

5.5

5.6

5.7

5.8

5.9

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

Input Voltage (V)

V_OUT= 5.5 V, I_OUT= 1 mA

图 3. 5.5-V Line Regulation vs V_IN

图 4. 3.3-V Dropout Voltage vs I_OUT

320

280

240

200

160

120

1,280

1,200

1,120

1,040

960

T_J

œ20èC

0èC

T_J

œ20èC

0èC

œ50èC

œ40èC

25èC

85èC

125èC

150èC

œ50èC

œ40èC

25èC

85èC

125èC

150èC

880

800

720

640

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

图 5. 0.55-V Dropout Voltage vs I_OUT

图 6. 5.5-V Dropout Voltage vs I_OUT

TLV752

www.ti.com.cn

ZHCSKJ0A –DECEMBER 2019–REVISED MARCH 2020

Typical Characteristics (接下页)

at operating temperature range T_J= 25°C, V_IN= V_OUT(NOM)+ 0.5 V or 1.5 V (whichever is greater), I_OUT= 1 mA, V_EN= V_IN, and

C_IN= C_OUT= 1 μF (unless otherwise noted)

1,100

1,000

900

800

700

600

500

400

300

200

100

1,200

1,050

900

750

600

450

300

150

T_J

œ20èC

0èC

œ50èC

œ40èC

25èC

85èC

125èC

150èC

T_J

œ20èC

0èC

œ50èC

œ40èC

25èC

85èC

125èC

150èC

0.5

1.5

2.5

Output Voltage (V)

3.5

4.5

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

I_OUT= 1 A

图 7. V_DOvs V_OUT

图 8. I_GNDvs I_OUT

2,100

1,800

1,500

1,200

900

560

480

400

320

240

160

T_J

œ20èC

0èC

T_J

œ20èC

0èC

œ50èC

œ40èC

25èC

85èC

125èC

150èC

œ50èC

œ40èC

25èC

85èC

125èC

150èC

600

300

-300

-80

0.6 1.2 1.8 2.4

Input Voltage (V)

3.6 4.2 4.8 5.4

0.6 1.2 1.8 2.4

Input Voltage (V)

3.6 4.2 4.8 5.4

V_EN= 0 V

V_OUT= 3.3 V, I_OUT= 0 mA

图 9. I_SHDNvs V_IN

图 10. I_GNDvs V_IN

1.6

1.2

0.8

0.4

0.8

0.6

0.4

0.2

T_J

œ20èC

0èC

T_J

œ20èC

0èC

œ50èC

œ40èC

25èC

85èC

125èC

150èC

œ50èC

œ40èC

25èC

85èC

125èC

150èC

-0.4

-0.8

-1.2

-1.6

-0.2

-0.4

-0.6

-0.8

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

V_IN= 3.8 V, V_OUT= 3.3 V

V_IN= 2 V, V_OUT= 0.55 V

图 11. 3.3-V Load Regulation vs I_OUT

图 12. 0.55-V Load Regulation vs I_OUT

TLV752

ZHCSKJ0A –DECEMBER 2019–REVISED MARCH 2020

www.ti.com.cn

Typical Characteristics (接下页)

at operating temperature range T_J= 25°C, V_IN= V_OUT(NOM)+ 0.5 V or 1.5 V (whichever is greater), I_OUT= 1 mA, V_EN= V_IN, and

C_IN= C_OUT= 1 μF (unless otherwise noted)

1.2

0.9

0.6

0.3

640

560

480

400

320

240

160

T_J

œ20èC

0èC

T_J

œ20èC

0èC

œ50èC

œ40èC

25èC

85èC

125èC

150èC

œ50èC

œ40èC

25èC

85èC

125èC

150èC

-0.3

-0.6

-0.9

-1.2

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

0.5

1.5

2.5

Pulldown Current (mA)

3.5

4.5

V_IN= 6 V, V_OUT= 5.5 V

图 13. 5-V Load Regulation vs I_OUT

图 14. V_OUTvs I_OUTPulldown Resistor

840

800

760

720

680

640

600

560

520

480

440

300

250

200

150

100

V_EN(LO)

V_EN(HI)

T_J

œ20èC

0èC

œ50èC

œ40èC

125èC

85èC

125èC

150èC

-50

-25

100

125

150

0.5

1.5

2.5

3.5

Input Voltage (V)

4.5

5.5

Temperature (èC)

V_EN= 5.5 V

图 15. V_EN(HI)and V_EN(LO)vs Temperature

图 16. I_ENvs V_IN

T_J

-20èC

0èC

Vin

Vout

4.5

-50èC

-40èC

25èC

85èC

125èC

3.5

-5

2.5

-10

-15

-20

-25

-30

-35

-40

-45

1.5

0.5

0.2 0.4 0.6 0.8

Output Current (A)

1.2 1.4 1.6 1.8

0.5

Time (ms)

1.5

V_OUT= 0.55 V, I_OUT= 1 mA, V_INslew rate = 1 V/µs

图 18. 0.55-V Line Transient

图 17. 3.3-V Foldback Current Limit vs I_OUT

TLV752

www.ti.com.cn

ZHCSKJ0A –DECEMBER 2019–REVISED MARCH 2020

Typical Characteristics (接下页)

at operating temperature range T_J= 25°C, V_IN= V_OUT(NOM)+ 0.5 V or 1.5 V (whichever is greater), I_OUT= 1 mA, V_EN= V_IN, and

C_IN= C_OUT= 1 μF (unless otherwise noted)

9.5

120

100

4.5

200

150

100

Iout

Vout

Vin

Vout

3.5

8.5

7.5

2.5

-50

6.5

-20

-40

-60

-80

-100

-120

-140

-160

1.5

-100

-150

-200

-250

-300

5.5

4.5

0.5

3.5

-0.5

50 100 150 200 250 300 350 400 450 500

Time (us)

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Time (ms)

V_OUT= 0.55 V, V_IN= 2 V, I_OUTslew rate = 1 A/µs

V_OUT= 3.3 V, I_OUT= 1 mA, V_INslew rate = 1 V/µs

图 20. 1-mA to 1-A Load Transient (0.55 V)

图 19. 3.3-V Line Transient

4.5

240

160

4.5

240

Iout

Vout

Iout

Vout

160

3.5

2.5

-80

2.5

-80

-160

-240

-320

-400

-480

-560

-160

-240

-320

-400

-480

-560

1.5

0.5

-0.5

50 100 150 200 250 300 350 400 450 500

Time (us)

60 120 180 240 300 360 420 480 540 600

Time (us)

V_OUT= 5 V, V_IN= 5.5 V, I_OUTslew rate = 1 A/µs

V_OUT= 3.3 V, V_IN= 3.8 V, I_OUTslew rate = 1 A/µs

图 21. 1-mA to 1-A Load Transient (5 V)

图 22. 1-mA to 1-A Load Transient (3.3 V)

4.5

3.5

2.5

1.5

0.5

Vout

Venable

Vin

Vout

Vin

-0.5

-1

200

400

600

800

1,000

200

400

600

800

1,000

Time (us)

V_IN= 3.8 V, V_OUT= 3.3 V, I_OUT= 1 mA

图 23. V_INPower-Up

图 24. Startup With EN

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Typical Characteristics (接下页)

at operating temperature range T_J= 25°C, V_IN= V_OUT(NOM)+ 0.5 V or 1.5 V (whichever is greater), I_OUT= 1 mA, V_EN= V_IN, and

C_IN= C_OUT= 1 μF (unless otherwise noted)

V_IN= 3.5 V

V_IN= 3.6 V

V_IN= 3.7 V

V_IN= 3.8 V

V_IN= 3.9 V

V_IN= 4.0 V

V_IN= 4.1 V

V_IN= 4.2 V

V_IN= 4.3 V

100

10k 100k

Frequency (Hz)

10M

100

10k

Frequency (Hz)

100k

10M

D001

V_OUT= 3.3 V, I_OUT= 500 mA, C_OUT= 2.2 µF

图 26. PSRR vs Frequency and V_IN

图 25. PSRR vs Frequency and V_IN

V_IN= 3.5 V

V_IN= 3.6 V

V_IN= 3.7 V

V_IN= 3.8 V

V_IN= 3.9 V

V_IN= 4.0 V

V_IN= 4.1 V

V_IN= 4.2 V

V_IN= 4.3 V

100

10k 100k

Frequency (Hz)

10M

100

10k 100k

Frequency (Hz)

10M

V_OUT= 3.3 V, I_OUT= 250 mA, C_OUT= 2.2 µF

图 27. PSRR vs Frequency and V_IN

图 28. PSRR vs Frequency and V_IN

V_IN= 1.9 V, V_OUT= 0.9 V

V_IN= 2.8 V, V_OUT= 1.8 V

V_IN= 4.3 V, V_OUT= 3.3 V

V_IN= 2.3 V, V_OUT= 1.8 V

V_IN= 2.8 V, V_OUT= 1.8 V

V_IN= 3.8 V, V_OUT= 3.3 V

V_IN= 4.3 V, V_OUT= 3.3 V

100

10k 100k

Frequency (Hz)

10M

100

10k 100k

Frequency (Hz)

10M

I_OUT= 500 mA, C_OUT= 2.2 µF

I_OUT= 1 A, C_OUT= 2.2 µF

图 29. PSRR vs Frequency

图 30. PSRR vs Frequency

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Typical Characteristics (接下页)

at operating temperature range T_J= 25°C, V_IN= V_OUT(NOM)+ 0.5 V or 1.5 V (whichever is greater), I_OUT= 1 mA, V_EN= V_IN, and

C_IN= C_OUT= 1 μF (unless otherwise noted)

C_OUT= 1 mF

C_FF= 0 nF

C_FF= 1 nF

C_FF= 10 nF

C_FF= 100 nF

C_OUT= 2.2 mF

C_OUT= 4.7 mF

C_OUT= 47 mF

100

10k 100k

Frequency (Hz)

10M

100

10k 100k

Frequency (Hz)

10M

V_IN= 3.8 V, V_OUT= 3.3 V, I_OUT= 500 mA

图 31. PSRR vs Frequency and C_OUT

图 32. PSRR vs Frequency and C_FF

I_OUT= 100mA, 170mV_RMS

I_OUT= 500mA, 169mV_RMS

I_OUT= 1A, 160mV_RMS

0.5

0.2

0.1

I_LOAD= 10 mA

I_LOAD= 100 mA

I_LOAD= 250 mA

I_LOAD= 500 mA

I_LOAD= 1 A

0.05

0.02

0.01

-10

0.005

100

10k 100k

Frequency (Hz)

10M

100

10k 100k

Frequency (Hz)

10M

V_IN= 3.8 V, V_OUT= 3.3 V, C_OUT= 2.2 µF

V_IN= 3.8 V, V_OUT= 3.3 V, C_OUT= 4.7 µF,

V_RMSBW = 10 Hz to 100 kHz

图 34. Output Spectral Noise Density vs Frequency

图 33. PSRR vs Frequency and I_LOAD

I_OUT= 10mA, 159mV_RMS

I_OUT= 100mA, 160mV_RMS

I_OUT= 500mA, 160mV_RMS

C_FF= 0 nF, 160 mV_RMS

C_FF= 1 nF, 108 mV_RMS

C_FF= 10 nF, 74 mV_RMS

C_FF= 100 nF, 44 mV_RMS

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

100

10k 100k

Frequency (Hz)

10M

100

10k 100k

Frequency (Hz)

10M

V_IN= 3.8 V, V_OUT= 3.3 V, C_OUT= 2.2 µF,

V_RMSBW = 10 Hz to 100 kHz

V_IN= 3.8 V, V_OUT= 3.3 V, I_OUT= 500 mA, C_OUT= 2.2 µF,

V_RMSBW = 10 Hz to 100 kHz

图 35. Output Spectral Noise Density vs Frequency

图 36. Output Spectral Noise Density vs

Frequency and C_FF

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Typical Characteristics (接下页)

at operating temperature range T_J= 25°C, V_IN= V_OUT(NOM)+ 0.5 V or 1.5 V (whichever is greater), I_OUT= 1 mA, V_EN= V_IN, and

C_IN= C_OUT= 1 μF (unless otherwise noted)

C_OUT= 2.2mF, 160 mV_RMS

C_OUT= 4.7mF, 170 mV_RMS

C_OUT= 47mF, 138 mV_RMS

V_IN=1.9V, V_OUT=0.9V, 53mV_RMS

V_IN=2.8V, V_OUT=1.8V, 96mV_RMS

V_IN=3.8V, V_OUT=3.3V, 160mV_RMS

0.5

0.2

0.1

0.2

0.1

0.05

0.02

0.01

0.02

0.01

0.005

100

10k 100k

Frequency (Hz)

10M

100

10k 100k

Frequency (Hz)

10M

V_IN= 3.8 V, V_OUT= 3.3 V, I_OUT= 100 mA, C_FF= 0 µF,

V_RMSBW = 10 Hz to 100 kHz

I_OUT= 500 mA, C_OUT= 2.2 µF, V_RMSBW = 10 Hz to 100 kHz

图 37. Output Spectral Noise Density vs

图 38. Output Spectral Noise Density vs Frequency

Frequency and C_OUT

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7 Detailed Description

7.1 Overview

The TLV752 is a low-dropout regulator (LDO) that consumes low quiescent current and delivers excellent line

and load transient performance. These characteristics, combined with low noise and good PSRR with low

dropout voltage, make this device ideal for portable consumer applications.

This regulator offers foldback current limit, shutdown, and thermal protection. The operating junction temperature

for this device is –40°C to +125°C.

7.2 Functional Block Diagram

OUT

Current

Limit

Thermal

Shutdown

–

UVLO

Band Gap

GND

Logic

7.3 Feature Description

7.3.1 Undervoltage Lockout (UVLO)

The TLV752 uses an undervoltage lockout (UVLO) circuit that disables the output until the input voltage is

greater than the rising UVLO voltage (V_UVLO). This circuit ensures that the device does not exhibit any

unpredictable behavior when the supply voltage is lower than the operational range of the internal circuitry. When

V_INis less than V_UVLO, the output is connected to ground with a pulldown resistor (R_PULLDOWN).

7.3.2 Shutdown

The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed V_EN(HI). Turn off the device

by forcing the EN pin to drop below V_EN(LO). If shutdown capability is not required, connect EN to IN.

The TLV752 has an internal pulldown MOSFET that connects an R_PULLDOWNresistor to ground when the device

is disabled. The discharge time after disabling depends on the output capacitance (C_OUT) and the load resistance

(R_L) in parallel with the pulldown resistor (R_PULLDOWN). 公式 1 calculates the time constant:

τ = ( R_PULLDOWN× R_L) / (R_PULLDOWN+ R_L)

(1)

7.3.3 Foldback Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults

or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a

brickwall scheme to a foldback scheme at the foldback voltage (V_FOLDBACK). In a high-load current fault with the

output voltage above V_FOLDBACK, the brickwall scheme limits the output current to the current limit (I_CL). When the

voltage drops below V_FOLDBACK, a foldback current limit activates that scales back the current as the output

voltage approaches GND. When the output is shorted, the device supplies a typical current called the short-

circuit current limit (I_SC). I_CLand I_SCare listed in the Electrical Characteristics table.

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Feature Description (continued)

For this device, V_FOLDBACK= 0.4 V × V_OUT(NOM)

The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the

device begins to heat up because of the increase in power dissipation. When the device is in brickwall current

limit, the pass transistor dissipates power [(V_IN– V_OUT) × I_CL]. When the device output is shorted and the output

is below V_FOLDBACK, the pass transistor dissipates power [(V_IN– V_OUT) × I_SC]. If thermal shutdown is triggered, the

device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If

the output current fault condition continues, the device cycles between current limit and thermal shutdown. For

more information on current limits, see the Know Your Limits application report.

Figure 39 shows a diagram of the foldback current limit.

V_OUT

Brickwall

V_OUT(NOM)

V_FOLDBACK

Foldback

0 V

I_OUT

I_RATED

0 mA

I_SC

I_CL

Figure 39. Foldback Current Limit

7.3.4 Thermal Shutdown

Thermal shutdown protection disables the output when the junction temperature rises to approximately 170°C.

Disabling the device eliminates the power dissipated by the device, allowing the device to cool. When the

junction temperature cools to approximately 155°C, the output circuitry is again enabled. Depending on power

dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off.

This cycling limits regulator dissipation, protecting the LDO from damage as a result of overheating.

Activating the thermal shutdown feature usually indicates excessive power dissipation as a result of the product

of the (V_IN– V_OUT) voltage and the load current. For reliable operation, limit junction temperature to 125°C

maximum. To estimate the margin of safety in a complete design, increase the ambient temperature until the

thermal protection is triggered; use worst-case loads and signal conditions.

The TLV752 internal protection circuitry protects against overload conditions but is not intended to be activated in

normal operation. Continuously running the TLV752 into thermal shutdown degrades device reliability.

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7.4 Device Functional Modes

7.4.1 Device Functional Mode Comparison

The Device Functional Mode Comparison table shows the conditions that lead to the different modes of

operation. See the Electrical Characteristics table for parameter values.

Table 1. Device Functional Mode Comparison

PARAMETER

OPERATING MODE

V_IN

V_EN

I_OUT

T_J

Normal operation

Dropout operation

V_IN> V_OUT(nom)+ V_DOand V_IN> V_IN(min)

V_IN(min)< V_IN< V_OUT(nom)+ V_DO

V_EN> V_EN(HI)

I_OUT< I_OUT(max)

T_J< T_SD(shutdown)

Disabled

(any true condition

disables the device)

V_IN< V_UVLO

V_EN< V_EN(LOW)

Not applicable

T_J> T_SD(shutdown)

7.4.2 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:

•

The input voltage is greater than the nominal output voltage plus the dropout voltage (V_OUT(nom)+ V_DO

The output current is less than the current limit (I_OUT< I_CL

The device junction temperature is less than the thermal shutdown temperature (T_J< T_SD

The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased to

less than the enable falling threshold

)

7.4.3 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage

tracks the input voltage. During this mode, the transient performance of the device becomes significantly

degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load

transients in dropout can result in large output-voltage deviations.

When the device is in a steady dropout state (defined as when the device is in dropout, V_IN< V_OUT(NOM)+ V_DO

directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the

ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output

voltage plus the dropout voltage (V_OUT(NOM)+ V_DO), the output voltage can overshoot for a short period of time

while the device pulls the pass transistor back into the linear region.

7.4.4 Disabled

The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN

pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned

off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal

discharge circuit from the output to ground.

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Adjustable Device Feedback Resistors

图 40 shows that the output voltage of the TLV752 can be adjusted from 0.55 V to 5.5 V by using a resistor

divider network.

V_OUT

OUT

C_IN

R₁

R₂

C_OUT

TLV752

GND

V_EN

DNC

图 40. Adjustable Operation

The adjustable-version device requires external feedback divider resistors to set the output voltage. V_OUTis set

using the feedback divider resistors, R₁and R₂, according to the following equation:

V_OUT= V_FB× (1 + R₁/ R₂)

(2)

For this device, V_FB= 0.55 V.

To ignore the FB pin current error term in the V_OUTequation, set the feedback divider current to 100x the FB pin

current listed in the Electrical Characteristics table. This setting provides the maximum feedback divider series

resistance, as shown in the following equation:

R₁+ R₂≤ V_OUT/ (I_FB× 100)

(3)

For this device, I_FB= 10 nA.

8.1.2 Input and Output Capacitor Selection

The TLV752 requires an output capacitance of 0.47 μF or larger for stability. Use X5R- and X7R-type ceramic

capacitors because these capacitors have minimal variation in value and equivalent series resistance (ESR) over

temperature. When choosing a capacitor for a specific application, pay attention to the dc bias characteristics for

the capacitor. Higher output voltages cause a significant derating of the capacitor. For best performance, the

maximum recommended output capacitance is 220 µF.

Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor

from IN to GND. Some input supplies have a high impedance, thus placing the input capacitor on the input

supply helps reduce the input impedance. This capacitor counteracts reactive input sources and improves

transient response, input ripple, and PSRR. If the input supply has a high impedance over a large range of

frequencies, several input capacitors can be used in parallel to lower the impedance over frequency. Use a

higher-value capacitor if large, fast, rise-time load transients are anticipated, or if the device is located several

inches from the input power source.

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Application Information (接下页)

8.1.3 Dropout Voltage

The TLV752 uses a PMOS pass transistor to achieve low dropout. When (V_IN– V_OUT) is less than the dropout

voltage (V_DO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the

R_DS(ON)of the PMOS pass element. V_DOscales approximately with output current because the PMOS device

behaves like a resistor in dropout mode. As with any linear regulator, PSRR and transient response degrade as

(V_IN– V_OUT) approaches dropout operation.

8.1.4 Exiting Dropout

Some applications have transients that place the LDO into dropout, such as slower ramps on V_INduring start-up.

As with other LDOs, the output may overshoot on recovery from these conditions. A ramping input supply causes

an LDO to overshoot on start-up, as shown in 图 41, when the slew rate and voltage levels are in the correct

range. Use an enable signal to avoid this condition.

Input Voltage

Response time for

LDO to get back into

regulation.

Load current discharges

output voltage.

V_IN= V_OUT(nom)+ V_DO

Output Voltage

Dropout

V_OUT= V_IN- V_DO

Output Voltage in

normal regulation.

Time

图 41. Startup Into Dropout

Line transients out of dropout can also cause overshoot on the output of the regulator. These overshoots are

caused by the error amplifier having to drive the gate capacitance of the pass element and bring the gate back to

the correct voltage for proper regulation. 图 42 illustrates what is happening internally with the gate voltage and

how overshoot can be caused during operation. When the LDO is placed in dropout, the gate voltage (VGS) is

pulled all the way down to ground to give the pass device the lowest on-resistance as possible. However, if a line

transient occurs when the device is in dropout, the loop is not in regulation and can cause the output to

overshoot until the loop responds and the output current pulls the output voltage back down into regulation. If

these transients are not acceptable, then continue to add input capacitance in the system until the transient is

slow enough to reduce the overshoot.

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Application Information (接下页)

Transient response

time of the LDO

Input Voltage

Load current

discharges

output

voltage

Output Voltage

V_DO

Output Voltage in

normal regulation

Dropout

V_OUT= V_IN- V_DO

VGS voltage

(pass device

fully off)

Input Voltage

VGS voltage for

normal operation

VGS voltage for

normal operation

Gate Voltage

VGS voltage in

dropout (pass device

fully on)

Time

图 42. Line Transients From Dropout

8.1.5 Reverse Current

As with most LDOs, excessive reverse current can damage this device.

Reverse current flows through the body diode on the pass element instead of the normal conducting channel. At

high magnitudes, this current flow degrades the long-term reliability of the device, as a result of one of the

following conditions:

•

Degradation caused by electromigration

Excessive heat dissipation

Potential for a latch-up condition

Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute

maximum rating of V_OUT> V_IN+ 0.3 V:

•

If the device has a large C_OUTand the input supply collapses with little or no load current

The output is biased when the input supply is not established

The output is biased above the input supply

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Application Information (接下页)

If reverse current flow is expected in the application, external protection must be used to protect the device. 图

43 shows one approach of protecting the device.

Schottky Diode

Internal Body Diode

OUT

Device

C_OUT

C_IN

GND

图 43. Example Circuit for Reverse Current Protection Using a Schottky Diode

8.1.6 Power Dissipation (P_D)

Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit

board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no

other heat-generating devices that cause added thermal stress.

To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference

and load conditions. Equation 4 calculates power dissipation (P_D).

P_D= (V_IN– V_OUT) × I_OUT

(4)

NOTE

Power dissipation can be minimized, and therefore greater efficiency can be achieved, by

correct selection of the system voltage rails. For the lowest power dissipation use the

minimum input voltage required for correct output regulation.

For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal

pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an

array of plated vias that conduct heat to additional copper planes for increased heat dissipation.

The maximum power dissipation determines the maximum allowable ambient temperature (T_A) for the device.

According to Equation 5, power dissipation and junction temperature are most often related by the junction-to-

ambient thermal resistance (R_θJA) of the combined PCB and device package and the temperature of the ambient

air (T_A).

T_J= T_A+ (R_θJA× P_D)

(5)

Thermal resistance (R_θJA) is highly dependent on the heat-spreading capability built into the particular PCB

design, and therefore varies according to the total copper area, copper weight, and location of the planes. The

junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC

standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.

8.1.7 Feed-Forward Capacitor (C_FF)

For the adjustable-voltage version device, a feed-forward capacitor (C_FF) can be connected from the OUT pin to

the FB pin. C_FFimproves transient, noise, and PSRR performance, but is not required for regulator stability.

Recommended C_FFvalues are listed in the Recommended Operating Conditions table. A higher capacitance C_FF

can be used; however, the startup time increases. For a detailed description of C_FFtradeoffs, see the Pros and

Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report.

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8.2 Typical Application

图 44 shows the typical application circuit for the TLV752. Input and output capacitances must be at least 1 µF.

V_OUT

OUT

C_IN

R₁

R₂

C_OUT

TLV752

GND

V_EN

DNC

图 44. TLV752 Typical Application

8.2.1 Design Requirements

Use the parameters listed in 表 2 for typical linear regulator applications.

表 2. Design Parameters

PARAMETER

Input voltage

DESIGN REQUIREMENT

3.8 V

Output voltage

3.3 V, ±1%

1 A (maximum)

1-A dc

Input current

Output load

Maximum ambient temperature

70°C

8.2.2 Detailed Design Procedure

Input and output capacitors are required to achieve the output voltage transient requirements. Capacitance

values of 2.2 µF are selected to give the maximum output capacitance in a small, low-cost package; see the

Input and Output Capacitor Selection section for details.

图 40 illustrates the output voltage of the TLV752. Set the output voltage using the resistor divider.

8.2.2.1 Input Current

During normal operation, the input current to the LDO is approximately equal to the output current of the LDO.

During startup, the input current is higher as a result of the inrush current charging the output capacitor. Use 公式

6 to calculate the current through the input.

_OUT´ dV_OUT(t)

V_OUT(t)

R_LOAD

I_OUT(t)

where:

•

V_OUT(t) is the instantaneous output voltage of the turn-on ramp

dV_OUT(t) / dt is the slope of the V_OUTramp

R_LOADis the resistive load impedance

(6)

8.2.2.2 Thermal Dissipation

The junction temperature can be determined using the junction-to-ambient thermal resistance (R_θJA) and the total

power dissipation (P_D). Use 公式 7 to calculate the power dissipation. Multiply P_Dby R_θJAas 公式 8 shows and

add the ambient temperature (T_A) to calculate the junction temperature (T_J).

P_D= (I_GND+ I_OUT) × (V_IN– V_OUT

)

(7)

(8)

T_J= R_θJA× P_D+ T_A

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Calculate the maximum ambient temperature as 公式 9 shows if the (T_J(MAX)) value does not exceed 125°C. 公式

10 calculates the maximum ambient temperature with a value of 84.85°C.

T_A(MAX)= T_J(MAX)– R_θJA× P_D

(9)

T_A(MAX)= 125°C – 80.3°C/W × (3.8 V – 3.3 V) × (1 A) = 84.85°C

(10)

8.2.3 Application Curve

I_LOAD= 10 mA

I_LOAD= 100 mA

I_LOAD= 250 mA

I_LOAD= 500 mA

I_LOAD= 1 A

-10

100

10k 100k

Frequency (Hz)

10M

V_IN= 3.8 V, V_OUT= 3.3 V, C_OUT= 2.2 µF

图 45. PSRR vs Frequency and I_LOAD

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9 Power Supply Recommendations

Connect a low output impedance power supply directly to the IN pin of the TLV752.

10 Layout

10.1 Layout Guidelines

•

Place input and output capacitors as close to the device as possible.

Use copper planes for device connections in order to optimize thermal performance.

Place thermal vias around the device to distribute heat.

Do not place a thermal via directly beneath the thermal pad of the DSQ package. A via can wick solder or

solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder

joint on the thermal pad.

10.2 Layout Example

Cff1

OUT1

IN1

FB1

GND

EN1

GND

EN2

OUT2

CFF2

FB2

IN2

GND

图 46. Layout Example for the DSQ Package

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11 器件和文档支持

11.1 器件支持

11.1.1 器件命名规则

表 3. 器件命名规则⁽¹⁾⁽²⁾

产品

V_OUT

P 表示有源输出放电功能。TPS746 系列的所有产品在器件处于禁用状态时都可以对输出进行主动放电。

yyy 为封装标识符。

TLV75201Pyyyz

z 为封装数量。R 表示卷（3000 片），T 表示带（250 片）。

(1) 要获得最新的封装和订货信息，请参阅本文档末尾的封装选项附录，或者访问器件产品文件夹（www.ti.com.cn）。

(2) 可提供 0.6V 至 5.0V 范围内的输出电压（以 50mV 为单位增量）。有关器件的详细信息和供货情况，请联系制造商。

11.2 文档支持

11.2.1 相关文档

请参阅如下相关文档：

德州仪器 (TI)，《使用前馈电容器和低压降稳压器的优缺点》应用报告

11.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 社区资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.5 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

18-Sep-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TLV75201PDSQR

TLV75201PDSQT

ACTIVE

WSON

DSQ

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

1XVH

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

18-Sep-2021

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

10-Feb-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV75201PDSQR

TLV75201PDSQT

WSON

DSQ

3000

250

180.0

8.4

2.3

1.15

4.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

10-Feb-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLV75201PDSQR

TLV75201PDSQT

WSON

DSQ

3000

250

210.0

185.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

DSQ0010A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

2.1

1.9

PIN 1 INDEX AREA

2.1

1.9

0.8

0.7

SEATING PLANE

0.08 C

0.05

0.00

0.9 0.1

SYMM

EXPOSED

THERMAL PAD

(0.2) TYP

SYMM

1.5 0.1

2X 1.6

8X 0.4

PIN 1 ID

0.25

0.15

10X

0.4

0.2

10X

0.1

C A B

0.05

4218906/A 04/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DSQ0010A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(0.9)

SEE SOLDER MASK

DETAIL

10X (0.5)

10X (0.2)

SYMM

(1.5)

8X (0.4)

SYMM

(0.5)

(R0.05) TYP

(

0.2) TYP

VIA

(1.9)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218906/A 04/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DSQ0010A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

10X (0.5)

10X (0.2)

(0.85)

8X (0.4)

SYMM

(1.38)

(R0.05) TYP

SYMM

(1.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 11

87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4218906/A 04/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知

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