TLV76701DRVR [TI]

具有可调节输出和固定输出的 1A、16V 正电压低压降 (LDO) 线性稳压器 | DRV | 6 | -40 to 125;


型号：	TLV76701DRVR
厂家：	TEXAS INSTRUMENTS
描述：	具有可调节输出和固定输出的 1A、16V 正电压低压降 (LDO) 线性稳压器 \| DRV \| 6 \| -40 to 125 稳压器
文件：	总38页 (文件大小：4422K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TLV767

SLVSE84C –DECEMBER 2018–REVISED JUNE 2020

TLV767 1-A, 16-V Precision Linear Voltage Regulator

1 Features

3 Description

The TLV767 is a wide input linear voltage regulator

supporting an input voltage range from 2.5 V to 16 V

and up to 1 A of load current. The output range is

from 0.8 V to 6.6 V or up to 13.6 V in the adjustable

version.

•

V_IN: 2.5 V to 16 V

V_OUT

–

0.8 V to 13.6 V (adjustable)

0.8 V to 6.6 V (fixed, 50-mV steps)

•

1% output accuracy over load and temperature

Low I_Q: 50 µA (typical, ~1.5 µA in shutdown)

Internal soft-start time: 500 µs (typical)

Fold-back current limiting and thermal protection

Stable with 1-µF ceramic capacitors

High PSRR: 70 dB at 1 kHz, 46 dB at 1 MHz

Temperature range: –40°C to +125°C

Package:

Additionally, the TLV767 has a 1% output accuracy

that can meet the needs of low voltage

microcontrollers (MCUs) and processors.

The TLV767 is designed to have a much lower I_Q

than traditional wide-V_INregulators, thus making the

device well positioned to meet the needs of

increasingly stringent standby power requirements.

When disabled, the TLV767 draws only 1.5 µA of I_Q.

The internal soft-start time and foldback current limit

reduce inrush current during startup, thus minimizing

input capacitance.

–

6-pin 2-mm × 2-mm WSON

8-pin 3-mm x 3-mm HVSSOP

Wide bandwidth PSRR performance is greater than

70 dB at 1 kHz and 46 dB at 1 MHz, which helps

attenuate the switching frequency of an upstream

DC/DC converter and minimizes post regulator

filtering. To allow for more flexibility, the TLV767 has

both fixed and adjustable versions.

2 Applications

•

Appliances

TVs, monitors, and set top boxes

Motion detectors (PIR, uWave, and so forth)

Motor drives and control boards

Printers and PC peripherals

Wi-Fi access points and routers

The TLV767 is available in a 6-pin, 2-mm × 2-mm

WSON (DRV) and an 8-pin 3-mm x 3-mm HVSSOP

(DGN) package.

Device Information⁽¹⁾

PART

NUMBER

PACKAGE

BODY SIZE (NOM)

WSON (6)

HVSSOP (8)

2.00 mm × 2.00 mm

3.00 mm x 3.00 mm

TLV767

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Typical Application Circuit

Reduced Inrush Current With 22 µF at C_OUT

0.75

OUT

0.5

0.25

R₁

C_FF

(opt.)

TLV767

C_OUT

C_IN

-0.25

-0.5

-0.75

-1

V_OUT

I_IN

V_IN

GND

R₂

V_EN

-1.25

-1.5

-1.75

-1

0.5

1.5

2.5

Time (ms)

3.5

4.5

D003

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TLV767

SLVSE84C –DECEMBER 2018–REVISED JUNE 2020

www.ti.com

Table of Contents

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 7

Detailed Description ............................................ 13

7.1 Overview ................................................................. 13

7.2 Functional Block Diagrams ..................................... 13

7.3 Feature Description................................................. 14

7.4 Device Functional Modes........................................ 16

Application and Implementation ........................ 17

8.1 Application Information............................................ 17

8.2 Typical Application .................................................. 20

Power Supply Recommendations...................... 21

10 Layout................................................................... 22

10.1 Layout Guidelines ................................................. 22

10.2 Layout Examples................................................... 22

11 Device and Documentation Support ................. 23

11.1 Device Support...................................................... 23

11.2 Documentation Support ....................................... 23

11.3 Receiving Notification of Documentation Updates 23

11.4 Support Resources ............................................... 23

11.5 Trademarks........................................................... 23

11.6 Electrostatic Discharge Caution............................ 23

11.7 Glossary................................................................ 23

12 Mechanical, Packaging, and Orderable

Information ........................................................... 24

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (April 2019) to Revision C

Page

•

Added DGN (HVSSOP) package to document ...................................................................................................................... 1

Changed Applications section ................................................................................................................................................ 1

Added DGN pinouts and pin information to Pin Configuration and Functions section........................................................... 3

Added HVSSOP thermal information .................................................................................................................................... 5

Added Layout Example for the Fixed HVSSOP Version and Layout Example for the Adjustable HVSSOP Version

figures to the Layout Examples section................................................................................................................................ 22

Changes from Revision A (December 2018) to Revision B

Page

•

Added Feedback divider current for adjustable device only.................................................................................................. 4

Added Quiescent current for fixed output devices.................................................................................................................. 5

Changed order of curves in Typical Characteristics to keep key figures side by side........................................................... 7

Added condition to V_OUTAccuracy vs V_INfigure..................................................................................................................... 7

Added adjustable-voltage version devices to condition statement of I_Qvs V_INfigure ............................................................ 7

Added I_Qvs Temperature figure ............................................................................................................................................ 7

Added in Dropout to caption of V_INTransient in Dropout From 4 V to 13 V figure ................................................................ 9

Changes from Original (December 2018) to Revision A

Page

•

Changed status from Advance Information to Production Data ............................................................................................ 1

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SLVSE84C –DECEMBER 2018–REVISED JUNE 2020

5 Pin Configuration and Functions

DRV Package (Adjustable)

6-Pin WSON

DGN Package (Adjustable)

8-Pin HVSSOP

Top View

OUT

Thermal

pad

GND

Thermal pad

GND

Not to scale

DRV Package (Fixed)

6-Pin WSON

DGN Package (Fixed)

8-Pin HVSSOP

Top View

OUT

SNS

GND

OUT

SNS

Thermal

pad

GND

Thermal pad

GND

Not to scale

Pin Functions

I/O

DESCRIPTION

DRV

(Adj)

DRV

(Fixed)

DGN

(Adj)

DGN

(Fixed)

NAME

Enable pin. Driving the enable pin high enables the device. Driving this pin low

disables the device. High and low thresholds are listed in the Electrical

Characteristics table. This pin has an internal pullup and can be left floating to

enable the device or the pin can be connected to the input pin.

Feedback pin. Input to the control-loop error amplifier. This pin is used to set the

output voltage of the device with the use of external resistors. Do not float this

pin. For adjustable-voltage version devices only.

3, 5

—

3, 5

4, 6

—

4, 6

GND

—

Ground pin. All ground pins must be grounded.

Input pin. Use the recommended capacitor value as listed in the Recommended

Operating Conditions table. Place the input capacitor as close to the IN and GND

pins of the device as possible.

Output pin. Use the recommended capacitor value as listed in the

Recommended Operating Conditions table. Place the output capacitor as close

to the OUT and GND pins of the device as possible.

OUT

SNS

Output sense pin. Connect the SNS pin to the OUT pin, or to remotely sense the

output voltage at the load, connect the SNS pin to the load. Do not float this pin.

For fixed-voltage version devices only.

—

Exposed pad of the package. Connect this pad to ground or leave floating.

Connect the thermal pad to a large-area ground plane for best thermal

performance.

Thermal

pad

Pad

—

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SLVSE84C –DECEMBER 2018–REVISED JUNE 2020

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

V_IN

–0.3

(3)

V_OUT

–0.3

V_IN+ 0.3

(3)

Voltage⁽²⁾

V_SNS

–0.3

V_FB

–0.3

V_EN

–0.3

Current

Maximum output current

Operating junction (T_J)

Internally Limited

–50

–65

150

Temperature

°C

Storage (T_STG

)

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages with respect to GND.

(3) V_IN+ 0.3 V or 18 V (whichever is smaller)

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per

±3000

ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2.5

NOM

MAX

UNIT

V_IN

Input voltage

V_EN

Enable voltage

V_OUT

I_OUT

Output voltage

0.8

13.6

0.8

Output current (2.5 V ≤ V_IN< 3 V)

Output current (V_IN≥ 3 V)

Output capacitor⁽¹⁾

I_OUT

C_OUT

C_OUTESR

C_IN

2.2

220

500

µF

mΩ

µF

µA

°C

Output capacitor ESR

Input capacitor

C_FF

Feed-forward capacitor (optional⁽²⁾, for adjustable device only)

Feedback divider current⁽²⁾(adjustable device only)

Junction temperature

I_{FB_DIVIDER}

T_J

–40

125

(1) Effective output capacitance of 0.5 µF minimum required for stability.

(2) C_FFrequired for stability if the feedback divider current < 5 µA. Feedback divider current = V_OUT/ (R₁+ R₂). See Feed-Forward

Capacitor (C_FF) section for details.

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SLVSE84C –DECEMBER 2018–REVISED JUNE 2020

6.4 Thermal Information

TLV767

THERMAL METRIC⁽¹⁾

DGN (HVSSOP)

DRV (WSON)

6 PINS

77.7

UNIT

8 PINS

60.1

81.7

32.8

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

92.3

40.8

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

4.3

Ψ_JB

32.7

15.5

40.8

R_θJC(bot)

18.9

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

Specified at T_J= –40°C to 125°C, V_IN= V_OUT(nom)+ 1.5 V or V_IN= 2.5 V (whichever is greater), FB/SNS tied to OUT, I_OUT= 10

mA, V_EN= 2 V, C_IN= 1.0 µF, C_OUT= 1.0 µF (unless otherwise noted). Typical values are at T_J= 25ºC.

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNIT

V_OUT

V_FB

Nominal output accuracy

T_J= 25°C

–0.5

–1

0.5

V_IN≥ 3.0 V, 1 mA ≤ I_OUT≤ 1 A

Output accuracy over temperature

Feedback voltage

2.5 V ≤ V_IN< 3.0 V, 1 mA ≤ I_OUT≤ 800 mA

–1

0.8

T_J= 25ºC

–0.5

–1

0.5

V_REF

I_FB

Internal reference (adjustable device)

Feedback pin current

V_FB= 1 V

ΔV_OUT(ΔVIN)Line regulation⁽¹⁾

V_OUT(NOM)+1.5 V ≤ V_IN≤ 16 V, I_OUT= 10 mA

1 mA ≤ I_OUT≤ 1 A, V_IN≥ 3.0 V

1 mA ≤ I_OUT≤ 800 mA, 2.5 V ≤ V_IN< 3.0 V

0.02 %/V

0.1

0.9

0.8

0.5

ΔV_OUT(ΔIOUT)Load regulation

%/A

0.5

_IN≥ 3.0V, I_OUT= 1 A, DGN package

_IN≥ 3.0V, I_OUT= 1 A, DRV package

1.5

V_DO

Dropout voltage⁽²⁾

1.4

1.3

1.6

2.5 V ≤ V_IN< 3.0 V, I_OUT= 800 mA

V_OUT= 0.9 x V_{OUT(NOM), IN}≥ 3.0V

1.1

I_CL

I_SC

I_Q

Output current limit

Short-circuit current limit

Quiescent current

V_OUT= 0.9 x V_OUT(NOM), 2.5 V ≤ V_IN< 3.0 V

V_OUT= 0 V, DGN package

V_OUT= 0 V, DRV package

I_OUT= 0 mA

0.81

250

150

350

µA

Fixed output devices, I_OUT= 0 mA

I_OUT= 1 A, V_IN≥ 3.0 V

I_GND

Ground current

1.5

µA

I_SHUTDOWN

V_EN(HIGH)

V_EN(LOW)

I_EN

Shutdown current

V_EN≤ 0.4 V, V_IN= 16 V

Enable pin logic high

Enable pin logic low

Enable pullup current

Output pulldown current

Power-supply rejection ratio

2.5 V ≤ V_IN≤ 16 V

1.2

2.5 V ≤ V_IN≤ 16 V

0.4

V_EN= 0 V

400

1.2

I_PULLDOWN

PSRR

V_IN= 16 V, V_OUT= 2.5 V, V_EN=0V

V_IN= 3.3 V, V_OUT= 1.8 V, I_OUT= 300 mA, f = 120 Hz

BW = 10 Hz to 100 kHz, V_IN= 3.3 V, V_OUT= 0.8 V,

I_OUT= 100 mA

V_n

Output noise voltage

µV_RMS

V_UVLO+

UVLO threshold rising

UVLO hysteresis

V_INrising

2.2

2.4

V_UVLO(HYS)

V_UVLO-

130

UVLO threshold falling

V_INfalling

1.9

(1) Line regulation is measured with V_IN= V_OUT(NOM)+ 1.5 V or 2.5 V (whichever is greater)

(2) V_DOis measured with V_IN= 95% x V_OUT(nom)for fixed output devices. V_DOis not measured for fixed output devices when V_OUT< 2.5 V.

For adjustable output device, V_DOis measured with V_FB= 95% x V_FB(nom)

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Electrical Characteristics (continued)

Specified at T_J= –40°C to 125°C, V_IN= V_OUT(nom)+ 1.5 V or V_IN= 2.5 V (whichever is greater), FB/SNS tied to OUT, I_OUT= 10

mA, V_EN= 2 V, C_IN= 1.0 µF, C_OUT= 1.0 µF (unless otherwise noted). Typical values are at T_J= 25ºC.

PARAMETER

TEST CONDITIONS

Temperature increasing

MIN TYP MAX UNIT

T_SD(shutdown)Thermal shutdown temperature

180

160

ºC

T_SD(reset)

Thermal shutdown reset temperature

Temperature falling

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SLVSE84C –DECEMBER 2018–REVISED JUNE 2020

6.6 Typical Characteristics

at operating temperature T_J= 25°C, V_IN= V_OUT(NOM)+ 1.5 V or 2.5 V (whichever is greater), I_OUT= 10 mA, V_EN= 2.0 V, C_IN

1.0 µF, and C_OUT= 1.0 µF (unless otherwise noted)

0.2

0.1

0.2

0.1

-0.1

-0.2

-0.3

-0.4

-0.1

-0.2

T_J

-0.3

-50°C

-40°C

0°C

25°C

85°C

125°C

150°C

-50°C

-40°C

0°C

25°C

85°C

125°C

150°C

0.6

-0.4

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

0.1

0.2

0.3

0.4

Output Current (A)

0.5

0.7

0.8

V_IN= 3.0 V

V_IN= 2.5 V

Figure 1. V_OUTAccuracy vs I_OUT

Figure 2. V_OUTAccuracy vs I_OUT

0.2

0.1

T_J

-50°C

-40°C

0°C

25°C

85°C

125°C

150°C

-0.1

-0.2

-0.3

-0.4

T_J

-50°C

-40°C

0°C

25°C

85°C

125°C

150°C

Input Voltage (V)

2.5

5.5

8.5 10 11.5 13 14.5 16

Input Voltage (V)

I_OUT= 10 mA

Figure 4. I_SHUTDOWNvs V_IN

Figure 3. V_OUTAccuracy vs V_IN

T_J

V_OUT

2.8 V

3.3 V

-50°C

-40°C

0°C

25°C

85°C

125°C

150°C

0.8 V

1.8 V

5.0 V

2.5

4.5

6.5

8.5 10.5

Input Voltage (V)

12.5

14.5

-50

-25

Temperature (°C)

100

125

150

I_OUT= 0 mA, adjustable-voltage version devices

I_OUT= 0 mA, fixed-voltage version devices

Figure 5. I_Qvs V_IN

Figure 6. I_Qvs Temperature

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Typical Characteristics (continued)

at operating temperature T_J= 25°C, V_IN= V_OUT(NOM)+ 1.5 V or 2.5 V (whichever is greater), I_OUT= 10 mA, V_EN= 2.0 V, C_IN

1.0 µF, and C_OUT= 1.0 µF (unless otherwise noted)

2.5

T_J

-50°C

-40°C

-0°C

25°C

85°C

125°C

150°C

1.5

0.5

T_J

-50°C

-40°C

-0°C

25°C

85°C

125°C

150°C

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

0.1

0.2

0.3

Output Current (A)

0.4

0.5

0.6

0.7

0.8

V_IN= 3.0 V

V_IN= 2.5 V

Figure 7. I_GNDvs I_OUT

Figure 8. I_GNDvs I_OUT

300

700

150

T_J

I_OUT

V_OUT

200

100

600

500

400

300

200

100

-50°C

-40°C

0°C

25°C

85°C

125°C

150°C

130

110

-100

-200

-300

-400

-500

-600

-700

-800

-900

-100

-200

-300

-400

-500

-10

0.5

1.5

Input Voltage (V)

2.5

100 200 300 400 500 600 700 800 900 1000

Time (µs)

D021

I_OUT= 0 mA

Figure 9. I_QIncrease Below Minimum V_IN

V_IN= 5 V, V_OUT= 3.3 V, C_FF= 10 pF, ramp rate = 0.4 A/µs

Figure 10. I_OUTTransient From 0 mA to 100 mA

1000

700

1500

1000

500

700

600

500

400

300

200

100

I_OUT

V_OUT

750

500

600

500

400

300

200

100

250

-500

-250

-500

-750

-1000

-1250

-1500

-1750

-2000

-1000

-1500

-2000

-2500

-3000

-3500

-4000

-4500

-100

-200

-300

-400

-500

-100

-200

-300

-400

-500

I_OUT

V_OUT

80 100 120 140 160 180 200

Time (µs)

50 100 150 200 250 300 350 400 450 500

Time (µs)

D035

D034

V_IN= 5 V, V_OUT= 3.3 V, ramp rate = 0.8 A/µs

V_IN= 5 V, V_OUT= 3.3 V, C_FF= 10 pF, ramp rate = 0.5 A/µs

Figure 12. I_OUTTransient From 250 mA to 850 mA

Figure 11. I_OUTTransient From 1 mA to 1 A

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Typical Characteristics (continued)

at operating temperature T_J= 25°C, V_IN= V_OUT(NOM)+ 1.5 V or 2.5 V (whichever is greater), I_OUT= 10 mA, V_EN= 2.0 V, C_IN

1.0 µF, and C_OUT= 1.0 µF (unless otherwise noted)

800

V_OUT

V_IN

V_OUT

V_IN

600

400

200

-10

-20

-30

-40

-50

-200

-400

-600

-800

100 200 300 400 500 600 700 800 900 1000

Time (µs)

100 200 300 400 500 600 700 800 900 1000

Time (µs)

D037

D038

V_OUT= 3.3 V, I_OUT= 1 A, V_INramp rate = 0.6 V/µs

V_OUT= 3.3 V, I_OUT= 33 µA, V_INramp rate = 1.6 V/µs

Figure 13. V_INTransient in Dropout From 4 V to 13 V

Figure 14. V_INTransient From 5 V to 16 V

1.4

1.3

1.2

1.1

1.4

1.3

1.2

1.1

T_J

-50°C

-40°C

0°C

25°C

85°C

125°C

150°C

-50°C

-40°C

0°C

25°C

85°C

125°C

150°C

0.9

0.8

0.7

0.6

0.5

0.9

0.8

0.7

0.6

0.5

4.5

7.5

Input Voltage (V)

10.5

13.5

15 16

2.5

5.5

8.5

Input Voltage (V)

11.5

14.5

I_OUT= 1.0 A

I_OUT= 0.8 A

Figure 15. V_DOvs V_IN

Figure 16. V_DOvs V_IN

1.4

1.2

1.4

1.2

T_J

-50°C

-40°C

0°C

25°C

85°C

125°C

150°C

-50°C

-40°C

0°C

25°C

85°C

125°C

150°C

0.8

0.6

0.4

0.2

0.8

0.6

0.4

0.2

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

0.1

0.2

0.3

0.4

0.5

Output Current (A)

0.6

0.7

0.8

V_IN= 3.0 V

V_IN= 2.5 V

Figure 17. V_DOvs I_OUT

Figure 18. V_DOvs I_OUT

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Typical Characteristics (continued)

at operating temperature T_J= 25°C, V_IN= V_OUT(NOM)+ 1.5 V or 2.5 V (whichever is greater), I_OUT= 10 mA, V_EN= 2.0 V, C_IN

1.0 µF, and C_OUT= 1.0 µF (unless otherwise noted)

150

125

100

150

125

100

T_J

-50°C

-40°C

0°C

25°C

85°C

125°C

150°C

-50°C

-40°C

0°C

25°C

85°C

125°C

150°C

0.2

0.4

0.6

Output Current (A)

0.8

1.2

1.4

1.6

0.2

0.4

0.6

Output Current (A)

0.8

1.2

1.4

1.6

V_IN= 3.0 V

V_IN= 2.5 V

Figure 19. Foldback Current Limit vs Temperature

Figure 20. Foldback Current Limit vs Temperature

5.5

V_OUT

V_IN

V_EN

V_OUT

V_IN

V_EN

4.5

3.5

2.5

1.5

0.5

-0.5

0.5

1.5

2.5

Time (ms)

3.5

4.5

0.5

1.5

2.5

Time (ms)

3.5

4.5

D004

D032

Enable pulled up internally, V_OUT= 0.8 V

V_OUT= 3.3 V

Figure 21. Startup With Separate V_ENand V_IN

Figure 22. Startup With V_ENFloating

0.9

0.85

0.8

0.9

0.85

0.8

V_EN(HIGH)

V_EN(LOW)

0.75

0.7

0.75

0.7

0.65

0.6

0.65

0.6

V_EN(HIGH)

V_EN(LOW)

-50

-25

100

125

150

-50

-25

100

125

150

Temperature (èC)

V_IN= 2.5 V

V_IN= 16 V

Figure 23. V_ENThresholds vs Temperature

Figure 24. V_ENThresholds vs Temperature

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Typical Characteristics (continued)

at operating temperature T_J= 25°C, V_IN= V_OUT(NOM)+ 1.5 V or 2.5 V (whichever is greater), I_OUT= 10 mA, V_EN= 2.0 V, C_IN

1.0 µF, and C_OUT= 1.0 µF (unless otherwise noted)

2.3

100

V_UVLO+(V_INrising)

V_UVLO-(V_INfalling)

2.25

2.2

2.15

2.1

I_OUT

60 mA

300 mA

550 mA

1.0 A

2.05

-50

-25

100

125

150

100

10k 100k

Frequency (Hz)

10M

Temperature (èC)

V_OUT= 1.8 V, V_IN= 3.3 V, C_FF= 1 nF

Figure 25. UVLO Thresholds vs Temperature

Figure 26. PSRR vs I_OUT

100

V_IN

2.8 V

3.0 V

3.3 V

3.5 V

3.8 V

4.0 V

4.3 V

C_FF

0 nF

1.0 nF

100

10k 100k

Frequency (Hz)

10M

100

10k

Frequency (Hz)

100k

10M

D001

V_OUT= 3.3 V, V_IN= 4.8 V, I_OUT= 0.33 A

V_OUT= 1.8 V, I_OUT= 0.55 A, C_FF= 1 nF

Figure 28. PSRR vs C_FF

Figure 27. PSRR vs V_IN

700

600

500

400

300

200

100

0.5

0.2

0.1

0.05

V_OUT

0.8 V, RMS Noise = 66.4 mV_RMS

3.3 V, RMS Noise = 216.5 mV_RMS

T_J

0.02

0.01

-50°C

-40°C

0°C

25°C

85°C

125°C

150°C

0.005

100

10k

Frequency (Hz)

100k

10M

2.5

4.5

6.5

8.5 10.5

Input Voltage (V)

12.5

14.5

C_FF= 0 nF, I_OUT= 0.1 A, RMS noise BW = 10 Hz to 100 kHz

V_EN= 0 V

Figure 30. I_ENvs V_IN

Figure 29. Output Noise (V_n) vs V_OUT

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Typical Characteristics (continued)

at operating temperature T_J= 25°C, V_IN= V_OUT(NOM)+ 1.5 V or 2.5 V (whichever is greater), I_OUT= 10 mA, V_EN= 2.0 V, C_IN

1.0 µF, and C_OUT= 1.0 µF (unless otherwise noted)

1.5

1.4

1.3

1.2

1.1

100

V_IN

2.5 V

7.5 V

12.5 V

16 V

T_J

-50°C

-40°C

0°C

25°C

85°C

125°C

150°C

0.9

-10

2.5

4.5

6.5

8.5 10.5

Input Voltage (V)

12.5

14.5

-50

-25

Temperature (°C)

100

125

150

V_OUT= 2.5 V

V_FB= 1.0 V

Figure 31. I_PULLDOWNvs V_IN

Figure 32. I_FBvs Temperature

0.75

0.5

0.75

0.5

0.25

-0.25

-0.5

-0.75

-1

-0.25

-0.5

V_OUT

I_IN

V_IN

V_EN

V_OUT

I_IN

V_IN

V_EN

-0.75

-1

-1.25

-1.5

-1.75

-1.25

-1.5

-1

-1.75

0.5

1.5

2.5

Time (ms)

3.5

4.5

0.5

1.5

2.5

Time (ms)

3.5

4.5

D003

D031

V_OUT= 3.3 V, I_OUT= 33 µA

Figure 33. Startup Inrush Current With C_OUT= 22 µF

V_OUT= 3.3 V, I_OUT= 33 µA

Figure 34. Startup Inrush Current With C_OUT= 47 µF

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7 Detailed Description

7.1 Overview

The TLV767 is a low quiescent current, high PSRR linear regulator capable of handling up to 1 A of load current.

Unlike typical high current linear regulators, the TLV767 consumes significantly less quiescent current. This

device is ideal for high current applications that require very sensitive power-supply rails.

This device features integrated foldback current limit, thermal shutdown, output enable, internal output pulldown

and undervoltage lockout (UVLO). This device delivers excellent line and load transient performance. This device

is low noise and exhibits a very good PSRR. The operating ambient temperature range of the device is –40°C to

125°C.

7.2 Functional Block Diagrams

Current Limit

OUT

Internal

Controller

UVLO

0.8-V

Reference

Thermal

Shutdown

Output

Pulldown

GND

Figure 35. Adjustable Version Block Diagram

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Functional Block Diagrams (continued)

Current Limit

OUT

SNS

R₁

2 pF

Internal

Controller

UVLO

R₂

0.8-V

Reference

Thermal

Shutdown

Output

Pulldown

Internal Resistors

R1 531 kΩ or 1.062 MΩ

66.9 kΩ œ 8.5 MΩ

GND

Figure 36. Fixed Version Block Diagram

7.3 Feature Description

7.3.1 Output Enable

The enable pin for the device is an active-high pin. The output voltage is enabled when the voltage of the enable

pin is greater than the high-level input voltage of the EN pin and disabled with the enable pin voltage is less than

the low-level input voltage of the EN pin. If independent control of the output voltage is not needed, connect the

enable pin to the input of the device.

This device has an internal pullup current on the EN pin. The EN pin can be left floating to enable the device.

The device has an internal pulldown circuit that activates when the device is disabled to actively discharge the

output voltage.

7.3.2 Dropout Voltage

Dropout voltage (V_DO) is defined as the input voltage minus the output voltage (V_IN– V_OUT) at the rated output

current (I_RATED), where the pass transistor is fully on. I_RATEDis the maximum I_OUTlisted in the Recommended

Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch.

The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output

voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the

nominal output regulation, then the output voltage falls as well.

For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (R_DS(ON)) of the

pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for

that current scales accordingly. Use Equation 1 to calculate the R_DS(ON)of the device.

V_DO

R_DS(ON)

I_RATED

(1)

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Feature Description (continued)

7.3.3 Foldback Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults

or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a

brickwall scheme to a foldback scheme at the foldback voltage (V_FOLDBACK). In a high-load current fault with the

output voltage above V_FOLDBACK, the brickwall scheme limits the output current to the current limit (I_CL). When the

voltage drops below V_FOLDBACK, a foldback current limit activates that scales back the current as the output

voltage approaches GND. When the output is shorted, the device supplies a typical current called the short-

circuit current limit (I_SC). I_CLand I_SCare listed in the Electrical Characteristics table.

For this device, V_FOLDBACK= 50% × V_OUT(nom)

The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the

device begins to heat up because of the increase in power dissipation. When the device is in brickwall current

limit, the pass transistor dissipates power [(V_IN– V_OUT) × I_CL]. When the device output is shorted and the output

is below V_FOLDBACK, the pass transistor dissipates power [(V_IN– V_OUT) × I_SC]. If thermal shutdown is triggered, the

device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If

the output current fault condition continues, the device cycles between current limit and thermal shutdown. For

more information on current limits, see the Know Your Limits application report.

Figure 37 shows a diagram of the foldback current limit.

V_OUT

Brickwall

V_OUT(NOM)

V_FOLDBACK

Foldback

0 V

I_OUT

I_RATED

0 mA

I_SC

I_CL

Figure 37. Foldback Current Limit

7.3.4 Undervoltage Lockout (UVLO)

The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a

controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input

drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.

7.3.5 Output Pulldown

The device has an output pulldown circuit. V_OUTpulldown sink to ground capability is listed in the Electrical

Characteristics table. The output pulldown activates under the following conditions:

•

Device disabled

1.0 V < V_IN< V_UVLO

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Feature Description (continued)

The output pulldown current for this device is 1.2 mA typical, as listed in the Electrical Characteristics table.

Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input

supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can

cause damage to the device. See the Reverse Current section for more details.

7.3.6 Thermal Shutdown

The device contains a thermal shutdown protection circuit to disable the device when the junction temperature

(T_J) of the pass transistor rises to T_SD(shutdown)(typical). Thermal shutdown hysteresis assures that the device

resets (turns on) when the temperature falls to T_SD(reset)(typical).

The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when

thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can be high

from large V_IN– V_OUTvoltage drops across the device or from high inrush currents charging large output

capacitors. Under some conditions, the thermal shutdown protection disables the device before startup

completes.

For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating

Conditions table. Operation above this maximum temperature causes the device to exceed its operational

specifications. Although the internal protection circuitry of the device is designed to protect against thermal

overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device

into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.

7.4 Device Functional Modes

7.4.1 Device Functional Mode Comparison

The Device Functional Mode Comparison table shows the conditions that lead to the different modes of

operation. See the Electrical Characteristics table for parameter values.

Table 1. Device Functional Mode Comparison

PARAMETER

OPERATING MODE

V_IN

V_EN

I_OUT

T_J

Normal operation

Dropout operation

V_IN> V_OUT(nom)+ V_DOand V_IN> V_IN(min)

V_IN(min)< V_IN< V_OUT(nom)+ V_DO

V_EN> V_EN(HI)

I_OUT< I_OUT(max)

T_J< T_SD(shutdown)

Disabled

(any true condition

disables the device)

V_IN< V_UVLO

V_EN< V_EN(LOW)

Not applicable

T_J> T_SD(shutdown)

7.4.2 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:

•

The input voltage is greater than the nominal output voltage plus the dropout voltage (V_OUT(nom)+ V_DO

The output current is less than the current limit (I_OUT< I_CL

The device junction temperature is less than the thermal shutdown temperature (T_J< T_SD

The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased to

less than the enable falling threshold

)

7.4.3 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage

tracks the input voltage. During this mode, the transient performance of the device becomes significantly

degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load

transients in dropout can result in large output-voltage deviations.

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When the device is in a steady dropout state (defined as when the device is in dropout, V_IN< V_OUT(NOM)+ V_DO

directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the

ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output

voltage plus the dropout voltage (V_OUT(NOM)+ V_DO), the output voltage can overshoot for a short period of time

while the device pulls the pass transistor back into the linear region.

7.4.4 Disabled

The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN

pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned

off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal

discharge circuit from the output to ground.

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Adjustable Device Feedback Resistors

The adjustable-version device requires external feedback divider resistors to set the output voltage. V_OUTis set

using the feedback divider resistors, R₁and R₂, according to the following equation:

V_OUT= V_FB× (1 + R₁/ R₂)

(2)

To ignore the FB pin current error term in the V_OUTequation, set the feedback divider current to 100x the FB pin

current listed in the Electrical Characteristics table. This setting provides the maximum feedback divider series

resistance, as shown in the following equation:

R₁+ R₂≤ V_OUT/ (I_FB× 100)

(3)

8.1.2 Recommended Capacitor Types

The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input

and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and

are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and

C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of

Y5V-rated capacitors is discouraged because of large variations in capacitance.

Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and

temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input

and output capacitors recommended in the Recommended Operating Conditions table account for an effective

capacitance of approximately 50% of the nominal value.

8.1.3 Input and Output Capacitor Requirements

Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor

from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple,

and PSRR. An input capacitor is recommended if the source impedance is more than 0.5 Ω. A higher value

capacitor may be necessary if large, fast rise-time load or line transients are anticipated or if the device is located

several inches from the input power source.

Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor

within the range specified in the Recommended Operating Conditions table for stability.

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Application Information (continued)

8.1.4 Reverse Current

Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the

pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the

long-term reliability of the device.

Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute

maximum rating of V_OUT≤ V_IN+ 0.3 V.

•

If the device has a large C_OUTand the input supply collapses with little or no load current

The output is biased when the input supply is not established

The output is biased above the input supply

If reverse current flow is expected in the application, external protection is recommended to protect the device.

Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation

is anticipated.

Figure 38 shows one approach for protecting the device.

Schottky Diode

Internal Body Diode

OUT

Device

C_OUT

C_IN

GND

Figure 38. Example Circuit for Reverse Current Protection Using a Schottky Diode

8.1.5 Feed-Forward Capacitor (C_FF)

For the adjustable-voltage version device, a feed-forward capacitor (C_FF) can be connected from the OUT pin to

the FB pin. C_FFimproves transient, noise, and PSRR performance, but is not required for regulator stability.

Recommended C_FFvalues are listed in the Recommended Operating Conditions table. A higher capacitance C_FF

can be used; however, the startup time increases. For a detailed description of C_FFtradeoffs, see the Pros and

Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report.

C_FFand R₁form a zero in the loop gain at frequency f_Z, while C_FF, R₁, and R₂form a pole in the loop gain at

frequency f_P. C_FFzero and pole frequencies can be calculated from the following equations:

f_Z= 1 / (2 × π × C_FF× R₁)

(4)

(5)

f_P= 1 / (2 × π × C_FF× (R₁|| R₂))

C_FF≥ 10 pF is required for stability if the feedback divider current is less than 5 µA. Equation 6 calculates the

feedback divider current.

I_{FB_Divider}= V_OUT/ (R₁+ R₂)

(6)

To avoid startup time increases from C_FF, limit the product C_FF× R₁< 50 µs.

For an output voltage of 0.8 V with the FB pin tied to the OUT pin, no C_FFis used.

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Application Information (continued)

8.1.6 Power Dissipation (P_D)

Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit

board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no

other heat-generating devices that cause added thermal stress.

To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference

and load conditions. Equation 7 calculates power dissipation (P_D).

P_D= (V_IN– V_OUT) × I_OUT

(7)

NOTE

Power dissipation can be minimized, and therefore greater efficiency can be achieved, by

correct selection of the system voltage rails. For the lowest power dissipation use the

minimum input voltage required for correct output regulation.

For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal

pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an

array of plated vias that conduct heat to additional copper planes for increased heat dissipation.

The maximum power dissipation determines the maximum allowable ambient temperature (T_A) for the device.

According to Equation 8, power dissipation and junction temperature are most often related by the junction-to-

ambient thermal resistance (R_θJA) of the combined PCB and device package and the temperature of the ambient

air (T_A).

T_J= T_A+ (R_θJA× P_D)

(8)

Thermal resistance (R_θJA) is highly dependent on the heat-spreading capability built into the particular PCB

design, and therefore varies according to the total copper area, copper weight, and location of the planes. The

junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC

standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.

8.1.7 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures

of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal

resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi

metrics are determined to be significantly independent of the copper area available for heat-spreading. The

Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization

parameter (ψ_JT) and junction-to-board characterization parameter (ψ_JB). These parameters provide two methods

for calculating the junction temperature (T_J). As described in , use the junction-to-top characterization parameter

(ψ_JT) with the temperature at the center-top of device package (T_T) to calculate the junction temperature. As

described in , use the junction-to-board characterization parameter (ψ_JB) with the PCB surface temperature 1 mm

from the device package (T_B) to calculate the junction temperature.

T_J= T_T+ ψ_JT× P_D

where:

•

P_Dis the dissipated power

T_Tis the temperature at the center-top of the device package

(9)

T_J= T_B+ ψ_JB× P_D

where

•

T_Bis the PCB surface temperature measured 1 mm from the device package and centered on the package

edge

(10)

For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package

Thermal Metrics application report.

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8.2 Typical Application

This section discusses implementing this device for a typical application. Figure 39 shows the application circuit.

OUT

R₁

C_FF

(opt.)

TLV767

C_OUT

C_IN

GND

R₂

Figure 39. Typical Application Circuit

8.2.1 Design Requirements

Table 2 summarizes the design requirements for this application.

Table 2. Design Parameters

PARAMETER

Input voltage

Output voltage

Output current

DESIGN REQUIREMENT

5 V

3.3 V

100 mA

8.2.2 Detailed Design Procedure

8.2.2.1 Transient Response

As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude.

If load transients are expected with ramp rates greater than 0.5 A/µs, use a 2.2-µF or larger output capacitor.

8.2.3 Choose Feedback Resistors

For this design example, V_OUTis set to 3.3 V. The following equations set the feedback divider resistors for the

desired output voltage:

V_OUT= V_FB× (1 + R₁/ R₂)

(11)

(12)

R₁+ R₂≤ V_OUT/ (I_FB× 100)

For improved output accuracy, use Equation 12 and I_FB= 50 nA as listed in the Electrical Characteristics table to

calculate the upper limit for series feedback resistance (R₁+ R₂≤ 660 kΩ).

The control-loop error amplifier drives the FB pin to the same voltage as the internal reference (V_FB= 0.8 V, as

listed in the Electrical Characteristics table). Use Equation 11 to determine the ratio of R₁/ R₂= 3.125. Use this

ratio and solve Equation 12 for R₂. Now calculate the upper limit for R₂≤ 160 kΩ. Select a standard value

resistor for R₂= 160 kΩ.

Reference Equation 11 and solve for R₁:

R₁= (V_OUT/ V_FB– 1) × R₂

(13)

From Equation 13, R₁= 500 kΩ can be determined. Select a standard value resistor for R₁= 499 kΩ. V_OUT

3.3 V (as determined by Equation 11).

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8.2.4 Application Curves

300

200

700

600

500

400

300

200

100

I_OUT

V_OUT

100

-100

-200

-300

-400

-500

-600

-700

-800

-900

-100

-200

-300

-400

-500

I_OUT

100 mA

100

10k

Frequency (Hz)

100k

10M

100 200 300 400 500 600 700 800 900 1000

Time (µs)

D021

V_IN= 5 V, V_OUT= 3.3 V, C_OUT= 1 µF, C_FF= 0 pF

V_IN= 5 V, V_OUT= 3.3 V, C_OUT= 1 µF, C_FF= 10 pF

Figure 41. PSRR Performance

Figure 40. Load Transient Response, I_OUT0 mA to 100 mA

9 Power Supply Recommendations

This device is designed to operate from an input supply voltage range of 2.5 V to 16 V. To ensure that the output

voltage is well regulated and dynamic performance is optimum, the input supply must be at least V_OUT(nom)

1.5 V. For 1-A output current operation, the input supply must be 3 V or greater. Connect a low output

impedance power supply directly to the input pin of the TLV767.

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10 Layout

10.1 Layout Guidelines

•

Place input and output capacitors as close to the device as possible

Use copper planes for device connections to IN, OUT, and GND pins to optimize thermal performance

Place thermal vias around the device to distribute heat

10.2 Layout Examples

V_IN

C_IN

V_OUT

C_FF

(opt.)

V_OUT

V_IN

C_IN

R₁

C_OUT

GND

R₂

GND PLANE

Represents via used for application-specific connections

Figure 42. Layout Example for the Adjustable

WSON Version

Figure 43. Layout Example for the Fixed WSON

Version

V_OUT

V_IN

V_OUT

V_IN

C_OUT

C_FF

(OPT)

C_OUT

R₁

R₂

C_IN

GND

GND PLANE

Represents via used for application-specific connections

GND PLANE

Represents via used for application-specific connections

Figure 44. Layout Example for the Fixed HVSSOP

Version

Figure 45. Layout Example for the Adjustable

HVSSOP Version

Submit Documentation Feedback

Product Folder Links: TLV767

TLV767

www.ti.com

SLVSE84C –DECEMBER 2018–REVISED JUNE 2020

11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

Table 3. Available Options⁽¹⁾

PRODUCT

V_OUT

xx(x) is nominal output voltage. For output voltages with a resolution of 100 mV, two

digits are used in the ordering number; otherwise, three digits are used (for example, 33

= 3.3 V; 125 = 1.25 V). 01 indicates adjustable output version.

yyy is package designator.

TLV767xx(x)yyyz

z is package quantity. R is for large quantity reel, T is for small quantity reel.

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

•

Texas Instruments, TLV767EVM-014 Evaluation module user's guide

Texas Instruments, Pros and cons of using a feedforward capacitor with a low-dropout regulator application

report

•

Texas Instruments, Know your limits application report

Texas Instruments, Universal low-dropout (LDO) linear voltage regulator MultiPkgLDOEVM-823 evaluation

module user's guide

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.5 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

Submit Documentation Feedback

Product Folder Links: TLV767

TLV767

SLVSE84C –DECEMBER 2018–REVISED JUNE 2020

www.ti.com

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Documentation Feedback

Product Folder Links: TLV767

PACKAGE OPTION ADDENDUM

www.ti.com

2-May-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TLV76701DGNR

PREVIEW

HVSSOP

DGN

2500

Non-RoHS &

Non-Green

Call TI

-40 to 125

TLV76701DRVR

TLV76701DRVT

TLV76708DGNR

ACTIVE

WSON

DRV

DGN

3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR

-40 to 125

1RMH

250

RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR

1RMH

PREVIEW

HVSSOP

2500

Non-RoHS &

Non-Green

Call TI

TLV76708DRVR

TLV76708DRVT

TLV76718DGNR

TLV76718DRVR

TLV76718DRVT

TLV76725DGNR

TLV76728DGNR

TLV76728DRVR

TLV76728DRVT

TLV76733DGNR

TLV76733DRVR

TLV76733DRVT

TLV76750DGNR

TLV76750DRVR

TLV76750DRVT

ACTIVE

WSON

DRV

DGN

DRV

DGN

DRV

DGN

DRV

DGN

DRV

3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR

250 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR

2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR

3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR

250 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR

-40 to 125

1RNH

2BMX

1ROH

2GT7

2BNX

1RPH

2BOX

1RQH

2BPX

1RRH

HVSSOP

WSON

HVSSOP

WSON

2500 RoHS & Green

NIPDAUAG

Level-2-260C-1 YEAR

3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR

250 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR

2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR

3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR

250 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR

2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR

3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR

250 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR

WSON

HVSSOP

WSON

HVSSOP

WSON

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

2-May-2021

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TLV767 :

Automotive : TLV767-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-May-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV76701DRVR

TLV76701DRVT

TLV76708DRVR

TLV76708DRVT

TLV76718DGNR

TLV76718DRVR

TLV76718DRVT

TLV76725DGNR

TLV76728DGNR

TLV76728DRVR

TLV76728DRVT

TLV76733DGNR

WSON

DRV

3000

250

180.0

178.0

180.0

178.0

180.0

330.0

178.0

180.0

178.0

330.0

180.0

178.0

180.0

178.0

330.0

8.4

12.4

8.4

12.4

8.4

12.4

2.3

1.15

1.0

4.0

8.0

4.0

8.0

4.0

8.0

12.0

8.0

12.0

8.0

12.0

3000

250

2.25

2.3

2.25

2.3

1.15

1.0

2.25

2.3

2.25

2.3

250

1.15

1.4

HVSSOP DGN

2500

3000

250

5.3

3.4

WSON

DRV

2.25

2.3

2.25

2.3

1.0

1.15

1.0

2.3

250

2.25

5.3

2.25

3.4

HVSSOP DGN

2500

3000

250

1.4

5.3

3.4

1.4

WSON

DRV

2.3

1.15

1.0

2.25

2.3

2.25

2.3

1.15

1.0

250

2.25

5.3

2.25

3.4

HVSSOP DGN

2500

1.4

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-May-2021

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV76733DRVR

TLV76733DRVT

TLV76750DGNR

TLV76750DRVR

TLV76750DRVT

WSON

DRV

3000

250

180.0

178.0

180.0

330.0

180.0

178.0

180.0

178.0

8.4

12.4

8.4

2.3

2.25

2.3

2.25

2.3

1.15

1.0

4.0

8.0

4.0

8.0

12.0

8.0

1.0

250

1.15

1.4

HVSSOP DGN

2500

3000

250

5.3

3.4

WSON

DRV

2.3

1.15

1.0

2.25

2.3

2.25

2.3

1.15

1.0

250

2.25

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLV76701DRVR

TLV76701DRVT

TLV76708DRVR

TLV76708DRVT

TLV76718DGNR

TLV76718DRVR

WSON

HVSSOP

WSON

DRV

DGN

DRV

3000

250

210.0

205.0

210.0

205.0

210.0

366.0

205.0

185.0

200.0

185.0

200.0

185.0

364.0

200.0

35.0

33.0

35.0

33.0

35.0

50.0

33.0

3000

250

2500

3000

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-May-2021

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLV76718DRVR

TLV76718DRVT

TLV76725DGNR

TLV76728DGNR

TLV76728DRVR

TLV76728DRVT

TLV76733DGNR

TLV76733DRVR

TLV76733DRVT

TLV76750DGNR

TLV76750DRVR

TLV76750DRVT

WSON

HVSSOP

WSON

HVSSOP

WSON

HVSSOP

WSON

DRV

DGN

DRV

DGN

DRV

DGN

DRV

3000

250

210.0

205.0

366.0

210.0

205.0

210.0

205.0

366.0

210.0

205.0

210.0

366.0

210.0

205.0

210.0

205.0

185.0

200.0

364.0

185.0

200.0

185.0

200.0

364.0

185.0

200.0

185.0

364.0

185.0

200.0

185.0

200.0

35.0

33.0

50.0

35.0

33.0

35.0

33.0

50.0

35.0

33.0

35.0

50.0

35.0

33.0

35.0

33.0

250

2500

3000

250

2500

3000

250

2500

3000

250

Pack Materials-Page 3

GENERIC PACKAGE VIEW

DRV 6

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4206925/F

PACKAGE OUTLINE

DRV0006A

WSON - 0.8 mm max height

SCALE 5.500

PLASTIC SMALL OUTLINE - NO LEAD

2.1

1.9

PIN 1 INDEX AREA

2.1

1.9

0.8

0.7

SEATING PLANE

0.08 C

(0.2) TYP

0.05

0.00

0.1

EXPOSED

THERMAL PAD

1.3

1.6 0.1

4X 0.65

0.35

0.25

PIN 1 ID

(OPTIONAL)

0.3

0.2

0.1

C A

0.05

4222173/B 04/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DRV0006A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

6X (0.45)

6X (0.3)

(1)

SYMM

(1.6)

(1.1)

4X (0.65)

SYMM

(1.95)

(R0.05) TYP

(

0.2) VIA

TYP

LAND PATTERN EXAMPLE

SCALE:25X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222173/B 04/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.

www.ti.com

EXAMPLE STENCIL DESIGN

DRV0006A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

SYMM

6X (0.45)

METAL

6X (0.3)

(0.45)

SYMM

4X (0.65)

(0.7)

(R0.05) TYP

(1)

(1.95)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD #7

88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:30X

4222173/B 04/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

GENERIC PACKAGE VIEW

DGN 8

3 x 3, 0.65 mm pitch

PowerPAD VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225482/A

www.ti.com

PACKAGE OUTLINE

DGN0008G

PowerPAD^TMVSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

5.05

4.75

TYP

0.1 C

SEATING

PLANE

PIN 1 INDEX AREA

6X 0.65

3.1

2.9

1.95

NOTE 3

0.38

0.25

3.1

2.9

0.13

C A B

NOTE 4

0.23

0.13

SEE DETAIL A

EXPOSED THERMAL PAD

0.25

GAGE PLANE

2.15

1.95

1.1 MAX

0.15

0.05

0.7

0.4

0 -8

DETAIL A

TYPICAL

1.846

1.646

4225480/A 11/2019

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187.

www.ti.com

EXAMPLE BOARD LAYOUT

DGN0008G

PowerPAD^TMVSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

(2)

NOTE 9

(1.846)

SYMM

METAL COVERED

BY SOLDER MASK

SOLDER MASK

DEFINED PAD

8X (1.4)

(R0.05) TYP

8X (0.45)

(3)

NOTE 9

SYMM

(2.15)

(1.22)

6X (0.65)

(

0.2) TYP

VIA

SEE DETAILS

(0.55)

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 15X

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4225480/A 11/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

9. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

DGN0008G

PowerPAD^TMVSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

(1.846)

BASED ON

0.125 THICK

STENCIL

SYMM

(R0.05) TYP

8X (1.4)

8X (0.45)

(2.15)

SYMM

BASED ON

0.125 THICK

STENCIL

6X (0.65)

METAL COVERED

BY SOLDER MASK

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

(4.4)

SOLDER PASTE EXAMPLE

EXPOSED PAD 9:

100% PRINTED SOLDER COVERAGE BY AREA

SCALE: 15X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

2.06 X 2.40

1.846 X 2.15 (SHOWN)

1.69 X 1.96

0.125

0.15

0.175

1.56 X 1.82

4225480/A 11/2019

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party

intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,

costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s

applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TLV76701DRVR [TI]

相关型号：

TLV76701DRVT

TLV76701QWDRBRQ1

TLV76708DGNR

TLV76708DRVR

TLV76708DRVT

TLV76718DGNR

TLV76718DRVR

TLV76718DRVT

TLV76725DGNR

TLV76728DGNR

TLV76728DRVR

TLV76728DRVT