TLV840CADL28DBVR [TI]
TLV840 Nano-Power Ultra-Low Voltage Supervisor with Adjustable Reset Time Delay;
| 型号： | TLV840CADL28DBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TLV840 Nano-Power Ultra-Low Voltage Supervisor with Adjustable Reset Time Delay |
| 文件： | 总29页 (文件大小：1937K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV840
SNVSBC3C – DECEMBER 2019 – REVISED SEPTEMBER 2020
TLV840 Nano-Power Ultra-Low Voltage Supervisor with Adjustable Reset Time Delay
1 Features
3 Description
•
•
•
Operating voltage range : 0.7 V to 6 V
Nano supply current : 120 nA (Typical)
Fixed threshold voltage (VIT-): 0.8 V to 5.4 V
– Threshold voltages available in 100mV steps
– High accuracy: ±0.5% (Typical)
– Built-in hysteresis (VHYS): 5% (Typical)
Reset time delay (tD): capacitor-based
programmable (TLV840C, TLV840M)
– Minimum time delay: 40 µs (typical) without
capacitor
The TLV840 family of voltage supervisors or reset ICs
can operate at high voltage levels while maintaining
very low quiescent current across the whole VDD and
temperature range. TLV840 offers best combination of
low power consumption, high accuracy and low
propagation delay (tp_HL= 30 µs typical).
Reset output signal is asserted when the voltage at
VDD drops below the negative voltage threshold
(VIT-). Reset signal is cleared when VDD rise above
VIT- plus hysteresis (VHYS) and the reset time delay
(tD) expires. Reset time delay can be programmed by
connecting a capacitor between the CT pin and
ground for TLV840C and TLV840M. For a minimum
reset delay time the CT pin can be left floating.
TLV840N does not offer a programmable delay and
offers fixed reset delay timing options: 40 µs, 2 ms, 10
ms, 30 ms, 50 ms, 80 ms, 100 ms, 150 ms, 200 ms.
•
•
•
Active-low manual reset (MR) (TLV840M)
Four output topologies:
– TLV840xxDL: open-drain, active-low (RESET)
– TLV840xxPL: push-pull, active-low (RESET)
– TLV840xxDH: open-drain, active-high (RESET)
– TLV840xxPH: push-pull, active-high (RESET)
Wide temperature range: –40°C to +125°C
Package: SOT23-5 (DBV)
•
•
Additional features: Low power-on reset voltage
(VPOR), built-in glitch immunity protection for VDD,
built-in hysteresis, low open-drain output leakage
2 Applications
current (Ilkg(OD)). TLV840 is
a
perfect voltage
•
•
•
•
•
•
•
Motor Drives
monitoring solution for industrial applications and
battery-powered / low-power applications.
Factory Automation and Control
Home Theater and Entertainment
Electronic Point of Sale
Grid Infrastructure
Data Center and Enterprise Computing
Multifunction Printer
Device Information
PART NUMBER
TLV840
PACKAGE(1)
BODY SIZE (NOM)
SOT-23 (5) (DBV)
2.90 mm × 1.60 mm
(1) For package details, see the mechanical drawing addendum
at the end of the data sheet.
0.4
25°C
-40°C
125°C
0.36
0.32
0.28
0.24
0.2
3.3 V
5 V
IN
LDO
OUT
*Rpu
VDD
VDD
Microcontroller
RESET
CT
RESET
TLV840CADL29
GND
0.16
0.12
0.08
*Rpu only for open-drain output
Typical Application Circuit
0.5
1
1.5
2
2.5
3 3.5
VDD (V)
4
4.5
5
5.5
6
IDDv
Typical Supply Current
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV840
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SNVSBC3C – DECEMBER 2019 – REVISED SEPTEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................3
6 Pin Configuration and Functions...................................4
Pin Functions.................................................................... 4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................5
7.4 Thermal Information ...................................................5
7.5 Electrical Characteristics ............................................6
7.6 Timing Requirements .................................................7
7.7 Timing Diagrams ........................................................8
7.8 Typical Characteristics................................................9
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram.........................................10
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................14
9 Application and Implementation..................................15
9.1 Application Information............................................. 15
9.2 Typical Application.................................................... 15
10 Power Supply Recommendations..............................18
11 Layout...........................................................................19
11.1 Layout Guidelines................................................... 19
11.2 Layout Example...................................................... 19
12 Device and Documentation Support..........................20
12.1 Device Nomenclature..............................................20
12.2 Receiving Notification of Documentation Updates..21
12.3 Support Resources................................................. 21
12.4 Trademarks.............................................................21
13 Mechanical, Packaging, and Orderable
Information.................................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (July 2020) to Revision C (September 2020)
Page
•
•
•
•
Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Updated Pin Connections...................................................................................................................................4
Added Timing Diagram....................................................................................................................................... 8
New Typical Characteristics................................................................................................................................9
Changes from Revision A (February 2020) to Revision B (July 2020)
Page
•
APL to RTM release............................................................................................................................................1
Changes from Revision * (December 2019) to Revision A (February 2020)
Page
•
Initial APL Release............................................................................................................................................. 1
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5 Device Comparison
Figure 5-1 shows the device naming nomenclature to compare the different device variants. See Table 12-1 for a
more detailed explanation.
TLV 840 X X XX XX XXX
Package
DBV: SOT23
Detect Voltage Threshold
Output Type
DL: Open-drain,
active-low
PL: Push-pull,
active-low
Feature Option
Delay Option
A: 40 µs
B: 2 ms
C: 10 ms
D: 30 ms
E: 50 ms
F: 80 ms
08: 0.8V
...
54: 5.4V
N: no capacitor delay (CT),
no manual reset (MR)
C: Capacitor delay (CT)
M: Capacitor delay (CT) and
manual reset (MR)
DH: Open-drain,
active-high
PH: Push-pull,
active-high
G: 100 ms
H: 150 ms
I: 200 ms
Figure 5-1. Device Naming Nomenclature
Orderable part numbers starting with TLV840C and TLV840M are only available with the delay option A.
However, longer delays can be achieved through an external capacitor on the CT pin. Leaving the CT pin
floating will result in typical 40us delay for these 2 feature options.
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6 Pin Configuration and Functions
CT
CT
RESET
VDD
1
2
3
RESET
VDD
1
2
3
5
5
NC
MR
GND
4
GND
4
Not to scale
Not to scale
Figure 6-1. Pin Configuration TLV840C,
DBV Package, 5-Pin SOT-23,
TLV840C Top View
Figure 6-2. Pin Configuration TLV840M,
DBV Package, 5-Pin SOT-23,
TLV840M Top View
RESET
VDD
1
2
3
5
NC
NC
GND
4
Not to scale
Figure 6-3. Pin Configuration TLV840N,
DBV Package, 5-Pin SOT-23,
TLV840N Top View
Pin Functions
PIN
TLV840CxL TLV840MxL
I/O
DESCRIPTION
PIN
TLV840NxL
NUMBER
1
RESET
RESET
RESET
O
Active-Low Output Reset Signal: This pin is driven logic low when
VDD voltage falls below the negative voltage threshold (VIT-). RESET
remains low (asserted) for the delay time period (tD) after VDD voltage
rises above VIT+=VIT-+VHYS
.
2
3
4
VDD
GND
NC
VDD
GND
MR
VDD
GND
NC
I
_
I
Input Supply Voltage TLV840 monitors VDD voltage
Ground
Manual Reset Pull this pin to a logic low to assert a reset signal in the
RESEToutput pin. After MRpin is left floating or pulls to logic high, the
RESEToutput deasserts to the nominal state after the reset delay time
(tD)expires.
NC stands for “No Connect”. The pin can be left floating.
Recommended connection to GND.
5
CT
CT
NC
-
Capacitor Time Delay Pin. The CT pin offers a user-programmable
delay time. Connect an external capacitor on this pin to adjust time
delay. When not in use leave pin floating for the smallest fixed time
delay.
NC stands for “No Connect”. The pin can be left floating.
Recommended connection to GND.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted(1)
MIN
–0.3
–0.3
–0.3
–20
–40
–65
MAX
6.5
UNIT
Voltage
Voltage
VDD
V
CT, MR (2), RESET (TLV840xxPL)
RESET (TLV840xxDL)
RESET, RESET pin
VDD+0.3 (3)
V
6.5
Current
20
mA
℃
Temperature (4)
Temperature (4)
Operating ambient temperature, TA
Storage, Tstg
125
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) If the logic signal driving MRis less than VDD, then additional current flows into VDD and out of MR.
(3) The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller
(4) As a result of the low dissipated power in this device, it is assumed that TJ = TA.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
± 2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101(2)
± 750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0.7
0
NOM
MAX
6
UNIT
VDD (TLV840xxxL)
Voltage
V
CT, RESET (TLV840xxxL), MR
RESET pin current
6
Current
TA
–5
5
mA
Operating ambient temperature
–40
125
℃
7.4 Thermal Information
TLV840
DBV (SOT23-5)
5 PINS
193.5
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
117.9
98.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
43.4
ψJB
97.8
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
At 0.7 V ≤ VDD ≤ 6 V, CT = MR= Open, RESETpull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset
load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted.
VDD ramp rate ≤ 100 mV/µs. Typical values are at TA = 25℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COMMON PARAMETERS
VDD
VIT–
VHYS
Input supply voltage
TLV840xxxL
0.7
–2.5
–2
6
2.5
2
V
%
%
VIT- = 0.8 V to 1.7 V
VIT- = 1.8 V to 5.4 V
±0.5
±0.5
5
Negative-going input threshold accuracy
(1)
Hysteresis on VIT– pin
2.5
7
TA = –40℃ to
85℃
0.12
0.12
0.15
0.15
0.3
1.0
0.4
VDD = 2 V
VIT– = 0.8 V to 1.8 V
IDD
Supply current into VDD pin (2)
µA
TA = –40℃ to
85℃
VDD = 6 V
VIT– = 0.8 V to 5.5 V
1.2
V MR_L
V MR_H
R MR
Manual reset logic low input (2)
Manual reset logic high input (2)
Manual reset internal pull-up resistance
CT pin internal resistance
0.3VDD
V
V
0.7VDD
100
500
kΩ
kΩ
RCT
TLV840xxDL (Open-drain active-low)
VOL(max) = 300 mV
IOUT(Sink) = 15 µA
VPOR
Power on Reset Voltage (3)
700
300
300
300
mV
mV
VDD = 0.7 V, 0.8 V ≤ VIT– ≤ 1.5 V
IOUT(Sink) = 15 µA
Low level output voltage
VDD =1.5 V, 1.6 V ≤ VIT– ≤ 3.3 V
IOUT(Sink) = 500 µA
VOL
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.5 V
IOUT(Sink) = 2 mA
VDD = VPULLUP = 6V
TA = –40℃ to 85℃
10
10
100
350
nA
nA
Ilkg(OD)
Open-Drain output leakage current
VDD = VPULLUP = 6V
TLV840xxPL (Push-pull active-low)
VOL(max) = 300 mV
IOUT(Sink) = 15 µA
VPOR
Power on Reset Voltage (3)
Low level output voltage
700
300
300
300
mV
mV
VDD = 0.7 V, 0.8 V ≤ VIT– ≤ 1.5 V
IOUT(Sink) = 15 µA
VDD = 1.5 V, 1.6 V ≤ VIT– ≤ 3.3 V
IOUT(Sink) = 500 µA
VOL
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.5 V
IOUT(Sink) = 2 mA
VDD = 1.8 V, 0.8 V ≤ VIT– ≤ 1.4 V
IOUT(Source) = 500 µA
0.8VDD
0.8VDD
0.8VDD
High level output voltage
VDD = 3.3 V, 1.5 V ≤ VIT– ≤ 3.0 V
IOUT(Source) = 500 µA
VOH
V
VDD = 6 V, 3.1 V ≤ VIT– ≤ 5.5 V
IOUT(Source) = 2 mA
(1) VIT– threshold voltage range from 0.8 V to 5.4 V (for DL, PL versions) in 100 mV steps
(2) If the logic signal driving MRis less than VDD, then IDD current increases based on voltage differential
(3) VPOR is the minimum VDD voltage level for a controlled output state
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7.6 Timing Requirements
At 0.7 V ≤ VDD ≤ 6 V, CT = MR= Open, RESETpull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset
load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted.
VDD ramp rate ≤ 100 mV/µs. Typical values are at TA = 25℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Propagation detect delay for VDD falling
below VIT–
VDD : (VIT+ + 10%) to (VIT– – 10%)
tP_HL
30
50
µs
(1)
CT pin = Open or NC
(VIT- - 10%) to (VIT+ + 10%)
TLV840xA
40
80
µs
tD
Reset time delay
TLV840CA,
CT pin = 10 nF
CT pin = 1 µF
6.2
619
10
ms
ms
µs
TLV840MA
tGI_VIT–
t MR_PW
Glitch immunity VIT–
5% VIT– overdrive(2)
MR pin pulse duration to assert reset (3)
500
ns
Propagation delay from MR low to reset
assertion
VDD = 3.3 V,
MR= V MR_H to V MR_L
t MR_RES
t MR_tD
1
µs
VDD = 3.3 V,
MR= V MR_L to V MR_H
Delay from MR release to reset deassert
tD
ms
(1) tP_HL measured from threshold trip point (VIT–) to RESET assert. VIT+ = VIT– + VHYS
(2) Overdrive % = [(VDD/ VIT–) – 1] × 100%
(3) Refer section on Manual Reset Input for min pulse width needed on MR pin
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7.7 Timing Diagrams
VIT+
VIT-
VDD
VPOR
VDD(0v)
tD
tP_HL
tD
tP_HL
tD
VOH
RESET
VOL
(1) Open-Drain timing diagram where RESET is pulled up to VDD via a pull-up resistor
(2) RESEToutput is undefined when VDD is < VPOR
Figure 7-1. Timing Diagram TLV840DL (Open-Drain Active-Low)
VIT+
VIT-
VDD
VPOR
tP_HL
tD
tD
tD
tP_HL
VOH
RESET
VOL
(3) RESEToutput is undefined when VDD is < VPOR and limited to VOL for VDD slew rate = 100mV / μS
Figure 7-2. Timing Diagram TLV840PL (Push-Pull Active-Low)
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7.8 Typical Characteristics
Typical characteristics show the typical performance of the TLV840 device. Test conditions are TA = 25°C,
VDD = 3.3 V, RPull-Up = 100 kΩ, CLOAD = 50 pF, unless otherwise noted.
0.4
25°C
-40°C
125°C
0.36
0.32
0.28
0.24
0.2
0.16
0.12
0.08
0.5
1
1.5
2
2.5
3 3.5
VDD (V)
4
4.5
5
5.5
6
IDDv
Figure 7-3. Supply Current vs Supply Voltage for
TLV840MADL13
Figure 7-4. Low Output Voltage (VOL) vs
Temperature for TLV840MADL13 (VDD = 0.7 V)
Figure 7-5. Voltage Threshold Accuracy vs
Temperature for TLV840MADL13
Figure 7-6. Voltage Hysteresis vs Temperature for
TLV840MADL13
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8 Detailed Description
8.1 Overview
The TLV840 is a family of nano-quiescent current voltage detectors with fixed threshold voltage. TLV840
features include programable reset time delay using external capacitor, active-low manual reset, 0.5% typical
monitor threshold accuracy with hysteresis and glitch immunity.
Fixed negative threshold voltages (VIT-) can be factory set from 0.8 V to 5.4 V. TLV840 is available in
SOT-23 5-pin industry standard package.
8.2 Functional Block Diagram
VDD
Push-pull (TLV840xxxPx)
version only
RMR
VDD
MR
TLV840M
only
RESET
LOGIC
TIMER
RESET
+
VDD
œ
Reference
GND
TLV840C,
TLV840M
only
RCT
CT
GND
8.3 Feature Description
8.3.1 Input Voltage (VDD)
VDD pin is monitored by the internal comparator to indicate when VDD falls below the fixed threshold voltage.
VDD also functions as the supply for the internal bandgap, internal regulator, state machine, buffers and other
control logic blocks. Good design practice involve placing a 0.1 μF to 1 μF bypass capacitor at VDD input for
noisy applications to ensure enough charge is available for the device to power up correctly.
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8.3.1.1 VDD Hysteresis
The internal comparator has built-in hysteresis to avoid erroneous output reset release. If the voltage at the VDD
pin falls below VIT- the output reset is asserted. When the voltage at the VDD pin goes above VIT- plus hysteresis
(VHYS) the output reset is deasserted after tD delay.
Hystersis Width
Hystersis Width
RESET
RESET
VIT-
VIT-
VIT+
VIT+
VDD
VDD
Figure 8-1. Hysteresis Diagram
8.3.1.2 VDD Transient Immunity
The TLV840 is immune to quick voltage transients or excursion on VDD. Sensitivity to transients depends on
both pulse duration (tGI_VIT-) found in Section 7.6 and overdrive. Overdrive is defined by how much VDD deviates
from the specified threshold. Threshold overdrive is calculated as a percent of the threshold in question, as
shown in Equation 1.
Overdrive = | (VDD / VIT- – 1) × 100% |
(1)
VDD
VIT+
VIT-
Overdrive
Pulse
Duration
Figure 8-2. Overdrive vs Pulse Duration
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8.3.2 User-Programmable Reset Time Delay
The reset time delay can be set to a minimum value of 80 µs by leaving the CT pin floating, or a maximum value
of approximately 6.2 seconds by connecting 10 µF delay capacitor. The reset time delay (tD) can be
programmed by connecting a capacitor no larger than 10 µF between CT pin and GND.
The relationship between external capacitor (CCT) in µF at CT pin and the time delay (tD) in seconds is given by
Equation 2.
tD = -ln (0.29) x RCT x CCT + tD (CT pin = Open)
(2)
Equation 2 is simplified to Equation 3 by plugging RCT and tD (CT pin = Open) given in Section 7.5 section:
tD = 618937 x CCT + 80µs
(3)
Equation 4 solves for external capacitor value (CCT) in units of µF where tD is in units of seconds
CCT = (tD- 80µs) ÷ 618937
(4)
The recommended maximum delay capacitor for the TLV840 is limited to 10 µF as this ensures there is enough
time for the capacitor to fully discharge when the reset condition occurs. When a voltage fault occurs, the
previously charged up capacitor discharges, and if the monitored voltage returns from the fault condition before
the delay capacitor discharges completely, the reset delay will be shorter than expected because the delay
capacitor will begin charging from a voltage above zero. Larger delay capacitors can be used so long as the
capacitor has enough time to fully discharge during the duration of the voltage fault. The amount of time required
to discharge the delay capacitor relative to the reset delay increases as VDD overdrive increases as shown in
Figure 8-3.
55
25°C
50
45
40
35
30
25
20
15
10
5
0.6
0.8
1
1.2
1.4
VDD Fault Underoltage (V)
1.6
1.8
2
CTR_
Figure 8-3. CCT Discharge Time During Fault Condition (VIT- = 2.1 V, CCT = 1 µF)
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8.3.3 Manual Reset (MR) Input for TLV840M Only
The manual reset (MR) input allows a processor GPIO or other logic circuits to initiate a reset. A logic low on MR
with pulse duration longer than t MR_PW will cause the reset output to assert. After MRreturns to a logic high
(V MR_H) and VDD is above VIT+, reset is deasserted after the user programmed reset time delay (tD) expires.
The minimum duration for which MRis held under V MR_L must be at least 1% of t MR_tD. Otherwise, the effective
reset delay will be shorter roughly by the difference between 1% of t MR_tD and the actual MR pulse width. For
large capacitor based delays this difference could be noticeable unless care is taken to lengthen the MR pulse
width.
MR is internally connected to VDD through a pull-up resistor R
shown in Section 8.2. If the logic signal
MR
controlling MRis less than VDD, then additional current flows from VDD into MRinternally. For minimum current
consumption, drive MRto either VDD or GND. V MR should not be higher than VDD voltage.
VIT+
VHYS
VIT-
VIT+
VHYS
VIT-
VDD
tP_HL
tD
tMR_tD
RESET
(2)
tMR_RES
VMR_H
VMR_L
MR
(1)
tMR_PW
Time
(1) MR pulse width too small to assert RESET
(2) MR voltage not low enough to assert RESET
Figure 8-4. Timing Diagram MR and RESET (TLV840M)
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8.3.4 Output Logic
8.3.4.1 RESET Output, Active-Low
RESET(Active-Low) applies to TLV840DL (Open-Drain) and TLV840PL (Push-Pull) hence the "L" in the device
name. RESETremains high (deasserted) as long as VDD is above the negative threshold (VIT-) and the MRpin is
floating or above V MR_H. If VDD falls below the negative threshold (VIT-) or if MR is driven low, then RESET is
asserted.
When MRis again logic high or floating and VDD rise above VIT+, the delay circuit will hold RESETlow for the
specified reset time delay (tD). When the reset time delay has elapsed, the RESETpin goes back to logic high
voltage (VOH).
The TLV840DL (Open-Drain) version, denoted with "D" in the device name, requires a pull-up resistor to hold
RESETpin high. Connect the pull-up resistor to the desired pull-up voltage source and RESETcan be pulled up
to any voltage up to 6.5 V independent of the VDD voltage. To ensure proper voltage levels, give some
consideration when choosing the pull-up resistor values. The pull-up resistor value determines the actual VOL
,
the output capacitive loading, and the output leakage current (Ilkg(OD)).
The Push-Pull variants (TLV840PL and TLV840PH), denoted with "P" in the device name, does not require an
external pull-up resistor.
8.4 Device Functional Modes
Table 8-1 summarizes the various functional modes of the device. Logic high is represented by "H" and logic low
is represented by "L".
Table 8-1. Truth Table
VDD
VDD < VPOR
VPOR < VDD < VIT-
VDD ≥ VIT-
MR
Ignored
Ignored
L
RESET
RESET
Undefined
Undefined
H
H
L
L
L
VDD ≥ VIT-
H
H
H
VDD ≥ VIT-
Floating
L
8.4.1 Normal Operation (VDD > VPOR)
When VDD is greater than VPOR, the reset signal is determined by the voltage on the VDD pin with respect to
the trip point (VIT-)
•
•
MR high: the reset signal corresponds to VDD with respect to the threshold voltage.
MR low: in this mode, the reset is asserted regardless of the threshold voltage.
8.4.2 Below Power-On-Reset (VDD < VPOR
)
When the voltage on VDD is lower than VPOR, the device does not have enough bias voltage to internally pull the
asserted output low or high and reset voltage level is undefined.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The following sections describe in detail how to properly use this device, depending on the requirements of the
final application.
9.2 Typical Application
9.2.1 Design 1: Dual Rail Monitoring with Power-up Sequencing
A typical application for the TLV840 is voltage rail monitoring and power-up sequencing as shown in Figure 9-1.
The TLV840 can be used to monitor any rail above 0.9 V. In this design application, two TLV840 devices monitor
two separate voltage rails and sequences the rails upon power-up. The TLV840CAPL29 is used to monitor the
3.3-V main power rail and the TLV840CADL09 is used to monitor the 1.2-V rail provided by the LDO for other
system peripherals. The RESEToutput of the TLV840CAPL29 is connected to the ENABLE input of the LDO. A
reset event is initiated on either voltage supervisor when the VDD voltage is less than VIT-.
LDO
VDD
EN
1.2 V
3.3 V
1 µF
1 µF
VCORE
VI/O
40kΩ
Microcontroller
VDD
VDD
RESET
RESET
RESET
TLV840CAPL29
TLV840CADL09
NC CT
GND
CT
GND
0.047µF
Figure 9-1. TLV840 Voltage Rail Monitor and Power-Up Sequencer Design Block Diagram
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9.2.1.1 Design Requirements
This design requires voltage supervision on two separate rails: 3.3-V and 1.2-V rails. The voltage rail needs to
sequence upon power up with the 3.3-V rail coming up first followed by the 1.2-V rail at least 25 ms after.
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
Two TLV840 devices provide voltage monitoring
with 1% accuracy with device options available in
0.1 V variations
Two Rail Voltage Supervision
Monitor 3.3-V and 1.2-V rails
Power up the 3.3-V rail first followed by 1.2-V rail
25 ms after
The CT capacitor on TLV840CAPL29 is set to
0.047 µF for a reset time delay of 29 ms typical
Voltage Rail Sequencing
Maximum device current
consumption
1 µA
Each TLV840 requires 350 nA typical
9.2.1.2 Detailed Design Procedure
The primary constraint for this application is choosing the correct device to monitor the supply voltage of the
microprocessor. The TLV840 can monitor any voltage between 0.8 V and 5.4 V. Depending on how far away
from the nominal voltage rail the user wants the voltage supervisor to trigger determines the correct voltage
supervisor variant to choose. In this example, the first TLV840 triggers when the 3.3-V rail falls to 2.9 V. The
second TLV840 triggers a reset when the 1.2-V rail falls to 0.9 V. The secondary constraint for this application is
the reset time delay that must be at least 25 ms to allow the microprocessor, and all other devices using the
3.3-V rail, enough time to startup correctly before the 1.2-V rail is enabled via the LDO. Because a minimum time
is required, the user must account for capacitor tolerance. For applications with ambient temperatures ranging
from –40°C to +125°C, CCT can be calculated using RCT and solving for CCT in Equation 2. Solving Equation 2
for 25 ms gives a minimum capacitor value of 0.04 µF which is rounded up to a standard value 0.047 µF to
account for capacitor tolerance.
A 1 µF decoupling capacitor is connected to the VDD pin as a good analog design practice. The pull-up resistor
is only required for the Open-Drain device variants and is calculated to ensure that VOL does not exceed max
limit given the Isink possible at the expected supply voltage. In this design example nominal VDD is 1.2 V but
dropping to 0.9 V. The Recommended Operating Conditions table provides 15 µA I sink for 0.7 V VDD, which is
the closest voltage to this design example. Using 15 µA of Isink and 300 mV max VOL, gives us 40 kΩ for the
pull-up resistor. Any value higher than 40 kΩ would ensure that VOL will not exceed 300 mV max specification.
9.2.1.3 Application Curves
VDD
30ms delay from VDD (3.3 V) to LDO Enable set by 0.047 µF on CT of TLV840CAPL29
RESET
(LDO Enable)
VOUT (LDO)
Negligible delay from LDO Enable to 1.2 V V
OUT
Figure 9-2. Startup Sequence Highlighting the Delay Between 3.3V and 1.2V Rails
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9.2.2 Application Curve: TLV840EVM
These application curves are taken with the TLV840EVM. Please see the TLV840EVM User Guide for more
information.
VDD
VDD
Reset Delay (tD)= 57.6 µs
Reset Delay (tD)= 5.42 ms
RESET
RESET
Figure 9-4. TLV840EVM RESETTime Delay (tD) with
0.01-µF Capacitor
Figure 9-3. TLV840EVM RESETTime Delay (tD) with
No Capacitor
VDD
Reset Delay (tD)= 56.8 ms
RESET
Figure 9-5. TLV840EVM RESETTime Delay (tD) with 0.1-µF Capacitor
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10 Power Supply Recommendations
These devices are designed to operate from an input supply with a voltage range between 0.7 V and 6 V. TI
recommends an input supply capacitor between the VDD pin and GND pin. This device has a 6.5 V absolute
maximum rating on the VDD pin. If the voltage supply providing power to VDD is susceptible to any large voltage
transient that can exceed 6.5 V, additional precautions must be taken.
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11 Layout
11.1 Layout Guidelines
Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends
placing a minimum 0.1 µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected
to the CT pin, then minimize parasitic capacitance on this pin so the rest time delay is not adversely affected.
•
•
•
Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a
>0.1 µF ceramic capacitor as near as possible to the VDD pin.
If a CCT capacitor is used, place these components as close as possible to the CT pin. If the CT pin is left
unconnected, make sure to minimize the amount of parasitic capacitance on the pin to <5 pF.
Place the pull-up resistors on RESET pin as close to the pin as possible.
11.2 Layout Example
The layout example in shows how the TLV840 is laid out on a printed circuit board (PCB) with a user-defined
delay.
Pull-up resistor required for Open-Drain
(TLV840XXDX) only
CT
RESET
CCT
Rpull-up
VDD
GND
CIN
NC
VDD
GND
Figure 11-1. TLV840C Recommended Layout
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12 Device and Documentation Support
12.1 Device Nomenclature
Table 12-1 shows how to decode the function of the device based on its part number
Table 12-1. Device Naming Convention
DESCRIPTION
Generic Part number
NOMENCLATURE
VALUE
TLV840
N
TLV840
Feature Option
No capacitor adjustable delay or manual
reset options
C 1
CT pin for programmable delay using
external capacitor
M 1
A
Manual Reset option in addition to CT pin
40 µs (No internal reset time delay)
2 ms reset time delay
Delay Option
B
C
10 ms reset time delay
30 ms reset time delay
50 ms reset time delay
80 ms reset time delay
100 ms reset time delay
150 ms reset time delay
200 ms reset time delay
Open-Drain, Active-Low
Push-Pull, Active-Low
D
E
F
G
H
I
Variant code (Output Topology)
DL
PL
DH
PH
Open-Drain, Active-High
Push-Pull, Active-High
Example: 12 stands for 1.2 V threshold
SOT23-5
Detect Voltage Option
Package
## (two characters)
DBV
R
Reel
Large Reel
1. Orderable part numbers starting with TLV840C and TLV840M are only available with the delay option A.
However, longer delays can be achieved through an external capacitor on the CT pin. Leaving the CT pin
floating will result in typical 40us delay for these 2 feature options
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12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
12.4 Trademarks
All other trademarks are the property of their respective owners.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV840CADL11DBVR
TLV840CADL14DBVR
TLV840CADL28DBVR
TLV840CADL29DBVR
TLV840MADL10DBVR
TLV840MADL13DBVR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2CLF
2G1F
2CKF
2CNF
2G2F
2CMF
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
TLV840MADL29DBVR
TLV840MADL30DBVR
TLV840NADL20DBVR
PREVIEW
PREVIEW
PREVIEW
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
5
5
5
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
2G3F
2G4F
2G6F
3000
RoHS (In
work) & Green
(In work)
TLV840NADL33DBVR
TLV840NADL35DBVR
TLV840NADL46DBVR
TLV840NAPL50DBVR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
5
5
5
5
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2CIF
2CJF
2G7F
2GOF
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jan-2021
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV840 :
Automotive: TLV840-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV840CADL11DBVR
TLV840CADL11DBVR
TLV840CADL14DBVR
TLV840CADL28DBVR
TLV840CADL28DBVR
TLV840CADL29DBVR
TLV840CADL29DBVR
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
178.0
180.0
178.0
180.0
178.0
180.0
178.0
178.0
180.0
178.0
178.0
180.0
180.0
178.0
178.0
178.0
9.0
8.4
9.0
8.4
9.0
8.4
9.0
9.0
8.4
9.0
9.0
8.4
8.4
9.0
9.0
9.0
3.3
3.2
3.3
3.2
3.3
3.2
3.3
3.3
3.2
3.3
3.3
3.2
3.2
3.3
3.3
3.3
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
TLV840MADL10DBVR SOT-23
TLV840MADL13DBVR SOT-23
TLV840MADL13DBVR SOT-23
TLV840NADL33DBVR
TLV840NADL33DBVR
TLV840NADL35DBVR
TLV840NADL35DBVR
TLV840NADL46DBVR
TLV840NAPL50DBVR
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV840CADL11DBVR
TLV840CADL11DBVR
TLV840CADL14DBVR
TLV840CADL28DBVR
TLV840CADL28DBVR
TLV840CADL29DBVR
TLV840CADL29DBVR
TLV840MADL10DBVR
TLV840MADL13DBVR
TLV840MADL13DBVR
TLV840NADL33DBVR
TLV840NADL33DBVR
TLV840NADL35DBVR
TLV840NADL35DBVR
TLV840NADL46DBVR
TLV840NAPL50DBVR
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
180.0
210.0
180.0
210.0
180.0
210.0
180.0
180.0
210.0
180.0
180.0
210.0
210.0
180.0
180.0
180.0
180.0
185.0
180.0
185.0
180.0
185.0
180.0
180.0
185.0
180.0
180.0
185.0
185.0
180.0
180.0
180.0
18.0
35.0
18.0
35.0
18.0
35.0
18.0
18.0
35.0
18.0
18.0
35.0
35.0
18.0
18.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
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EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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