TLV8542 [TI]
双路、3.6V、8kHz、超低静态电流 (500nA)、RRIO 运算放大器;
| 型号： | TLV8542 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路、3.6V、8kHz、超低静态电流 (500nA)、RRIO 运算放大器 放大器 运算放大器 |
| 文件： | 总38页 (文件大小：1921K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Reference
Design
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
TLV8544, TLV8542, TLV8541
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
适用于成本优化型系统的 TLV854x 500nA RRIO 纳瓦级功率运算放大器
1 特性
3 说明
1
•
对于成本优化型系统
TLV854x 超低功耗运算放大器适用于无线和低功耗有
线设备中的 成本优化型 传感应用。TLV854x 系列运算
放大器可最大限度地减少极其注重电池使用寿命的运动
检测安全系统（如微波和 PIR 运动传感系统）等设备
的功耗。此类器件的互补金属氧化物半导体 (CMOS)
输入级经过精心设计，能够实现超低飞安级失调电流，
从而降低 IBIAS 和 IOS 误差，否则会影响敏感 应用。这
些方面的示例包括带有兆欧级反馈电阻器的跨阻放大器
(TIA) 配置以及高源阻抗传感 应用。此外，内置的 EMI
保护可降低器件对手机、WiFi、无线电发射器和标签阅
读器等发出的无用射频信号的敏感度。
•
•
•
•
•
•
•
•
•
•
纳瓦级功率电源电流：500nA/通道
失调电压：3.1mV（最大值）
TcVos：0.8µV/°C
增益带宽：8kHz
单位增益稳定
低输入失调电流：100fA
宽电源电压范围：1.7V 至 3.6V
轨至轨输入和输出 (RRIO)
温度范围：–40°C 至 +125°C
行业标准封装
–
–
–
四通道 14 引脚 TSSOP 和 SOIC 封装
双通道 8 引脚 SOIC 封装
器件信息(1)
器件型号
TLV8544
封装
TSSOP封装(14)
SOIC (14)（预览）
SOIC (8)
封装尺寸
单通道 5 引脚 SOT-23 封装
5.00mm x 4.40mm
8.65mm × 3.91mm
4.9mm × 3.90mm
1.50mm × 1.50mm
2.90mm x 1.60mm
•
无引线封装
双通道 8 引脚 X2QFN 封装
–
TLV8542
TLV8541
X2QFN (8)（预览）
SOT-23 (5)
2 应用
•
•
•
•
•
•
•
•
•
使用 PIR 传感器的运动检测器 SNAA301
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
使用微波传感器的运动检测器
气体检测器
纳瓦级功率放大器系列
VOS（最大
值）
离子化烟雾报警器
每通道的
IQ
系列
通道数
VSUPPLY
温度调节装置
TLV854x
TLV880x
LPV81x
1、2、4
1、2
500nA
320nA
425nA
3.1mV
4.5mV
0.3mV
1.7 至 3.6V
1.7 至 5.5V
1.6 至 5.5V
远程传感器、IoT（物联网）
有效的射频识别 (RFID) 阅读器和标签
便携式医疗设备
1、2
血糖监测
低功耗 PIR 运动检测器
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
English Data Sheet: SNOSD29
TLV8544, TLV8542, TLV8541
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
目录
9.1 Application Information............................................ 14
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information ................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 12
Application and Implementation ........................ 14
9.2 Typical Application: Battery-Powered Wireless PIR
Motion Detectors...................................................... 15
9.3 Typical Application: 60-Hz Twin T Notch Filter....... 19
9.4 Dos and Don'ts ....................................................... 20
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
12 器件和文档支持 ..................................................... 22
12.1 器件支持 ............................................................... 22
12.2 文档支持 ............................................................... 22
12.3 相关链接................................................................ 22
12.4 接收文档更新通知 ................................................. 22
12.5 社区资源................................................................ 22
12.6 商标....................................................................... 23
12.7 静电放电警告......................................................... 23
12.8 Glossary................................................................ 23
13 机械、封装和可订购信息....................................... 23
8
9
4 修订历史记录
Changes from Revision C (October 2017) to Revision D
Page
•
•
TLV8541 的生产数据发布....................................................................................................................................................... 1
为 TLV8542 添加了 8 引脚 X2QFN 封装................................................................................................................................ 1
Changes from Revision B (June 2017) to Revision C
Page
•
已更改 将 TLV8542 双通道数据表更改为生产数据................................................................................................................. 1
Changes from Revision A (March 2017) to Revision B
Page
•
已添加 向 TLV8544 数据表中添加预告信息 TLV8542............................................................................................................ 1
Changes from Original (December 2016) to Revision A
Page
•
已更改 将“产品预览”更改为“生产数据”发布。 ......................................................................................................................... 1
5 说明 （续）
TLV854x 运算放大器采用低至 1.7V 的单电源电压供电，并且可在 –40°C 至 +125°C 的扩展温度范围内、在低电量
情况下连续运行。所有版本的额定工作温度范围均为 –40°C 至 125°C。TLV8541（单通道版本）采用 5 引脚 SOT-
23 封装，而 TLV8542（双通道版本）采用 8 引脚 SOIC 封装。四通道 TLV8544（四通道版本）采用行业标准 14
引脚 TSSOP 封装。
2
Copyright © 2016–2017, Texas Instruments Incorporated
TLV8544, TLV8542, TLV8541
www.ti.com.cn
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
6 Pin Configuration and Functions
TLV8541 DBV Package
5-Pin SOT-23
Top View
Pin Functions: TLV8541 DBV
PIN
I/O
DESCRIPTION
NUMBER
NAME
OUT
V–
1
2
3
4
5
O
P
I
Output
Negative (lowest) power supply
Non-Inverting Input
+IN
–IN
I
Inverting Input
V+
P
Positive (highest) power supply
TLV8542 D Package
8-Pin SOIC
TLV8542 RUG Package
8-Pin X2QFN
Top View
Top View
V+
OUT A
-IN A
1
2
3
7
6
5
OUT B
-IN B
+IN A
+IN B
V-
Pin Functions: TLV8542 D (X2QFN RUG Package Preview)
PIN
I/O
DESCRIPTION
NUMBER
NAME
OUT A
–IN A
+IN A
V–
1
2
3
4
5
6
7
8
O
I
Channel A Output
Channel A Inverting Input
Channel A Non-Inverting Input
Negative (lowest) power supply
Channel B Non-Inverting Input
Channel B Inverting Input
Channel B Output
I
P
I
+IN B
–IN B
OUT B
V+
I
O
P
Positive (highest) power supply
Copyright © 2016–2017, Texas Instruments Incorporated
3
TLV8544, TLV8542, TLV8541
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
TLV8544 PW and D Package
14-Pin TSSOP and SOIC
Top View
Pin Functions: TLV8544 PW (D SOIC Package Preview)
PIN
I/O
DESCRIPTION
NUMBER
NAME
OUTA
–INA
+INA
V+
1
O
I
Channel A output
2
Channel A inverting input
Channel A non-inverting input
Positive (highest) power supply
Channel B non-inverting input
Channel B inverting input
Channel B output
3
I
4
P
I
5
+INB
–INB
OUTB
OUTC
–INC
+INC
V–
6
I
7
O
O
I
8
Channel C output
9
Channel C inverting input
Channel C non-inverting input
Negative (lowest) power supply
Channel D non-inverting input
Channel D inverting input
Channel D output
10
11
12
13
14
I
P
I
+IND
–IND
OUTD
I
O
4
Copyright © 2016–2017, Texas Instruments Incorporated
TLV8544, TLV8542, TLV8541
www.ti.com.cn
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
(1) (2) (3)
MIN
–0.3
MAX
4
UNIT
V
Supply voltage, Vs = (V+) – (V–)
Common mode
Differential
(V–) – 0.3
(V–) – 0.3
–10
(V+) + 0.3
(V+) + 0.3
10
V
Input pins
Input pins
Voltage
Current
V
mA
Output short current(4)
Continuous
–40
Continuous
125
Operating ambient temperature
Storage temperature, Tstg
Junction temperature
°C
°C
°C
–65
150
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails must
be current-limited to 10 mA or less.
(3) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(4) Short-circuit to ground.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±750 V may actually have higher performance.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.7
NOM
MAX
3.6
UNIT
V
Supply voltage (V+ – V–)
Specified ambient temperature
–40
125
°C
7.4 Thermal Information
TLV8544
PW (TSSOP)
14 PINS
124.5
TLV8542
D (SOIC)
8 PINS
141.6
85.7
TLV8541
THERMAL METRIC(1)
DBV (SOT-23)
5 PINS
244.6
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
52.7
127.3
66.2
84.7
79.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
7.3
36.3
44.1
ψJB
65.7
84.0
78.8
RθJC(bot)
N/A
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2016–2017, Texas Instruments Incorporated
5
TLV8544, TLV8542, TLV8541
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
7.5 Electrical Characteristics
TA = 25°C, VS = 1.8 V to 3.3 V, VCM = VOUT = VS / 2, and RL≥ 10 MΩ to VS / 2, unless otherwise noted.
PARAMETER
OFFSET VOLTAGE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCM = V– , VS = 1.8 V and 3.3 V
VCM = V+, VS = 1.8 V and 3.3 V
VCM = V–, TA = –40°C to 125°C
VCM = V– , VS =1.8 V and 3.3 V
–3.1 See Plots
–3.4 See Plots
0.8
3.1
3.4
VOS
Input offset voltage
mV
dVOS/dT
PSRR
Input offset drift
µV/°C
dB
Power-supply rejection ratio
66
90
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
VS = 3.3 V
0
3.3
V
(V–) ≤ VCM ≤ (V+), Vs = 3.3 V
(V–) ≤ VCM ≤ (V+) – 1.2 V
60
80
90
CMRR
Common-mode rejection ratio
dB
INPUT BIAS CURRENT
IB
Input bias current
Input offset current
100
100
fA
fA
IOS
INPUT IMPEDANCE
Differential
2
4
pF
pF
Common mode
NOISE
En
Input voltage noise
ƒ = 0.1 Hz to 10 Hz
ƒ = 1 kHz
8.6
µVp–p
en
Input voltage noise density
264
nV/√Hz
OPEN-LOOP GAIN
(V–) + 0.3 V ≤ VO ≤ (V+) – 0.3 V, RL
100 kΩ to V+/2
=
AOL
Open-loop voltage gain
120
dB
OUTPUT
VOH
Voltage output swing from
positive rail
RL = 100 kΩ to V+/2, VS = 3.3 V
RL = 100 kΩ to V+/2, VS = 3.3 V
12
12
mV
mV
Voltage output swing from
negative rail
VOL
Sourcing, VO to V–, VIN(diff) = 100 mV,
VS = 3.3 V
15
ISC
Short-circuit current
mA
Sinking, VO to V+, VIN(diff) = –100 mV,
VS = 3.3 V
30
8
ZO
Open loop output impedance
ƒ = 1 kHz, IO = 0 mA
kΩ
FREQUENCY RESPONSE
GBP
Gain-bandwidth product
CL = 20 pF, RL = 10 MΩ
8
3.5
4.5
kHz
G = 1, rising edge, CL = 20 pF
G = 1, falling edge, CL = 20 pF
SR
Slew rate (10% to 90%)
V/ms
POWER SUPPLY
IQ–TLV8541 Quiescent Current
VCM = V–, IO = 0 mA, VS = 3.3 V
VCM = V–, IO = 0 mA, VS = 3.3 V
VCM = V–, IO = 0 mA, VS = 3.3 V
550
550
500
640
640
640
nA
nA
nA
IQ–TLV8542 Quiescent Current, per channel
IQ–TLV8544 Quiescent current, per channel
6
Copyright © 2016–2017, Texas Instruments Incorporated
TLV8544, TLV8542, TLV8541
www.ti.com.cn
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
7.6 Typical Characteristics
TA = 25°C, RL = 10 MΩ to VS/2 ,CL = 20 pF, VCM = VS / 2 V unless otherwise specified.
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
VOS_
VOS_
Offset Voltage (µV)
Offset Voltage (µV)
VS = 1.8 V
VCM = V+ Data from 1500 4-channel devices
VS = 1.8 V
VCM = V– Data from 1500 4-channel devices
Figure 1. Offset Voltage Production Distribution
Figure 2. Offset Voltage Production Distribution
10
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
VOS_
VOS_
Offset Voltage (µV)
Offset Voltage (µV)
VS = 3.3 V
VCM = V+ Data from 1500 4-channel devices
VS = 3.3 V
VCM = V– Data from 1500 4-channel devices
Figure 3. Offset Voltage Production Distribution
Figure 4. Offset Voltage Production Distribution
800
720
640
560
480
400
320
240
160
80
800
720
640
560
480
400
320
240
160
80
IQ (nA) at 125 °C
IQ (nA) at 25 °C
IQ (nA) at -40 °C
IQ (nA) at 125 °C
IQ (nA) at 25 °C
IQ (nA) at -40 °C
0
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Common Mode Voltage (V)
3
3.3
Common Mode Voltage (V)
SNOS
SNOS
VS = 1.8 V
TA = –40, 25, 125°C
Per Channel
VS = 3.3 V
TA = –40, 25, 125°C
Per Channel
Figure 5. Supply Current vs Common Mode Voltage
Figure 6. Supply Current vs Common Mode Voltage
Copyright © 2016–2017, Texas Instruments Incorporated
7
TLV8544, TLV8542, TLV8541
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
Typical Characteristics (continued)
TA = 25°C, RL = 10 MΩ to VS/2 ,CL = 20 pF, VCM = VS / 2 V unless otherwise specified.
50
50
Vos (mV) at 125 èC
Vos (mV) at 25 èC
Vos (mV) at -40 èC
0
0
-50
-50
-100
-150
-200
-250
-300
-350
-100
-150
-200
-250
-300
-350
Vos (mV) at 125 èC
Vos (mV) at 25 èC
Vos (mV) at -40 èC
-0.5 -0.25
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
Common Mode Voltage (V)
Common Mode Voltage (V)
Vos-
Vos-
VS = 1.8 V
TA = –40, 25, 125°C
VS = 3.3 V
TA = –40, 25, 125°C
Figure 7. Typical Offset Voltage vs Common Mode Voltage
Figure 8. Typical Offset Voltage vs Common Mode Voltage
625
600
575
550
525
500
475
450
425
400
375
120
100
80
60
IQ (nA) at 125 °C
IQ (nA) at 25 °C
IQ (nA) at -40 °C
350
325
300
1.6 1.8
40
10
2
2.2 2.4 2.6 2.8
Supply Voltage (V)
3
3.2 3.4 3.6
100
1k
10k
Frequency (Hz)
SNOS
SNOS
VS = 1.6 to 3.6V
TA = –40, 25, 125°C
VCM = V-
VS= 3.3V
TA = 25°C
Figure 9. Supply Current vs Supply Voltage, Low VCM
Figure 10. CMRR vs Frequency
135
1
120
105
90
100m
10m
1m
Vout (V) at 125 °C
Vout (V) at 25 °C
Vout (V) at -40 °C
75
100m
60
10
10m
100m
1
10
100
1k
10k
100k
Output Sinking Current (mA)
SNOS
Frequency (Hz)
PSRR
VS = 1.8 V
TA = –40, 25, 125°C
VS= 3.3V
TA = 25°C
VCM = V–
Figure 12. Output Swing vs Sinking Current
Figure 11. PSRR vs Frequency
8
Copyright © 2016–2017, Texas Instruments Incorporated
TLV8544, TLV8542, TLV8541
www.ti.com.cn
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
Typical Characteristics (continued)
TA = 25°C, RL = 10 MΩ to VS/2 ,CL = 20 pF, VCM = VS / 2 V unless otherwise specified.
1
100m
10m
1m
1
100m
10m
1m
Vout (V) at 125 °C
Vout (V) at 25 °C
Vout (V) at -40 °C
Vout (V) at 125 °C
Vout (V) at 25 °C
Vout (V) at -40 °C
100m
100m
100m
1
10
1m
10m
100m
1
10
Output Sinking Current (mA)
Output Sourcing Current (mA)
SNOS
SNOS
VS = 3.3 V
TA = –40, 25, 125°C
VS = 1.8 V
TA = –40, 25, 125°C
Figure 13. Output Swing vs Sinking Current
Figure 14. Output Swing vs Sourcing Current
100
80
1
100m
10m
1m
60
40
20
0
-20
-40
-60
-80
-100
Vout (V) at 125 °C
Vout (V) at 25 °C
Vout (V) at -40 °C
10m
100m
1
10
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Output Sourcing Current (mA)
Common Mode Voltage (V)
SNOS
SNOS
VS = 3.3 V
TA = –40, 25, 125°C
VS = 1.8 V
TA = –40°C
Figure 15. Output Swing vs Sourcing Current
Figure 16. Input Bias Current vs Common Mode Voltage
200
160
120
80
100
80
60
40
40
20
0
0
-40
-80
-120
-160
-200
-20
-40
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
3.5
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Common Mode Voltage (V)
Common Mode Voltage
SNOS
SNOS
VS = 3.3 V
TA = –40°C
VS = 1.8 V
TA = 25°C
Figure 17. Input Bias Current vs Common Mode Voltage
Figure 18. Input Bias Current vs Common Mode Voltage
Copyright © 2016–2017, Texas Instruments Incorporated
9
TLV8544, TLV8542, TLV8541
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
Typical Characteristics (continued)
TA = 25°C, RL = 10 MΩ to VS/2 ,CL = 20 pF, VCM = VS / 2 V unless otherwise specified.
200
160
120
80
100
80
60
40
40
20
0
0
-40
-80
-120
-160
-200
-20
-40
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
3.5
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Common Mode Voltage (V)
Common Mode Voltage (V)
SNOS
SNOS
VS = 3.3 V
TA = 25°C
VS= 1.8V
TA = 125°C
Figure 19. Input Bias Current vs Common Mode Voltage
Figure 20. Input Bias Current vs Common Mode Voltage
120
150
125
100
75
200
160
120
80
100
80
60
40
20
0
Phase
40
0
50
-40
-80
-120
-160
-200
25
125 èC
25 èC
-40 èC
0
Gain
-20
-25
100k
10
100
1k
10k
0
0.5
1
1.5
2
2.5
3
3.5
Frequency (Hz)]
Common Mode Voltage (V)
AOL_
SNOS
VS = 3.3 V
TA = 125°C
VS = 3.3 V
TA = –40, 25, 125°C
CL = 50 pF
Figure 21. Input Bias Current vs Common Mode Voltage
20000
Figure 22. Open Loop Gain and Phase
1k
10000
1000
100
100
10
1
10
100m
10
100
1k
10k
100k
1
10
100
1k
10k
Frequency (Hz)
Frequency (Hz)
SNOS
SNOS
VS = 3.3 V
TA = 25°C
VS = 3.3 V
TA = 25°C
Figure 24. Open Loop Output Impedance
Figure 23. Input Voltage Noise vs Frequency
10
Copyright © 2016–2017, Texas Instruments Incorporated
TLV8544, TLV8542, TLV8541
www.ti.com.cn
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
Typical Characteristics (continued)
TA = 25°C, RL = 10 MΩ to VS/2 ,CL = 20 pF, VCM = VS / 2 V unless otherwise specified.
120
Input
Output
100
80
60
40
0dBm
-10dBm
-20dBm
20
0
10
2 ms/div
100
1000
Frequency (MHz)
SNOS
SNOS
VS = 1.8 V
TA = 25°C
AV = 1
CL = 50 pF
VS = 3.3 V
AV = 1
TA = 25°C
VIN = 0.9 ± 0.1 V
Figure 26. Small Signal Pulse Response, 1.8 V
Figure 25. EMIRR Performance
Input
Input
Output
Output
2 ms/div
2 ms/div
SNOS
SNOS
VS = 3.3 V
VIN = 1.65 ± 0.1 V
TA = 25 °C
AV = 1
CL = 50 pF
VS = 1.8 V
TA = 25°C
AV = 1
CL = 50 pF
VIN = 0.9 ± 0.5 V
Figure 27. Small Signal Pulse Response, 3.3 V
Figure 28. Large Signal Pulse Response, 1.8 V
Input
Output
2 ms/div
SNOS
VS = 3.3 V
TA = 25°C
AV = 1
CL = 50 pF
VIN = 1.65 ± 1 V
Figure 29. Large Signal Pulse Response, 3.3 V
Copyright © 2016–2017, Texas Instruments Incorporated
11
TLV8544, TLV8542, TLV8541
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
8 Detailed Description
8.1 Overview
The TLV854x amplifiers are unity-gain stable and can operate on a single supply, making them highly versatile
and easy to use.
Parameters that vary significantly with operating voltages or temperature are shown in the Typical Characteristics
curves.
8.2 Functional Block Diagram
V+
-IN
OUT
+IN
+
8.3 Feature Description
The differential inputs of the TLV854x device consist of a non-inverting input (+IN) and an inverting input (–IN).
The device amplifies only the difference in voltage between the two inputs, which is called the differential input
voltage. The output voltage of the op-amps VOUT are given by Equation 1:
VOUT = AOL [(+IN) – (–IN)]
where
•
AOL is the open-loop gain of the amplifier, typically around 100 dB.
(1)
8.4 Device Functional Modes
8.4.1 Rail-To-Rail Input
The input common-mode voltage range of the TLV854x extends to the supply rails. This is achieved with a
complementary input stage — an N-channel input differential pair in parallel with a P-channel differential pair.
The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 800 mV to 200 mV above
the positive supply, while the P-channel pair is on for inputs from 300 mV below the negative supply to
approximately (V+) – 800 mV. There is a small transition region, typically (V+) – 1.2 V to (V+) – 0.8 V, in which
both pairs are on. This 400-mV transition region can vary 200 mV with process variation. Within the 400-mV
transition region PSRR, CMRR, offset voltage, offset drift, and THD may be degraded compared to operation
outside this region.
8.4.2 Supply Current Changes Over Common Mode
Because of the ultra-low supply current, changes in common mode voltages cause a noticeable change in the
supply current as the input stages transition through the transition region, as shown in Figure 30.
12
Copyright © 2016–2017, Texas Instruments Incorporated
TLV8544, TLV8542, TLV8541
www.ti.com.cn
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
Device Functional Modes (continued)
800
720
640
560
480
400
320
240
160
80
IQ (nA) at 125 °C
IQ (nA) at 25 °C
IQ (nA) at -40 °C
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Common Mode Voltage (V)
SNOS
Figure 30. Supply Current Change Over Common Mode at 1.8 V
For the lowest supply current operation, keep the input common mode range between V– and 1 V below V+.
8.4.3 Design Optimization With Rail-To-Rail Input
In most applications, operation is within the range of only one differential pair. However, some applications can
subject the amplifier to a common-mode signal in the transition region. Under this condition, the inherent
mismatch between the two differential pairs may lead to degradation of the CMRR and THD. The unity-gain
buffer configuration is the most problematic as it traverses through the transition region if a sufficiently wide input
swing is required.
8.4.4 Design Optimization for Nanopower Operation
When designing for ultra-low power, choose system components carefully. To minimize current consumption,
select large-value resistors. Any resistors react with stray capacitance in the circuit and the input capacitance of
the operational amplifier (op amp). These parasitic RC combinations can affect the stability of the overall system.
A feedback capacitor may be required to assure stability and limit overshoot or gain peaking.
When possible, use AC coupling and AC feedback to reduce static current draw through the feedback elements.
Use film or ceramic capacitors because large electolytics may have static leakage currents in the tens to
hundreds of nanoamps.
8.4.5 Common-Mode Rejection
The CMRR for the TLV854x is specified in two ways so the best match for a given application may be used.
First, the CMRR of the device in the common-mode range below the transition region (VCM < (V+) – 1.2 V) is
given. This specification is the best indicator of the capability of the device when the application requires use of
one of the differential input pairs. Second, the CMRR at VS = 3.3 V over the entire common-mode range is
specified.
8.4.6 Output Stage
The TLV854x output voltage swings 20 mV from rails at a 3.3-V supply, which provides the maximum possible
dynamic range at the output. This is particularly important when operating on low supply voltages.
The TLV854x maximum output voltage swing defines the maximum swing possible under a particular output
load.
Copyright © 2016–2017, Texas Instruments Incorporated
13
TLV8544, TLV8542, TLV8541
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
Device Functional Modes (continued)
8.4.7 Driving Capacitive Load
The TLV854x is internally compensated for stable unity-gain operation, with a 8-kHz typical gain bandwidth.
However, the unity-gain follower is the most sensitive configuration-to-capacitive load. The combination of a
capacitive load placed directly on the output of an amplifier along with the output impedance of the amplifier
creates a phase lag, which reduces the phase margin of the amplifier. If the phase margin is significantly
reduced, the response is under-damped, which causes peaking in the transfer and, when there is too much
peaking, the op amp might start oscillating.
In order to drive heavy (> 50 pF) capacitive loads, use an isolation resistor, RISO, as shown in Figure 31. By
using this isolation resistor, the capacitive load is isolated from the output of the amplifier. The larger the value of
RISO, the more stable the amplifier will be. If the value of RISO is sufficiently large, the feedback loop is stable,
independent of the value of CL. However, larger values of RISO (e.g. 50 kΩ) result in reduced output swing and
reduced output current drive.
RISO
VOUT
VIN
+
CL
Figure 31. Resistive Isolation of Capacitive Load
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLV854x is a nanopower op amps that provides 8-kHz bandwidth with only 500-nA typical quiescent current
per channel and near precision drift specifications at a low cost. These rail-to-rail input and output amplifiers are
specifically designed for battery-powered applications. The input common-mode voltage range extends to the
power-supply rails and the output swings to within millivolts of the rails, maintaining a wide dynamic range.
14
Copyright © 2016–2017, Texas Instruments Incorporated
TLV8544, TLV8542, TLV8541
www.ti.com.cn
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
9.2 Typical Application: Battery-Powered Wireless PIR Motion Detectors
VBAT
CR2032
coin cell
VBAT
R7
C7
Quad Package
Supply Pin
R1
+
MCU I/O
MCU I/O
C1
C2
PIR
TLV8544
R8
VBAT
C
_
D
+
Vin
+
S
TLV8544
_
Rg
R2
B
Signal
VBAT
TLV8544
A
+
_
R4
C4
R3
C3
Fresnel
Lens
TLV8544
R9
D
R5
_
C8
R10
C5
D1
D2
VREF generator
network
R6
C6
Gain Stages,
bandpass filters
Window
Comparator
Figure 32. PIR Motion Detector Circuit
9.2.1 Design Requirements
Smart building automation systems employ a large number of various sensing nodes distributed throughout
small, medium, and large infrastructures. The sensing nodes measure motion, temperature, vibration, and other
parameters of interest. Wireless nodes are monitored in a central location. Because of the large number of
distributed nodes , battery-operation and cost-optimized electronic components are required. Typically, the
wireless nodes need to run on a single CR2032 coin battery for eight to ten years.
For more information see Design of Ultra-Low Power Discrete Signal Conditioning Circuit for Battery-Power,
Ultra-Low-Power Wireless PIR Motion Detector Reference Design and BOOSTXL-TLV8544PIR User's Guide.
The BOOSTXL-TLV8544PIR along with the companion CC2650 LaunchPad, LAUNCHXL-CC2650 can be
obtained from the TI website for hands-on experiments.
9.2.2 Detailed Design Procedure
Referring to Figure 32, the TLV8544 4-channel op amp is powered directly by a 3.3-V CR2032 coin battery. The
first two amplifier stages of the TLV8544 implement active filter functionality. The remaining two amplifiers of the
TLV8544 are used for building a window comparator. The comparator flags the detection of a motion event to an
ultra-low-power wireless microcontroller on the same board. Due to the higher gain in the filter stages and higher
output noise from the sensor, it is necessary to optimize the placement of the high-frequency filter pole and the
window comparator thresholds to avoid false detection.
The first two amplifiers (A and B) in the circuit are used in identical active bandpass filters with corner
frequencies of 0.7 and 10.6 Hz. Each filter stage has a gain of about 220 V/V to account for the reduced
sensitivity of the sensor due to the low current biasing of the PIR sensor. Considering the 8-kHz unity gain
bandwidth (UGBW) product of the TLV8544, the bandwidth of each stage is limited to approximately 36 Hz. The
above choice of cutoff frequencies give a relatively wide bandwidth to detect a person running in the field of view,
yet narrow enough to limit the peak-to-peak noise at the output of the filters.
Amplifier A is a noninverting gain/filter stage providing the high input impedance needed to prevent loading of the
sensor. The DC gain of the stage due to the presence of C6 is unity. Therefore, the sensor output provides the
bias voltage needed at the A stage to avoid clipping of the lower cycle of the input signal. Diodes D1 and D2 limit
the output signal, avoiding overdriving of the second stage and consequently placing a large charge on coupling
capacitor C4, which helps with the recovery time.
9.2.2.1 Calculation of the Cutoff Frequencies and Gain of Stage A:
The low cutoff frequency of the bandpass filter in stage A is:
Copyright © 2016–2017, Texas Instruments Incorporated
15
TLV8544, TLV8542, TLV8541
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
Typical Application: Battery-Powered Wireless PIR Motion Detectors (continued)
1
ƒClow
=
2pìR6 ì C6
(2)
Choosing R6 = 6.81 kΩ and C6 = 33 μF, the low cutoff frequency is fClow= 0.71 Hz. The high cutoff frequency of
the filter is:
1
ƒChigh
=
2pìR5 ì C5
(3)
(4)
For R5 = 1.5 MΩ and C5 = 0.01 µF, the high cutoff frequency is fChigh= 10.6 Hz. The gain of the stage is:
R5
G = 1+
R6
Choosing R5 = 1.5 MΩ and R6 = 6.81 kΩ, the gain of the stage A is G = 221.26 V/V (46.9 dB).
9.2.2.2 Calculation of the Cutoff Frequencies and Gain of Stage B
As shown in Figure 32, amplifier B is an inverting bandpass filter and gain stage. Capacitor C4 creates an AC
coupled path between the A and the B stages. Thus the signal level must be shifted at the input of the amplifier
B. This is done by connecting a midpoint voltage of the reference voltage dividers comprising R10, R9, R8 and
R7 to the non-inverting input of amplifier B, biasing the input signal to the mid-rail (1.65 V). A very large feedback
resistor R3 is chosen to minimize the dynamic current due to presence of peak-to-peak noise voltage at the
output of this stage.
The low cutoff frequency of the filter of the stage B is:
1
ƒClow
=
2pìR4 ì C4
(5)
Choosing R4 = 68.1 kΩ and C4 = 3.3 μF, the low cutoff frequency is fClow = 0.71 Hz. The high cutoff frequency of
the filter is:
1
ƒChigh
=
2pìR3 ì C3
(6)
(7)
For R3 = 15 MΩ and C3 = 1000 pF, the high cutoff frequency is fChigh= 10.6 Hz. The gain of the stage is:
R3
G = -
R4
For R3 = 15 MΩ and R4 = 68.1 kΩ, the gain is calculated |G| = 220.26 V/V (46.9 dB).
9.2.2.3 Calculation of the Total Gain of Stages A and B
The overall gain of the two stages A and B is: GTotal= GA × GB= 221.26 × 220.26 = 48810 V/V = 93.77 dB.
9.2.2.4 Window Comparator Stage
The signal from a moving object in front of the PIR sensor, after amplification and filtering, is connected to a
window comparator. The comparator converts the analog signal to digital pulses for interrupting an on-board
microcontroller unit (MCU), flagging detection of motion. A different approach is to digitize the analog signal
continuously by an analog-to-digital converter (ADC) and implement the comparator functionality in the digital
domain. This method has the advantage of enabling the post processing of the data to reduce the chance of
false detection. However, continuous conversion and processing of data by the MCU increases the power
consumption, lowering the lifetime of the battery substantially.
Rather than using a separate low-power comparator integrated circuits to implement the window comparator
section of the circuit, the remaining op amps in the TLV8544 package are used to implement the comparator
stage. Benefits of this approach include fewer components and thus reduced system cost.
Although an op amp can sometimes be used as a comparator, an amplifier cannot be used as a comparator
interchangeably in all applications because of relatively long recovery time of the amplifier from output saturation
and relatively long propagation delay due to internal compensation. Particularly, the nanopower op amps have
very slow slew rate, limiting their usage as a comparator in only applications with very low frequency input signal.
Fortunately, PIR sensor signals are relatively slow and this should not be an issue.
16
Copyright © 2016–2017, Texas Instruments Incorporated
TLV8544, TLV8542, TLV8541
www.ti.com.cn
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
Typical Application: Battery-Powered Wireless PIR Motion Detectors (continued)
The new TLV8544 device is particularly suitable for implementing a window comparator in a battery operated PIR
motion detector application because of its rail-to-rail operation capability, relatively low offset voltage, low offset
voltage drift, very low bias current, and nanopower consumption, all at an optimal cost. The input signal of the
comparator stage in the presence of moving heat source across the sensor is shown in Figure 33. The signal is
centered at mid-rail and can swing up or down from the center.
The window comparator is a combination of a non-inverting comparator implemented with amplifier D and an
inverting comparator implemented with amplifier C, as shown in Figure 32.
VBAT
VREF_High
PIR signal
Vbias
VREF_Low
GND
Comp —D“ Output
Comp —C“ Output
Order of the pulses depends on the
direction of the motion
Figure 33. Ideal Amplified PIR Signal and the Output of the Window Comparator Circuit
9.2.2.5 Reference Voltages
Referring to Figure 32, the divider networks comprising R7, R8, R9, and R10, generate the reference voltages
VREF_High and VREF_Low of the window comparator. The center point of the divider provides the bias voltage
of the gain in the stage B through the connection to the noninverting input of the amplifier.
Due to the very low bias current of the TLV8544 device, it is possible to use very large values of resistors in the
divider networks to minimize the current to ground through the resistors to a negligible amount. For R7 = R8 =
R9 = R10 = 15 MΩ:
R7 +R8 +R9
R7 +R8 +R9 +R10
4.5ì106
6ì106
≈
’
VREF_High =
VCC
=
ì VCC = 0.75ì VCC
∆
«
÷
◊
(8)
R7
1.5ì106
6ì106
≈
’
VREF_Low =
VCC
=
ì VCC = 0.25ì VCC
∆
÷
R8 +R9 +R10 +R7
«
◊
(9)
Low leakage ceramic capacitors C7, and C8, maintain constant threshold voltages, preventing potential chatter at
the output of the comparators. It should be noted that using cheap electrolytic capacitors must be avoided as
they have high (many µA) leakage current. The comparator outputs stay low in the absence of motion across the
sensor. In the presence of motion, comparators C and D generate high output pulses as shown in Figure 33. The
order of the pulses depends on the direction of the motion in front of the sensor.
Copyright © 2016–2017, Texas Instruments Incorporated
17
TLV8544, TLV8542, TLV8541
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
Typical Application: Battery-Powered Wireless PIR Motion Detectors (continued)
9.2.3 Application Curve
Scope plots of the amplified PIR signal at the input of the noninverting comparator and the corresponding output
signal are shown in Figure 34 and Figure 35. As the PIR signal (blue line) crosses the VREF_High threshold, the
output of the comparator switches from the cutoff (slightly higher than ground) state to the saturation state
(slightly lower than VBAT = 3.3 V). Depending on the speed of the object, the PIR signal peaks to its maximum
and roles off within several seconds. When the signal crosses the VREF_High threshold on the way down, the
output of the noninverting amplifier toggles back to the cutoff region (low).
The data for plot of Figure 34 was captured using the BOOSTXL-TLV8544PIR board. Because the motion was
created at very close proximity of the sensor on the booster board used to collect the data, the signal was limited
by the diode in the first stage as shown in the plot.
Figure 34. Noninverting Comparator Input and Output Signals
Referring to Figure 34, the output of the inverting comparator during the lower cycle of the PIR signal switches
form the cutoff region to the saturation region as the input signal crosses the VREF_Low threshold.
Figure 35. Noninverting Comparator Input and Output Signals
18
Copyright © 2016–2017, Texas Instruments Incorporated
TLV8544, TLV8542, TLV8541
www.ti.com.cn
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
9.3 Typical Application: 60-Hz Twin T Notch Filter
VBAT
CR2032 coin cell
10 Mꢀ
10 Mꢀ
VBAT
Signal from a remote sensor
containing 60 Hz noise
+
To ADC
VOUT
¼
TLV8544
VIN
-
10 MΩ
10 MΩ
270 pF
270 pF
10 MΩ
10 MΩ
60 Hz Twin notch filter
With gain of Av = 2 V/V
Copyright © 2017, Texas Instruments Incorporated
Figure 36. 60 Hz-Notch Filter
9.3.1 Design Requirements
Small signals from transducers in remote and distributed sensing applications commonly suffer strong 60-Hz
interference from AC power lines. The circuit of Figure 36 filters out (notches out) the 60 Hz and provides a
system gain of AV = 2 V/V for the sensor signal represented by a 1-kHz sine wave. Similar stages may be
cascaded to remove 2nd and 3rd harmonics of 60 Hz. Thanks to the nanopower consumption of the TLV8544,
even five such circuits can run for 9.5 years from a small CR2032 lithium cell. These batteries have a nominal
voltage of 3 V and an end of life voltage of 2 V. With an operating voltage from 1.7 V to 3.6 V the TLV8544
device can function over this voltage range.
9.3.2 Detailed Design Procedure
The notch frequency is set by:
F0 = 1 / 2πRC.
(10)
To achieve a 60-Hz notch use R = 10 MΩ and C = 270 pF. If eliminating 50-Hz noise, use R = 11.8 MΩ and C =
270 pF.
The twin T notch filter works by having two separate paths from VIN to the input of the amplifier. A low-frequency
path through the series input resistors and another separate high-frequency path through the series input
capacitors. However, at frequencies around the notch frequency, the two paths have opposing phase angles,
and the two signals tend to cancel at the input of the amplifier.
To ensure that the target center frequency is achieved and to maximize the notch depth (Q factor) the filter must
be as balanced as possible. To obtain circuit balance, while overcoming limitations of available standard resistor
and capacitor values, use passives in parallel to achieve the 2C and R/2 circuit requirements for the filter
components that connect to ground.
To make sure passive component values stay as expected, clean the board with alcohol, rinse with deionized
water, and air dry. Make sure board remains in a relatively low humidity environment to minimize moisture which
may increase the conductivity of board components. Also large resistors come with considerable parasitic stray
capacitance which effects can be reduced by cutting out the ground plane below components of concern.
Copyright © 2016–2017, Texas Instruments Incorporated
19
TLV8544, TLV8542, TLV8541
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
Typical Application: 60-Hz Twin T Notch Filter (continued)
Large resistors are used in the feedback network to minimize battery drain. When designing with large resistors,
resistor thermal noise, op amp current noise, as well as op-amp voltage noise, must be considered in the noise
analysis of the circuit. The noise analysis for the circuit in Figure 36 can be done over a bandwidth of 2 kHz,
which takes the conservative approach of overestimating the bandwidth (TLV8544 typical GBW/AV is lower,
where AV is the gain of the system). The total noise at the output is approximately 800 µVpp, which is excellent
considering the total consumption of the circuit is only 500 nA per channel. The dominant noise terms are op-
amp voltage noise, current noise through the feedback network (430 µVp-p), and current noise through the notch
filter network (280 µVp-p). Thus the total noise of the circuit is below 1/2 LSB of a 10-bit system with a 2-V
reference, which is 1 mV.
9.3.3 Application Curve
Figure 37. 60-Hz Notch Filter Waveform
9.4 Dos and Don'ts
Do properly bypass the power supplies.
Do add series resistance to the output when driving capacitive loads, particularly cables, multiplexers, and ADC
inputs.
Do add series current limiting resistors and external Schottky clamp diodes if input voltage is expected to exceed
the supplies. Limit the current to 1 mA or less (1 KΩ per volt).
10 Power Supply Recommendations
The TLV854x is specified for operation from 1.7 V to 3.6 V (±0.85 V to ±1.8 V) over a –40°C to +125°C
temperature range. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 3.6 V can permanently damage the device.
For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines it is
suggested that 100-nF capacitors be placed as close as possible to the op-amp power supply pins. For single
supply, place a capacitor between V+ and V– supply leads. For dual supplies, place one capacitor between V+
and ground and one capacitor between V– and ground.
Low bandwidth nanopower devices do not have good high frequency (> 1 kHz) AC PSRR rejection against high-
frequency switching supplies and other 1-kHz and above noise sources, so extra supply filtering is recommended
if kilohertz or above noise is expected on the power supply lines.
20
Copyright © 2016–2017, Texas Instruments Incorporated
TLV8544, TLV8542, TLV8541
www.ti.com.cn
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
11 Layout
11.1 Layout Guidelines
•
•
•
•
•
The V+ pin must be bypassed to ground with a low ESR capacitor.
The optimum placement is closest to the V+ and ground pins.
Take care to minimize the loop area formed by the bypass capacitor connection between V+ and ground.
Connect the ground pin to the PCB ground plane at the pin of the device.
Place the feedback components as close as possible to the device to minimize stray impedance.
11.2 Layout Example
VOUTA
Place components close to
device and to each other to
reduce parasitic error
RF
OUTA
-INA
1
2
OUTD
-IND
14
13
RG
V+
D
A
+
+
GND
+INA
V+
3
+IND
V-
12
11
10
VIN
Run the input traces as
far away from the supply
lines as possible
4
5
6
7
GND
+INB
-INB
+INC
-INC
OUTC
Place low-ESR ceramic
bypass capacitor close to
device
9
8
+
+
B
C
GND
OUTB
Figure 38. Layout Example of a Typical Dual Channel Package (Top View)
版权 © 2016–2017, Texas Instruments Incorporated
21
TLV8544, TLV8542, TLV8541
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
基于 SPICE 的 TINA-TI 模拟仿真程序
DIP 适配器评估模块
TI 通用运算放大器评估模块
TI FilterPro 滤波器设计软件
12.2 文档支持
12.2.1 相关文档
相关文档如下：
•
•
•
•
•
•
•
•
AN-1798《设计电化学传感器》
《AN-1803 跨阻放大器设计注意事项》
《AN-1852 使用 pH 电极进行设计》
《用直观方式补偿互阻抗放大器》
《高速运算放大器跨阻注意事项》
《FET 跨阻放大器噪声分析》
《电路板布局布线技巧》
《运算放大器应用 手册》
12.3 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件以及立即订购快速访问。
表 1. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
工具和软件
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
TLV8544
TLV8542
TLV8541
12.4 接收文档更新通知
要接收文档更新通知，请转至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品信
息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.5 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
22
版权 © 2016–2017, Texas Instruments Incorporated
TLV8544, TLV8542, TLV8541
www.ti.com.cn
ZHCSG36D –DECEMBER 2016–REVISED NOVEMBER 2017
12.6 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
版权 © 2016–2017, Texas Instruments Incorporated
23
PACKAGE OPTION ADDENDUM
www.ti.com
2-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV8541DBVR
TLV8542DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOIC
DBV
D
5
8
3000 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1D5L
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAUAG
NIPDAU
TL8542
AR
TLV8542RUGR
TLV8544DR
X2QFN
SOIC
RUG
D
8
14
14
14
TLV8544
TLV8544
TL8544
TLV8544DT
SOIC
D
250
RoHS & Green
NIPDAU
TLV8544PWR
TSSOP
PW
2000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Mar-2023
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV8541DBVR
TLV8542DR
SOT-23
SOIC
DBV
D
5
8
3000
2500
3000
2500
2000
180.0
330.0
180.0
330.0
330.0
8.4
12.4
8.4
3.2
6.4
1.6
6.5
6.9
3.2
5.2
1.6
9.0
5.6
1.4
2.1
4.0
8.0
4.0
8.0
8.0
8.0
12.0
8.0
Q3
Q1
Q2
Q1
Q1
TLV8542RUGR
TLV8544DR
X2QFN
SOIC
RUG
D
8
0.66
2.1
14
14
16.4
12.4
16.0
12.0
TLV8544PWR
TSSOP
PW
1.6
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV8541DBVR
TLV8542DR
SOT-23
SOIC
DBV
D
5
8
3000
2500
3000
2500
2000
210.0
340.5
183.0
340.5
356.0
185.0
336.1
183.0
336.1
356.0
35.0
25.0
20.0
32.0
35.0
TLV8542RUGR
TLV8544DR
X2QFN
SOIC
RUG
D
8
14
14
TLV8544PWR
TSSOP
PW
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
TLV8542DR
双路、3.6V、8kHz、超低静态电流 (500nA)、RRIO 运算放大器 | D | 8 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV8542RUGR
双路、3.6V、8kHz、超低静态电流 (500nA)、RRIO 运算放大器 | RUG | 8 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV8544
四路、3.6V、8kHz、超低静态电流 (500nA)、RRIO 运算放大器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV8544DR
四路、3.6V、8kHz、超低静态电流 (500nA)、RRIO 运算放大器 | D | 14 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV8544DT
四路、3.6V、8kHz、超低静态电流 (500nA)、RRIO 运算放大器 | D | 14 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV8544PWR
四路、3.6V、8kHz、超低静态电流 (500nA)、RRIO 运算放大器 | PW | 14 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV863M
采用反向引脚排列、具有低电平有效开漏复位功能的 3 引脚电压监控器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV863MDBZR
3-Pin Voltage Supervisors with Active-Low, Open-Drain ResetWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV863MDBZT
3-Pin Voltage Supervisors with Active-Low, Open-Drain ResetWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV8801
单路、5.5V、6kHz、超低静态电流 (450nA)、RRIO 运算放大器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV8801DBVR
单路、5.5V、6kHz、超低静态电流 (450nA)、RRIO 运算放大器 | DBV | 5 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TLV8801DBVT
单路、5.5V、6kHz、超低静态电流 (450nA)、RRIO 运算放大器 | DBV | 5 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
©2020 ICPDF网 联系我们和版权申明