TLV9004QDYYRQ1 [TI]
TLV900x-Q1 Low-Power RRIO 1-MHz Automotive Operational Amplifier;
| 型号： | TLV9004QDYYRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TLV900x-Q1 Low-Power RRIO 1-MHz Automotive Operational Amplifier |
| 文件： | 总44页 (文件大小：2702K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV9001-Q1, TLV9002-Q1, TLV9004-Q1
SBOS980C – MAY 2019 – REVISED OCTOBER 2021
TLV900x-Q1 Low-Power RRIO 1-MHz Automotive Operational Amplifier
1 Features
3 Description
•
AEC-Q100 qualified for automotive applications
– Temperature grade 1: –40°C to +125°C, TA
– Device HBM ESD classification level 2
– Device CDM ESD classification level C6
Scalable CMOS amplifier for low-cost applications
Rail-to-rail input and output
Low input offset voltage: ±0.4 mV
Unity-gain bandwidth: 1 MHz
Low broadband noise: 27 nV/√ Hz
Low input bias current: 5 pA
Low quiescent current: 60 µA\/Ch
Unity-gain stable
Internal RFI and EMI filter
Operational at supply voltages as low as 1.8 V
Easier to stabilize with higher capacitive load due
to resistive open-loop output impedance
Functional Safety-Capable
– Documentation avialable to aid functional safety
system design
The TLV900x-Q1 family includes single (TLV9001-
Q1), dual (TLV9002-Q1), and quad-channel
(TLV9004-Q1) low-voltage (1.8 V to 5.5 V) operational
amplifiers (op amps) with rail-to-rail input and output
swing capabilities. These op amps provide a cost-
effective solution for space-constrained automotive
applications such as infotainment and lighting where
low-voltage operation and high capacitive-load drive
are required. The capacitive-load drive of the
TLV900x-Q1 family is 500 pF, and the resistive open-
loop output impedance makes stabilization easier with
much higher capacitive loads. These op amps are
designed specifically for low-voltage operation (1.8 V
to 5.5 V) with performance specifications similar to the
TLV600x-Q1 devices.
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The robust design of the TLV900x-Q1 family simplifies
circuit design. The op amps feature unity-gain
stability, an integrated RFI and EMI rejection filter, and
no-phase reversal in overdrive conditions.
•
2 Applications
Device Information
PACKAGE
SOT-23 (5)(2)
PART NUMBER (1)
BODY SIZE (NOM)
1.60 mm × 2.90 mm
1.25 mm × 2.00 mm
3.91 mm × 4.90 mm
3.00 mm × 4.40 mm
3.00 mm × 3.00 mm
4.20 mm × 1.90 mm
8.65 mm × 3.91 mm
4.40 mm × 5.00 mm
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Optimized for AEC-Q100 grade 1 applications
Infotainment & Cluster
Passive safety
Body electronics and lighting
HEV/EV inverter and motor control
On-board (OBC) & wireless charger
Powertrain current sensor
Advanced driver assistance systems (ADAS)
Single-supply, low-side, unidirectional current-
sensing circuit
TLV9001-Q1
SC70 (5)(2)
SOIC (8)
TLV9002-Q1
TLV9004-Q1
TSSOP (8)(2)
VSSOP (8)
SOT-23 (14)
SOIC (14)
TSSOP (14)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Package is for preview only.
Single-Pole, Low-Pass Filter
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV9001-Q1, TLV9002-Q1, TLV9004-Q1
SBOS980C – MAY 2019 – REVISED OCTOBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 7
7.1 Absolute Maximum Ratings ....................................... 7
7.2 ESD Ratings .............................................................. 7
7.3 Recommended Operating Conditions ........................7
7.4 Thermal Information for Single Channel .................... 7
7.5 Thermal Information for Dual Channel .......................8
7.6 Thermal Information for Quad Channel ..................... 8
7.7 Electrical Characteristics ............................................9
7.8 Typical Characteristics.............................................. 11
8 Detailed Description......................................................17
8.1 Overview...................................................................17
8.2 Functional Block Diagram.........................................17
8.3 Feature Description...................................................18
8.4 Device Functional Modes..........................................18
9 Application and Implementation..................................19
9.1 Application Information............................................. 19
9.2 Typical Application.................................................... 19
10 Power Supply Recommendations..............................24
10.1 Input and ESD Protection....................................... 24
11 Layout...........................................................................25
11.1 Layout Guidelines................................................... 25
11.2 Layout Example...................................................... 25
12 Device and Documentation Support..........................26
12.1 Documentation Support.......................................... 26
12.2 Related Links.......................................................... 26
12.3 Receiving Notification of Documentation Updates..26
12.4 Support Resources................................................. 26
12.5 Trademarks.............................................................26
12.6 Electrostatic Discharge Caution..............................26
12.7 Glossary..................................................................26
13 Mechanical, Packaging, and Orderable
Information.................................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2021) to Revision C (October 2021)
Page
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Deleted preview tag for SOT-23 (14) and TSSOP (14) from Device information section...................................1
Added preview tags for TLV9001-Q1 SOT-23 (5) and SC70 (5) packages to Device information section.........1
Added TLV9001-Q1 GPN to the data sheet....................................................................................................... 1
Added TLV9001-Q1 to Device Comparison Table section .................................................................................3
Added TLV9001-Q1 DBV (SOT-23) and DCK (SC70) in Pin Configuration and Functions section .................. 4
Added Thermal Information for Single Channel..................................................................................................7
Added TLV9001-Q1 to Related Links .............................................................................................................. 26
Changes from Revision A (June 2020) to Revision B (March 2021)
Page
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Updated the numbering format for tables, figures and cross-references throughout the document...................1
Functional Safety-Capable document link added in the Features section..........................................................1
Deleted preview tag for VSSOP (8) from Device information section.................................................................1
Added note 4 to differential input voltage in Absolute Maximum Ratings table .................................................7
Added Thermal Information for DGK package....................................................................................................8
Added Thermal Information for DYY package....................................................................................................8
Changes from Revision * (May 2019) to Revision A (June 2020)
Page
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Changed the device status from Advance Information to Production Data ....................................................... 1
Added end equipment links in Application section .............................................................................................1
Deleted preview tag for SOIC (8) from Device information section.................................................................... 1
Added SOT-23 (14) in Device Information section ............................................................................................ 1
Deleted preview tag for SOIC (14) from Device information section.................................................................. 1
Added SOT-23 (DYY) package in Device Comparison Table section ............................................................... 3
Added DYY (SOT-23) in Pin Functions: TLV9004-Q1 section ...........................................................................4
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5 Device Comparison Table
PACKAGE LEADS
NO. OF
DEVICE
SOT-23
DBV
SC70
DCK
SOIC
D
TSSOP
PW
VSSOP
DGK
SOT-23
DYY
CHANNELS
TLV9001-Q1
TLV9002-Q1
TLV9004-Q1
1
2
4
5
5
—
8
—
8
—
8
—
—
—
—
—
14
14
—
14
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6 Pin Configuration and Functions
OUT
Vœ
1
2
3
5
V+
IN+
4
INœ
Not to scale
Figure 6-1. TLV9001-Q1 DBV Package 5-Pin SOT-23 Top View
IN+
Vœ
1
2
3
5
V+
INœ
4
OUT
Not to scale
Figure 6-2. TLV9001-Q1 DCK Package 5-Pin SC70 Top View
Table 6-1. Pin Functions: TLV9001-Q1
PIN
I/O
DESCRIPTION
NAME
IN–
SOT-23
SC70
X2SON
4
3
1
2
5
3
1
4
2
5
2
4
1
3
5
I
I
Inverting input
Noninverting input
Output
IN+
OUT
V–
O
I or — Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
V+
I
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OUT1
IN1œ
IN1+
Vœ
1
2
3
4
8
7
6
5
V+
OUT2
IN2œ
IN2+
Not to scale
Figure 6-3. TLV9002-Q1 D, DGK, PW Packages 8-Pin SOIC, VSSOP, TSSOP Top View
Table 6-2. Pin Functions: TLV9002-Q1
PIN
I/O
DESCRIPTION
NAME
IN1–
NO.
2
I
I
Inverting input, channel 1
Noninverting input, channel 1
Inverting input, channel 2
Noninverting input, channel 2
Output, channel 1
IN1+
3
IN2–
6
I
IN2+
5
I
OUT1
OUT2
V–
1
O
O
7
Output, channel 2
4
I or — Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
V+
8
I
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OUT1
IN1œ
IN1+
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT4
IN4œ
IN4+
Vœ
IN2+
IN2œ
OUT2
IN3+
IN3œ
OUT3
8
Not to scale
Figure 6-4. TLV9004-Q1 D, PW, DYY Packages 14-Pin SOIC, TSSOP, SOT-23 Top View
Table 6-3. Pin Functions: TLV9004-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
2
IN1–
IN1+
IN2–
IN2+
IN3–
IN3+
IN4–
IN4+
NC
I
Inverting input, channel 1
Noninverting input, channel 1
Inverting input, channel 2
Noninverting input, channel 2
Inverting input, channel 3
Noninverting input, channel 3
Inverting input, channel 4
Noninverting input, channel 4
No internal connection
Output, channel 1
3
I
6
I
5
I
9
I
10
13
12
—
1
I
I
I
—
O
OUT1
OUT2
OUT3
OUT4
V–
7
O
Output, channel 2
8
O
Output, channel 3
14
11
4
O
Output, channel 4
I or —
I
Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
V+
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
0
MAX
UNIT
V
Supply voltage ([V+] – [V–])
6
(V+) + 0.5
Common-mode
Voltage(2)
(V–) – 0.5
V
Signal input pins
Differential (4)
(V+) – (V–) + 0.2
10
V
Current(2)
–10
mA
mA
°C
°C
°C
Output short-circuit(3)
Operating, TA
Junction, TJ
Continuous
–55
–65
150
150
150
Storage, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
(4) Differential input voltages greater than 0.5 V applied continuously can result in a shift to the input offset voltage and quiescent current
above the maximum specifications of these parameters. The magnitude of this effect increases as the ambient operating temperature
rises.
7.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with ANSI/ESDA/JEDEC JS-001 Specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
5.5
UNIT
V
VS
TA
Supply voltage
1.8
Specified temperature
–40
125
°C
7.4 Thermal Information for Single Channel
TLV9001-Q1
DBV (2)
(SOT-23)
DCK (2)
(SC70)
THERMAL METRIC (1)
UNIT
5 PINS
TBD
TBD
TBD
TBD
TBD
TBD
5 PINS
TBD
TBD
TBD
TBD
TBD
TBD
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) This package option is preview for TLV9001-Q1.
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UNIT
SBOS980C – MAY 2019 – REVISED OCTOBER 2021
7.5 Thermal Information for Dual Channel
TLV9002-Q1
DGK (VSSOP)
8 PINS
196.6
THERMAL METRIC (1)
D (SOIC)
8 PINS
151.9
92.0
PW (TSSOP)
8 PINS
TBD
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
86.2
TBD
95.4
118.3
TBD
Junction-to-top characterization parameter
Junction-to-board characterization parameter
40.2
23.2
TBD
ψJB
94.7
116.7
TBD
(1) For more information about traditional and new thermalmetrics, see Semiconductor and ICPackage Thermal Metrics application report.
7.6 Thermal Information for Quad Channel
TLV9004-Q1
THERMAL METRIC (1)
D (SOIC)
14 PINS
115.1
71.2
DYY (SOT-23)
14 PINS
154.3
PW (TSSOP)
14 PINS
135.3
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
86.8
63.5
71.1
67.9
78.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
29.6
10.1
13.6
ψJB
70.7
67.5
77.9
(1) For more information about traditional and new thermalmetrics, see Semiconductor and ICPackage Thermal Metrics application report.
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7.7 Electrical Characteristics
For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25 °C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS /
2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
Vs = 5 V
±0.4
±1.85
±2
mV
mV
VOS
Input offset voltage
Vs = 5 V, TA = –40°C to 125°C
TA = –40°C to 125°C
dVOS/dT
PSRR
VOS vs temperature
±0.6
105
μV/°C
VS = 1.8 to 5.5 V, VCM = (V–)
Power-supply rejection ratio
80
dB
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
No phase reversal, rail-to-rail input
(V–) – 0.1
(V+) + 0.1
V
VS = 1.8 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V,
TA = –40°C to 125°C
86
95
77
68
dB
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V,
TA = –40°C to 125°C
dB
dB
dB
CMRR
Common-mode rejection ratio
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V,
TA = –40°C to 125°C
63
VS = 1.8 V, (V–) – 0.1 V < VCM < (V+)+ 0.1 V,
TA = –40°C to 125°C
INPUT BIAS CURRENT
IB
Input bias current
Vs = 5 V
±5
±2
pA
pA
IOS
Input offset current
NOISE
En
Input voltage noise (peak-to-peak)
Input voltage noise density
Input current noise density
ƒ = 0.1 Hz to 10 Hz, Vs = 5 V
ƒ = 1 kHz, Vs = 5 V
4.7
30
27
23
μVPP
nV/√Hz
nV/√Hz
fA/√Hz
en
ƒ = 10 kHz, Vs = 5 V
ƒ = 1 kHz, Vs = 5 V
in
INPUT CAPACITANCE
CID
CIC
Differential
1.5
5
pF
pF
Common-mode
OPEN-LOOP GAIN
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
RL = 10 kΩ
104
117
100
115
130
dB
dB
dB
dB
VS = 1.8 V, (V–) + 0.04 V < VO < (V+) – 0.04 V,
RL = 10 kΩ
AOL
Open-loop voltage gain
VS = 1.8 V, (V–) + 0.1 V < VO < (V+) – 0.1 V,
RL = 2 kΩ
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
RL = 2 kΩ
FREQUENCY RESPONSE
GBW
φm
Gain-bandwidth product
Vs = 5 V
1
78
MHz
degrees
V/µs
μs
Phase margin
Slew rate
VS = 5.5 V, G = 1
SR
Vs = 5 V
2
To 0.1%, VS = 5 V, 2 V Step , G = +1, CL = 100 pF
To 0.01%, VS = 5 V, 2 V Step , G = +1, CL = 100 pF
VS = 5 V, VIN × gain > VS
2.5
3
tS
Settling time
μs
tOR
Overload recovery time
0.85
μs
VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1,
f = 1 kHz, 80 kHz measurement BW
THD+N
OUTPUT
Total harmonic distortion + noise
0.004
%
VS = 5.5 V, RL = 10 kΩ
VS = 5.5 V, RL = 2 kΩ
Vs = 5.5 V
10
35
20
55
mV
mV
mA
Ω
VO
Voltage output swing from supply rails
ISC
ZO
Short-circuit current
±40
1200
Open-loop output impedance
Vs = 5 V, f = 1 MHz
POWER SUPPLY
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7.7 Electrical Characteristics (continued)
For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25 °C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS /
2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
5.5 (±2.75)
80
UNIT
VS
IQ
Specified voltage range
1.8 (±0.9)
V
IO = 0 mA, VS = 5.5 V
60
µA
µA
µs
Quiescent current per amplifier
Power-on time
IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C
VS = 0 V to 5 V, to 90% IQ level
85
50
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7.8 Typical Characteristics
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
40
35
30
25
20
15
10
5
25
20
15
10
5
0
0
0
-
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
1200 -900 -600 -300
0
300 600 900 1200 1500 1800
D001
D002
Offset Voltage (μV)
Offset Voltage Drift (μV/°C)
VS = 5 V
VS = 5 V, TA = –40°C to +125°C
Figure 7-1. Offset Voltage Distribution Histogram
Figure 7-2. Offset Voltage Drift Distribution Histogram
1000
2000
800
600
1500
1000
500
400
200
0
0
-200
-400
-600
-800
-1000
-500
-1000
-1500
-2000
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-4
-3
-2
-1
0
1
Common-Mode Voltage (V)
2
3
4
D003
D004
Figure 7-3. Input Offset Voltage vs Temperature
Figure 7-4. Offset Voltage vs Common-Mode
1000
6
4
IB-
IB+
IOS
800
600
2
400
0
200
0
-2
-4
-6
-8
-10
-200
-400
-600
-800
-1000
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
6
-40
-20
0
20
40
60
80
100 120 140
D005
Temperature (èC)
D006
Figure 7-5. Offset Voltage vs Supply Voltage
Figure 7-6. IB and IOS vs Temperature
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7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
3.5
3
160
140
120
100
80
IB-
IB+
IOS
2.5
2
1.5
1
0.5
0
60
-0.5
-1
40
-1.5
-2
20
VS = 5.5 V
VS = 1.8 V
-2.5
0
-3
-2
-1
0
1
Common-Mode Voltage (V)
2
3
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D007
D008
Figure 7-7. IB and IOS vs Common-Mode Voltage
Figure 7-8. Open-Loop Gain vs Temperature
100
80
60
40
20
0
120
160
140
120
100
80
100
80
60
40
20
0
60
40
Gain
Phase
20
-20
1k
10k
100k
Frequency (Hz)
1M
0
-3
-2
-1 0
Output Voltage (V)
1
2
3
D009
D010
CL = 10 pF
Figure 7-10. Open-Loop Gain vs Output Voltage
Figure 7-9. Open-Loop Gain and Phase vs Frequency
80
3
2.5
2
Gain = -1
Gain = 1
Gain = 100
Gain = 1000
Gain = 10
70
60
1.5
1
125°C
50
40
30
20
10
0
85°C
25°C
-40°C
0.5
0
-0.5
-1
85°C
25°C
-40°C
-1.5
-2
125°C
-10
-20
-2.5
-3
100
1k
10k 100k
Frequency (Hz)
1M
0
5
10
15
20
25
30
Output Current (mA)
35
40
45
50
D011
D012
Figure 7-12. Output Voltage vs Output Current (Claw)
CL = 10 pF
Figure 7-11. Closed-Loop Gain vs Frequency
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7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
120
100
80
60
40
20
0
120
100
80
60
40
20
0
PSRR+
PSRR-
-40
-20
0
20
40
60
80
100 120 140
100
1k
10k
Frequency (Hz)
100k
1M
Temperature (èC)
D014
D013
Figure 7-13. PSRR vs Frequency
VS = 1.8 V to 5.5 V
Figure 7-14. DC PSRR vs Temperature
120
100
80
60
40
20
0
160
140
120
100
80
60
40
20
VS = 1.8 V
VS = 5.5 V
0
-40
-20
0
20
40
60
80
100 120 140
100
1k
10k
Frequency (Hz)
100k
1M
Temperature (èC)
D016
D015
Figure 7-15. CMRR vs Frequency
VCM = (V–) – 0.1 V to (V+) – 1.4 V
Figure 7-16. DC CMRR vs Temperature
120
100
80
60
40
20
0
Time (1 s/div)
10
100
1k
Frequency (Hz)
10k
100k
D017
D018
Figure 7-17. 0.1 Hz to 10 Hz Integrated Voltage Noise
Figure 7-18. Input Voltage Noise Spectral Density
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7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
-50
0
G = +1, RL = 2 kW
G = +1, RL = 10 kW
G = -1, RL = 2 kW
G = -1, RL = 10 kW
-60
-20
-70
-40
-80
-60
-90
-80
RL = 2K
RL = 10K
-100
-100
100
1k
Frequency (Hz)
10k
0.001
0.01
0.1
Amplitude (VRMS)
1
2
D019
D020
VS = 5.5 V
BW = 80 kHz
VCM = 2.5 V
G = 1
VS = 5.5 V
G = 1
VCM = 2.5 V
f = 1 kHz
VOUT = 0.5 VRMS
BW = 80 kHz
Figure 7-19. THD + N vs Frequency
Figure 7-20. THD + N vs Amplitude
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
-40
-20
0
20
40
60
80
100 120 140
1.5
2
2.5
3
3.5
4
Voltage Supply (V)
4.5
5
5.5
Temperature (èC)
D022
D021
Figure 7-22. Quiescent Current vs Temperature
Figure 7-21. Quiescent Current vs Supply Voltage
2000
50
1800
1600
1400
1200
1000
800
600
400
200
0
45
40
35
30
25
20
15
10
5
Overshoot (+)
Overshoot (–)
0
1k
10k
100k
Frequency (Hz)
1M
10M
0
200
400 600
Capacitance Load (pF)
800
1000
D023
D024
Figure 7-23. Open-Loop Output Impedance vs Frequency
G = 1
VIN = 100 mVpp
Figure 7-24. Small Signal Overshoot vs Capacitive Load
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7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
50
45
40
35
30
25
20
15
10
5
90
80
70
60
50
40
30
20
10
0
Overshoot (+)
Overshoot (–)
0
0
200
400 600
Capacitance Load (pF)
800
1000
0
200
400 600
Capacitance Load (pF)
800
1000
D025
D026
Figure 7-26. Phase Margin vs Capacitive Load
G = –1
VIN = 100 mVpp
Figure 7-25. Small Signal Overshoot vs Capacitive Load
VOUT
VIN
VOUT
VIN
Time (100 ms/div)
Time (20 ms/div)
D027
D028
G = 1
VIN = 6.5 VPP
G = –10
VIN = 600 mVPP
Figure 7-27. No Phase Reversal
Figure 7-28. Overload Recovery
VOUT
VIN
VOUT
VIN
Time (10 ms/div)
Time (10 ms/div)
D029
D030
G = 1
VIN = 100 mVPP
CL = 10 pF
G = 1
VIN = 4 VPP
CL = 10 pF
Figure 7-29. Small-Signal Step Response
Figure 7-30. Large-Signal Step Response
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7.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
Time (1 ms/div)
Time (1 μs/div)
D032
D031
G = 1
CL = 100 pF
2-V step
G = 1
CL = 100 pF
2-V step
Figure 7-32. Large-Signal Settling Time (Positive)
Figure 7-31. Large-Signal Settling Time (Negative)
80
6
VS = 5.5 V
VS = 1.8 V
60
40
20
0
5
4
3
2
1
0
-20
-40
-60
-80
Sinking
Sourcing
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M 100M
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
D034
D033
Figure 7-34. Maximum Output Voltage vs Frequency
Figure 7-33. Short-Circuit Current vs Temperature
140
0
-20
-40
120
100
80
60
40
20
0
-60
-80
-100
-120
-140
1k
10k
100k
Frequency (Hz)
1M
10M
10M
100M
Frequency (Hz)
1G
10G
D036
D035
Figure 7-36. Channel Separation
Figure 7-35. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency
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8 Detailed Description
8.1 Overview
The TLV900x-Q1 is a family of automotive qualified, low-power, rail-to-rail input and output op amps. These
devices operate from 1.8 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose
applications. The input common-mode voltage range includes both rails and allows the TLV900x-Q1 family to be
used in virtually any single-supply application. Rail-to-rail input and output swing significantly increases dynamic
range, especially in low-supply applications, and makes them suitable for driving sampling analog-to-digital
converters (ADCs).
8.2 Functional Block Diagram
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8.3 Feature Description
8.3.1 Operating Voltage
The TLV900x-Q1 family of op amps are for operation from 1.8 V to 5.5 V. In addition, many specifications such
as input offset voltage, quiescent current, offset current, and short circuit current apply from –40°C to 125°C.
Parameters that vary significantly with operating voltages or temperature are shown in the typical characteristics
section.
8.3.2 Rail-to-Rail Input
The input common-mode voltage range of the TLV900x-Q1 family extends 100 mV beyond the supply rails for
the full supply voltage range of 1.8 V to 5.5 V. This performance is achieved with a complementary input stage:
an N-channel input differential pair in parallel with a P-channel differential pair, as shown in the Functional Block
Diagram section. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V
to 100 mV above the positive supply, whereas the P-channel pair is active for inputs from 100 mV below the
negative supply to approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1
V, in which both pairs are on. This 100-mV transition region can vary up to 100 mV with process variation. Thus,
the transition region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to
(V+) – 1 V to (V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift,
and THD can degrade compared to device operation outside this region.
8.3.3 Rail-to-Rail Output
Designed as a low-power, low-voltage operational amplifier, the TLV900x-Q1 family delivers a robust output
drive capability. A class-AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads of 10 kΩ, the output swings to within 20 mV of either supply rail, regardless of the
applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the
rails.
8.3.4 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device
enters the saturation region, the charge carriers in the output devices require time to return to the linear state.
After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore,
the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew
time. The overload recovery time for the TLV900x-Q1 family is approximately 850 ns.
8.4 Device Functional Modes
The TLV900x-Q1 family has a single functional mode. The devices are powered on as long as the power-supply
voltage is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TLV900x-Q1 family of low-power, rail-to-rail input and output operational amplifiers is specifically designed
for portable applications. The devices operate from 1.8 V to 5.5 V, are unity-gain stable, and are suitable for a
wide range of general-purpose applications. The class AB output stage is capable of driving less than or equal to
10‑kΩ loads connected to any point between V+ and V–. The input common-mode voltage range includes both
rails, and allows the TLV900x-Q1 devices to be used in any single-supply application.
9.2 Typical Application
9.2.1 TLV900x-Q1 Low-Side, Current Sensing Application
Figure 9-1 shows the TLV900x-Q1 configured in a low-side current sensing application.
VBUS
ILOAD
ZLOAD
5 V
+
TLV9002
VOUT
Þ
+
RSHUNT
VSHUNT
RF
0.1 Ω
57.6 kΩ
Þ
RG
1.2 kΩ
Figure 9-1. TLV900x-Q1 in a Low-Side, Current-Sensing Application
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9.2.1.1 Design Requirements
The design requirements for this design are:
•
•
•
Load current: 0 A to 1 A
Output voltage: 4.9 V
Maximum shunt voltage: 100 mV
9.2.1.2 Detailed Design Procedure
The transfer function of the circuit in Figure 9-1 is given in Equation 1:
VOUT = ILOAD ìRSHUNT ìGain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set
from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
shown using Equation 2:
VSHUNT _MAX
100mV
1A
RSHUNT
=
=
=100mW
ILOAD_MAX
(2)
Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the TLV900x-Q1 to produce an output voltage of approximately 0 V to 4.9 V. The gain needed by
the TLV900x-Q1 to produce the necessary output voltage is calculated using Equation 3:
V
OUT _MAX - VOUT _MIN
(
)
Gain =
VIN_MAX - V
IN_MIN
(3)
Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 4
sizes the resistors RF and RG, to set the gain of the TLV900x-Q1 to 49 V/V.
R
(
)
F
Gain = 1+
R
G
(4)
Selecting RF as 57.6 kΩ and RG as 1.2 kΩ provides a combination that equals 49 V/V. Figure 9-2 shows the
measured transfer function of the circuit shown in Figure 9-1. Notice that the gain is only a function of the
feedback and gain resistors. This gain is adjusted by varying the ratio of the resistors and the actual resistors
values are determined by the impedance levels that the designer wants to establish. The impedance level
determines the current drain, the effect that stray capacitance has, and a few other behaviors. There is no
optimal impedance selection that works for every system, you must choose an impedance that is ideal for your
system parameters.
9.2.1.3 Application Curve
5
4
3
2
1
0
0
0.2
0.4
0.6
0.8
1
ILOAD (A)
C219
Figure 9-2. Low-Side, Current-Sense Transfer Function
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9.2.2 Single-Supply Photodiode Amplifier
Photodiodes are used in many applications to convert light signals to electrical signals. The current through
the photodiode is proportional to the photon energy absorbed, and is commonly in the range of a few hundred
picoamps to a few tens of microamps. An amplifier in a transimpedance configuration is typically used to convert
the low-level photodiode current to a voltage signal for processing in an MCU. The circuit shown in Figure 9-3 is
an example of a single-supply photodiode amplifier circuit using the TLV9002-Q1.
+3.3V
R1
11.5 kΩ
10 pF
CF
VREF
R2
357 Ω
RF
309 kΩ
3.3 V
œ
TLV9002
VOUT
+
VREF
CPD
IIN
0-10 µA
RL
10 kꢀ
47 pF
Figure 9-3. Single-Supply Photodiode Amplifier Circuit
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9.2.2.1 Design Requirements
The design requirements for this design are:
•
•
•
•
Supply voltage: 3.3 V
Input: 0 µA to 10 µA
Output: 0.1 V to 3.2 V
Bandwidth: 50 kHz
9.2.2.2 Detailed Design Procedure
The transfer function between the output voltage (VOUT), the input current, (IIN) and the reference voltage (VREF
)
is defined in Equation 5.
VOUT = IIN ìRF + VREF
(5)
(6)
Where:
≈
∆
«
’
÷
R1 ìR2
R1 + R2 ◊
VREF = V ì
+
Set VREF to 100 mV to meet the minimum output voltage level by setting R1 and R2 to meet the required ratio
calculated in Equation 7.
VREF
0.1 V
3.3 V
=
= 0.0303
V+
(7)
The closest resistor ratio to meet this ratio sets R1 to 11.5 kΩ and R2 to 357 Ω.
The required feedback resistance can be calculated based on the input current and desired output voltage.
VOUT - VREF
3.2 V - 0.1 V
10 mA
kV
A
RF =
=
= 310
ö 309 kW
I
IN
(8)
Calculate the value for the feedback capacitor based on RF and the desired –3-dB bandwidth, (f–3dB) using
Equation 9.
1
1
CF =
=
= 10.3 pF ö 10 pF
2ì pìRF ì f-3dB 2ì pì309 kWì50 kHz
(9)
The minimum op amp bandwidth required for this application is based on the value of RF, CF, and the
capacitance on the INx– pin of the TLV9002-Q1 which is equal to the sum of the photodiode shunt capacitance,
(CPD) the common-mode input capacitance, (CCM) and the differential input capacitance (CD) as Equation 10
shows.
C
= CPD + CCM + CD = 47 pF+ 5 pF +1pF = 53 pF
IN
(10)
The minimum op amp bandwidth is calculated in Equation 11.
CIN + CF
f=BGW
í
í 324 kHz
2
2ì pìRF ì CF
(11)
The 1-MHz bandwidth of the TLV900x-Q1 meets the minimum bandwidth requirement and remains stable in this
application configuration.
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9.2.2.3 Application Curves
The measured current-to-voltage transfer function for the photodiode amplifier circuit is shown in Figure 9-4. The
measured performance of the photodiode amplifier circuit is shown in Figure 9-5.
120
100
80
3
2.5
2
1.5
1
60
0.5
0
40
10
100
1k 10k
Frequency (Hz)
100k
1M
0
2E-6
4E-6 6E-6
Input Current (A)
8E-6
1E-5
D001
D002
Figure 9-4. Photodiode Amplifier Circuit AC Gain
Results
Figure 9-5. Photodiode Amplifier Circuit DC
Results
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10 Power Supply Recommendations
The TLV900x-Q1 family is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications
apply from –40°C to 125°C. The Typical Characteristics section presents parameters that may exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 6 V may permanently damage the device; see the Absolute Maximum
Ratings table.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce coupling errors from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines section.
10.1 Input and ESD Protection
The TLV900x-Q1 family incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA. Figure 10-1 shows how a series input resistor can be added to the driven input to limit the input current.
The added resistor contributes thermal noise at the amplifier input and the value must be kept to a minimum in
noise-sensitive applications.
V+
IOVERLOAD
10-mA maximum
VOUT
Device
VIN
5 kW
Figure 10-1. Input Current Protection
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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Noise can propagate into analog circuitry through the power connections of the board and propagate to the
power pins of the op amp itself. Bypass capacitors are used to reduce the coupled noise by providing a
low-impedance path to ground.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is adequate for single-supply
applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care
to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more
detailed information, see Circuit Board Layout Techniques.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible.
If these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is much better as
opposed to running the traces in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible, as shown in Figure 11-2. Keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Remember that the input traces are the most sensitive
part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended
to remove moisture introduced into the device packaging during the cleaning process. A low-temperature,
post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
11.2 Layout Example
VIN 1
VIN 2
+
+
VOUT 1
VOUT 2
RG
RG
RF
RF
Figure 11-1. Schematic Representation for Figure 11-2
Place components
close to device and to
each other to reduce
parasitic errors.
OUT 1
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
VS+
GND
OUT1
V+
RF
RG
OUT 2
GND
IN1œ
IN1+
Vœ
OUT2
IN2œ
IN2+
RF
RG
VIN 1
GND
VIN 2
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
GND
ceramic bypass
capacitor . Place as
close to the device
as possible .
VSœ
Ground (GND) plane on another layer
as possible .
Figure 11-2. Layout Example
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
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Product Folder Links: TLV9001-Q1 TLV9002-Q1 TLV9004-Q1
TLV9001-Q1, TLV9002-Q1, TLV9004-Q1
SBOS980C – MAY 2019 – REVISED OCTOBER 2021
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
•
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 12-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
TLV9001-Q1
TLV9002-Q1
TLV9004-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2021 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: TLV9001-Q1 TLV9002-Q1 TLV9004-Q1
TLV9001-Q1, TLV9002-Q1, TLV9004-Q1
SBOS980C – MAY 2019 – REVISED OCTOBER 2021
www.ti.com
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: TLV9001-Q1 TLV9002-Q1 TLV9004-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Nov-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTLV9004QPWRQ1
TLV9002QDGKRQ1
TLV9002QDRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
VSSOP
SOIC
PW
DGK
D
14
8
2000
TBD
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
27DT
8
T9002Q
TLV9004QDRQ1
SOIC
D
14
14
14
LV9004Q
TLV9004Q
T9004Q
TLV9004QDYYRQ1
TLV9004QPWRQ1
ACTIVE SOT-23-THIN
ACTIVE TSSOP
DYY
PW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Nov-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV9002-Q1, TLV9004-Q1 :
Catalog : TLV9002, TLV9004
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV9002QDGKRQ1
TLV9002QDRQ1
TLV9004QDRQ1
TLV9004QDYYRQ1
VSSOP
SOIC
DGK
D
8
8
2500
2500
2500
3000
330.0
330.0
330.0
330.0
12.4
12.4
16.4
12.4
5.3
6.4
6.5
4.8
3.4
5.2
9.0
3.6
1.4
2.1
2.1
1.6
8.0
8.0
8.0
8.0
12.0
12.0
16.0
12.0
Q1
Q1
Q1
Q3
SOIC
D
14
14
SOT-
DYY
23-THIN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV9002QDGKRQ1
TLV9002QDRQ1
TLV9004QDRQ1
TLV9004QDYYRQ1
VSSOP
SOIC
DGK
D
8
8
2500
2500
2500
3000
366.0
853.0
853.0
336.6
364.0
449.0
449.0
336.6
50.0
35.0
35.0
31.8
SOIC
D
14
14
SOT-23-THIN
DYY
Pack Materials-Page 2
PACKAGE OUTLINE
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
C
3.36
3.16
SEATING PLANE
PIN 1 INDEX
AREA
A
0.1 C
12X 0.5
14
1
4.3
4.1
NOTE 3
2X
3
7
8
0.31
0.11
14X
0.1
C A
B
1.1 MAX
2.1
1.9
B
0.2
0.08
TYP
SEE DETAIL A
0.25
GAUGE PLANE
0°- 8°
0.1
0.0
0.63
0.33
DETAIL A
TYP
4224643/B 07/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
5. Reference JEDEC Registration MO-345, Variation AB
www.ti.com
EXAMPLE BOARD LAYOUT
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
SYMM
14X (1.05)
1
14
14X (0.3)
SYMM
12X (0.5)
8
7
(R0.05) TYP
(3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224643/B 07/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
SYMM
14X (1.05)
1
14
14X (0.3)
SYMM
12X (0.5)
8
7
(R0.05) TYP
(3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 20X
4224643/B 07/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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