TLV9051IDBVR [TI]
适用于成本优化型应用的单路、5.5V、5MHz、15V/μs 压摆率、RRIO 运算放大器 | DBV | 5 | -40 to 125;
| 型号： | TLV9051IDBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于成本优化型应用的单路、5.5V、5MHz、15V/μs 压摆率、RRIO 运算放大器 | DBV | 5 | -40 to 125 放大器 运算放大器 |
| 文件： | 总82页 (文件大小：6021K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV9051, TLV9052, TLV9054
ZHCSI62I –AUGUST 2018 –REVISED NOVEMBER 2022
TLV9051/TLV9052/TLV9054 5MHz 15V/µs 高压摆率RRIO 运算放大器
器件信息(1)
1 特性
封装尺寸（标称值）
器件型号
封装
SOT-23 (5)
• 高压摆率：15V/µs
1.60mm × 2.90mm
1.25mm × 2.00mm
1.65mm × 1.20mm
0.80mm × 0.80mm
1.60mm × 2.90mm
3.91mm × 4.90mm
3.00mm × 4.40mm
3.00mm × 3.00mm
1.60mm × 2.90mm
2.00mm × 2.00mm
3.00mm × 3.00mm
1.50mm x 2.00mm
8.65mm × 3.91mm
4.40mm × 5.00mm
2.00mm × 2.00mm
3.00mm × 3.00mm
3.00mm × 3.00mm
• 低静态电流：330µA
• 轨至轨输入和输出
• 低输入失调电压：±0.33 mV
• 单位增益带宽：5MHz
• 低宽带噪声：15 nV/√Hz
• 低输入偏置电流：2pA
• 单位增益稳定
• 内置RFI 和EMI 滤波器
• 适用于低成本应用的可扩展CMOS 运算放大器系列
• 可在电源电压低至1.8V 的情况下运行
• 工作温度范围：–40°C 至125°C
SC70 (5)
TLV9051
SOT553 (5)(2)
X2SON (5)
SOT-23 (6)
SOIC (8)
TLV9051S
TLV9052
TSSOP (8)
VSSOP (8)
SOT-23 (8)
WSON (8)
VSSOP (10)
X2QFN (10)
SOIC (14)
TLV9052S
2 应用
• HVAC：暖通空调
• 光电二极管放大器
• 用于实现直流电机控制的电流分流监控
• 白色家电（冰箱、洗衣机等）
• 传感器信号调节
TSSOP (14)
X2QFN (14)
WQFN (16)
WQFN (16)
TLV9054
TLV9054S
• 有源滤波器
• 低侧电流检测
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) 封装仅为预发布版。
3 说明
RG
RF
TLV9051、TLV9052 和 TLV9054 器件分别为单通道、
双通道和四通道的运算放大器。这些器件旨在 1.8V 至
6.0V 的低电压下运行。它们可以在非常高的压摆率下
实现轨到轨输入和输出。这些器件非常适合需要低工作
电压、高压摆率和低静态电流的成本受限应用。
TLV905x 系列的容性负载驱动器具有 150pF 的电容，
而电阻式开环输出阻抗使其能够在更高的容性负载下更
轻松地实现稳定。
R1
VOUT
VIN
C1
1
2pR1C1
f
=
-3 dB
VOUT
VIN
RF
1
1 + sR1C1
=
1 +
(
(
RG
单极低通滤波器
TLV905xS 器件具有关断模式，允许放大器切换至典型
电流消耗低于1µA 的待机模式。
17
16.5
16
TLV905x 系列易于使用，因为它具有稳定的单位增
益，集成了 RFI 和 EMI 滤波器，且不会在过驱动情况
下出现相位反转。
15.5
15
14.5
14
13.5
13
50
100
150
200
Capacitive Load (pF)
250
300
350
D019
压摆率与负载电容间的关系
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS942
TLV9051, TLV9052, TLV9054
ZHCSI62I –AUGUST 2018 –REVISED NOVEMBER 2022
www.ti.com.cn
Table of Contents
8.2 Functional Block Diagram.........................................22
8.3 Feature Description...................................................23
8.4 Device Functional Modes..........................................26
9 Application and Implementation..................................27
9.1 Application Information............................................. 27
9.2 Typical Low-Side Current Sense Application............27
9.3 Power Supply Recommendations.............................29
9.4 Layout....................................................................... 29
10 Device and Documentation Support..........................31
10.1 Documentation Support.......................................... 31
10.2 Related Links.......................................................... 31
10.3 Receiving Notification of Documentation Updates..31
10.4 支持资源..................................................................31
10.5 Trademarks.............................................................31
10.6 Electrostatic Discharge Caution..............................31
10.7 术语表..................................................................... 31
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................4
6 Pin Configuration and Functions...................................5
7 Specifications................................................................ 11
7.1 绝对最大额定值.........................................................11
7.2 ESD Ratings..............................................................11
7.3 Recommended Operating Conditions.......................11
7.4 Thermal Information for Single Channel................... 11
7.5 Thermal Information for Dual Channel......................12
7.6 Thermal Information for Quad Channel.................... 12
7.7 电气特性：VS（总电源电压）= (V+) –(V-) =
1.8V 至5.5V................................................................13
7.8 Typical Characteristics..............................................15
8 Detailed Description......................................................22
8.1 Overview...................................................................22
Information.................................................................... 32
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision H (October 2019) to Revision I (November 2022)
Page
• 将绝对最大额定值中的最大电源电压从6V 更改为7V..................................................................................... 11
• 添加了输入偏置电流和输入失调电流的最大值..................................................................................................13
Changes from Revision G (September 2019) to Revision H (October 2019)
Page
• Added new human-body model and charged-device model ratings for TLV9051 X2SON package to the ESD
Ratings .............................................................................................................................................................11
• Added Packages With an Exposed Thermal Pad section to Feature Description section................................24
Changes from Revision F (June 2019) to Revision G (September 2019)
Page
• 删除了所有TLV9051 封装的预发布标记.............................................................................................................1
• 删除了TLV9052 SOT-23 (8) - DDF 封装的预发布标记.......................................................................................1
• Added link to Shutdown Function section in all of the SHDN pin function rows................................................. 5
• Added EMI Rejection section to Feature Description section...........................................................................23
• Added clarification to the Shutdown Function section...................................................................................... 25
Changes from Revision E (May 2019) to Revision F (June 2019)
Page
• 删除了器件信息中TLV9052S 器件的封装预发布标记....................................................................................... 1
• Deleted package preview notation for TLV9052S devices under Device Comparison Table ............................ 4
• Deleted preview notation for TLV9052S devices in Device Comparison Table ................................................. 4
• Deleted package preview notation for TLV9052S in Pin Configuration and Functions section.......................... 5
• Deleted package preview notation for TLV9052S under Thermal Information for Dual Channel .................... 12
Changes from Revision D (April 2019) to Revision E (May 2019)
Page
• Added DDF (SOT-23) information to Thermal Information for Dual Channel table.......................................... 12
Changes from Revision C (April 2019) to Revision D (April 2019)
Page
• 删除了器件信息中TLV9054/S 器件的预发布标记..............................................................................................1
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• Deleted preview notations for TLV9054 devices in Device Comparison Table ..................................................4
• Deleted preview notations for TLV9054S device in Device Comparison Table ................................................. 4
• Deleted preview notations for TLV9054 packages in Pin Configurations and Functions section....................... 5
• Deleted preview notation for TLV9054S RTE package in Pin Configurations and Functions section................ 5
• Deleted preview notation for TLV9054/S packages in Thermal Information for Quad Channel ...................... 12
Changes from Revision B (March 2019) to Revision C (April 2019)
Page
• Added TLV9051 thermal information for DPW, DBV, and DCK packages........................................................ 11
Changes from Revision A (December 2018) to Revision B (March 2019)
Page
• 向说明部分添加了关断器件说明........................................................................................................................ 1
• 向器件信息中添加了SOT-23 (8) 封装............................................................................................................... 1
• 向器件信息中添加了关断器件............................................................................................................................1
• 向TLV9054 器件信息中添加了X2QFN (RUC) 封装..........................................................................................1
• Added DDF package information to Device Comparison Table .........................................................................4
• Added Shutdown devices (TLV9051S/TLV9052S/TLV9054S) and packages (DGS/RUG/RTE) to Device
Comparison Table ..............................................................................................................................................4
• Added DDF (SOT-23) package...........................................................................................................................5
• Added TLV9051S pinout information to Pin Configurations and Functions section............................................5
• Added TLV9052S pinout information to Pin Configurations and Functions section............................................5
• Added TLV9054S and TLV9054 X2QFN (RUC) pinout information to Pin Configurations and Functions
section................................................................................................................................................................ 5
• Added TLV9051 and TLV9051S thermal information to Thermal Information for Single Channel ...................11
• Added TLV9052S thermal info to Thermal Information for Dual Channel ........................................................12
• Added DDF (SOT-23) package to Thermal Information for Dual Channel ...................................................... 12
• Added TLV9054 and TLV9054S thermal information to Thermal Information for Quad Channel ....................12
• Added Shutdown Function information in Feature Description section............................................................ 25
• Added "S" suffix to Related Links to reflect the addition of Shutdown devices.................................................31
Changes from Revision * (August 2018) to Revision A (December 2018)
Page
• 将器件状态从预告信息更改为量产数据.............................................................................................................1
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5 Device Comparison Table
PACKAGE LEADS
VSSOP TSSOP
NO. OF
CH.
SOT-553
DEVICE
SC70
DCK
SOT-23
DBV
X2SON
DPW
SOIC
D
WSON
DSG
SOT-23
DDF
VSSOP
DGS
X2QFN
RUG
X2QFN
RUC
WQFN
RTE
(1)
DGK
PW
DRL
5
TLV9051
TLV9051S
TLV9052
TLV9052S
TLV9054
TLV9054S
5
5
5
—
—
8
—
—
8
—
—
8
—
—
8
—
—
8
—
—
—
10
—
—
—
10
—
—
—
—
14
—
—
—
—
16
16
1
2
4
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
14
14
—
—
—
—
—
—
—
(1) Package is for preview only.
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6 Pin Configuration and Functions
OUT
Vœ
1
2
3
5
V+
IN+
Vœ
1
2
3
5
V+
IN+
4
INœ
INœ
4
OUT
Not to scale
Not to scale
图6-1. TLV9051 DBV, DRL Packages 5-Pin SOT-23, 图6-2. TLV9051 DCK Package 5-Pin SC70 Top View
SOT-553 Top View
OUT
1
5
V+
3
Vœ
INœ
2
4
IN+
Not to scale
图6-3. TLV9051 DPW Package 5-Pin X2SON Top View
表6-1. Pin Functions: TLV9051
PIN
I/O
DESCRIPTION
SOT-23,
SOT-553
NAME
SC-70
X2SON
4
3
1
2
5
3
1
4
2
5
2
4
1
3
5
I
I
Inverting input
Noninverting input
Output
IN–
IN+
OUT
V–
V+
O
Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
—
—
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+IN
Vœ
1
2
3
6
5
4
V+
SHDN
OUT
œIN
Not to scale
图6-4. TLV9051S DBV Package 6-Pin SOT-23 Top View
表6-2. Pin Functions: TLV9051S
PIN
I/O
DESCRIPTION
NAME
–IN
NO.
4
I
I
Inverting input
Noninverting input
Output
+IN
3
OUT
SHDN
1
O
I
5
Shutdown: low = amp disabled, high = amp enabled. See 节8.3.9 for more information.
Negative (lowest) supply or ground (for single-supply operation).
Positive (highest) supply
2
V–
—
—
V+
6
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OUT1
1
2
3
4
8
7
6
5
V+
OUT1
IN1œ
IN1+
Vœ
1
2
3
4
8
7
6
5
V+
IN1œ
IN1+
Vœ
OUT2
IN2œ
IN2+
OUT2
IN2œ
IN2+
Thermal
Pad
Not to scale
Not to scale
Connect exposed thermal pad to V–. See 节8.3.6 for more
图6-5. TLV9052 D, DGK, PW, DDF Packages 8-Pin
information.
SOIC, VSSOP, TSSOP, SOT-23 Top View
图6-6. TLV9052 DSG Package 8-Pin WSON With
Exposed Thermal Pad Top View
表6-3. Pin Functions: TLV9052
PIN
I/O
DESCRIPTION
NAME
IN1–
NO.
2
I
I
Inverting input, channel 1
IN1+
IN2–
IN2+
OUT1
OUT2
V–
3
Noninverting input, channel 1
Inverting input, channel 2
6
I
5
I
Noninverting input, channel 2
Output, channel 1
1
O
O
7
Output, channel 2
4
Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
—
—
V+
8
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OUT1
IN1œ
1
2
3
4
5
10
9
V+
OUT2
IN2œ
IN2+
SHDN2
Vœ
SHDN1
SHDN2
IN2+
1
2
3
4
9
8
7
6
IN1œ
IN1+
8
Vœ
7
OUT1
SHDN1
6
V+
Not to scale
图6-7. TLV9052S DGS Package 10-Pin VSSOP Top
View
OUT2
Not to scale
图6-8. TLV9052S RUG Package 10-Pin X2QFN Top
View
表6-4. Pin Functions: TLV9052S
PIN
I/O
DESCRIPTION
NAME
IN1–
VSSOP
X2QFN
2
3
8
7
1
9
9
10
5
I
I
Inverting input, channel 1
IN1+
Noninverting input, channel 1
Inverting input, channel 2
Noninverting input, channel 2
Output, channel 1
I
IN2–
IN2+
4
I
OUT1
OUT2
8
O
O
6
Output, channel 2
Shutdown: low = amp disabled, high = amp enabled, channel 1. See 节8.3.9 for
more information.
SHDN1
SHDN2
5
6
2
3
I
I
Shutdown: low = amp disabled, high = amp enabled, channel 2. See 节8.3.9 for
more information.
4
1
7
Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
V–
—
—
V+
10
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OUT1
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT4
IN4œ
IN4+
Vœ
IN1œ
IN1+
V+
IN1œ
IN1+
V+
1
2
3
4
5
12
11
10
9
IN4œ
IN4+
Vœ
IN2+
IN2œ
OUT2
IN3+
IN3œ
OUT3
IN2+
IN2œ
IN3+
IN3œ
8
8
Not to scale
Not to scale
图6-9. TLV9054 D, PW Packages 14-Pin SOIC,
TSSOP Top View
图6-10. TLV9054 RUC Package 14-Pin X2QFN Top
View
IN1+
V+
1
2
3
4
12
11
10
9
IN4+
Vœ
Thermal
Pad
IN2+
IN2œ
IN3+
IN3œ
Not to scale
Connect exposed thermal pad to V–. See 节8.3.6 for more information.
图6-11. TLV9054 RTE Package 16-Pin WQFN With Exposed Thermal Pad Top View
表6-5. Pin Functions: TLV9054
PIN
I/O
DESCRIPTION
SOIC,
TSSOP
NAME
IN1–
WQFN
X2QFN
2
3
16
1
1
2
I
I
I
I
I
I
I
I
Inverting input, channel 1
IN1+
IN2–
IN2+
IN3–
IN3+
IN4–
IN4+
NC
Noninverting input, channel 1
Inverting input, channel 2
Noninverting input, channel 2
Inverting input, channel 3
Noninverting input, channel 3
Inverting input, channel 4
Noninverting input, channel 4
No internal connection
6
4
5
5
3
4
9
9
8
10
13
12
10
13
12
6, 7
15
5
9
12
11
—
1
—
14
6
—
O
O
O
O
OUT1
OUT2
OUT3
OUT4
V–
Output, channel 1
7
Output, channel 2
8
8
7
Output, channel 3
14
14
11
2
13
Output, channel 4
11
4
10
3
Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
—
—
V+
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IN1+
V+
1
2
3
4
12
11
10
9
IN4+
Vœ
Thermal
Pad
IN2+
IN2œ
IN3+
IN3œ
Not to scale
Connect exposed thermal pad to V–. See 节8.3.6 for more information.
图6-12. TLV9054S RTE Package 16-Pin WQFN With Exposed Thermal Pad Top View
表6-6. Pin Functions: TLV9054S
PIN
I/O
DESCRIPTION
NAME
IN1+
NO.
1
I
I
I
I
I
I
I
I
Noninverting input, channel 1
Inverting input, channel 1
Noninverting input, channel 2
Inverting input, channel 2
Noninverting input, channel 3
Inverting input, channel 3
Noninverting input, channel 4
Inverting input, channel 4
16
3
IN1–
IN2+
4
IN2–
IN3+
10
9
IN3–
IN4+
12
13
IN4–
Shutdown: low = amp disabled, high = amp enabled, channel 1 and 2. See 节8.3.9 for more
information.
SHDN12
SHDN34
6
7
I
I
Shutdown: low = amp disabled, high = amp enabled, channel 3 and 4. See 节8.3.9 for more
information.
OUT1
OUT2
OUT3
OUT4
V–
15
5
O
O
O
O
Output, channel 1
Output, channel 2
8
Output, channel 3
14
11
2
Output, channel 4
Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
—
—
V+
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7 Specifications
7.1 绝对最大额定值
在自然通风温度下测得（除非另有说明）(1)
最小值
最大值
单位
7
V
电源电压
(V+) + 0.5
(V+) –(V–) + 0.2
10
(V–) –0.5
共模
电压(2)
V
信号输入引脚
输出短路(3)
温度
差分
电流(2)
-10
mA
mA
连续
-40
125
150
150
额定温度，TA
结温，TJ
°C
-65
贮存温度，Tstg
(1) 应力超出绝对最大额定值下所列的值可能会对器件造成永久损坏。这些仅为压力额定值，并不表示器件在这些条件下以及在建议运行条
件以外的任何其他条件下能够正常运行。长时间处于绝对最大额定条件下可能会影响器件的可靠性。
(2) 输入引脚被二极管钳制至电源轨。对于摆幅能超过电源轨0.5V 的输入信号，应将其电流限制在10mA 或者更低。
(3) 接地短路，每个封装对应一个放大器。
7.2 ESD Ratings
VALUE
UNIT
TLV9051 X2SON PACKAGE
V(ESD) Electrostatic discharge
ALL OTHER PACKAGES
V(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±3000
±1500
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
±1500
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
1.8
MAX
6.0
UNIT
V
VS
Supply voltage, VS = (V+) –(V–)
Input pin voltage
VIN
(V+) + 0.1
125
V
(V–) –0.1
–40
Specified temperature
°C
7.4 Thermal Information for Single Channel
TLV9051, TLV9051S
DBV (SOT-23)
DCK
(SC70)
DRL (SOT553)
THERMAL METRIC(1)
DPW (X2SON)
UNIT
(2)
5 PINS
5 PINS
6 PINS
5 PINS
5 PINS
Junction-to-ambient thermal
resistance
RθJA
470.0
228.1
210.8
231.2
TBD
°C/W
Rθ
Junction-to-case(top) thermal
resistance
211.9
334.8
29.8
152.1
97.7
74.1
152.1
92.3
76.2
144.4
78.6
51.3
TBD
TBD
TBD
°C/W
°C/W
°C/W
JC(top)
RθJB
Junction-to-board thermal resistance
Junction-to-top characterization
parameter
ψJT
Junction-to-board characterization
parameter
333.2
97.3
92.1
78.3
TBD
°C/W
ψJB
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TLV9051, TLV9051S
DBV (SOT-23)
DCK
(SC70)
DRL (SOT553)
THERMAL METRIC(1)
DPW (X2SON)
5 PINS
UNIT
(2)
5 PINS
N/A
6 PINS
5 PINS
5 PINS
Rθ
Junction-to-case(bottom) thermal
resistance
N/A
N/A
N/A
TBD
°C/W
JC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) This package option is for preview only.
7.5 Thermal Information for Dual Channel
TLV9052, TLV9052S
D
DGK
(VSSOP)
DSG
PW
DDF
(SOT-23)
DGS
(VSSOP)
RUG
(X2QFN)
THERMAL METRIC(1)
UNIT
(SOIC)
(WSON) (TSSOP)
8 PINS
8 PINS
8 PINS
8 PINS
8 PINS
10 PINS
10 PINS
Junction-to-ambient
thermal resistance
RθJA
155.4
208.8
102.3
205.1
184.4
170.4
197.2
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Rθ
Junction-to-case(top)
thermal resistance
95.5
98.9
41.9
98.1
N/A
93.3
130.7
26.1
120.0
68.2
15.1
68.2
43.6
93.7
135.7
25.0
112.8
99.9
18.7
99.3
N/A
84.9
113.5
16.4
112.3
N/A
93.3
123.8
3.7
JC(top)
Junction-to-board thermal
resistance
RθJB
ψJT
Junction-to-top
characterization parameter
Junction-to-board
characterization parameter
128.9
N/A
134.0
N/A
120.2
N/A
ψJB
Rθ
Junction-to-case(bottom)
thermal resistance
JC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Thermal Information for Quad Channel
TLV9054, TLV9054S
THERMAL METRIC(1)
D (SOIC) PW (TSSOP)
RTE (WQFN)
RUC (X2SQFN) UNIT
14 PINS
14 PINS
14 PINS
14 PINS
16 PINS
Junction-to-ambient thermal
resistance
RθJA
115.0
147.2
65.5
65.6
209.4
°C/W
Rθ
Junction-to-case(top) thermal
resistance
71.1
71.0
29.7
67.2
91.6
16.6
70.6
40.5
5.8
70.6
40.5
5.8
68.8
153.3
3.0
°C/W
°C/W
°C/W
JC(top)
RθJB
Junction-to-board thermal resistance
Junction-to-top characterization
parameter
ψJT
Junction-to-board characterization
parameter
70.6
N/A
90.7
N/A
40.5
24.5
40.5
24.5
152.8
N/A
°C/W
°C/W
ψJB
Rθ
Junction-to-case(bottom) thermal
resistance
JC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.7 电气特性：VS（总电源电压）= (V+) –(V-) = 1.8V 至5.5V
TA = 25°C，RL = 10kΩ（连接至VS/2），VCM = VS/2，VOUT = VS/2（除非另有说明）；
参数
测试条件
最小值
典型值
最大值
单位
失调电压
VS = 5V
±0.33
±1.6
±2
VOS
mV
输入失调电压
VS = 5V，TA = –40°C 至+125°C
VS = 5V，TA = –40°C 至+125°C
VS = 1.8V –5.5V，VCM = (V–)
在直流
dVOS/dT
PSRR
±0.5
±13
115
µV/°C
µV/V
dB
漂移
±80
电源抑制比
通道分离，直流
输入电压范围
VCM
(V+)+0.1
V
VS = 1.8V 至5.5V
(V–) –0.1
共模电压
VS = 5.5 V，(V–) –0.1V < VCM < (V+) –1.4V，
TA = –40°C 至+125°C
80
96
79
88
72
VS = 5.5V，VCM = -0.1V 至5.6V，
TA = -40°C 至+125°C
62
CMRR
dB
共模抑制比
VS = 1.8V，(V–) –0.1V < VCM < (V+) –1.4V，
TA = –40°C 至+125°C
VS = 1.8V，VCM = -0.1V 至1.9V，
TA = -40°C 至+125°C
输入偏置电流
±2
±1
±18(2)
±525(2)
±15(2)
pA
pA
pA
pA
IB
输入偏置电流
输入失调电流
TA=-40°C 至+125°C
TA=-40°C 至+125°C
IOS
±440(2)
噪声
En
6
15
20
18
µVPP
输入电压噪声（峰峰值）
输入电压噪声密度
VS = 5V，f = 0.1Hz 至10Hz
VS = 5V，f = 10kHz
VS = 5V，f = 1kHz
f = 1kHz
nV/√Hz
nV/√Hz
fA/√Hz
en
in
输入电流噪声密度
输入电容
CID
2
4
pF
pF
差分
共模
CIC
开环增益
VS = 1.8V，(V–) + 0.04V < VO < (V+) –0.04V，
RL = 10kΩ
106
128
108
130
VS = 5.5V，(V–) + 0.05V < VO < (V+) –0.05V，
RL = 10kΩ
104
AOL
dB
开环电压增益
VS = 1.8V，(V–) + 0.06V < VO < (V+) –0.06V，
RL = 2kΩ
VS = 5.5V，(V–) + 0.15V < VO < (V+) –0.15V，
RL = 2kΩ
频率响应
GBP
VS = 5.5V，G = +1
5
60
15
MHz
增益带宽积
相位裕度
压摆率
VS = 5.5V，G = +1
φm
度
SR
VS = 5.5V，G = +1，CL = 130pF
V/µs
精度达到0.1%，VS = 5.5V，2V 阶跃，G = +1，CL
=
0.75
1
100pF
tS
µs
µs
趋稳时间
精度达到0.01%，VS = 5.5V，2V 阶跃，G = +1，CL
100pF
=
tOR
0.3
VS = 5.5V，VIN × 增益> VS
过载恢复时间
总谐波失真+ 噪声(1)
THD + N
输出
VS = 5.5V，VCM = 2.5V，VO = 1VRMS，G = +1，f = 1kHz
0.0006%
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7.7 电气特性：VS（总电源电压）= (V+) –(V-) = 1.8V 至5.5V (continued)
TA = 25°C，RL = 10kΩ（连接至VS/2），VCM = VS/2，VOUT = VS/2（除非另有说明）；
参数
测试条件
最小值
典型值
最大值
单位
16
VS = 5.5V，RL = 10kΩ，
VS = 5.5V，RL = 2kΩ，
VS = 5V
相对于电源轨的电压输出摆
幅
VO
mV
40
ISC
±50
250
mA
短路电流
ZO
VS = 5V，f = 5 MHz
开环输出阻抗
Ω
电源
VS = 5.5V，IO = 0mA，
330
450
475
IQ
µA
每个放大器的静态电流
VS = 5.5V，IO = 0mA，TA = -40°C 至+125°C
(1) 三阶滤波器；–3dB 时的带宽= 80kHz。
(2) 根据设计和特征确定；未经生产测试。
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7.8 Typical Characteristics
at TA = 25°C, VS = 5.5 V, RL = 10 kΩconnected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
21
18
15
12
9
40
30
20
10
0
6
3
0
-1200 -900 -600 -300
0
300
600
900 1200
DC15
0
0.4
0.8
1.2
1.6
2
DC16
Offset Voltage (µV)
Offset Voltage Drift (µV/C)
VS = 5.5 V
VS = 5.5 V, TA = –40°C to 125°C
图7-1. Offset Voltage Production Distribution
图7-2. Offset Voltage Drift Distribution
600
500
400
300
200
100
0
450
350
250
150
50
-100
-200
-300
-400
-500
-600
-50
-150
-250
-350
-3
-2
-1
0
1
Common-Mode Voltage (V)
2
3
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
DC21
DC08
图7-4. Offset Voltage vs Common-Mode Voltage
图7-3. Offset Voltage vs Temperature
500
400
300
200
100
0
120
IB-
IB+
IOS
110
100
90
80
70
60
50
40
30
20
10
0
-100
-200
-300
-400
-500
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
-50
-25
0
25 50
Temperature (°C)
75
100
125
DC23
DC02
图7-5. Offset Voltage vs Power Supply
图7-6. Input Bias Current vs Temperature
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7.8 Typical Characteristics
at TA = 25°C, VS = 5.5 V, RL = 10 kΩconnected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
18
IB-
IB+
IOS
16
14
12
10
8
6
4
2
0
-3
Time (1s/div)
-2
-1
0
1
Input Common-Mode Voltage (V)
2
3
D008
DC03
图7-8. 0.1-Hz to 10-Hz Input Voltage Noise
图7-7. Input Bias Current and Offset Current vs Common-Mode
Voltage
120
100
80
60
40
20
0
140
120
100
80
PSRR+
PSRR-
CMRR
60
40
20
0
100
1k
10k 100k
Frequency (Hz)
1M
10
100
1k
Frequency (Hz)
10k
100k
D018
D024
图7-10. CMRR and PSRR vs Frequency (Referred to Input)
图7-9. Input Voltage Noise Spectral Density vs Frequency
220
200
20
19
18
17
16
15
14
13
12
11
10
180
VS = 5.5 V, VCM = -0.1 V to (V+) - 1.4 V
VS = 5.5 V, VCM = -0.1 V to 5.6 V
VS = 1.8 V, VCM = -0.1 V to (V+) - 1.4 V
VS = 1.8 V, VCM = -0.1 V to 5.6 V
160
140
120
100
80
60
40
20
0
-50
-25
0
25 50
Temperature (°C)
75
100
125
-50
-25
0
25 50
Temperature (°C)
75
100
125
DC17
DC18
图7-11. CMRR vs Temperature
VS = 1.8 V to 5.5 V
图7-12. PSRR vs Temperature
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7.8 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩconnected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
100
80
60
40
20
0
120
100
80
60
40
20
0
135
130
125
120
115
110
105
100
95
VS = 1.8V, RL = 2kW
VS = 5.5V, RL = 2kW
VS = 1.8V, RL = 10kW
VS = 5.5V, RL = 10kW
Gain
Phase
-20
100
1k
10k 100k
Frequency (Hz)
1M
10M
D004
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
图7-13. Open Loop Voltage Gain and Phase vs Frequency
DC01
图7-14. Open Loop Voltage Gain vs Temperature
180
160
140
120
100
80
70
G = 1
G = -1
G = 10
G = 100
G = 1000
60
50
40
30
20
10
0
60
40
-10
-20
-30
20
0
-0.5
0.5
1.5
2.5 3.5
Output Voltage (V)
4.5
5.5
1k
10k
100k
Frequency (Hz)
1M
10M
DC26
D005
图7-15. Open Loop Voltage Gain vs Output Voltage
图7-16. Closed Loop Voltage Gain vs Frequency
70
VOUT
VIN
60
50
40
30
20
10
0
Time (100 ms/div)
0
50
100
150 200
Capacitive Load (pF)
250
300
350
D013
D017
图7-18. No Phase Reversal
图7-17. Phase Margin vs Capacitive Load
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7.8 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩconnected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
60
50
40
30
20
10
0
60
50
40
30
20
10
Overshoot(+)
Overshoot(-)
Overshoot(+)
Overshoot(-)
0
50
100 150 200 250 300 350 400 450
Capacitive Load (pF)
0
50
100 150 200 250 300 350 400 450
Capacitive Load (pF)
D016
D015
G = +1 V/V
G = –1 V/V
VOUT step = 100 mVp-p
VOUT step = 100 mVp-p
图7-19. Small-Signal Overshoot vs Load Capacitance
图7-20. Small-Signal Overshoot vs Load Capacitance
17
16.5
16
Output
Input
15.5
15
14.5
14
13.5
13
50
100
150
200
Capacitive Load (pF)
250
300
350
Time (2 us/div)
D019
D014
图7-21. Slew Rate vs Capacitive Load
G = –10 V/V
图7-22. Overload Recovery
VOUT
VIN
VOUT
VIN
Time (1 ms/div)
Time (1 ms)
D021
D020
G = +1 V/V
VOUT step = 10
mVp-p
G = –1 V/V
VOUT step = 10
mVp-p
图7-23. Small-Signal Step Response
图7-24. Small-Signal Step Response
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7.8 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩconnected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
VOUT
VIN
VOUT
VIN
Time (1 ms/div)
Time (1 ms/div)
D012
D011
G = +1 V/V
G = –1 V/V
VOUT step = 4 Vp-p
VOUT step = 4 Vp-p
图7-25. Large-Signal Step Response
图7-26. Large-Signal Step Response
20
10
20
10
0
0
0.1% Settling = ê 2 mV
0.1% Settling = ê 2 mV
-10
-20
-30
-10
-20
-30
0.2
0.4
0.6
0.8
Time (µs)
1
1.2
1.4
0.2
0.4
0.6
0.8
Time (µs)
1
1.2
1.4
D010
D009
CL = 100 pF
G = +1 V/V
CL = 100 pF
G = +1 V/V
图7-27. Positive Large-Signal Settling Time
图7-28. Negative Large-Signal Settling Time
-65
-10
RL = 10 kW
RL = 2 kW
RL = 600 W
G = +1, RL = 10 kW
G = +1, RL = 2 kW
G = +1, RL = 600 W
-30
-50
-75
-85
-70
-95
-90
-105
-110
100
1k
Frequency (Hz)
10k
1m
10m 100m
Output Voltage Amplitude (VRMS)
1
D023
D022
VOUT = 0.5 VRMS
G = +1
VCM = 2.5 V
f = 1 kHz
G = +1
VCM = 2.5 V
BW = 80 kHz
BW = 80 kHz
图7-29. THD + N vs Frequency
图7-30. THD + N vs Amplitude
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7.8 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩconnected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
3
2.5
2
6
5
4
3
2
1
0
1.5
1
125èC
125èC
25èC
-40èC
-40èC
85èC
85èC
0.5
0
-0.5
-1
25èC
-1.5
-2
VS = 5.5 V
VS = 1.8 V
-2.5
-3
0
10
20
30
Output Current (mA)
40
50
60
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M 100M
DC07
DC25
图7-31. Output Voltage Swing vs Output Current
图7-32. Maximum Output Voltage vs Frequency and Supply
Voltage
100
330
325
320
315
310
305
300
Sinking
Sourcing
80
60
40
20
0
-20
-40
-60
-80
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
1.8
2.3
2.8
3.3
3.8
Supply Voltage (V)
4.3
4.8
5.3
DC06
DC05
图7-33. Short-Circuit Current vs Temperature
图7-34. Quiescent Current vs Supply Voltage
330
325
320
315
310
305
300
500
400
VS = 1.8V
VS = 5.5V
300
200
IOUT = 0 mA
IOUT = 5 mA
IOUT = -5 mA
100
70
50
40
30
20
-40
-20
0
20
40
60
Temperature (°C)
80
100
120
10k
100k
Frequency (Hz)
1M
DC04
D025
图7-35. Quiescent Current vs Temperature
图7-36. Open-Loop Output Impedance vs Frequency
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7.8 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩconnected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
140
120
100
80
-70
-80
-90
-100
-110
-120
-130
60
40
20
0
10M
100
1k
10k 100k
Frequency (Hz)
1M
100M
Frequency (Hz)
1G
D006
D007
PRF = –10 dBm
PRF = –10 dBm
图7-38. Channel Separation vs Frequency
图7-37. Electromagnetic Interference Rejection Ratio Referred
to Noninverting Input (EMIRR+) vs Frequency
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8 Detailed Description
8.1 Overview
The TLV905x devices are a 5-MHz family of low-power, rail-to-rail input and output op amps. These devices
operate from 1.8 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose
applications. The input common-mode voltage range includes both rails and allows the TLV905x family to be
used in virtually any single-supply application. The unique combination of a high slew rate and low quiescent
current makes this family a potential choice for battery-powered motor-drive applications. Rail-to-rail input and
output swing significantly increase dynamic range, especially in low-supply applications.
8.2 Functional Block Diagram
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8.3 Feature Description
8.3.1 Operating Voltage
The TLV905x family of op amps is specified for operation from 1.8 V to 6.0 V. In addition, many specifications
apply from –40°C to 125°C. Parameters that vary significantly with operating voltages or temperature are
illustrated in the 节7.8.
8.3.2 Rail-to-Rail Input
The input common-mode voltage range of the TLV905x family extends 100 mV beyond the supply rails for the
full supply voltage range of 1.8 V to 6.0 V. This performance is achieved with a complementary input stage: an
N-channel input differential pair in parallel with a P-channel differential pair, as shown in the 节 8.2. The N-
channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 200 mV above the
positive supply, whereas the P-channel pair is active for inputs from 200 mV below the negative supply to
approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in which
both pairs are on. This 200-mV transition region can vary up to 200 mV with process variation. Thus, the
transition region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to
(V+) – 1 V to (V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset
drift, and THD can degrade compared to device operation outside this region.
8.3.3 Rail-to-Rail Output
Designed as low-power, low-voltage operational amplifiers, the TLV905x family delivers a robust output drive
capability. A class AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads of 10 kΩ, the output swings to within 16 mV of either supply rail, regardless of the
applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the
rails.
8.3.4 EMI Rejection
The TLV905x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the TLV905x benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. 图 8-1
shows the results of this testing on the TLV905x. 表 8-1 shows the EMIRR IN+ values for the TLV905x at
particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational
Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op
amps and is available for download from www.ti.com.
140
120
100
80
60
40
20
0
10M
100M
Frequency (Hz)
1G
D007
图8-1. EMIRR Testing
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表8-1. TLV905x EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
400 MHz
41.8 dB
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
5 GHz
53.1 dB
71.8 dB
70.0 dB
81.2 dB
92.5 dB
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
8.3.5 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, because of the high input voltage or high gain. After the device
enters the saturation region, the output devices require time to return to the linear operating state. After the
output devices return to their linear operating state, the device begins to slew at the specified slew rate.
Therefore, the propagation delay (in case of an overload condition) is the sum of the overload recovery time and
the slew time. The overload recovery time for the TLV905x family is approximately 300 ns.
8.3.6 Packages With an Exposed Thermal Pad
The TLV905x family is available in packages such as the WSON-8 (DSG) and WQFN-16 (RTE) which feature an
exposed thermal pad. Inside the package, the die is attached to this thermal pad using an electrically conductive
compound. For this reason, when using a package with an exposed thermal pad, the thermal pad must either be
connected to V– or left floating. Attaching the thermal pad to a potential other then V– is not allowed, and the
performance of the device is not verified when doing so.
8.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. 图 8-2 shows the ESD circuits contained in the TLV905x devices. The ESD protection circuitry involves
several current-steering diodes connected from the input and output pins and routed back to the internal power
supply lines, where they meet at an absorption device internal to the operational amplifier. This protection
circuitry is intended to remain inactive during normal circuit operation.
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V+
Power Supply
ESD Cell
+IN
+
œ
OUT
œ IN
Vœ
图8-2. Equivalent Internal ESD Circuitry
8.3.8 Input Protection
The TLV905x family incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to 10
mA, as shown in the 节7.1. 图8-3 shows how a series input resistor can be added to the driven input to limit the
input current. The added resistor contributes thermal noise at the amplifier input and the value must be kept to a
minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA maximum
VOUT
Device
VIN
5 kW
图8-3. Input Current Protection
8.3.9 Shutdown Function
The TLV905xS devices feature SHDN pins that disable the op amp, placing the device into a low-power standby
mode. In this mode, the op amp typically consumes less than 1 µA. The SHDN pins are active low, meaning that
shutdown mode is enabled when the input to the SHDN pin is a valid logic low.
The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown
feature lies around 800 mV (typical) and does not change with respect to the supply voltage. Hysteresis has
been included in the switching threshold to ensure smooth switching characteristics. To ensure shutdown
behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage
between V– and V– + 0.4 V. A valid logic high is defined as a voltage between V– + 1.2 V and V+. The
shutdown pin circuitry includes a pull-up resistor, which will inherently pull the voltage of the pin to the positive
supply rail if not driven. Thus, to enable the amplifier, the SHDN pins must either be left floating or driven to a
valid logic high. To disable the amplifier, the SHDN pins must be driven to a valid logic low .While TI highly
recommends that the shutdown pin be connected to a valid high or a low voltage or driven, TI has included a
pull-up resistor connected to VCC. The maximum voltage allowed at the SHDN pins is (V+) + 0.5 V. Exceeding
this voltage level will damage the device.
The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled and quad
op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature may be
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used to greatly reduce the average current and extend battery life. The enable time is 35 µs for full shutdown of
all channels; disable time is 6 µs. When disabled, the output assumes a high-impedance state. This architecture
allows the TLV905xS to be operated as a gated amplifier (or to have the device output multiplexed onto a
common analog output bus). Shutdown time (tOFF) depends on loading conditions and increases as load
resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to
midsupply (VS / 2) is required. If using the TLV905xS without a load, the resulting turnoff time is significantly
increased.
8.4 Device Functional Modes
The TLV905x family is operational when the power-supply voltage is between 1.8 V (±0.9 V) and 6.0 V (±3.0 V).
The TLV905xS devices feature a shutdown mode and are shutdown when a valid logic low is applied to the
shutdown pin.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TLV905x family features 5-MHz bandwidth and very high slew rate of 15 V/µs with only 330 µA of supply
current per channel, providing excellent AC performance at very low-power consumption. DC applications are
well served with a very low input noise voltage of 15 nV/√ Hz at 10 kHz, low input bias current, and a typical
input offset voltage of 0.33 mV.
9.2 Typical Low-Side Current Sense Application
图9-1 shows the TLV905x configured in a low-side current sensing application.
VBUS
ILOAD
ZLOAD
5 V
+
TLV905x
VOUT
Þ
+
RSHUNT
VSHUNT
RF
0.1 Ω
165 kΩ
Þ
RG
3.4 kΩ
图9-1. TLV905x in a Low-Side, Current-Sensing Application
9.2.1 Design Requirements
The design requirements for this design are:
• Load current: 0 A to 1 A
• Output voltage: 4.95 V
• Maximum shunt voltage: 100 mV
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9.2.2 Detailed Design Procedure
The transfer function of the circuit in 图9-1 is given in 方程式1.
VOUT = ILOAD × RSHUNT × Gain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using 方程式2.
V
SHUNT_MAX
100 mV
1 A
R
=
=
= 100 mΩ
(2)
SHUNT
I
LOAD_MAX
Using 方程式 2, RSHUNT equals 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is amplified by the
TLV905x device to produce an output voltage of approximately 0 V to 4.95 V. 方程式 3 calculates the gain
required for the TLV905x device to produce the required output voltage.
V
− V
− V
OUT_MAX
OUT
MIN
Gain =
(3)
V
IN_MAX
IN_MIN
Using 方程式 3, the required gain equals 49.5 V/V, which is set with the RF and RG resistors. 方程式 4 sizes the
RF and RG, resistors to set the gain of the TLV905x device to 49.5 V/V.
R
F
Gain = 1 +
(4)
R
G
Selecting RF to equal 165 kΩ and RG to equal 3.4 kΩ provides a combination that equals approximately 49.5
V/V. 图9-2 shows the measured transfer function of the circuit shown in 图9-1.
9.2.3 Application Curve
5
4
3
2
1
0
0
0.2
0.4
0.6
0.8
1
ILOAD (A)
C219
图9-2. Low-Side, Current-Sense Transfer Function
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9.3 Power Supply Recommendations
The TLV905x family is specified for operation from 1.8 V to 6.0 V (±0.9 V to ±3.0 V); many specifications apply
from –40°C to 125°C. The 节 7.8 section presents parameters that can exhibit significant variance with regard
to operating voltage or temperature.
CAUTION
Supply voltages larger than 7 V can permanently damage the device; see the 节7.1 table.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more-detailed information on bypass capacitor placement, see the 节 9.4.2
section.
9.4 Layout
9.4.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care
to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more
detailed information, see Circuit Board Layout Techniques.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed
to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in 图9-4, keeping RF and RG
close to the inverting input minimizes parasitic capacitance on the inverting input.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended
to remove moisture introduced into the device packaging during the cleaning process. A low-temperature,
post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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9.4.2 Layout Example
VIN 1
VIN 2
+
+
VOUT 1
VOUT 2
RG
RG
RF
RF
图9-3. Schematic Representation for 图9-4
Place components
close to device and to
each other to reduce
parasitic errors.
OUT 1
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
VS+
GND
OUT1
V+
RF
RG
OUT 2
GND
IN1œ
IN1+
Vœ
OUT2
IN2œ
IN2+
RF
RG
VIN 1
GND
VIN 2
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
GND
ceramic bypass
capacitor . Place as
close to the device
as possible .
VSœ
Ground (GND) plane on another layer
as possible .
图9-4. Layout Example
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10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
Texas Instruments, TLVx313 Low-Power, Rail-to-Rail In/Out, 500-µV Typical Offset, 1-MHz Operational Amplifier
for Cost-Sensitive Systems
Texas Instruments, TLVx314 3-MHz, Low-Power, Internal EMI Filter, RRIO, Operational Amplifier
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers
Texas Instruments, QFN/SON PCB Attachment
Texas Instruments, Quad Flatpack No-Lead Logic Packages
Texas Instruments, Circuit Board Layout Techniques
Texas Instruments, Single-Ended Input to Differential Output Conversion Circuit Reference Design
10.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
表10-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
TLV9051/S
TLV9052/S
TLV9054/S
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
10.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
所有商标均为其各自所有者的财产。
10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV9051IDBVR
TLV9051IDCKR
TLV9051IDPWR
TLV9051SIDBVR
TLV9052IDDFR
TLV9052IDGKR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SC70
DBV
DCK
DPW
DBV
DDF
DGK
5
5
5
6
8
8
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
T51D
T51
Samples
Samples
Samples
Samples
Samples
Samples
SN
X2SON
SOT-23
NIPDAUAG
NIPDAU
NIPDAU
FH
T51S
T052
ACTIVE SOT-23-THIN
ACTIVE
VSSOP
NIPDAU | SN
| NIPDAUAG
1PWX
TLV9052IDR
TLV9052IDSGR
TLV9052IPWR
TLV9052SIDGSR
TLV9052SIRUGR
TLV9054IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
WSON
TSSOP
VSSOP
X2QFN
SOIC
D
8
2500 RoHS & Green
3000 RoHS & Green
2000 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
2000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAUAG
NIPDAUAG
NIPDAU
SN
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TL9052
9052
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
DSG
PW
8
8
TL9052
T052
DGS
RUG
D
10
10
14
14
16
14
16
FPF
TLV9054D
T9054PW
T54RT
1FF
TLV9054IPWR
TLV9054IRTER
TLV9054IRUCR
TLV9054SIRTER
TSSOP
WQFN
QFN
PW
RTE
RUC
RTE
NIPDAU
NIPDAU
NIPDAU
WQFN
T9054S
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jul-2023
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV9051IDBVR
TLV9051IDCKR
TLV9051IDPWR
TLV9051SIDBVR
TLV9052IDDFR
SOT-23
SC70
DBV
DCK
DPW
DBV
DDF
5
5
5
6
8
3000
3000
3000
3000
3000
180.0
178.0
178.0
180.0
180.0
8.4
9.0
8.4
8.4
8.4
3.2
2.4
3.2
2.5
1.4
1.2
0.5
1.4
1.4
4.0
4.0
2.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q2
Q3
Q3
X2SON
SOT-23
0.91
3.2
0.91
3.2
SOT-23-
THIN
3.2
3.2
TLV9052IDGKR
TLV9052IDGKR
TLV9052IDSGR
TLV9052IPWR
TLV9052SIDGSR
TLV9052SIRUGR
TLV9054IDR
VSSOP
VSSOP
WSON
TSSOP
VSSOP
X2QFN
SOIC
DGK
DGK
DSG
PW
8
8
2500
2500
3000
2000
2500
3000
2500
2000
3000
3000
330.0
330.0
180.0
330.0
330.0
178.0
330.0
330.0
330.0
180.0
12.4
12.4
8.4
5.3
5.3
2.3
7.0
5.3
1.75
6.5
6.9
3.3
2.16
3.4
3.4
2.3
3.6
3.4
2.25
9.0
5.6
3.3
2.16
1.4
1.4
1.15
1.6
1.4
0.56
2.1
1.6
1.1
0.5
8.0
8.0
4.0
8.0
8.0
4.0
8.0
8.0
8.0
4.0
12.0
12.0
8.0
Q1
Q1
Q2
Q1
Q1
Q1
Q1
Q1
Q2
Q2
8
8
12.4
12.4
8.4
12.0
12.0
8.0
DGS
RUG
D
10
10
14
14
16
14
16.4
12.4
12.4
9.5
16.0
12.0
12.0
8.0
TLV9054IPWR
TLV9054IRTER
TLV9054IRUCR
TSSOP
WQFN
QFN
PW
RTE
RUC
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV9054SIRTER
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV9051IDBVR
TLV9051IDCKR
TLV9051IDPWR
TLV9051SIDBVR
TLV9052IDDFR
TLV9052IDGKR
TLV9052IDGKR
TLV9052IDSGR
TLV9052IPWR
TLV9052SIDGSR
TLV9052SIRUGR
TLV9054IDR
SOT-23
SC70
DBV
DCK
DPW
DBV
DDF
DGK
DGK
DSG
PW
5
5
3000
3000
3000
3000
3000
2500
2500
3000
2000
2500
3000
2500
2000
3000
3000
3000
210.0
190.0
205.0
210.0
210.0
366.0
366.0
210.0
356.0
366.0
205.0
356.0
366.0
367.0
205.0
367.0
185.0
190.0
200.0
185.0
185.0
364.0
364.0
185.0
356.0
364.0
200.0
356.0
364.0
367.0
200.0
367.0
35.0
30.0
33.0
35.0
35.0
50.0
50.0
35.0
35.0
50.0
33.0
35.0
50.0
35.0
30.0
35.0
X2SON
SOT-23
SOT-23-THIN
VSSOP
VSSOP
WSON
TSSOP
VSSOP
X2QFN
SOIC
5
6
8
8
8
8
8
DGS
RUG
D
10
10
14
14
16
14
16
TLV9054IPWR
TLV9054IRTER
TLV9054IRUCR
TLV9054SIRTER
TSSOP
WQFN
PW
RTE
RUC
RTE
QFN
WQFN
Pack Materials-Page 3
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DPW0005A
X2SON - 0.4 mm max height
S
C
A
L
E
1
2
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
0.85
0.75
A
B
PIN 1 INDEX AREA
0.85
0.75
0.4 MAX
C
SEATING PLANE
NOTE 3
(0.1)
0.05
0.00
(0.324)
4X (0.05)
0.25 0.1
2
1
4
5
NOTE 3
2X
3
2X (0.26)
0.48
0.27
0.17
4X
0.239
0.139
0.1
C A B
C
0.288
0.188
3X
0.05
4223102/D 03/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The size and shape of this feature may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.78)
(
0.1)
SYMM
4X (0.42)
VIA
0.05 MIN
ALL AROUND
TYP
1
5
4X (0.22)
SYMM
4X (0.26)
(0.48)
3
2
4
(R0.05) TYP
SOLDER MASK
OPENING, TYP
4X (0.06)
(
0.25)
(0.21) TYP
EXPOSED METAL
CLEARANCE
METAL UNDER
SOLDER MASK
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:60X
4223102/D 03/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.42)
4X (0.06)
5
1
4X (0.22)
SYMM
(
0.24)
4X (0.26)
(0.21)
(0.48)
TYP
SOLDER MASK
EDGE
3
2
4
(R0.05) TYP
SYMM
(0.78)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 3
92% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:100X
4223102/D 03/2022
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
8
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
SEATING PLANE
TYP
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
5
1
3.1
2.9
NOTE 3
2X
1.95
4
0.30
0.19
8X
4.5
4.3
1.2 MAX
B
0.1
C A
B
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 - 8
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
8X (0.45)
(R0.05)
1
4
TYP
8
SYMM
6X (0.65)
5
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
(R0.05) TYP
8X (0.45)
1
4
8
SYMM
6X (0.65)
5
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
X2QFN - 0.4 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RUC0014A
A
2.1
1.9
B
2.1
1.9
PIN 1 INDEX AREA
0.4 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
(0.15) TYP
2X 0.4
6
7
8X 0.4
5
8
SYMM
1.6
12
1
0.25
0.15
14
13
14X
0.5
PIN 1 ID
SYMM
(45oX0.1)
0.1
C A B
C
14X
0.3
0.05
4220584/A 05/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
X2QFN - 0.4 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RUC0014A
SYMM
14X (0.6)
14X (0.2)
8X (0.4)
SYMM
(1.6) (1.8)
(R0.05)
2X (0.4)
(1.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 23X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220584/A 05/2019
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
X2QFN - 0.4 mm max height
RUC0014A
PLASTIC QUAD FLAT PACK- NO LEAD
SYMM
14X (0.6)
14X (0.2)
8X (0.4)
SYMM
(1.6) (1.8)
(R0.05)
2X (0.4)
(1.8)
SOLDER PASTE EXAMPLE
BASED ON 0.100mm THICK STENCIL
SCALE: 23X
4220584/A 05/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.38
0.22
8X
0.1
C A B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/C 10/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/C 10/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/C 10/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RTE 16
3 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
PACKAGE OUTLINE
RTE0016C
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
17
1.5
1
12
0.30
16X
0.18
PIN 1 ID
(OPTIONAL)
13
16
0.1
C A B
SYMM
0.05
0.5
0.3
16X
4219117/B 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
17
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
8
(R0.05)
ALL PAD CORNERS
(0.58) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219117/B 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4219117/B 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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