TLV9061QDCKRQ1 [TI]
汽车类单通道 40V 10MHz 轨至轨输入和输出低噪声运算放大器 | DCK | 5 | -40 to 125;
| 型号： | TLV9061QDCKRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类单通道 40V 10MHz 轨至轨输入和输出低噪声运算放大器 | DCK | 5 | -40 to 125 放大器 运算放大器 |
| 文件： | 总44页 (文件大小：3227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV9061-Q1, TLV9062-Q1, TLV9064-Q1
SBOS966D – APRIL 2019 – REVISED OCTOBER 2020
TLV906xS-Q1 Automotive 10-MHz, RRIO, CMOS Operational Amplifiers
1 Features
3 Description
•
AEC-Q100 qualified for automotive applications
– Temperature grade 1: –40°C to +125°C, TA
– Device HBM ESD classification level 3A
– Device CDM ESD classification level C6
Rail-to-rail input and output
Low input offset voltage: ±0.3 mV
Unity-gain bandwidth: 10 MHz
Low broadband noise: 10 nV/√ Hz
Low input bias current: 0.5 pA
Low quiescent current: 538 µA
Unity-gain stable
Internal RFI and EMI filter
Wide supply range: 1.8 V to 5.5 V
Easier to stabilize with higher capacitive load due
to resistive open-loop output impedance
Shutdown version: TLV906xS
Functional Safety-Capable
– Documentation available to aid functional safety
system design
The TLV9061-Q1 (single), TLV9062-Q1 (dual) and
TLV9064-Q1 (quad) are single-, dual- and quad-low-
voltage (1.8 V to 5.5 V) operational amplifiers (op
amps) with rail-to-rail input- and output-swing
capabilities. These devices are cost-effective
solutions for automotive applications where low-
•
•
•
•
•
•
•
•
•
•
voltage operation,
a
small footprint, and high
capacitive load drive are required. Although the
capacitive load drive of the TLV906x-Q1 is 100 pF, the
resistive open-loop output impedance makes
stabilizing with higher capacitive loads simpler. These
op amps are designed specifically for low-voltage
operation (1.8
V to 5.5 V) with performance
specifications similar to the OPAx316 and TLVx316
devices, and identical to their non-automotive
qualified TLV906x counterparts.
Device Information
PACKAGE
SOT-23 (6)(2)
•
•
PART NUMBER (1)
BODY SIZE (NOM)
1.60 mm × 2.90 mm
3.91 mm × 4.90 mm
3.00 mm × 4.40 mm
3.00 mm × 3.00 mm
8.65 mm × 3.91 mm
4.40 mm × 5.00 mm
TLV9061S-Q1
SOIC (8)
TLV9062-Q1
TLV9064-Q1
TSSOP (8)(2)
VSSOP (8)
SOIC (14)
TSSOP (14)
2 Applications
•
•
•
•
•
•
•
•
•
Optimized for AEC-Q100 grade 1 applications
Infotainment and cluster
Passive safety
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Body electronics and lighting
HEV/EV inverter and motor control
On-board (OBC) and wireless charger
Powertrain current sensor
Advanced driver assistance systems (ADAS)
Single-supply, low-side, unidirectional current-
sensing circuit
(2) Package is preview only.
60
50
40
30
20
RG
RF
R1
VOUT
VIN
C1
1
2pR1C1
f
=
-3 dB
10
0
Overshoot+
Overshoot-
VOUT
VIN
RF
1
1 + sR1C1
=
1 +
(
(
RG
0
50
100
150
200
250
300
Capacitive Load (pF)
C025
Single-Pole, Low-Pass Filter
Small-Signal Overshoot vs Load Capacitance
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TLV9061-Q1, TLV9062-Q1, TLV9064-Q1
SBOS966D – APRIL 2019 – REVISED OCTOBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Device Comparison Table...............................................3
7 Pin Configuration and Functions...................................4
Pin Functions: TLV9061S-Q1........................................... 4
Pin Functions: TLV9062-Q1..............................................4
Pin Functions: TLV9064-Q1..............................................5
8 Specifications.................................................................. 6
8.1 Absolute Maximum Ratings........................................ 6
8.2 ESD Ratings............................................................... 6
8.3 Recommended Operating Conditions.........................6
8.4 Thermal Information: TLV9061S-Q1...........................6
8.5 Thermal Information: TLV9062-Q1............................. 7
8.6 Thermal Information: TLV9064-Q1............................. 7
8.7 Electrical Characteristics.............................................8
8.8 Typical Characteristics..............................................10
9 Detailed Description......................................................16
9.1 Overview...................................................................16
9.2 Functional Block Diagram.........................................16
9.3 Feature Description...................................................17
9.4 Device Functional Modes..........................................18
10 Application and Implementation................................19
10.1 Application Information........................................... 19
10.2 Typical Applications................................................ 19
11 Power Supply Recommendations..............................23
11.1 Input and ESD Protection........................................23
12 Layout...........................................................................24
12.1 Layout Guidelines................................................... 24
12.2 Layout Example...................................................... 25
13 Device and Documentation Support..........................26
13.1 Documentation Support.......................................... 26
13.2 Related Links.......................................................... 26
13.3 Receiving Notification of Documentation Updates..26
13.4 Support Resources................................................. 26
13.5 Trademarks.............................................................26
13.6 Electrostatic Discharge Caution..............................26
13.7 Glossary..................................................................26
14 Mechanical, Packaging, and Orderable
Information.................................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2020) to Revision D (October 2020)
Page
•
Added TLV9061-Q1 GPN throughout the data sheet......................................................................................... 1
Changes from Revision B (September 2020) to Revision C (September 2020)
Page
•
•
•
Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Functional Safety-Capable document link added in the Features section..........................................................1
Added note 5 to differential input voltage in Absolute Maximum Ratings table..................................................6
Changes from Revision A (March 2020) to Revision B (September 2020)
Page
•
•
•
Deleted preview note form VSSOP (8) and TSSOP (14) package from Device Information section................. 1
Added thermal information for VSSOP (8) package in Thermal Information section..........................................7
Added thermal information for TSSOP (14) package in Thermal Information section........................................7
Changes from Revision * (April 2019) to Revision A (March 2020)
Page
•
First public release of data sheet .......................................................................................................................1
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5 Description (continued)
The TLV906x-Q1 family of devices serve as general-purpose automotive amplifiers, for use in low-voltage
systems requiring low noise and/or wide bandwidth.
The TLV906x-Q1 family helps simplify system design, because the family is unity-gain stable, integrates the RFI
and EMI rejection filter, and provides no phase reversal in overdrive condition.
These devices are available in both dual (TLV9062-Q1), and quad (TLV9064-Q1) versions. Both versions are
available in industry standard SOIC and TSSOP packages, with the dual channel also available as a VSSOP.
6 Device Comparison Table
PACKAGE LEADS
NO. OF
DEVICE
CHANNELS
D
—
8
DGK
—
PW
—
8
TLV9061S-Q1
TLV9062-Q1
TLV9064-Q1
1
2
4
8
14
—
14
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7 Pin Configuration and Functions
+IN
Vœ
1
2
3
6
5
4
V+
SHDN
OUT
œIN
Not to scale
Figure 7-1. TLV9061S-Q1 DBV Package
6-Pin SOT-23
Top View
Pin Functions: TLV9061S-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
4
IN–
IN+
I
I
Inverting input
Noninverting input
Output
3
OUT
1
O
Shutdown: low = amp disabled, high = amp enabled. See Shutdown Function section for
more information.
SHDN
5
I
V–
V+
2
6
I or — Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
I
OUT1
1
2
3
4
8
7
6
5
V+
IN1œ
IN1+
Vœ
OUT2
IN2œ
IN2+
Not to scale
Figure 7-2. TLV9062-Q1 D, DGK, and PW Package
8-Pin SOIC, VSSOP, and TSSOP
Top View
Pin Functions: TLV9062-Q1
PIN
I/O
DESCRIPTION
NAME
IN1–
NO.
2
I
I
Inverting input, channel 1
Noninverting input, channel 1
Inverting input, channel 2
Noninverting input, channel 2
Output, channel 1
IN1+
IN2–
IN2+
OUT1
OUT2
V–
3
6
I
5
I
1
O
O
—
—
7
Output, channel 2
4
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
V+
8
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OUT1
IN1œ
IN1+
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT4
IN4œ
IN4+
Vœ
IN2+
IN2œ
OUT2
IN3+
IN3œ
OUT3
8
Not to scale
Figure 7-3. TLV9064-Q1 D and PW Package
14-Pin SOIC and TSSOP
Top View
Pin Functions: TLV9064-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
2
IN1–
IN1+
IN2–
IN2+
IN3–
IN3+
IN4–
IN4+
NC
I
Inverting input, channel 1
Noninverting input, channel 1
Inverting input, channel 2
Noninverting input, channel 2
Inverting input, channel 3
Noninverting input, channel 3
Inverting input, channel 4
Noninverting input, channel 4
No internal connection
3
I
6
I
5
I
9
I
10
13
12
—
1
I
I
I
—
O
OUT1
OUT2
OUT3
OUT4
V–
Output, channel 1
7
O
Output, channel 2
8
O
Output, channel 3
14
11
4
O
Output, channel 4
I or —
I
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
V+
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8 Specifications
8.1 Absolute Maximum Ratings
over operating ambient temperature (unless otherwise noted)(1)
MIN
0
MAX
UNIT
V
Supply voltage [(V+) – (V–)]
6
(V+) + 0.5
Common-mode
Voltage(2)
(V–) – 0.5
V
Signal input pins
Differential(5)
(V+) – (V–) + 0.2
10
V
Current(2)
Output short-circuit(3) (4)
Specified, TA
–10
mA
mA
Continuous
–40
125
150
150
Temperature
Junction, TJ
Storage, Tstg
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply
rails to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
(4) Long term continuous current limit is determined by electromigration limits.
(5) Differential input voltages greater than 0.5 V applied continuously can result in a shift to the input offset voltage above the maximum
specification of this parameter. The magnitude of this effect increases as the ambient operating temperature rises.
8.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with ANSI/ESDA/JEDEC JS-001 Specification.
8.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
1.8
MAX
UNIT
V
VS
Supply voltage (VS = [V+] – [V–])
Input voltage
5.5
(V+) + 0.1
V+
VI
(V–) – 0.1
V–
V
VO
Output voltage
V
VSHDN_IH
VSHDN_IL
TA
High level input voltage at shutdown pin (amplifier enabled)
Low level input voltage at shutdown pin (amplifier disabled)
Specified temperature
1.1
V+
V
V–
0.2
V
–40
125
°C
8.4 Thermal Information: TLV9061S-Q1
TLV9061S-Q1
DBV (SOT-23)
6 PINS
TBD
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
TBD
TBD
ψJT
TBD
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TLV9061S-Q1
THERMAL METRIC(1)
DBV (SOT-23)
6 PINS
UNIT
ψJB
Junction-to-board characterization parameter
TBD
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Thermal Information: TLV9062-Q1
TLV9062-Q1
THERMAL METRIC(1)
D (SOIC)
8 PINS
152.0
92.1
DGK (VSSOP)
8 PINS
198.5
PW (TSSOP)
8 PINS
TBD
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
RθJC(top)
RθJB
87.2
TBD
95.6
120.3
TBD
Junction-to-top characterization
parameter
ψJT
ψJB
40.1
94.8
23.8
TBD
TBD
°C/W
°C/W
Junction-to-board characterization
parameter
118.7
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
8.6 Thermal Information: TLV9064-Q1
TLV9064-Q1
THERMAL METRIC(1)
PW (TSSOP)
14 PINS
133.8
D (SOIC)
14 PINS
111.1
67.6
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
62.1
76.9
67
Junction-to-top characterization parameter
Junction-to-board characterization parameter
13.2
27.4
ψJB
76.3
66.6
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
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8.7 Electrical Characteristics
For VS (total supply voltage) = (V+) – (V–) = 1.8 V to 5.5 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM
VS / 2, and VOUT = VS / 2 (unless otherwise noted)
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VS = 5 V
±0.3
±1.85
±2
VOS
Input offset voltage
mV
VS = 5 V, TA = –40°C to 125°C
VS = 5 V, TA = –40°C to 125°C
VS = 1.8 V – 5.5 V, VCM = (V–)
At DC
dVOS/dT Drift
PSRR Power-supply rejection ratio
Channel separation, DC
INPUT VOLTAGE RANGE
±0.53
±7
µV/°C
µV/V
dB
±80
100
VCM
Common-mode voltage range
VS = 1.8 V to 5.5 V
(V–) – 0.1
80
(V+) + 0.1
V
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V
TA = –40°C to 125°C
103
75
VS = 5.5 V, VCM = –0.1 V to 5.6 V
TA = –40°C to 125°C
57
CMRR
Common-mode rejection ratio
dB
VS = 1.8 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V,
TA = –40°C to 125°C
88
VS = 1.8 V, VCM = –0.1 V to 1.9 V
TA = –40°C to 125°C
70
INPUT BIAS CURRENT
IB
Input bias current
Input offset current
±5
±5
pA
pA
IOS
NOISE
En
Input voltage noise (peak-to-peak) VS = 5 V, f = 0.1 Hz to 10 Hz
4.77
10
µVPP
VS = 5 V, f = 10 kHz
Input voltage noise density
en
nV/√ Hz
fA/√ Hz
VS = 5 V, f = 1 kHz
16
in
Input current noise density
f = 1 kHz
23
INPUT CAPACITANCE
CID
CIC
Differential
2
4
pF
pF
Common-mode
OPEN-LOOP GAIN
VS = 1.8 V, (V–) + 0.04 V < VO < (V+) – 0.04 V,
RL = 10 kΩ
100
130
100
130
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
RL = 10 kΩ
104
AOL
Open-loop voltage gain
dB
VS = 1.8 V, (V–) + 0.06 V < VO < (V+) – 0.06 V,
RL = 2 kΩ
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
RL = 2 kΩ
FREQUENCY RESPONSE
GBP
φm
Gain bandwidth product
VS = 5 V, G = +1
10
55
MHz
°
Phase margin
Slew rate
VS = 5 V, G = +1
SR
VS = 5 V, G = +1
6.5
0.5
V/µs
To 0.1%, VS = 5 V, 2-V step , G = +1, CL = 100 pF
tS
Settling time
µs
µs
To 0.01%, VS = 5 V, 2-V step,
G = +1, CL = 100 pF
1
0.2
tOR
Overload recovery time
VS = 5 V, VIN × gain > VS
VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1,
f = 1 kHz
THD + N Total harmonic distortion + noise(1)
0.0008%
OUTPUT
VS = 5.5 V, RL = 10 kΩ
VS = 5.5 V, RL = 2 kΩ
VS = 5 V
20
60
Voltage output swing from supply
rails
VO
mV
ISC
ZO
Short-circuit current
±50
100
mA
Ω
Open-loop output impedance
VS = 5 V, f = 10 MHz
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For VS (total supply voltage) = (V+) – (V–) = 1.8 V to 5.5 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM
VS / 2, and VOUT = VS / 2 (unless otherwise noted)
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VS = 5.5 V, IO = 0 mA
538
750
800
IQ
Quiescent current per amplifier
µA
VS = 5.5 V, IO = 0 mA TA = –40°C to 125°C
SHUTDOWN (2)
VS = 1.8 V to 5.5 V, all amplifiers disabled, SHDN =
Low
IQSD
Quiescent current per amplifier
0.5
10 || 8
1.5
µA
ZSHDN
Output impedance during shutdown VS = 1.8 V to 5.5 V, amplifier disabled
GΩ || pF
V
VSHDN_TH High level voltage shutdown
VS = 1.8 V to 5.5 V
VS = 1.8 V to 5.5 V
(V–) + 0.9
(V–) + 1.1
threshold (amplifier enabled)
R_HI
VSDHN_TH Low level voltage shutdown
(V–) + 0.2
(V–) + 0.7
10
V
threshold (amplifier disabled)
R_LO
VS = 1.8 V to 5.5 V, full shutdown; G = 1, VOUT = 0.9 ×
VS / 2, RL connected to V–
tON
Amplifier enable time (shutdown)(3)
Amplifier disable time(3)
µs
µs
VS = 1.8 V to 5.5 V, G = 1, VOUT = 0.1 × VS / 2, RL
connected to V–
tOFF
0.6
VS = 1.8 V to 5.5 V, V+ ≥ SHDN ≥ (V+) – 0.8 V
VS = 1.8 V to 5.5 V, V– ≤ SHDN ≤ V– + 0.8 V
130
40
SHDN pin input bias current (per
pin)
pA
(1) Third-order filter; bandwidth = 80 kHz at –3 dB.
(2) Ensured by design and characterization; not production tested.
(3) Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
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8.8 Typical Characteristics
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
35
30
25
20
15
10
5
50
40
30
20
10
0
0
Offset Voltage Drift (µV/C)
C001
C002
Offset Voltage (µV)
TA = –40°C to 125°C
Figure 8-2. Offset Voltage Drift Distribution
Figure 8-1. Offset Voltage Production Distribution
500
400
2500
2000
1500
1000
500
300
200
100
0
0
œ500
œ1000
œ1500
œ2000
œ2500
œ100
œ200
œ300
œ400
œ500
-4
-3
-2
-1
0
1
2
3
4
0
25
50
75
100
125
150
œ50
œ25
Input Common Mode Voltage (V)
Temperature (°C)
C005
C003
V+ = 2.75 V
V– = –2.75 V
Figure 8-4. Offset Voltage vs Common-Mode
Voltage
Figure 8-3. Offset Voltage vs Temperature
1000
120
100
80
180
135
90
Gain
Phase
500
0
60
40
20
45
œ500
œ1000
0
œ20
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
100
1k
10k
100k
1M
10M
Supply Voltage (V)
Frequency (Hz)
C004
C006
VS = 1.8 V to 5.5 V
CL = 10 pF
Figure 8-5. Offset Voltage vs Power Supply
Figure 8-6. Open-Loop Gain and Phase vs
Frequency
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20
40
30
VS = 5.5 V
VS = 1.8 V
16
12
8
20
10
0
œ10
œ20
œ30
œ40
G=+1
G=-1
4
G=+10
0
0
25
50
75
100
125
1000
10k
100k
1M
10M
œ50
œ25
Temperature (°C)
Frequency (Hz)
C022
C007
RL = 2 kΩ
Figure 8-7. Open-Loop Gain vs Temperature
Figure 8-8. Closed-Loop Gain vs Frequency
250
3
IBN
200
150
100
50
IBP
IOS
2
-40°C
125°C
85°C
1
0
25°C
25°C
85°C
-40°C
œ1
œ2
œ3
125°C
0
œ50
0
25
50
75
100
125
œ50
œ25
10
20
30
40
50
60
Temperature (°C)
Output Current (mA)
C008
C009
V+ = 2.75 V
V– = –2.75 V
Figure 8-9. Input Bias Current vs Temperature
Figure 8-10. Output Voltage Swing vs Output
Current
120
55
50
45
40
35
30
CMRR
100
80
60
40
20
0
PSRR-
PSRR+
1000
10k
100k
1M
10M
Frequency (Hz)
0
25
50
75
100
125
œ50
œ25
C011
Temperature (°C)
C012
VS = 5.5 V VCM = –0.1 V to 5.6 V
RL= 10 kΩ
TA= –40°C to 125°C
Figure 8-12. CMRR vs Temperature
Figure 8-11. CMRR and PSRR vs Frequency
(Referred to Input)
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10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
0
25
50
75
100
125
150
œ50
œ25
0
25
50
75
100
125
œ50
œ25
Temperature (°C)
Temperature (°C)
C016
C013
VCM = (V–) – 0.1 V to (V+) – 1.4 V
TA= –40°C to 125°C RL= 10 kΩ
VS = 1.8 V to 5.5 V
VS = 5.5 V
Figure 8-13. CMRR vs Temperature
Figure 8-14. PSRR vs Temperature
120
100
80
60
40
20
0
Time (1s/div)
10
100
1k
10k
100k
Frequency (Hz)
C014
C015
VS = 1.8 V to 5.5 V
Figure 8-15. 0.1-Hz to 10-Hz Input Voltage Noise
Figure 8-16. Input Voltage Noise Spectral Density
vs Frequency
œ90
œ95
œ40
œ60
œ100
œ105
œ110
œ115
œ120
œ80
œ100
œ120
100
1k
10k
0.001
0.01
0.1
1
Frequency (Hz)
Output Voltage Amplitude (VRMS
)
C017
C018
VS = 5.5 V
VCM = 2.5 V
BW = 80 kHz
RL = 2 kΩ
G = +1
VS = 5.5 V
RL = 2 kΩ
G = +1
VOUT = 0.5 VRMS
VCM = 2.5 V
BW = 80 kHz
f = 1 kHz
Figure 8-17. THD + N vs Frequency
Figure 8-18. THD + N vs Amplitude
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œ40
600
580
560
540
520
500
œ60
œ80
œ100
œ120
0.001
0.01
0.1
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Output Voltage Amplitude (VRMS
)
Supply Voltage (V)
C019
C020
VS = 5.5 V
G = –1
VCM = 2.5 V
RL = 2 kΩ
f = 1 kHz
BW = 80 kHz
Figure 8-19. THD + N vs Amplitude
Figure 8-20. Quiescent Current vs Supply Voltage
800
200
700
600
500
400
300
200
100
0
160
120
80
40
0
0
25
50
75
100
125
10k
100k
Frequency (Hz)
1M
10M
œ50
œ25
Temperature (°C)
C021
C024
Figure 8-21. Quiescent Current vs Temperature
Figure 8-22. Open-Loop Output Impedance vs
Frequency
60
50
40
30
20
60
50
40
30
20
10
0
10
0
Overshoot+
Overshoot-
Overshoot(+)
Overshoot(-)
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Capacitive Load (pF)
Capacitive Load (pF)
C025
C026
V+ = 2.75 V
V– = –2.75 V
RL = 10 kΩ
G = +1 V/V
V+ = 2.75 V
V– = –2.75 V
RL = 10 kΩ
G = –1 V/V
VOUT step = 100 mVp-p
VOUT step = 100 mVp-p
Figure 8-23. Small-Signal Overshoot vs Load
Capacitance
Figure 8-24. Small-Signal Overshoot vs Load
Capacitance
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Input
INPUT
OUTPUT
Output
Time (200 µs/div)
Time (1 µs/div)
C036
C028
V+ = 2.75 V
V– = –2.75 V
V+ = 2.75 V
V– = –2.75 V
G = –10 V/V
Figure 8-25. No Phase Reversal
Figure 8-26. Overload Recovery
Input
Output
Input
Output
Time (0.1µs/div)
Time (1 µs/div)
C030
C031
V+ = 2.75 V
V– = –2.75 V
G = 1 V/V
V+ = 2.75 V
G = 1 V/V
V– = –2.75 V
CL = 100 pF
Figure 8-27. Small-Signal Step Response
Figure 8-28. Large-Signal Step Response
80
60
40
20
6
5
4
3
2
Sinking
0
Sourcing
œ20
œ40
œ60
œ80
1
0
VS = 5.5 V
VS = 1.8 V
0
25
50
75
100
125
1
10
100
1k
10k
100k
1M
10M
œ50
œ25
Temperature (°C)
Frequency (Hz)
C034
C035
RL = 10 kΩ
CL = 10 pF
Figure 8-29. Short-Circuit Current vs Temperature
Figure 8-30. Maximum Output Voltage vs
Frequency and Supply Voltage
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140
120
100
80
0
œ20
œ40
œ60
60
œ80
40
œ100
œ120
œ140
20
0
10M
100M
Frequency (Hz)
1G
100
1k
10k
100k
1M
10M
Frequency (Hz)
C041
C038
PRF = –10 dBm
V+ = 2.75 V
V– = –2.75 V
Figure 8-31. Electromagnetic Interference
Figure 8-32. Channel Separation vs Frequency
Rejection Ratio Referred to Noninverting Input
(EMIRR+) vs Frequency
90
75
60
45
30
15
0
200
160
120
80
40
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
0
10
20
30
40
50
60
70
80
90 100
Output Voltage (V)
Capacitive Load (pF)
C023
C037
VS = 5.5 V
VS = 5.5 V
Figure 8-34. Open Loop Voltage Gain vs Output
Voltage
Figure 8-33. Phase Margin vs Capacitive Load
100
75
100
75
50
50
25
25
0
0
-25
-50
-75
-100
-125
-150
œ25
œ50
œ75
œ100
0
0.3
0.6
0.9
0
0.3
0.6
0.9
1.2
1.5
Settling time (µs)
Settling time (µs)
C032
C033
Figure 8-35. Large Signal Settling Time (Positive)
Figure 8-36. Large Signal Settling Time (Negative)
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9 Detailed Description
9.1 Overview
The TLV906x-Q1 devices are a family of low-power, rail-to-rail input and output op amps. These devices operate
from 1.8 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications.
The input common-mode voltage range includes both rails and allows the TLV906x-Q1 series to be used in
virtually any single-supply application. Rail-to-rail input and output swing significantly increases dynamic range,
especially in low-supply applications. The high bandwidth enables this family to drive the sample-hold circuitry of
analog-to-digital converters (ADCs).
9.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINÛ
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
VÛ
(Ground)
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9.3 Feature Description
9.3.1 Rail-to-Rail Input
The input common-mode voltage range of the TLV906x-Q1 family extends 100 mV beyond the supply rails for
the full supply voltage range of 1.8 V to 5.5 V. This performance is achieved with a complementary input stage:
an N-channel input differential pair in parallel with a P-channel differential pair, as shown in the Functional Block
Diagram section. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to
200 mV above the positive supply, whereas the P-channel pair is active for inputs from 200 mV below the
negative supply to approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1
V, in which both pairs are on. This 200-mV transition region can vary up to 200 mV with process variation. Thus,
the transition region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to
(V+) – 1 V to (V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift,
and THD can degrade compared to device operation outside this region.
9.3.2 Rail-to-Rail Output
Designed as a low-power, low-voltage operational amplifier, the TLV906x-Q1 series delivers a robust output
drive capability. A class AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads of 10-kΩ, the output swings to within 15 mV of either supply rail, regardless of the
applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the
rails.
9.3.3 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device
enters the saturation region, the charge carriers in the output devices require time to return to the linear state.
After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore,
the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew
time. The overload recovery time for the TLV906x-Q1 family is approximately 200 ns.
9.3.4 Shutdown Function
The TLV906xS-Q1 devices feature SHDN pins that disable the op amp, placing it into a low-power standby
mode. In this mode, the op amp typically consumes less than 1 µA. The SHDN pins are active-low, meaning that
shutdown mode is enabled when the input to the SHDN pin is a valid logic low.
The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown
feature lies around 800 mV (typical) and does not change with respect to the supply voltage. Hysteresis has
been included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown
behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage
between V– and V– + 0.2 V. A valid logic high is defined as a voltage between V– + 1.2 V and V+. The shutdown
pin must either be connected to a valid high or a low voltage or driven, and not left as an open circuit.
The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled, and
quad op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature
may be used to greatly reduce the average current and extend battery life. The enable time is 10 µs for full
shutdown of all channels; disable time is 3 µs. When disabled, the output assumes a high-impedance state. This
architecture allows the TLV906xS-Q1 to be operated as a gated amplifier (or to have the device output
multiplexed onto a common analog output bus). Shutdown time (tOFF) depends on loading conditions and
increases as load resistance increases. To ensure shutdown (disable) within a specific shutdown time, the
specified 10-kΩ load to midsupply (VS / 2) is required. If using the TLV906xS-Q1 without a load, the resulting
turnoff time is significantly increased.
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9.4 Device Functional Modes
Devices in the TLV906x-Q1 family are operational when the power-supply voltage is between 1.8 V (±0.9 V) and
5.5 V (±2.75 V). The TLV906xS devices feature a shutdown mode and are shut down when a valid logic low is
applied to the shutdown pin.
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
The TLV906x-Q1 family features 10-MHz bandwidth and 6.5-V/µs slew rate with only 538 µA of supply current
per channel, providing good AC performance at very low power consumption. DC applications are well served
with a very low input noise voltage of 10 nV/√ Hz at 10 kHz, low input bias current, and a typical input offset
voltage of 0.3 mV.
10.2 Typical Applications
10.2.1 Typical Low-Side Current Sense Application
Figure 10-1 shows the TLV906x-Q1 configured in a low-side current-sensing application.
VBUS
ZLOAD
ILOAD
5V
+
TLV906x
VOUT
Rshunt
VSHUNT
0.1ꢀ
RF
165 kꢀ
RG
3.4 kꢀ
Figure 10-1. TLV906x-Q1 in a Low-Side, Current-Sensing Application
10.2.1.1 Design Requirements
The design requirements for this design are:
•
•
•
Load current: 0 A to 1 A
Output voltage: 4.95 V
Maximum shunt voltage: 100 mV
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10.2.1.2 Detailed Design Procedure
The transfer function of the circuit in Figure 10-1 is given in Equation 1.
VOUT = ILOAD ìRSHUNT ìGain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using Equation 2.
VSHUNT _MAX
100mV
1A
RSHUNT
=
=
=100mW
ILOAD_MAX
(2)
Using Equation 2, RSHUNT equals 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is amplified by the
TLV906x-Q1 to produce an output voltage of approximately 0 V to 4.95 V. Equation 3 calculates the gain
required for the TLV906x-Q1 to produce the required output voltage.
V
OUT _MAX - VOUT _MIN
(
)
Gain =
VIN_MAX - V
IN_MIN
(3)
Using Equation 3, the required gain equals 49.5 V/V, which is set with the RF and RG resistors. Equation 4 sizes
the RF and RG, resistors to set the gain of the TLV906x-Q1 to 49.5 V/V.
R
(
)
F
Gain = 1+
R
G
(4)
Selecting RF to equal 165 kΩ and RG to equal 3.4 kΩ provides a combination that equals approximately 49.5
V/V. Figure 10-2 shows the measured transfer function of the circuit shown in Figure 10-1. Notice that the gain is
only a function of the feedback and gain resistors. This gain is adjusted by varying the ratio of the resistors and
the actual resistor values are determined by the impedance levels that the designer wants to establish. The
impedance level determines the current drain, the effect that stray capacitance has, and a few other behaviors.
There is no optimal impedance selection that works for every system, you must choose an impedance that is
ideal for your system parameters.
10.2.1.3 Application Curve
5
4
3
2
1
0
0
0.2
0.4
0.6
0.8
1
ILOAD (A)
C219
Figure 10-2. Low-Side, Current-Sense, Transfer Function
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10.2.2 Typical Comparator Application
Comparators are used to differentiate between two different signal levels. For example, a comparator can be
used to differentiate between an overvoltage situation and normal operation. The TLV9062-Q1 can be used as a
comparator by applying the two voltages being compared to each input without any feedback from output to
inverting input.
The TLV9062-Q1 features a rail-to-rail input and output stage with an input common-mode range that exceeds
the supply rails by 100 mV. The TLV9062-Q1 is designed to prevent phase reversal over the entire input
common-mode range. The propagation delay for the TLV9062-Q1 used as a comparator is equal to the overload
recovery time plus the slew rate. Overdrive voltages less than 100 mV result in longer propagation delays
because the overload recovery time increases and the slew rate decreases.
V+
R1
100kꢀ
VTH
V+
+
R2
100kꢀ
TLV9062
VOUT
VIN
Figure 10-3. Typical Comparator Application
10.2.2.1 Design Requirements
The design requirements for this design are:
•
•
•
Supply voltage (V+): 5 V
Input (VIN): 0 V to 5 V
Threshold voltage (VTH): 2.5 V
10.2.2.2 Detailed Design Procedure
The inverting comparator circuit applies the input voltage (VIN) to the inverting terminal of the op amp. Two
resistors (R1 and R2) divide the supply voltage (VCC) to create a midsupply threshold voltage (VTH) as calculated
in Equation 5. The circuit is shown in Figure 10-3. When VIN is less then VTH, the output voltage transitions to the
positive supply and equals the high-level output voltage. When VIN is greater than VTH, the output voltage
transitions to the negative supply and equals the low-level output voltage, VTH
.
R2
R1 + R2
VTH
=
ì V+ = 2.5V
(5)
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10.2.2.3 Application Curves
5.5
5
5.5
5
Input
Output
Input
Output
4.5
4
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-0.5
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Time (us)
2
0
20
40
60
80 100 120 140 160 180 200
Time (us)
D102
D101
Figure 10-5. Rising Edge
Figure 10-4. Comparator Response to Input
Voltage (Propagation Delay Included)
5.5
5.5
5
Input
Output
20mV
50mV
100mV
200mV
500mV
5
4.5
4.5
4
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-0.5
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Time (us)
2
0
5
10
15
20
Time (us)
25
30
35
40
D103
D104
Figure 10-6. Falling Edge
Figure 10-7. Falling Edge Propagation Delay vs
Input Overdrive Voltage
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11 Power Supply Recommendations
The TLV906x-Q1 series is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications
apply from –40°C to 125°C. The Typical Characteristics section presents parameters that can exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 6 V can permanently damage the device; see the Absolute Maximum
Ratings table.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
11.1 Input and ESD Protection
The TLV906x-Q1 series incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA, as shown in the Absolute Maximum Ratings table. Figure 11-1 shows how a series input resistor can be
added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier
input and the value must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA maximum
VOUT
Device
VIN
5 kW
Figure 11-1. Input Current Protection
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12 Layout
12.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is adequate for single-supply
applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care
to physically separate digital and analog grounds, paying attention to the flow of the ground current.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is much
better as opposed to running the traces in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. As illustrated in Figure 12-2, keeping RF
and RG close to the inverting input minimizes parasitic capacitance on the inverting input.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended
to remove moisture introduced into the device packaging during the cleaning process. A low-temperature,
post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
Copyright © 2020 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: TLV9061-Q1 TLV9062-Q1 TLV9064-Q1
TLV9061-Q1, TLV9062-Q1, TLV9064-Q1
SBOS966D – APRIL 2019 – REVISED OCTOBER 2020
www.ti.com
12.2 Layout Example
VIN 1
VIN 2
+
+
VOUT 1
VOUT 2
RG
RG
RF
RF
Figure 12-1. Schematic Representation
Place components
close to device and to
each other to reduce
parasitic errors.
OUT 1
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
VS+
GND
OUT1
V+
RF
RG
OUT 2
GND
IN1œ
IN1+
Vœ
OUT2
IN2œ
IN2+
RF
RG
VIN 1
GND
VIN 2
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
GND
ceramic bypass
capacitor . Place as
close to the device
as possible .
VSœ
Ground (GND) plane on another layer
as possible .
Figure 12-2. Layout Example
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: TLV9061-Q1 TLV9062-Q1 TLV9064-Q1
TLV9061-Q1, TLV9062-Q1, TLV9064-Q1
SBOS966D – APRIL 2019 – REVISED OCTOBER 2020
www.ti.com
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
Texas Instruments, TLVx313-Q1 Low-Power, Rail-to-Rail In/Out, 500-μV Typical Offset, 1-MHz Operational
Amplifier for Cost-Sensitive Systems data sheet.
Texas Instruments, TLVx314-Q1 3-MHz, Low-Power, Internal EMI Filter, RRIO, Operational Amplifier data sheet.
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application report.
Texas Instruments, QFN/SON PCB Attachment application report.
Texas Instruments, Single-Ended Input to Differential Output Conversion Circuit Reference Design.
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 13-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
TLV9062-Q1
TLV9064-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2020 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: TLV9061-Q1 TLV9062-Q1 TLV9064-Q1
TLV9061-Q1, TLV9062-Q1, TLV9064-Q1
SBOS966D – APRIL 2019 – REVISED OCTOBER 2020
www.ti.com
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: TLV9061-Q1 TLV9062-Q1 TLV9064-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTLV9061SQDBVRQ1
PTLV9062QDGKRQ1
ACTIVE
ACTIVE
SOT-23
VSSOP
DBV
DGK
6
8
3000
2500
TBD
TBD
TBD
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
Call TI
TLV9061SQDBVRQ1
TLV9062QDGKRQ1
PREVIEW
PREVIEW
SOT-23
VSSOP
DBV
DGK
6
8
3000
2500
Call TI
Call TI
-40 to 125
-40 to 125
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
27CT
TLV9062QDRQ1
TLV9064QDRQ1
TLV9064QPWRQ1
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
2500
2500
2000
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
T9062Q
14
14
Green (RoHS
& no Sb/Br)
TLV9064QD
T9064Q
TSSOP
PW
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV9061-Q1, TLV9062-Q1, TLV9064-Q1 :
Catalog: TLV9061, TLV9062, TLV9064
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Oct-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV9062QDRQ1
TLV9064QDRQ1
TLV9064QPWRQ1
SOIC
SOIC
D
D
8
2500
2500
2000
330.0
330.0
330.0
12.4
16.4
12.4
6.4
6.5
6.9
5.2
9.0
5.6
2.1
2.1
1.6
8.0
8.0
8.0
12.0
16.0
12.0
Q1
Q1
Q1
14
14
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Oct-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV9062QDRQ1
TLV9064QDRQ1
TLV9064QPWRQ1
SOIC
SOIC
D
D
8
2500
2500
2000
367.0
367.0
367.0
367.0
367.0
367.0
35.0
38.0
35.0
14
14
TSSOP
PW
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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