TLV9104IPWR [TI]
TLV910x 16-V, 1-MHz, Rail-to-Rail Input/Output, Low Power Op Amp;
| 型号： | TLV9104IPWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TLV910x 16-V, 1-MHz, Rail-to-Rail Input/Output, Low Power Op Amp |
| 文件： | 总79页 (文件大小：6120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV9101, TLV9102, TLV9104
SBOS943D – FEBRUARY 2019 – REVISED JUNE 2021
TLV910x 16-V, 1-MHz, Rail-to-Rail Input/Output, Low Power Op Amp
1 Features
3 Description
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Rail-to-rail input and output
The TLV910x family (TLV9101, TLV9102, and
TLV9104) is a family of 16-V general purpose
operational amplifiers. This family offers excellent DC
precision and AC performance, including rail-to-rail
input/output, low offset (±300 µV, typ), low offset drift
(±0.6 µV/°C, typ), and 1.1-MHz bandwidth.
Wide bandwidth: 1.1-MHz GBW
Low quiescent current: 120 µA per amplifier
Low offset voltage: ±300 µV
Low offset voltage drift: ±0.6 µV/°C
Low noise: 28 nV/√ Hz at 10 kHz
High common-mode rejection: 110 dB
Low bias current: ±10 pA
High slew rate: 4.5 V/µs
Wide supply: ±1.35 V to ±8 V, 2.7 V to 16 V
Robust EMIRR performance: 77 dB at 1.8 GHz
Wide differential and common-mode input-voltage
range, high output current (±80 mA, typ), high slew
rate (4.5 V/µs, typ), low power operation (115 µA,
typ) and shutdown functionality make the TLV910x
a robust, low-power, high-performance operational
amplifier for industrial applications.
2 Applications
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Optical modules
The TLV910x family of op amps is available in micro-
size packages, as well as standard packages, and is
specified from –40°C to 125°C.
Portable test and measurement
Macro remote radio unit (RRU)
Baseband unit (BBU)
Appliances
Device Information
PART NUMBER (1)
PACKAGE
BODY SIZE (NOM)
2.90 mm × 1.60 mm
2.90 mm × 1.60 mm
2.00 mm × 1.25 mm
1.60 mm × 1.20 mm
4.90 mm × 3.90 mm
2.90 mm × 1.60 mm
3.00 mm × 4.40 mm
3.00 mm × 3.00 mm
3.00 mm × 3.00 mm
2.00 mm × 2.00 mm
1.50 mm × 1.50 mm
8.65 mm × 3.90 mm
5.00 mm × 4.40 mm
3.00 mm × 3.00 mm
2.00 mm × 2.00 mm
SOT-23 (5)
SOT-23 (6)
SC70 (5)
TLV9101
SOT-553 (5)(2)
RG
RF
SOIC (8)
SOT-23 (8)
TSSOP (8)
VSSOP (8)(2)
VSSOP (10)
WSON (8)
X2QFN (10)
SOIC (14)
R1
VOUT
VIN
TLV9102
TLV9104
C1
1
2pR1C1
f
=
-3 dB
VOUT
VIN
RF
1
1 + sR1C1
=
1 +
(
(
RG
TLV910x in a Single-Pole, Low-Pass Filter
TSSOP (14)
WQFN (16)
X2QFN (14)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) This package is preview only.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV9101, TLV9102, TLV9104
SBOS943D – FEBRUARY 2019 – REVISED JUNE 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications................................................................ 10
6.1 Absolute Maximum Ratings ..................................... 10
6.2 ESD Ratings ............................................................ 10
6.3 Recommended Operating Conditions ......................10
6.4 Thermal Information for Single Channel .................. 10
6.5 Thermal Information for Dual Channel .....................11
6.6 Thermal Information for Quad Channel ....................11
6.7 Electrical Characteristics ..........................................12
6.8 Typical Characteristics..............................................15
7 Detailed Description......................................................23
7.1 Overview...................................................................23
7.2 Functional Block Diagram.........................................23
7.3 Feature Description...................................................24
7.4 Device Functional Modes..........................................31
8 Application and Implementation .................................32
8.1 Application Information............................................. 32
8.2 Typical Applications.................................................. 32
9 Power Supply Recommendations................................34
10 Layout...........................................................................34
10.1 Layout Guidelines................................................... 34
10.2 Layout Example...................................................... 34
11 Device and Documentation Support..........................37
11.1 Device Support........................................................37
11.2 Documentation Support.......................................... 37
11.3 Receiving Notification of Documentation Updates..37
11.4 Support Resources................................................. 37
11.5 Trademarks............................................................. 37
11.6 Electrostatic Discharge Caution..............................37
11.7 Glossary..................................................................37
12 Mechanical, Packaging, and Orderable
Information.................................................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (May 2020) to Revision D (June 2021)
Page
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Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Removed preview notation from TLV9104 SOIC (14) package from Device Information table..........................1
Removed preview notation from TLV9104 TSSOP (14) package from Device Information table...................... 1
Removed preview notation from TLV9102 SOT-23 (8) package from Device Information table........................ 1
Removed preview notation from TLV9104 WQFN (16) package from Device Information table........................1
Removed preview notation from TLV9101 DBV package (SOT-23) in the Pin Configuration and Functions
section................................................................................................................................................................ 4
Adjusted DRL pinout in the Pin Configuration and Functions section................................................................ 4
Removed preview notation from TLV9101 DCK package (SC70) in the Pin Configuration and Functions
section................................................................................................................................................................ 4
Removed preview notation from TLV9101S DBV package (SOT-23) in the Pin Configuration and Functions
section................................................................................................................................................................ 4
Clarified shutdown notation in the Pin Configuration and Functions section......................................................4
Removed preview notation from TLV9102 DDF package (SOT-23-8) in the Pin Configuration and Functions
section................................................................................................................................................................ 4
Removed preview notation from TLV9104 SOIC (D) and TSSOP (PW) packages in the Pin Configuration and
Functions section................................................................................................................................................4
Removed preview notation from TLV9104 X2QFN (RUC) package in the Pin Configuration and Functions
section................................................................................................................................................................ 4
Removed preview notation from TLV9104 WQFN (RTE) package in the Pin Configuration and Functions
section................................................................................................................................................................ 4
Removed preview notation from TLV9104S WQFN (RTE) package in the Pin Configuration and Functions
section................................................................................................................................................................ 4
Removed Table of Graphs from the Specifications section.............................................................................. 10
Removed preview note from WQFN (RTE) package in thermal information for quad channel........................11
Removed Related Links section from the Device and Documentation Support section...................................37
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Changes from Revision B (May 2020) to Revision C (May 2020)
Page
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Removed preview notation from TLV9102 VSSOP (10) package from Device Information table...................... 1
Copyright © 2021 Texas Instruments Incorporated
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SBOS943D – FEBRUARY 2019 – REVISED JUNE 2021
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•
•
Removed preview notation from TLV9102 X2QFN (10) package from Device Information table.......................1
Removed preview notation from TLV9102 DGS package (VSSOP) in the Pin Configuration and Functions
section................................................................................................................................................................ 4
Removed preview notation from TLV9102 RUG package (X2QFN) in the Pin Configuration and Functions
section................................................................................................................................................................ 4
•
Changes from Revision A (April 2019) to Revision B (May 2020)
Page
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Changed the TLV9101 and TLV9104 device statuses from Advance Information to Production Data ..............1
Removed preview notation from TLV9101 SOT-23 (5) package from Device Information table........................ 1
Removed preview notation from TLV9101 SOT-23 (6) package from Device Information table........................ 1
Removed preview notation from TLV9101 SC70 (5) package from Device Information table............................1
Removed preview notation from TLV9102 TSSOP (8) package from Device Information table........................ 1
Removed preview notation from TLV9102 WSON (8) package from Device Information table......................... 1
Removed preview notation from TLV9102 DSG package (WSON) in the Pin Configuration and Functions
section................................................................................................................................................................ 4
Added SHUTDOWN to Electrical Characteristics ............................................................................................12
Added Packages With an Exposed Thermal Pad to the Feature Description ................................................. 30
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Changes from Revision * (February 2019) to Revision A (April 2019)
Page
Changed the TLV9102 device status from Advance Information to Production Data ........................................1
Removed preview notation from TLV9102 SOIC (8) package from Device Information table............................1
•
•
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SBOS943D – FEBRUARY 2019 – REVISED JUNE 2021
www.ti.com
5 Pin Configuration and Functions
OUT
Vœ
1
2
3
5
V+
IN+
Vœ
1
2
3
5
V+
IN+
4
INœ
INœ
4
OUT
Not to scale
Not to scale
A. Package is preview only.
Figure 5-1. TLV9101 DBV Package
5-Pin SOT-23
Figure 5-2. TLV9101 DCK and DRL Package(A)
5-Pin SC70 and SOT-553
Top View
Top View
Table 5-1. Pin Functions: TLV9101
PIN
DBV
I/O
DESCRIPTION
NAME
DCK and DRL
+IN
–IN
3
4
1
5
2
1
3
4
5
2
I
Noninverting input
I
Inverting input
OUT
V+
O
—
—
Output
Positive (highest) power supply
Negative (lowest) power supply
V–
OUT
V–
1
6
5
4
V+
2
3
SHDN
–IN
+IN
Not to scale
Figure 5-3. TLV9101S DBV Package
6-Pin SOT-23
Top View
Table 5-2. Pin Functions: TLV9101S
PIN
I/O
DESCRIPTION
NAME
NO.
3
IN+
I
I
Noninverting input
Inverting input
Output
IN–
4
OUT
1
O
Shutdown: low = amplifier enabled, high = amplifier disabled. See Section
7.3.10 for more information.
SHDN
5
I
V+
V–
6
2
—
—
Positive (highest) power supply
Negative (lowest) power supply
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OUT1
IN1œ
IN1+
Vœ
1
2
3
4
8
7
6
5
V+
OUT1
IN1œ
IN1+
Vœ
1
2
3
4
8
7
6
5
V+
OUT2
IN2œ
IN2+
OUT2
IN2œ
IN2+
Thermal
Pad
Not to scale
Not to scale
A. DGK package is preview only.
A. Connect thermal pad to V–. See Section 7.3.9 for more
information.
Figure 5-4. TLV9102 D, DDF, DGK, and PW
Package(A)
8-Pin SOIC, SOT-23, TSSOP, and VSSOP
Top View
Figure 5-5. TLV9102 DSG Package(A)
8-Pin WSON With Exposed Thermal Pad
Top View
Table 5-3. Pin Functions: TLV9102
PIN
I/O
DESCRIPTION
NAME
NO.
3
IN1+
IN1–
IN2+
IN2–
OUT1
OUT2
V+
I
I
Noninverting input, channel 1
2
Inverting input, channel 1
Noninverting input, channel 2
Inverting input, channel 2
Output, channel 1
5
I
6
I
1
O
O
—
—
7
Output, channel 2
8
Positive (highest) power supply
Negative (lowest) power supply
V–
4
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OUT1
IN1–
1
2
3
4
5
10
9
V+
V–
SHDN1
SHDN2
IN2+
1
2
3
4
9
8
7
6
IN1–
OUT1
V+
OUT2
IN2–
IN1+
8
V–
7
IN2+
SHDN1
6
SHDN2
Not to scale
OUT2
Figure 5-6. TLV9102S DGS Package
10-Pin VSSOP
Not to scale
Top View
Figure 5-7. TLV9102S RUG Package
10-Pin X2QFN
Top View
Table 5-4. Pin Functions: TLV9102S
PIN
I/O
DESCRIPTION
NAME
VSSOP
X2QFN
IN1+
IN1–
IN2+
IN2–
3
2
7
8
1
9
10
9
I
I
Noninverting input, channel 1
Inverting input, channel 1
Noninverting input, channel 2
Inverting input, channel 2
Output, channel 1
4
I
5
I
OUT1
OUT2
8
O
O
6
Output, channel 2
Shutdown, channel 1: low = amplifier enabled, high = amplifier
disabled. See Section 7.3.10 for more information.
SHDN1
SHDN2
5
6
2
3
I
I
Shutdown, channel 2: low = amplifier enabled, high = amplifier
disabled. See Section 7.3.10 for more information.
V+
V–
10
4
7
1
—
—
Positive (highest) power supply
Negative (lowest) power supply
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OUT1
IN1œ
IN1+
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT4
IN4œ
IN4+
Vœ
IN1+
V+
1
2
3
4
12
11
10
9
IN4+
Vœ
IN2+
IN2œ
OUT2
IN3+
IN3œ
OUT3
Thermal
Pad
IN2+
IN2œ
IN3+
IN3œ
8
Not to scale
Figure 5-8. TLV9104 D and PW Package
14-Pin SOIC and TSSOP
Top View
Not to scale
A. Connect thermal pad to V–. See Section 7.3.9 for more
information.
Figure 5-9. TLV9104 RTE Package(A)
16-Pin WQFN With Exposed Thermal Pad
Top View
IN1œ
IN1+
V+
1
2
3
4
5
12
11
10
9
IN4œ
IN4+
Vœ
IN2+
IN2œ
IN3+
IN3œ
8
Not to scale
Figure 5-10. TLV9104 RUC Package
14-Pin WQFN With Exposed Thermal Pad
Top View
Table 5-5. Pin Functions: TLV9104
PIN
I/O
DESCRIPTION
SOIC and
TSSOP
NAME
IN1+
WQFN
X2QFN
3
2
5
6
1
16
3
2
1
4
5
I
I
I
I
Noninverting input, channel 1
IN1–
IN2+
IN2–
Inverting input, channel 1
Noninverting input, channel 2
Inverting input, channel 2
4
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Table 5-5. Pin Functions: TLV9104 (continued)
PIN
I/O
DESCRIPTION
SOIC and
TSSOP
NAME
IN3+
WQFN
X2QFN
10
9
10
9
9
8
I
I
Noninverting input, channel 3
IN3–
IN4+
IN4–
NC
Inverting input, channel 3
Noninverting input, channel 4
Inverting input, channel 4
Do not connect
12
13
—
1
12
13
6, 7
15
5
11
12
—
14
6
I
I
—
O
O
O
O
—
—
OUT1
OUT2
OUT3
OUT4
V+
Output, channel 1
7
Output, channel 2
8
8
7
Output, channel 3
14
4
14
2
13
3
Output, channel 4
Positive (highest) power supply
Negative (lowest) power supply
V–
11
11
10
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IN1+
V+
1
2
3
4
12
11
10
9
IN4+
V–
Thermal
Pad
IN2+
IN2–
IN3+
IN3–
Not to scale
A. Connect thermal pad to V–. See Section 7.3.9 for more information.
Figure 5-11. TLV9104S RTE Package(A)
16-Pin WQFN With Exposed Thermal Pad
Top View
Table 5-6. Pin Functions: TLV9104S
PIN
I/O
DESCRIPTION
NAME
NO.
1
IN1+
IN1–
IN2+
IN2–
IN3+
IN3–
IN4+
IN4–
OUT1
OUT2
OUT3
OUT4
I
I
Noninverting input, channel 1
Inverting input, channel 1
Noninverting input, channel 2
Inverting input, channel 2
Noninverting input, channel 3
Inverting input, channel 3
Noninverting input, channel 4
Inverting input, channel 4
Output, channel 1
16
3
I
4
I
10
9
I
I
12
13
15
5
I
I
O
O
O
O
Output, channel 2
8
Output, channel 3
14
Output, channel 4
Shutdown, channels 1 and 2: low = amplifiers enabled, high = amplifiers
disabled. See Section 7.3.10 for more information.
SHDN12
SHDN34
6
7
I
I
Shutdown, channels 3 and 4: low = amplifiers enabled, high = amplifiers
disabled. See Section 7.3.10 for more information.
V+
V–
2
—
—
Positive (highest) power supply
Negative (lowest) power supply
11
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
0
MAX
20
UNIT
V
Supply voltage, VS = (V+) – (V–)
Common-mode voltage(3)
(V–) – 0.5
(V+) + 0.5
VS + 0.2
10
V
Signal input pins
Differential voltage(3)
Current(3)
V
–10
V–
mA
V
Shutdown pin voltage
V+
Output short-circuit(2)
Continuous
Operating ambient temperature, TA
Junction temperature, TJ
Storage temperature, Tstg
–55
–65
150
150
150
°C
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Short-circuit to ground, one amplifier per package.
(3) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
2.7
MAX
UNIT
VS
VI
Supply voltage, (V+) – (V–)
16
(V+) + 0.2
V+
V
V
Input voltage range
(V–) – 0.2
(V–) + 1.1
V–
VIH
VIL
TA
High level input voltage at shutdown pin (amplifier disabled)
Low level input voltage at shutdown pin (amplifier enabled)
Specified temperature
V
(V–) + 0.2
125
V
–40
°C
6.4 Thermal Information for Single Channel
TLV9101, TLV9101S
DBV
(SOT-23)
DCK
(SC70)
DRL(2)
(SOT-553)
THERMAL METRIC(1)
UNIT
5 PINS
192.2
113.7
60.6
6 PINS
174.6
113.5
55.9
5 PINS
204.7
116.6
51.9
5 PINS
TBD
TBD
TBD
TBD
TBD
TBD
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
37.4
39.7
24.9
ψJB
60.4
55.7
51.6
RθJC(bot)
N/A
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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(2) This package option is preview for TLV9101.
6.5 Thermal Information for Dual Channel
TLV9102, TLV9102S
D
DDF
(SOT-23-8)
DGK(2)
(VSSOP)
DGS
(VSSOP)
DSG
(WSON)
PW
(TSSOP)
RUG
(X2QFN)
THERMAL METRIC(1)
UNIT
(SOIC)
8 PINS
8 PINS
8 PINS
10 PINS
8 PINS
8 PINS
10 PINS
Junction-to-ambient
thermal resistance
RθJA
RθJC(top)
138.7
150.4
TBD
152.2
81.6
188.4
149.6
°C/W
°C/W
°C/W
Junction-to-case (top)
thermal resistance
78.7
82.2
85.6
70.0
TBD
TBD
67.3
95.5
101.6
48.3
77.1
58.3
77.7
Junction-to-board thermal
resistance
RθJB
119.1
Junction-to-top
characterization
parameter
ψJT
27.8
8.1
TBD
67.9
6.0
14.2
1.3
°C/W
Junction-to-board
characterization
parameter
ψJB
81.4
N/A
69.6
N/A
TBD
TBD
94.3
N/A
48.3
22.8
117.4
N/A
77.5
N/A
°C/W
°C/W
Junction-to-case (bottom)
thermal resistance
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) This package option is preview for TLV9102.
6.6 Thermal Information for Quad Channel
TLV9104, TLV9104S
D
PW
(TSSOP)
RTE
(WQFN)
RUC
(WQFN)
THERMAL METRIC(1)
UNIT
(SOIC)
14 PINS
105.2
61.2
14 PINS
134.7
55.0
16 PINS
53.5
58.3
28.6
2.1
14 PINS
143.0
46.4
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
61.1
79.0
81.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
21.4
9.2
1.0
ψJB
60.7
78.1
28.6
12.6
81.5
RθJC(bot)
N/A
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.7 Electrical Characteristics
For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VO UT
= VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
±0.3
±1.5
VOS
Input offset voltage
VCM = V–
mV
TA = –40°C to 125°C
±1.75
dVOS/dT
PSRR
Input offset voltage drift
TA = –40°C to 125°C
TA = –40°C to 125°C
±0.6
±0.1
5
µV/℃
µV/V
µV/V
Input offset voltage versus
power supply
VCM = V–
f = 0 Hz
±0.7
Channel separation
INPUT BIAS CURRENT
IB
Input bias current
±10
±5
pA
pA
IOS
Input offset current
NOISE
6
1
µVPP
EN
Input voltage noise
f = 0.1 Hz to 10 Hz
µVRMS
f = 1 kHz
f = 10 kHz
f = 1 kHz
30
28
2
eN
iN
Input voltage noise density
Input current noise
nV/√Hz
fA/√Hz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
(V–) – 0.2
90
(V+) + 0.2
V
VS = 16 V, (V–) – 0.1 V < VCM
(V+) – 2 V (Main input pair)
<
110
95
VS = 4 V, (V–) – 0.1 V < VCM
(V+) – 2 V (Main input pair)
<
75
dB
CMRR
Common-mode rejection ratio
TA = –40°C to 125°C
VS = 2.7 – 16 V, (V+) – 1 V < VCM
< (V+) + 0.1 V (Aux input pair)
80
See Offset Voltage (Transition Region) in the Typical
Characteristics section
(V+) – 2 V < VCM < (V+) – 1 V
INPUT CAPACITANCE
ZID
Differential
100 || 3
6 || 1
MΩ || pF
TΩ || pF
ZICM
Common-mode
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6.7 Electrical Characteristics (continued)
For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VO UT
= VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPEN-LOOP GAIN
VS = 16 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1 V
115
104
135
125
dB
dB
AOL
Open-loop voltage gain
TA = –40°C to 125°C
VS = 4 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1 V
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
1.1
4.5
4
MHz
V/µs
Slew rate
VS = 16 V, G = +1, CL = 20 pF
To 0.1%, VS = 16 V, VSTEP = 10 V, G = +1, CL = 20 pF
To 0.1%, VS = 16 V, VSTEP = 2 V, G = +1, CL = 20 pF
To 0.01%, VS = 16 V, VSTEP = 10 V, G = +1, CL = 20 pF
To 0.01%, VS = 16 V, VSTEP = 2 V, G = +1, CL = 20 pF
G = +1, RL = 10 kΩ, CL = 20 pF
2
tS
Settling time
µs
5
3
Phase margin
60
600
°
Overload recovery time
VIN × gain > VS
ns
Total harmonic distortion +
noise
THD+N
VS = 16 V, VO = 1 VRMS, G = -1, f = 1 kHz
0.0028%
OUTPUT
VS = 16 V, RL = no load
VS = 16 V, RL = 10 kΩ
3
45
200
1
60
VS = 16 V, RL = 2 kΩ
300
Positive and negative rail
headroom
Voltage output swing from rail
mV
mA
VS = 2.7 V, RL = no load
VS = 2.7 V, RL = 10 kΩ
VS = 2.7 V, RL = 2 kΩ
5
20
50
25
±80
ISC
Short-circuit current
See Small-Signal Overshoot vs Capacitive Load in the Typical
Characteristics section
CLOAD
Capacitive load drive
ZO
Open-loop output impedance
f = 1 MHz, IO = 0 A
600
Ω
POWER SUPPLY
115
150
160
IQ
Quiescent current per amplifier IO = 0 A
µA
TA = –40°C to 125°C
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6.7 Electrical Characteristics (continued)
For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VO UT
= VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SHUTDOWN
IQSD
Quiescent current per amplifier VS = 2.7 V to 16 V, all amplifiers disabled, SHDN = V+
20
30
µA
Output impedance during
ZSHDN
VS = 2.7 V to 16 V, amplifier disabled, SHDN = V+
shutdown
10 || 12
GΩ || pF
Logic high threshold voltage
(amplifier disabled)
For valid input high, the SHDN pin voltage should be greater than the
maximum threshold but less than or equal to V+
VIH
(V–) + 0.8
(V–) + 0.8
(V–) + 1.1
V
V
Logic low threshold voltage
(amplifier enabled)
For valid input low, the SHDN pin voltage should be less than the
minimum threshold but greater than or equal to V–
VIL
(V–) + 0.2
tON
Amplifier enable time (1)
Amplifier disable time (1)
G = +1, VCM = V–, VO = 0.1 × VS / 2
11
2.5
µs
µs
tOFF
VCM = V–, VO = VS / 2
VS = 2.7 V to 16 V, (V–) + 20 V ≥ SHDN ≥ (V–) + 0.9 V
VS = 2.7 V to 16 V, (V–) ≤ SHDN ≤ (V–) + 0.7 V
500
150
SHDN pin input bias current
(per pin)
nA
(1) Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
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6.8 Typical Characteristics
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
25%
20%
15%
10%
5%
25%
20%
15%
10%
5%
0
0
D001
Offset Voltage Drift (mV/èC)
Offset Voltage (mV)
D002
Distribution from 175 amplifiers
Distribution from 13, 481 amplifiers; TA = 25°C
Figure 6-2. Offset Voltage Drift Distribution
Figure 6-1. Offset Voltage Production Distribution
1000
800
800
600
600
400
200
0
400
200
0
-200
-400
-600
-800
-1000
-200
-400
-600
-800
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D003
D004
VCM = V+
VCM = V–
Each color represents one sample device.
Each color represents one sample device.
Figure 6-3. Offset Voltage vs Temperature
Figure 6-4. Offset Voltage vs Temperature
800
600
400
200
0
800
600
400
200
0
-200
-400
-600
-800
-200
-400
-600
-800
-8
-6
-4
-2
Common Mode Voltage (V)
0
2
4
6
8
4
4.5
5
5.5
Common Mode Voltage (V)
6
6.5
7
7.5
8
D005
D005
TA = 25°C
TA = 25°C
Each color represents one sample device.
Each color represents one sample device.
Figure 6-5. Offset Voltage vs Common-Mode Voltage
Figure 6-6. Offset Voltage vs Common-Mode Voltage
(Transition Region)
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
1000
800
800
600
600
400
400
200
200
0
0
-200
-400
-600
-800
-1000
-1200
-200
-400
-600
-800
-1000
-8
-6
-4
-2
Common Mode Voltage (V)
0
2
4
6
8
-8
-6
-4
-2
Common Mode Voltage (V)
0
2
4
6
8
D006
D007
TA = 125°C
TA = –40°C
Each color represents one sample device.
Each color represents one sample device.
Figure 6-8. Offset Voltage vs Common-Mode Voltage
Figure 6-7. Offset Voltage vs Common-Mode Voltage
750
600
450
300
150
0
100
150
125
100
75
Gain
Phase
80
60
40
20
0
-150
-300
-450
-600
-750
50
25
-20
100
0
2
4
6
8
10
12
Supply Voltage (V)
14
16
18
1k
10k
Frequency (Hz)
100k
1M
D008
C002
VCM = V–
CLOAD = 15 pF
Each color represents one sample device.
Figure 6-9. Offset Voltage vs Power Supply
Figure 6-10. Open-Loop Gain and Phase vs Frequency
70
60
50
40
30
20
10
0
3
G = 1
G = -1
G = 10
G = 100
G = 1000
IB-
2.5
IB+
IOS
2
1.5
1
0.5
0
-0.5
-1
-10
-20
-30
-1.5
-2
-2.5
-8
-6
-4
-2
0
2
Common Mode Voltage (V)
4
6
8
100
1k
10k
Frequency (Hz)
100k
1M
D010
C001
Figure 6-12. Input Bias Current vs Common-Mode Voltage
Figure 6-11. Closed-Loop Gain and Phase vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
320
280
240
200
160
120
80
V+
V+ ꢀ 1 V
V+ ꢀ 2 V
V+ ꢀ 3 V
V+ ꢀ 4 V
V+ ꢀ 5 V
V+ ꢀ 6 V
V+ ꢀ 7 V
V+ ꢀ 8 V
V+ ꢀ 9 V
V+ ꢀ 10 V
IB-
IB+
IOS
-40°C
25°C
85°C
125°C
40
0
-40
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
0
10
20
30
40
50
60
70
80
90 100
Output Current (mA)
D011
D012
Figure 6-13. Input Bias Current vs Temperature
Figure 6-14. Output Voltage Swing vs Output Current (Sourcing)
5
Vꢀ + 10 V
Vꢀ + 9 V
Vꢀ + 8 V
Vꢀ + 7 V
Vꢀ + 6 V
Vꢀ + 5 V
Vꢀ + 4 V
Vꢀ + 3 V
Vꢀ + 2 V
Vꢀ + 1 V
Vꢀ
-40°C
25°C
85°C
125°C
-40èC
4.5
4
3.5
3
25èC
125èC
85èC
2.5
2
1.5
1
0.5
0
0
10
20
30
40
50
60
Output Current (mA)
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
D013
Output Current (mA)
D012
VS = 5 V, RL connected to V–
Figure 6-16. Output Voltage Swing vs Output Current (Sourcing)
Figure 6-15. Output Voltage Swing vs Output Current (Sinking)
5
4.5
4
110
PSRR+
PSRR-
CMRR
100
90
80
70
60
50
40
30
20
10
0
3.5
3
85èC
2.5
125èC
2
1.5
1
-40èC
25èC
0.5
0
100
1k
10k 100k
Frequency (Hz)
1M
10M
0
10
20
30
40 60
Output Current (mA)
50
70
80
90 100
C003
D013
VS = 5 V, RL connected to V+
Figure 6-18. CMRR and PSRR vs Frequency
Figure 6-17. Output Voltage Swing vs Output Current (Sinking)
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
124
120
116
112
108
104
100
96
145
144
143
142
141
140
139
138
137
136
135
VS = 16 V
VS = 4 V
92
88
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D016
D015
f = 0 Hz
Figure 6-20. PSRR vs Temperature (dB)
f = 0 Hz
Figure 6-19. CMRR vs Temperature (dB)
120
110
100
90
80
70
60
50
40
30
20
10
0
Time (1s/Div)
10
100
1k
Frequency (Hz)
10k
100k
C015
C017
Figure 6-21. 0.1-Hz to 10-Hz Noise
Figure 6-22. Input Voltage Noise Spectral Density vs Frequency
-40
-50
-30
RL = 10 kW
RL = 2 kW
RL = 600 W
RL = 128 W
-40
-50
-60
-70
-60
-70
-80
-90
-80
RL = 10 kꢀ
RL = 2 kꢀ
-100
-110
-90
RL = 549 ꢀ
RL = 128 ꢀ
-100
0.001
100
1k
Frequency (Hz)
10k
0.01
0.1
Amplitude (V
1
8
)
RMS
C012
C023
BW = 80 kHz, VOUT = 3.5 VRMS
BW = 80 kHz, f = 1 kHz
Figure 6-24. THD+N vs Output Amplitude
Figure 6-23. THD+N Ratio vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
130
125
120
115
110
105
100
95
127.5
125
122.5
120
117.5
115
112.5
110
107.5
105
90
85
102.5
0
2
4
6
8
10
Supply Voltage (V)
12
14
16
18
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D021
D022
Figure 6-25. Quiescent Current per Channel vs Supply Voltage
Figure 6-26. Quiescent Current per Channel vs Temperature
146
780
720
660
600
540
480
420
360
300
240
180
120
VS = 16 V
VS = 4 V
144
142
140
138
136
134
132
130
128
126
124
100
1k
10k 100k
Frequency (Hz)
1M
10M
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
C013
D023
Figure 6-28. Open-Loop Output Impedance vs Frequency
Figure 6-27. Open-Loop Voltage Gain vs Temperature (dB)
33
30
27
24
21
18
15
55
50
45
40
35
30
25
12
20
RISO = 0 W, Positive Overshoot
RISO = 0 W, Positive Overshoot
9
15
RISO = 0 W, Negative Overshoot
RISO = 0 W, Negative Overshoot
RISO = 50 W, Positive Overshoot
RISO = 50 W, Negative Overshoot
RISO = 50 W, Positive Overshoot
RISO = 50 W, Negative Overshoot
6
10
3
5
0
40
80
120 160 200 240 280 320 360
Cap Load (pF)
0
40
80
120 160 200 240 280 320 360
Cap Load (pF)
C007
C008
G = –1, 100-mV output step
G = 1, 100-mV output step
Figure 6-29. Small-Signal Overshoot vs Capacitive Load
Figure 6-30. Small-Signal Overshoot vs Capacitive Load
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
64
Input
Output
60
56
52
48
44
40
36
32
28
24
20
Time (20µs/Div)
0
100 200 300 400 500 600 700 800 900 1000
Cap Load (pF)
C016
C018
C011
C009
G = –1, 100-mV output step
Figure 6-32. No Phase Reversal
Figure 6-31. Small-Signal Overshoot vs Capacitive Load
Input
Output
Input
Output
Time (500ns/div)
Time (500ns/div)
C018
G = –10
G = –10
Figure 6-33. Positive Overload Recovery
Figure 6-34. Negative Overload Recovery
Input
Output
Input
Output
Time (2ms/div)
Time (1µs/div)
C010
CL = 20 pF, G = 1, 20-mV step response
RL = 1 kΩ, CL = 20 pF, G = –1, 10-mV step response
Figure 6-35. Small-Signal Step Response
Figure 6-36. Small-Signal Step Response
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Input
Output
Input
Output
Time (1µs/div)
Time (1µs/div)
C005
C005
CL = 20 pF, G = 1
CL = 20 pF, G = 1
Figure 6-37. Large-Signal Step Response (Falling)
Figure 6-38. Large-Signal Step Response (Rising)
100
80
60
Input
Output
40
20
Sourcing
Sinking
0
-20
-40
-60
-80
-100
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Time (2µs/div)
D038
C021
CL = 10 pF, G = –1
Figure 6-40. Short-Circuit Current vs Temperature
-60
Figure 6-39. Large-Signal Step Response
20
VS = 15 V
VS = 2.7 V
-70
-80
15
10
5
-90
-100
-110
-120
-130
0
1k
10k
100k
Frequency (Hz)
1M
10M
100
1k
10k 100k
Frequency (Hz)
1M
10M
C020
C014
Figure 6-41. Maximum Output Voltage vs Frequency
Figure 6-42. Channel Separation vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
100
90
80
70
60
50
40
30
1M
10M
100M
Frequency (Hz)
1G
C004
Figure 6-43. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency
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7 Detailed Description
7.1 Overview
The TLV910x family (TLV9101, TLV9102, and TLV9104) is a family of 16-V general purpose operational
amplifiers.
These devices offer excellent DC precision and AC performance, including rail-to-rail input/output, low offset
(±300 µV, typ), low offset drift (±0.6 µV/°C, typ), and 1.1-MHz bandwidth.
Wide differential and common-mode input-voltage range, high output current (±80 mA), high slew rate (4.5
V/µs), low power operation (120 µA, typ), and shutdown functionality make the TLV910x a robust, low-power,
high-performance operational amplifier for industrial applications.
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINÛ
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
VÛ
(Ground)
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7.3 Feature Description
7.3.1 EMI Rejection
The TLV910x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the TLV910x benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure
7-1 shows the results of this testing on the TLV910x. Table 7-1 shows the EMIRR IN+ values for the TLV910x at
particular frequencies commonly encountered in real-world applications. Table 7-1 lists applications that can be
centered on or operated near the particular frequency shown. The EMI Rejection Ratio of Operational Amplifiers
application report contains detailed information on the topic of EMIRR performance as it relates to op amps and
is available for download from www.ti.com.
100
90
80
70
60
50
40
30
1M
10M
100M
Frequency (Hz)
1G
C004
Figure 7-1. TLV910x EMIRR Testing
Table 7-1. TLV910x EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
400 MHz
59.5 dB
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
5 GHz
68.9 dB
77.8 dB
78.0 dB
88.8 dB
87.6 dB
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
7.3.2 Phase Reversal Protection
The TLV910x family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The TLV910x is a rail-to-rail input op amp; therefore, the common-mode range can
extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into
the appropriate rail. This performance is shown in Figure 7-2.
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Input
Output
Time (20µs/Div)
C016
Figure 7-2. No Phase Reversal
7.3.3 Thermal Protection
The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This
phenomenon is called self heating. The absolute maximum junction temperature of the TLV910x is 150°C.
Exceeding this temperature causes damage to the device. The TLV910x has a thermal protection feature that
prevents damage from self heating. The protection works by monitoring the temperature of the device and
turning off the op amp output drive for temperatures above 140°C. Figure 7-3 shows an application example
for the TLV9101 that has significant self heating (154°C) because of its power dissipation (0.39 W). Thermal
calculations indicate that for an ambient temperature of 100°C, the device junction temperature must reach
154°C. The actual device, however, turns off the output drive to maintain a safe junction temperature. Figure 7-3
shows how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer
so the output is 3 V. When self heating causes the device junction temperature to increase above 140°C, the
thermal protection forces the output to a high-impedance state and the output is pulled to ground through resistor
RL.
Normal
Operation
3 V
TA = 100°C
16 V
PD = 0.39W
JA = 138.7°C/W
TJ = 138.7°C/W × 0.39W + 100°C
Output
High-Z
ꢀ
0 V
TJ = 154.1°C (expected)
-
150°C
140ºC
TLV9101
+
IOUT = 30 mA
+
3 V
œ
RL
100 Ω
+
VIN
3 V
œ
Figure 7-3. Thermal Protection
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7.3.4 Capacitive Load and Stability
The TLV910x features a resistive output stage capable of driving moderate capacitive loads, and by leveraging
an isolation resistor, the device can easily be configured to drive large capacitive loads. Increasing the gain
enhances the ability of the amplifier to drive greater capacitive loads; see Figure 7-4 and Figure 7-5. The
particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when
establishing whether an amplifier will be stable in operation.
55
50
45
40
35
30
25
20
15
10
5
33
30
27
24
21
18
15
12
9
RISO = 0 W, Positive Overshoot
RISO = 0 W, Negative Overshoot
RISO = 50 W, Positive Overshoot
RISO = 50 W, Negative Overshoot
RISO = 0 W, Positive Overshoot
RISO = 0 W, Negative Overshoot
RISO = 50 W, Positive Overshoot
RISO = 50 W, Negative Overshoot
6
3
0
40
80
120 160 200 240 280 320 360
Cap Load (pF)
0
40
80
120 160 200 240 280 320 360
Cap Load (pF)
C008
C007
Figure 7-4. Small-Signal Overshoot vs Capacitive
Load (100-mV Output Step, G = 1)
Figure 7-5. Small-Signal Overshoot vs Capacitive
Load (100-mV Output Step, G = –1)
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small (10
Ω to 20 Ω) resistor, RISO, in series with the output, as shown in Figure 7-6. This resistor significantly reduces
ringing and maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel
with the capacitive load, then a voltage divider is created, thus introducing a gain error at the output and
slightly reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally
negligible at low output levels. A high capacitive load drive makes the TLV910x well suited for applications such
as reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 7-6 uses an
isolation resistor, RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for
increased phase margin.
+Vs
Vout
Riso
+
Cload
+
Vin
-Vs
œ
Figure 7-6. Extending Capacitive Load Drive With the TLV9101
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7.3.5 Common-Mode Voltage Range
The TLV910x is a 16-V, true rail-to-rail input operational amplifier with an input common-mode range that
extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel
and P-channel differential input pairs, as shown in Figure 7-7. The N-channel pair is active for input voltages
close to the positive rail, typically (V+) – 1 V to 100 mV above the positive supply. The P-channel pair is active
for inputs from 100 mV below the negative supply to approximately (V+) – 2 V. There is a small transition region,
typically (V+) –2 V to (V+) – 1 V in which both input pairs are on. This transition region can vary modestly with
process variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance
can be degraded compared to operation outside this region. To achieve best performance with the TLV910x
family, avoid this transition region when possible.
V+
IN-
PMOS
PMOS
NMOS
IN+
NMOS
V-
Figure 7-7. Rail-to-Rail Input Stage
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7.3.6 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but can involve the supply voltage pins or even
the output pin. Each of these different pin functions have electrical stress limits determined by the voltage
breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to
the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them
from accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 7-8 shows an illustration of the ESD circuits contained in the TLV910x (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device
or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain
inactive during normal circuit operation.
TVS
RF
+VS
VDD
TLV960x
100 Ω
100 Ω
R1
RS
INœ
œ
IN+
+
Power-Supply
ESD Cell
RL
ID
+
VIN
œ
VSS
œVS
TVS
Figure 7-8. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
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An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit
(labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent damage caused by turning
on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting resistors and
TVS diodes allows for the use of device ESD diodes to protect against EOS events.
7.3.7 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to
a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds
the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the TLV910x is approximately 1 µs.
7.3.8 Typical Specifications and Distributions
Designers often have questions about a typical specification of an amplifier in order to design a more robust
circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an
amplifier will exhibit some amount of deviation from the ideal value, like the input offset voltage of an amplifier.
These deviations often follow Gaussian ("bell curve"), or normal distributions, and circuit designers can leverage
this information to guardband their system, even when there is not a minimum or maximum specification in
Section 6.7.
0.00312% 0.13185%
0.13185% 0.00312%
0.00002%
0.00002%
2.145% 13.59% 34.13% 34.13% 13.59% 2.145%
1
1 1 1 1 1 1 1 1
1
1
1
ꢀ-61 ꢀ-51 ꢀ-41 ꢀ-31 ꢀ-21 ꢀ-1
ꢀ+1 ꢀ+21 ꢀ+31 ꢀ+41 ꢀ+51 ꢀ+61
ꢀ
Figure 7-9. Ideal Gaussian Distribution
Figure 7-9 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ,
or sigma, is the standard deviation of a system. For a specification that exhibits this kind of distribution,
approximately two-thirds (68.26%) of all units can be expected to have a value within one standard deviation, or
one sigma, of the mean (from µ–σ to µ+σ).
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Depending on the specification, values listed in the typical column of Section 6.7 are represented in different
ways. As a general rule of thumb, if a specification naturally has a nonzero mean (for example, gain bandwidth),
then the typical value is equal to the mean (µ). However, if a specification naturally has a mean near zero (like
input offset voltage), then the typical value is equal to the mean plus one standard deviation (µ + σ) in order to
most accurately represent the typical value.
You can use this chart to calculate approximate probability of a specification in a unit; for example, for TLV910x,
the typical input voltage offset is 300 µV, so 68.2% of all TLV910x devices are expected to have an offset from
–300 µV to +300 µV. At 4 σ (±1200 µV), 99.9937% of the distribution has an offset voltage less than ±1200 µV,
which means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873 units.
Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits
will be removed from production material. For example, the TLV910x family has a maximum offset voltage of 1.5
mV at 25°C, and even though this corresponds to 5 σ (≈1 in 1.7 million units), which is extremely unlikely, TI
assures that any unit with larger offset than 1.5 mV will be removed from production material.
For specifications with no value in the minimum or maximum column, consider selecting a sigma value of
sufficient guardband for your application, and design worst-case conditions using this value. For example, the
6-σ value corresponds to about 1 in 500 million units, which is an extremely unlikely chance and can be an
option as a wide guardband to design a system around. In this case, the TLV910x family does not have a
maximum or minimum for offset voltage drift, but based on Figure 6-2 and the typical value of 0.6 µV/°C in
Section 6.7, it can be calculated that the 6-σ value for offset voltage drift is about 3.6 µV/°C. When designing for
worst-case system conditions, this value can be used to estimate the worst possible offset across temperature
without having an actual minimum or maximum value.
However, process variation and adjustments over time can shift typical means and standard deviations, and
unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a
device. This information should be used only to estimate the performance of a device.
7.3.9 Packages With an Exposed Thermal Pad
The TLV910x family is available in packages such as the WSON-8 (DSG) and WQFN-16 (RTE), which feature
an exposed thermal pad. Inside the package, the die is attached to this thermal pad using an electrically
conductive compound. For this reason, when using a package with an exposed thermal pad, the thermal pad
must either be connected to V– or left floating. Attaching the thermal pad to a potential other than V– is not
allowed, and performance of the device is not assured when doing so.
7.3.10 Shutdown
The TLV910xS devices feature one or more shutdown pins (SHDN) that disable the op amp, placing it into a
low-power standby mode. In this mode, the op amp typically consumes about 20 µA. The SHDN pins are active
high, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic high.
The SHDN pins are referenced to the negative supply rail of the op amp. The threshold of the shutdown feature
lies around 800 mV (typical) and does not change with respect to the supply voltage. Hysteresis has been
included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown
behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage
between V– and V– + 0.2 V. A valid logic high is defined as a voltage between V– + 1.1 V and V+. The shutdown
pin circuitry includes a pulldown resistor, which will inherently pull the voltage of the pin to the negative supply
rail if not driven. Thus, to enable the amplifier, the SHDN pins should either be left floating or driven to a valid
logic low. To disable the amplifier, the SHDN pins must be driven to a valid logic high. The maximum voltage
allowed at the SHDN pins is V+ or V– + 20 V, whichever is lower. Exceeding this voltage level will damage the
device.
The SHDN pins are high-impedance CMOS inputs. Channels of single and dual op amp packages are
independently controlled, and channels of quad op amp packages are controlled in pairs. For battery-operated
applications, this feature can be used to greatly reduce the average current and extend battery life. The
typical enable time out of shutdown is 30 µs; disable time is 3 µs. When disabled, the output assumes a
high-impedance state. This architecture allows the TLV910xS family to operate as a gated amplifier, multiplexer,
or programmable-gain amplifier. Shutdown time (tOFF) depends on loading conditions and increases as load
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resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load
to midsupply (VS / 2) is required. If using the TLV910xS without a load, the resulting turnoff time significantly
increases.
7.4 Device Functional Modes
The TLV910x has a single functional mode and is operational when the power-supply voltage is greater than 2.7
V (±1.35 V). The maximum power supply voltage for the TLV910x is 16 V (±8 V).
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TLV910x family offers excellent DC precision and DC performance. These devices operate up to 16-V
supply rails and offer true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as 1.1-MHz
bandwidth and high output drive. These features make the TLV910x a robust, high-performance operational
amplifier for high-voltage industrial applications.
8.2 Typical Applications
8.2.1 High Voltage Precision Comparator
Many different systems require controlled voltages across numerous system nodes to ensure robust operation.
A comparator can be used to monitor and control voltages by comparing a reference threshold voltage with an
input voltage and providing an output when the input crosses this threshold.
The TLV910x family of op amps make excellent high voltage, precision comparators due to their robust input
stage, low typical offset, and high slew rate. Previous generation high-voltage op amps often use back-to-back
diodes across the inputs to prevent damage to the op amp which greatly limits these op amps to be used as
comparators, but the patented input stage of the TLV910x allows the device to have a wide differential voltage
between the inputs.
V+
+
VIN
VOUT
VTH
V+
R1
R2
Figure 8-1. Typical Comparator Application
8.2.1.1 Design Requirements
The primary objective is to design a 15-V precision comparator.
•
•
•
•
•
•
System supply voltage (V+): 15 V
Resistor 1 value: 100 kΩ
Resistor 2 value: 100 kΩ
Reference threshold voltage (VTH): 7.5 V
Input voltage range (VIN): 2.5 V – 12.5 V
Output voltage range (VOUT): 0 V – 15 V
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8.2.1.2 Detailed Design Procedure
This noninverting comparator circuit applies the input voltage (VIN) to the noninverting terminal of the op amp.
Two resistors (R1 and R2) divide the supply voltage (V+) to create a mid-supply threshold voltage (VTH) as
calculated in Equation 1. The circuit is shown in Figure 8-1. When VIN is less then VTH, the output voltage
transitions to the negative supply and equals the low-level output voltage. When VIN is greater than VTH, the
output voltage transitions to the positive supply and equals the high-level output voltage.
In this example, resistor 1 and 2 have been selected to be 100 kΩ, which sets the reference threshold at 7.5 V.
However, resistor 1 and 2 can be adjusted to modify the threshold using Equation 1. The values of resistor 1 and
2 have also been selected to reduce power consumption, but these values can be further increased to reduce
power consumption, or reduced to improve noise performance.
R
2
V
=
ìV+
2
TH
R + R
1
(1)
8.2.1.3 Application Curve
16
14
12
10
8
Input
Output
6
4
2
0
-2
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Time (ms)
2
comp
Figure 8-2. Comparator Output Response to Input Voltage
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9 Power Supply Recommendations
The TLV910x is specified for operation from 2.7 V to 16 V (±1.35 V to ±8 V); many specifications apply from
–40°C to 125°C.
CAUTION
Supply voltages larger than 20 V can permanently damage the device; see Section 6.1.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high-impedance power supplies. For more detailed information on bypass capacitor placement, refer to Section
10.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. As illustrated in Figure 10-2, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
VIN
+
VOUT
RG
RF
Figure 10-1. Schematic Representation
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Place components close
to device and to each
other to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
NC
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
œIN
+IN
Vœ
V+
OUTPUT
NC
VIN
GND
GND
VSœ
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 10-2. Operational Amplifier Board Layout for Noninverting Configuration
GND
GND
OUT
V-
GND
Figure 10-3. Example Layout for SC70 (DCK) Package
GND
GND
GND
V+
INPUT A
OUTPUT B
V-
GND
GND
GND
Figure 10-4. Example Layout for VSSOP-8 (DGK) Package
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GND
GND
GND
-
+
OUT B
+
-
+IN A
GND
GND
GND
Figure 10-5. Example Layout for WSON-8 (DSG) Package
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional DC, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
Note
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
11.2 Documentation Support
11.2.1 Related Documentation
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application report
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TINA-TI™ are trademarks of Texas Instruments, Inc and DesignSoft, Inc.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: TLV9101 TLV9102 TLV9104
TLV9101, TLV9102, TLV9104
SBOS943D – FEBRUARY 2019 – REVISED JUNE 2021
www.ti.com
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
38
Submit Document Feedback
Product Folder Links: TLV9101 TLV9102 TLV9104
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jun-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV9101IDBVR
TLV9101IDCKR
TLV9101SIDBVR
TLV9102IDDFR
TLV9102IDR
ACTIVE
ACTIVE
ACTIVE
SOT-23
SC70
DBV
DCK
DBV
DDF
D
5
5
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
2000 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
T91V
1FO
SN
SOT-23
6
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAUAG
NIPDAUAG
NIPDAU
SN
T91S
T91F
ACTIVE SOT-23-THIN
8
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
WSON
TSSOP
VSSOP
X2QFN
SOIC
8
T9102D
TLV9102IDSGR
TLV9102IPWR
TLV9102SIDGSR
TLV9102SIRUGR
TLV9104IDR
DSG
PW
8
T912
8
T9102P
DGS
RUG
D
10
10
14
14
T910
HBF
TLV9104D
TLV9104IPWR
TSSOP
PW
(PTL91PW, TLV91PW)
TLV9104IRTER
TLV9104IRUCR
TLV9104SIRTER
ACTIVE
ACTIVE
ACTIVE
WQFN
QFN
RTE
RUC
RTE
16
14
16
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
T91RT
FOF
-40 to 125
-40 to 125
WQFN
T9104S
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jun-2021
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jun-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV9101IDBVR
TLV9101IDCKR
TLV9101SIDBVR
TLV9102IDDFR
SOT-23
SC70
DBV
DCK
DBV
DDF
5
5
6
8
3000
3000
3000
3000
180.0
178.0
180.0
180.0
8.4
9.0
8.4
8.4
3.2
2.4
3.2
3.2
3.2
2.5
3.2
3.2
1.4
1.2
1.4
1.4
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
SOT-23
SOT-
23-THIN
TLV9102IDR
TLV9102IDSGR
TLV9102IPWR
TLV9102SIDGSR
TLV9102SIRUGR
TLV9104IDR
SOIC
WSON
TSSOP
VSSOP
X2QFN
SOIC
D
8
2500
3000
2000
2500
3000
2500
2000
3000
3000
3000
330.0
180.0
330.0
330.0
178.0
330.0
330.0
330.0
180.0
330.0
12.4
8.4
6.4
2.3
7.0
5.3
1.75
6.5
6.9
3.3
2.16
3.3
5.2
2.3
3.6
3.4
2.25
9.0
5.6
3.3
2.16
3.3
2.1
1.15
1.6
1.4
0.56
2.1
1.6
1.1
0.5
1.1
8.0
4.0
8.0
8.0
4.0
8.0
8.0
8.0
4.0
8.0
12.0
8.0
Q1
Q2
Q1
Q1
Q1
Q1
Q1
Q2
Q2
Q2
DSG
PW
8
8
12.4
12.4
8.4
12.0
12.0
8.0
DGS
RUG
D
10
10
14
14
16
14
16
16.4
12.4
12.4
9.5
16.0
12.0
12.0
8.0
TLV9104IPWR
TLV9104IRTER
TLV9104IRUCR
TLV9104SIRTER
TSSOP
WQFN
QFN
PW
RTE
RUC
RTE
WQFN
12.4
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jun-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV9101IDBVR
TLV9101IDCKR
TLV9101SIDBVR
TLV9102IDDFR
TLV9102IDR
SOT-23
SC70
DBV
DCK
DBV
DDF
D
5
5
3000
3000
3000
3000
2500
3000
2000
2500
3000
2500
2000
3000
3000
3000
210.0
190.0
210.0
210.0
853.0
210.0
853.0
366.0
205.0
853.0
366.0
367.0
205.0
367.0
185.0
190.0
185.0
185.0
449.0
185.0
449.0
364.0
200.0
449.0
364.0
367.0
200.0
367.0
35.0
30.0
35.0
35.0
35.0
35.0
35.0
50.0
33.0
35.0
50.0
35.0
30.0
35.0
SOT-23
SOT-23-THIN
SOIC
6
8
8
TLV9102IDSGR
TLV9102IPWR
TLV9102SIDGSR
TLV9102SIRUGR
TLV9104IDR
WSON
TSSOP
VSSOP
X2QFN
SOIC
DSG
PW
8
8
DGS
RUG
D
10
10
14
14
16
14
16
TLV9104IPWR
TLV9104IRTER
TLV9104IRUCR
TLV9104SIRTER
TSSOP
WQFN
QFN
PW
RTE
RUC
RTE
WQFN
Pack Materials-Page 2
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.4
0.2
8X
0.1
C A
B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/B 11/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/B 11/2015
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/B 11/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.32
0.18
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
(0.2) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
8X
0.4
0.2
PIN 1 ID
8X
0.1
C A B
C
0.05
4218900/D 04/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/D 04/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/D 04/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
8
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
SEATING PLANE
TYP
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
5
1
3.1
2.9
NOTE 3
2X
1.95
4
0.30
0.19
8X
4.5
4.3
1.2 MAX
B
0.1
C A
B
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 - 8
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
8X (0.45)
(R0.05)
1
4
TYP
8
SYMM
6X (0.65)
5
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
(R0.05) TYP
8X (0.45)
1
4
8
SYMM
6X (0.65)
5
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
X2QFN - 0.4 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RUC0014A
A
2.1
1.9
B
2.1
1.9
PIN 1 INDEX AREA
0.4 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
(0.15) TYP
2X 0.4
6
7
8X 0.4
5
8
SYMM
1.6
12
1
0.25
0.15
14
13
14X
0.5
PIN 1 ID
SYMM
(45oX0.1)
0.1
C A B
C
14X
0.3
0.05
4220584/A 05/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
X2QFN - 0.4 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RUC0014A
SYMM
14X (0.6)
14X (0.2)
8X (0.4)
SYMM
(1.6) (1.8)
(R0.05)
2X (0.4)
(1.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 23X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220584/A 05/2019
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
X2QFN - 0.4 mm max height
RUC0014A
PLASTIC QUAD FLAT PACK- NO LEAD
SYMM
14X (0.6)
14X (0.2)
8X (0.4)
SYMM
(1.6) (1.8)
(R0.05)
2X (0.4)
(1.8)
SOLDER PASTE EXAMPLE
BASED ON 0.100mm THICK STENCIL
SCALE: 23X
4220584/A 05/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Copyright © 2021, Texas Instruments Incorporated
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