TLV9152-Q1_V01 [TI]
TLV915x-Q1 4.5-MHz, Rail-to-Rail Input/Output, Low Offset Voltage, Low Noise Automotive Op Amp;
| 型号： | TLV9152-Q1_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TLV915x-Q1 4.5-MHz, Rail-to-Rail Input/Output, Low Offset Voltage, Low Noise Automotive Op Amp |
| 文件： | 总41页 (文件大小：2250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV9152-Q1, TLV9154-Q1
SBOSA23A – MAY 2020 – REVISED JANUARY 2021
TLV915x-Q1 4.5-MHz, Rail-to-Rail Input/Output, Low Offset Voltage, Low Noise
Automotive Op Amp
1 Features
3 Description
•
AEC-Q100 qualified for automotive applications
– Temperature grade 1: –40°C to +125°C, TA
– Device HBM ESD classification level 3A
– Device CDM ESD classification level C6
Low offset voltage: ±125 µV
Low offset voltage drift: ±0.3 µV/°C
Low noise: 10.8 nV/√ Hz at 1 kHz
High common-mode rejection: 120 dB
Low bias current: ±10 pA
Rail-to-rail input and output
Wide bandwidth: 4.5-MHz GBW
High slew rate: 20 V/µs
Low quiescent current: 560 µA per amplifier
Wide supply: ±1.35 V to ±8 V, 2.7 V to 16 V
Robust EMIRR performance: EMI/RFI filters on
input pins
Differential and common-mode input voltage range
to supply rail
The TLV915x-Q1 family (TLV9151-Q1, TLV9152-Q1,
and TLV9154-Q1) is a family of 16-V, general purpose
automotive operational amplifiers. These devices offer
exceptional DC precision and AC performance,
including rail-to-rail output, low offset (±125 µV, typ),
low offset drift (±0.3 µV/°C, typ), and 4.5-MHz
bandwidth.
•
•
•
•
•
•
•
•
•
•
•
Convenient features such as wide differential input-
voltage range, high output current (±75 mA), high
slew rate (20 V/μs), and low noise (10.8 nV/√Hz)
make the TLV915x-Q1 a robust, low-noise operational
amplifier for automotive applications.
The TLV915x-Q1 family of op amps is available in
standard packages and is specified from –40°C to
125°C.
Device Information
PACKAGE
SOT-23 (5)(2)
PART NUMBER(1)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
4.90 mm × 3.90 mm
3.00 mm × 3.00 mm
8.65 mm × 3.90 mm
4.20 mm × 1.90 mm
5.00 mm × 4.40 mm
•
TLV9151-Q1
SOIC (8)(2)
2 Applications
TLV9152-Q1
TLV9154-Q1
VSSOP (8)(2)
SOIC (14)(2)
SOT-23 (14)(2)
TSSOP (14)(2)
•
•
•
•
•
•
•
•
•
Optimized for AEC-Q100 grade 1 applications
Infotainment and cluster
Passive safety
Body electronics and lighting
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
HEV/EV inverter and motor control
On-board (OBC) and wireless charger
Powertrain current sensor
Advanced driver assistance systems (ADAS)
High-side and low-side current sensing
(2) This package is preview only.
RG
RF
R1
VOUT
VIN
C1
1
2pR1C1
f
=
-3 dB
VOUT
VIN
RF
1
1 + sR1C1
=
1 +
(
(
RG
TLV915x-Q1 in a Single-Pole, Low-Pass Filter
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
TLV9152-Q1, TLV9154-Q1
SBOSA23A – MAY 2020 – REVISED JANUARY 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings ....................................... 6
6.2 ESD Ratings .............................................................. 6
6.3 Recommended Operating Conditions ........................6
6.4 Thermal Information for Single Channel .................... 6
6.5 Thermal Information for Dual Channel .......................7
6.6 Thermal Information for Quad Channel ..................... 7
6.7 Electrical Characteristics ............................................8
6.8 Typical Characteristics..............................................10
7 Detailed Description......................................................18
7.1 Overview...................................................................18
7.2 Functional Block Diagram.........................................18
7.3 Feature Description...................................................19
7.4 Device Functional Modes..........................................27
8 Application and Implementation..................................28
8.1 Application Information............................................. 28
8.2 Typical Applications.................................................. 28
9 Power Supply Recommendations................................30
10 Layout...........................................................................31
10.1 Layout Guidelines................................................... 31
10.2 Layout Example...................................................... 32
11 Device and Documentation Support..........................33
11.1 Device Support........................................................33
11.2 Documentation Support.......................................... 33
11.3 Receiving Notification of Documentation Updates..33
11.4 Support Resources................................................. 33
11.5 Trademarks............................................................. 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (May 2020) to Revision A (January 2021)
Page
•
•
Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Updated the Electrical Characteristics table in the Specifications section per additional test data.................... 6
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5 Pin Configuration and Functions
OUT
Vœ
1
2
3
5
V+
IN+
4
INœ
Not to scale
A. Package is preview only.
Figure 5-1. TLV9151-Q1 DBV Package(A)
5-Pin SOT-23
Top View
Table 5-1. Pin Functions: TLV9151-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
3
IN+
IN–
OUT
V+
I
Noninverting input
4
I
Inverting input
1
O
—
—
Output
5
Positive (highest) power supply
Negative (lowest) power supply
V–
2
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OUT1
IN1œ
IN1+
Vœ
1
2
3
4
8
7
6
5
V+
OUT2
IN2œ
IN2+
Not to scale
A. D and DGK packages are preview only.
Figure 5-2. TLV9152-Q1 D and DGK Package(A)
8-Pin SOIC and VSSOP
Top View
Table 5-2. Pin Functions: TLV9152-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
3
IN1+
IN2+
IN1–
IN2–
OUT1
OUT2
V+
I
I
Noninverting input, channel 1
Noninverting input, channel 2
Inverting input, channel 1
Inverting input, channel 2
Output, channel 1
5
2
I
6
I
1
O
O
—
—
7
Output, channel 2
8
Positive (highest) power supply
Negative (lowest) power supply
V–
4
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OUT1
IN1œ
IN1+
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT4
IN4œ
IN4+
Vœ
IN2+
IN2œ
OUT2
IN3+
IN3œ
OUT3
8
Not to scale
A. D, DYY, and PW packages are preview only.
Figure 5-3. TLV9154-Q1 D, DYY, and PW Package(A)
14-Pin SOIC, SOT-23, and TSSOP
Top View
Table 5-3. Pin Functions: TLV9154-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
3
IN1+
IN1–
IN2+
IN2–
IN3+
IN3–
IN4+
IN4–
NC
I
I
Noninverting input, channel 1
Inverting input, channel 1
Noninverting input, channel 2
Inverting input, channel 2
Noninverting input, channel 3
Inverting input, channel 3
Noninverting input, channel 4
Inverting input, channel 4
Do not connect
2
5
I
6
I
10
9
I
I
12
13
—
1
I
I
—
O
O
O
O
—
—
OUT1
OUT2
OUT3
OUT4
V+
Output, channel 1
7
Output, channel 2
8
Output, channel 3
14
4
Output, channel 4
Positive (highest) power supply
Negative (lowest) power supply
V–
11
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
MIN
0
MAX
20
UNIT
V
Supply voltage, VS = (V+) – (V–)
Common-mode voltage (3)
(V–) – 0.5
(V+) + 0.5
VS + 0.2
10
V
Signal input pins
Differential voltage (3)
Current (3)
V
–10
–55
–65
mA
Output short-circuit (2)
Continuous
Operating ambient temperature, TA
Junction temperature, TJ
150
150
150
°C
°C
°C
Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Short-circuit to ground, one amplifier per package.
(3) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
2.7
MAX
UNIT
VS
VI
Supply voltage, (V+) – (V–)
Input voltage range
16
(V+) + 0.1
125
V
V
(V–) – 0.1
–40
TA
Specified temperature
°C
6.4 Thermal Information for Single Channel
TLV9151-Q1
DBV (2)
(SOT-23)
THERMAL METRIC (1)
UNIT
5 PINS
TBD
TBD
TBD
TBD
TBD
TBD
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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(2) This package option is preview for TLV9151.
6.5 Thermal Information for Dual Channel
TLV9152-Q1
D(2)
(SOIC)
DGK (2)
(VSSOP)
THERMAL METRIC (1)
Unit
8 PINS
TBD
TBD
TBD
TBD
TBD
TBD
8 PINS
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
176.5
68.1
98.2
12.0
96.7
N/A
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) This package option is preview for TLV9152.
6.6 Thermal Information for Quad Channel
TLV9154-Q1
D (2)
(SOIC)
DYY (2)
(SOT-23)
PW (2)
(TSSOP)
THERMAL METRIC (1)
UNIT
14 PINS
TBD
14 PINS
110.7
55.9
14 PINS
118.0
47.6
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
RθJC(top)
RθJB
TBD
°C/W
°C/W
°C/W
°C/W
°C/W
TBD
35.3
60.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
TBD
2.3
6.0
ψJB
TBD
35.1
60.4
RθJC(bot)
TBD
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) This package option is preview for TLV9154.
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6.7 Electrical Characteristics
For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VO UT
= VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
±125
±895
±925
VOS
Input offset voltage
VCM = V–
µV
TA = –40°C to 125°C
Input offset voltage
drift
dVOS/dT
PSRR
TA = –40°C to 125°C
TA = –40°C to 125°C
±0.3
µV/℃
VCM = V–, VS = 4 V to 16 V
VCM = V–, VS = 2.7 V to 16 V(1)
f = 0 Hz
±0.3
±1
5
±1
±5
Input offset voltage
versus power supply
μV/V
µV/V
Channel separation
INPUT BIAS CURRENT
IB
Input bias current
±10
±10
pA
pA
IOS
Input offset current
NOISE
1.8
0.3
10.8
9.4
2
μVPP
EN
Input voltage noise
f = 0.1 Hz to 10 Hz
µVRMS
f = 1 kHz
f = 10 kHz
f = 1 kHz
Input voltage noise
density
eN
iN
nV/√Hz
fA/√Hz
Input current noise
INPUT VOLTAGE RANGE
Common-mode
VCM
(V–) –
0.1
(V+) +
0.1
V
voltage range
VS = 16 V, (V–) – 0.1 V < VCM
(V+) – 2 V (Main input pair)
<
107
82
130
100
95
VS = 4 V, (V–) – 0.1 V < VCM
(V+) – 2 V (Main input pair)
<
Common-mode
CMRR
TA = –40°C to 125°C
dB
VS = 2.7 V, (V–) – 0.1 V < VCM
< (V+) – 2 V (Main input pair)(1)
rejection ratio
75
VS = 2.7 V to 16 V, (V+) – 1 V <
VCM < (V+) + 0.1 V (Aux input
pair)
85
INPUT CAPACITANCE
ZID
Differential
100 || 9
6 || 1
MΩ || pF
TΩ || pF
ZICM
Common-mode
OPEN-LOOP GAIN
VS = 16 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1
V
120
104
101
145
142
130
125
120
118
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
VS = 4 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1
V
Open-loop voltage
gain
AOL
dB
VS = 2.7 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1
V(1)
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6.7 Electrical Characteristics (continued)
For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VO UT
= VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
Gain-bandwidth
product
GBW
4.5
MHz
V/μs
SR
Slew rate
VS = 16 V, G = +1, CL = 20 pF
20
2.5
1.5
2
To 0.01%, VS = 16 V, VSTEP = 10 V , G = +1, CL = 20 pF
To 0.01%, VS = 16 V, VSTEP = 2 V , G = +1, CL = 20 pF
To 0.1%, VS = 16 V, VSTEP = 10 V , G = +1, CL = 20 pF
To 0.1%, VS = 16 V, VSTEP = 2 V , G = +1, CL = 20 pF
G = +1, RL = 10 kΩ
tS
Settling time
μs
1
Phase margin
60
°
Overload recovery
time
VIN × gain > VS
600
ns
Total harmonic
distortion + noise
THD+N
VS = 16 V, VO = 3 VRMS, G = 1, f = 1 kHz
0.00021%
OUTPUT
VS = 16 V, RL = no
load(1)
5
10
VS = 16 V, RL = 10 kΩ
50
55
VS = 16 V, RL = 2 kΩ
200
250
Voltage output swing Positive and negative rail
mV
from rail
headroom
VS = 2.7 V, RL = no
load(1)
1
6
VS = 2.7 V, RL = 10 kΩ
VS = 2.7 V, RL = 2 kΩ
5
25
12
40
ISC
Short-circuit current
Capacitive load drive
±75
1000
mA
pF
CLOAD
Open-loop output
impedance
ZO
f = 1 MHz, IO = 0 A
525
Ω
POWER SUPPLY
560
685
735
Quiescent current per
amplifier
IQ
IO = 0 A
µA
TA = –40°C to 125°C
(1) Specified by characterization only.
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6.8 Typical Characteristics
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
33
30
27
24
21
18
15
12
9
50
40
30
20
10
0
6
3
0
D001
D002
Offset Voltage Drift (µV/C)
Offset Voltage (µV)
Distribution from 60 amplifiers
Distribution from 15462 amplifiers, TA = 25°C
Figure 6-2. Offset Voltage Drift Distribution
Figure 6-1. Offset Voltage Production Distribution
900
400
300
200
100
0
700
500
300
100
-100
-300
-500
-700
-900
-100
-200
-300
-400
-40 -20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
D003
D004
VCM = V–
VCM = V+
Figure 6-4. Offset Voltage vs Temperature
Figure 6-3. Offset Voltage vs Temperature
800
600
400
200
0
800
600
400
200
0
-200
-400
-600
-800
-200
-400
-600
-800
-8
-6
-4
-2
0
2
4
6
8
4
4.5
5
5.5
6
6.5
7
7.5
8
VCM
VCM
D005
D005
TA = 25°C
TA = 25°C
Figure 6-5. Offset Voltage vs Common-Mode Voltage
Figure 6-6. Offset Voltage vs Common-Mode Voltage (Transition
Region)
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
800
600
400
200
0
800
600
400
200
0
-200
-400
-600
-800
-200
-400
-600
-800
-8
-6
-4
-2
0
2
4
6
8
-8
-6
-4
-2
0
2
4
6
8
VCM
VCM
D006
D007
TA = 125°C
TA = –40°C
Figure 6-7. Offset Voltage vs Common-Mode Voltage
Figure 6-8. Offset Voltage vs Common-Mode Voltage
100
200
175
150
125
100
75
600
500
400
300
200
100
0
Gain (dB)
Phase (ꢀ)
90
80
70
60
50
40
30
20
10
0
50
25
-100
-200
-300
-400
-500
-600
0
-25
-50
-75
-10
-20
100
-100
10M
1k
10k
100k
1M
Frequency (Hz)
2
4
6
8
10
12
14
16
18
C002
Supply Voltage (V)
D008
CL = 20 pF
Figure 6-9. Offset Voltage vs Power Supply
Figure 6-10. Open-Loop Gain and Phase vs Frequency
80
70
60
50
40
30
20
10
0
6
4.5
3
G = ꢀ1
G = 1
G = 10
G = 100
G = 1000
1.5
0
-1.5
-3
-4.5
IBꢀ
IB+
IOS
-6
-10
-20
-7.5
-8 -7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
8
100
1k
10k
100k
1M
10M
Common Mode Voltage (V)
Frequency (Hz)
D010
C001
Figure 6-12. Input Bias Current vs Common-Mode Voltage
Figure 6-11. Closed-Loop Gain vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
V+
V+ ꢀ 1 V
V+ ꢀ 2 V
V+ ꢀ 3 V
V+ ꢀ 4 V
V+ ꢀ 5 V
V+ ꢀ 6 V
V+ ꢀ 7 V
V+ ꢀ 8 V
V+ ꢀ 9 V
V+ ꢀ 10 V
150
125
100
75
IBꢀ
IB+
IOS
50
25
0
-25
-50
-75
-100
-40°C
25°C
125°C
0
10
20
30
40
50
60
70
80
90 100
-40
-20
0
20
40
60
80
100 120 140
Output Current (mA)
D012
Temperature (°C)
D011
Figure 6-14. Output Voltage Swing vs Output Current (Sourcing)
Figure 6-13. Input Bias Current vs Temperature
Vꢀ + 8 V
135
-40°C
25°C
125°C
CMRR
PSRR+
PSRRꢀ
120
Vꢀ + 7 V
Vꢀ + 6 V
Vꢀ + 5 V
Vꢀ + 4 V
Vꢀ + 3 V
Vꢀ + 2 V
Vꢀ + 1 V
Vꢀ
105
90
75
60
45
30
15
0
0
10
20
30
40
50
60
70
80
90 100
Output Current (mA)
100
1k
10k
100k
1M
10M
D012
Frequency (Hz)
C003
Figure 6-15. Output Voltage Swing vs Output Current (Sinking)
Figure 6-16. CMRR and PSRR vs Frequency
135
130
125
120
170
165
160
155
150
145
140
115
PMOS (VCM ꢀ V+ ꢁ 1.5 V)
110
NMOS (VCM V+ ꢁ 1.5 V)
105
100
95
90
85
-40
-20
0
20
40
60
80
100 120 140
-40 -20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
D015
D016
f = 0 Hz
Figure 6-17. CMRR vs Temperature (dB)
f = 0 Hz
Figure 6-18. PSRR vs Temperature (dB)
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
1
0.8
0.6
0.4
0.2
0
200
100
10
-0.2
-0.4
-0.6
-0.8
-1
1
1
10
100
1k
10k
100k
Time (1s/div)
Frequency (Hz)
C017
C019
Figure 6-20. Input Voltage Noise Spectral Density vs Frequency
-20
Figure 6-19. 0.1-Hz to 10-Hz Noise
-32
-40
RL = 10 kꢀ
-30
-40
RL = 2 kꢀ
RL = 604 ꢀ
RL = 128 ꢀ
-48
-56
-50
-64
-60
-72
-70
-80
-80
-88
-90
-96
RL = 10 kꢀ
RL = 2 kꢀ
RL = 604 ꢀ
RL = 128 ꢀ
-100
-110
-104
-112
100
1k
10k
-120
C0121m
Frequency (Hz)
10m
100m
1
10
Amplitude (Vrms)
BW = 80 kHz, VOUT = 1 VRMS
C023
BW = 80 kHz, f = 1 kHz
Figure 6-22. THD+N vs Output Amplitude
Figure 6-21. THD+N Ratio vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
580
570
560
550
540
530
520
510
500
490
480
700
675
650
625
600
575
550
525
500
475
450
2
4
6
8
10
12
14
16
18
-40
-20
0
20
40
60
80
100 120 140
Supply Voltage (V)
Temperature (°C)
D021
D022
Figure 6-24. Quiescent Current vs Temperature
VCM = V–
Figure 6-23. Quiescent Current vs Supply Voltage
700
140
135
130
125
120
115
VS = 4 V
VS = 16 V
650
600
550
500
450
400
350
300
250
200
150
100
1k
10k
100k
1M
10M
Frequency (Hz)
-40
-20
0
20
40
60
80
100 120 140
C013
Temperature (°C)
D023
Figure 6-26. Open-Loop Output Impedance vs Frequency
Figure 6-25. Open-Loop Voltage Gain vs Temperature (dB)
60
80
70
60
50
40
30
50
40
30
20
20
RISO = 0 ꢀ, Positive Overshoot
RISO = 0 ꢀ, Positive Overshoot
RISO = 0 ꢀ, Negative Overshoot
RISO = 50 ꢀ, Positive Overshoot
RISO = 50 ꢀ, Negative Overshoot
RISO = 0 ꢀ, Negative Overshoot
10
0
10
0
RISO = 50 ꢀ, Positive Overshoot
RISO = 50 ꢀ, Negative Overshoot
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Cap Load (pF)
Cap Load (pF)
C007
C008
G = –1, 10-mV output step
G = 1, 10-mV output step
Figure 6-27. Small-Signal Overshoot vs Capacitive Load
Figure 6-28. Small-Signal Overshoot vs Capacitive Load
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
60
Input
Output
50
40
30
20
10
Time (20us/div)
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Cap Load (pF)
C016
C018
C011
C009
Figure 6-29. Phase Margin vs Capacitive Load
VIN = ±8 V; VS = VOUT = ±17 V
Figure 6-30. No Phase Reversal
Input
Output
Input
Output
Time (100ns/div)
Time (100ns/div)
C018
G = –10
G = –10
Figure 6-31. Positive Overload Recovery
Figure 6-32. Negative Overload Recovery
Input
Output
Input
Output
Time (300ns/div)
Time (1µs/div)
C010
CL = 20 pF, G = 1, 20-mV step response
CL = 20 pF, G = 1, 20-mV step response
Figure 6-34. Small-Signal Step Response, Falling
Figure 6-33. Small-Signal Step Response, Rising
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
Input
Output
Input
Output
Time (300ns/div)
Time (300ns/div)
C005
C005
CL = 20 pF, G = 1
CL = 20 pF, G = 1
Figure 6-35. Large-Signal Step Response (Rising)
Figure 6-36. Large-Signal Step Response (Falling)
100
80
60
Input
Output
40
20
Sourcing
Sinking
0
-20
-40
-60
-80
-100
Time (2µs/div)
-40 -20
0
20
40
60
80
100 120 140
Temperature (°C)
C021
D014
Figure 6-38. Short-Circuit Current vs Temperature
CL = 20 pF, G = –1
Figure 6-37. Large-Signal Step Response
20
18
16
14
12
10
8
-50
VS = 15 V
VS = 2.7 V
-60
-70
-80
-90
-100
-110
-120
-130
6
4
2
0
1k
100
1k
10k
100k
1M
10M
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
C014
C020
Figure 6-40. Channel Separation vs Frequency
Figure 6-39. Maximum Output Voltage vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
110
100
90
80
70
60
50
40
1M
10M
100M
1G
Frequency (Hz)
C004
Figure 6-41. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency
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7 Detailed Description
7.1 Overview
The TLV915x-Q1 family (TLV9151x-Q1, TLV9152x-Q1, and TLV9154x-Q1) is a family of 16-V general purpose
operational amplifiers.
These devices offer excellent DC precision and AC performance, including rail-to-rail input/output, low offset
(±125 µV, typ), low offset drift (±0.3 µV/°C, typ), and 4.5-MHz bandwidth.
Wide differential and common-mode input-voltage range, high output current (±80 mA), high slew rate (20 V/µs),
low power operation (560 µA, typ) and shutdown functionality make the TLV915x-Q1 a robust, high-speed, high-
performance operational amplifier for industrial applications.
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINÛ
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
VÛ
(Ground)
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7.3 Feature Description
7.3.1 EMI Rejection
The TLV915x-Q1 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the TLV915x-Q1 benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure
7-1 shows the results of this testing on the TLV915x-Q1 . Table 7-1 shows the EMIRR IN+ values for the
TLV915x-Q1 at particular frequencies commonly encountered in real-world applications. The EMI Rejection
Ratio of Operational Amplifiers application report contains detailed information on the topic of EMIRR
performance as it relates to op amps and is available for download from www.ti.com.
100
90
80
70
60
50
40
30
1M
10M
100M
Frequency (Hz)
1G
C004
Figure 7-1. EMIRR Testing
Table 7-1. TLV9151-Q1 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
400 MHz
59.5 dB
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
5 GHz
68.9 dB
77.8 dB
78.0 dB
88.8 dB
87.6 dB
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
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7.3.2 Thermal Protection
The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This
phenomenon is called self heating. The absolute maximum junction temperature of the TLV915x-Q1 is 150°C.
Exceeding this temperature causes damage to the device. The TLV915x-Q1 has a thermal protection feature
that reduces damage from self heating. The protection works by monitoring the temperature of the device and
turning off the op amp output drive for temperatures above 170°C. Figure 7-2 shows an application example for
the TLV9151-Q1 that has significant self heating because of its power dissipation (0.81 W). Thermal calculations
indicate that for an ambient temperature of 65°C, the device junction temperature must reach 177°C. The actual
device, however, turns off the output drive to recover towards a safe junction temperature. Figure 7-2 shows how
the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the output
is 3 V. When self heating causes the device junction temperature to increase above the internal limit, the thermal
protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL. If
the condition that caused excessive power dissipation is not removed, the amplifier will oscillate between a
shutdown and enabled state until the output fault is corrected.
Normal
Operation
3 V
TA = 100°C
16 V
PD = 0.39W
JA = 138.7°C/W
TJ = 138.7°C/W × 0.39W + 100°C
TJ = 154.1°C (expected)
Output
High-Z
0 V
ꢀ
150°C
140ºC
TLV9151
ꢁ
IOUT = 30 mA
+
3 V
–
RL
100
+
–
VIN
3 V
Figure 7-2. Thermal Protection
7.3.3 Capacitive Load and Stability
The TLV915x-Q1 features a resistive output stage capable of driving moderate capacitive loads, and by
leveraging an isolation resistor, the device can easily be configured to drive large capacitive loads. Increasing
the gain enhances the ability of the amplifier to drive greater capacitive loads; see Figure 7-3 and Figure 7-4.
The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider
when establishing whether an amplifier will be stable in operation.
55
50
45
40
35
30
25
20
15
10
5
33
30
27
24
21
18
15
12
9
RISO = 0 W, Positive Overshoot
RISO = 0 W, Negative Overshoot
RISO = 50 W, Positive Overshoot
RISO = 50 W, Negative Overshoot
RISO = 0 W, Positive Overshoot
RISO = 0 W, Negative Overshoot
RISO = 50 W, Positive Overshoot
RISO = 50 W, Negative Overshoot
6
3
0
40
80
120 160 200 240 280 320 360
Cap Load (pF)
0
40
80
120 160 200 240 280 320 360
Cap Load (pF)
C008
C007
Figure 7-3. Small-Signal Overshoot vs Capacitive
Load (10-mV Output Step, G = 1)
Figure 7-4. Small-Signal Overshoot vs Capacitive
Load (10-mV Output Step, G = –1)
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small
resistor, RISO, in series with the output, as shown in Figure 7-5. This resistor significantly reduces ringing and
maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with the
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capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing
the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low
output levels. A high capacitive load drive makes the TLV915x-Q1 well suited for applications such as reference
buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 7-5 uses an isolation resistor,
RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase
margin.
+Vs
Vout
Riso
+
Cload
+
Vin
-Vs
œ
Figure 7-5. Extending Capacitive Load Drive With the TLV9151
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7.3.4 Common-Mode Voltage Range
The TLV915x-Q1 is a 16-V, rail-to-rail input operational amplifier with an input common-mode range that extends
200 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel and P-
channel differential input pairs, as shown in Figure 7-6. The N-channel pair is active for input voltages close to
the positive rail, typically (V+) – 1 V to 100 mV above the positive supply. The P-channel pair is active for inputs
from 100 mV below the negative supply to approximately (V+) – 2 V. There is a small transition region, typically
(V+) – 2 V to (V+) – 1 V in which both input pairs are on. This transition region can vary modestly with process
variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance may be
degraded compared to operation outside this region.
Figure 6-5 shows this transition region for a typical device in terms of input voltage offset in more detail.
For more information on common-mode voltage range and PMOS/NMOS pair interaction, see Op Amps With
Complementary-Pair Input Stages application note.
V+
IN-
PMOS
PMOS
NMOS
IN+
NMOS
V-
Figure 7-6. Rail-to-Rail Input Stage
7.3.5 Phase Reversal Protection
The TLV915x-Q1 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This condition is most often encountered in non-inverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The TLV915x-Q1 is a rail-to-rail input op amp; therefore, the common-mode range
can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits
into the appropriate rail. This performance is shown in Figure 7-7. For more information on phase reversal, see
Op Amps With Complementary-Pair Input Stages application note.
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Input
Output
Time (20us/div)
C016
Figure 7-7. No Phase Reversal
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7.3.6 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage
breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to
the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them
from accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 7-8 shows an illustration of the ESD circuits contained in the TLV915x-Q1 (indicated by the
dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the
input and output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption
device or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to
remain inactive during normal circuit operation.
TVS
RF
+VS
VDD
TLV915x
100
100
R1
RS
IN–
IN+
–
+
Power Supply
ESD Cell
RL
ID
+
–
VIN
VSS
–VS
TVS
Figure 7-8. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event is very short in duration and very high voltage (for example; 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example; 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit
(labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
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7.3.7 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a
linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the TLV915x-Q1 is approximately 500 ns.
7.3.8 Typical Specifications and Distributions
Designers often have questions about a typical specification of an amplifier in order to design a more robust
circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an
amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These
deviations often follow Gaussian ("bell curve"), or normal distributions, and circuit designers can leverage this
information to guardband their system, even when there is not a minimum or maximum specification in the
Section 6.7.
0.00312% 0.13185%
0.13185% 0.00312%
0.010002%
1 1 1 1 1 1 1 1
0.010002%
2.145% 13.59% 34.13% 34.13% 13.59% 2.145%
1
1
ꢀ-61 ꢀ-51 ꢀ-41 ꢀ-31 ꢀ-21 ꢀ-1
ꢀ+1 ꢀ+21 ꢀ+31 ꢀ+41 ꢀ+51 ꢀ+61
ꢀ
Figure 7-9. Ideal Gaussian Distribution
Figure 7-9 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ, or
sigma, is the standard deviation of a system. For a specification that exhibits this kind of distribution,
approximately two-thirds (68.26%) of all units can be expected to have a value within one standard deviation, or
one sigma, of the mean (from µ – σ to µ + σ).
Depending on the specification, values listed in the typical column of the Section 6.7 are represented in different
ways. As a general rule of thumb, if a specification naturally has a nonzero mean (for example, like gain
bandwidth), then the typical value is equal to the mean (µ). However, if a specification naturally has a mean near
zero (like input offset voltage), then the typical value is equal to the mean plus one standard deviation (µ + σ) in
order to most accurately represent the typical value.
You can use this chart to calculate approximate probability of a specification in a unit; for example, for TLV915x-
Q1 , the typical input voltage offset is 125 µV, so 68.2% of all TLV915x-Q1 devices are expected to have an
offset from –125 µV to 125 µV. At 4 σ (±500 µV), 99.9937% of the distribution has an offset voltage less than
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±500 µV, which means 0.0063% of the population is outside of these limits, which corresponds to about 1 in
15,873 units.
Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits
will be removed from production material. For example, the TLV915x-Q1 family has a maximum offset voltage of
675 µV at 25°C, and even though this corresponds to about 5 σ (≈1 in 1.7 million units), which is extremely
unlikely, TI assures that any unit with larger offset than 675 µV will be removed from production material.
For specifications with no value in the minimum or maximum column, consider selecting a sigma value of
sufficient guardband for your application, and design worst-case conditions using this value. For example, the 6-
σ value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be an
option as a wide guardband to design a system around. In this case, the TLV915x-Q1 family does not have a
maximum or minimum for offset voltage drift, but based on Figure 6-2 and the typical value of 0.3 µV/°C in the
Section 6.7, it can be calculated that the 6 σ value for offset voltage drift is about 1.8 µV/°C. When designing for
worst-case system conditions, this value can be used to estimate the worst possible offset across temperature
without having an actual minimum or maximum value.
However, process variation and adjustments over time can shift typical means and standard deviations, and
unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a
device. This information should be used only to estimate the performance of a device.
7.3.9 Packages With an Exposed Thermal Pad
The TLV915x-Q1 family is available in packages such as the WSON-8 (DSG) and WQFN-16 (RTE) which
feature an exposed thermal pad. Inside the package, the die is attached to this thermal pad using an electrically
conductive compound. For this reason, when using a package with an exposed thermal pad, the thermal pad
must either be connected to V– or left floating. Attaching the thermal pad to a potential other than V– is not
allowed, and performance of the device is not assured when doing so.
7.3.10 Shutdown
The TLV915x-Q1 S devices feature one or more shutdown pins (SHDN) that disable the op amp, placing it into a
low-power standby mode. In this mode, the op amp typically consumes about 20 µA. The SHDN pins are active
high, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic high.
The SHDN pins are referenced to the negative supply rail of the op amp. The threshold of the shutdown feature
lies around 800 mV (typical) and does not change with respect to the supply voltage. Hysteresis has been
included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown
behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage
between V– and V– + 0.4 V. A valid logic high is defined as a voltage between V– + 1.2 V and V– + 20 V. The
shutdown pin circuitry includes a pull-down resistor, which will inherently pull the voltage of the pin to the
negative supply rail if not driven. Thus, to enable the amplifier, the SHDN pins should either be left floating or
driven to a valid logic low. To disable the amplifier, the SHDN pins must be driven to a valid logic high. The
maximum voltage allowed at the SHDN pins is V– + 20 V. Exceeding this voltage level will damage the device.
The SHDN pins are high-impedance CMOS inputs. Channels of single and dual op amp packages are
independently controlled, and channels of quad op amp packages are controlled in pairs. For battery-operated
applications, this feature may be used to greatly reduce the average current and extend battery life. The typical
enable time out of shutdown is 30 µs; disable time is 3 µs. When disabled, the output assumes a high-
impedance state. This architecture allows the TLV915x-Q1 S family to operate as a gated amplifier, multiplexer,
or programmable-gain amplifier. Shutdown time (tOFF) depends on loading conditions and increases as load
resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to
midsupply (VS / 2) is required. If using the TLV915x-Q1 S without a load, the resulting turnoff time significantly
increases.
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7.4 Device Functional Modes
The TLV915x-Q1 has a single functional mode and is operational when the power-supply voltage is greater than
2.7 V (±1.35 V). The maximum power supply voltage for the TLV915x-Q1 is 16 V (±8 V).
The TLV915x-Q1 S devices feature a shutdown pin, which can be used to place the op amp into a low-power
mode. See Section 7.3.10 section for more information.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The TLV915x-Q1 family offers excellent DC precision and DC performance. These devices operate up to 16-V
supply rails and offer true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as 4.5-MHz
bandwidth and high output drive. These features make the TLV915x-Q1 a robust, high-performance operational
amplifier for high-voltage industrial applications.
8.2 Typical Applications
8.2.1 Low-Side Current Measurement
Figure 8-1 shows the TLV9151-Q1 configured in a low-side current sensing application. For a full analysis of the
circuit shown in Figure 8-1 including theory, calculations, simulations, and measured data, see TI Precision
Design TIPD129, 0-A to 1-A Single-Supply Low-Side Current-Sensing Solution.
VCC
12 V
LOAD
TLV9151
+
VOUT
–
RSHUNT
ILOAD
100 m
LM7705
RF
360 k
RG
7.5 k
Figure 8-1. TLV9151-Q1 in a Low-Side, Current-Sensing Application
8.2.1.1 Design Requirements
The design requirements for this design are:
•
•
•
Load current: 0 A to 1 A
Output voltage: 4.9 V
Maximum shunt voltage: 100 mV
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8.2.1.2 Detailed Design Procedure
The transfer function of the circuit in Figure 8-1 is given in Equation 1.
VOUT = ILOAD ìRSHUNT ìGain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using Equation 2.
VSHUNT _MAX
100mV
1A
RSHUNT
=
=
=100mW
ILOAD_MAX
(2)
Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the TLV9151-Q1 to produce an output voltage of 0 V to 4.9 V. The gain needed by the TLV9151-Q1
to produce the necessary output voltage is calculated using Equation 3.
V
OUT _MAX - VOUT _MIN
(
)
Gain =
VIN_MAX - V
IN_MIN
(3)
Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 4
is used to size the resistors, RF and RG, to set the gain of the TLV9151-Q1 to 49 V/V.
R
(
)
F
Gain = 1+
R
G
(4)
Choosing RF as 360 kΩ, RG is calculated to be 7.5 kΩ. RF and RG were chosen as 360 kΩ and 7.5 kΩ because
they are standard value resistors that create a 49:1 ratio. Other resistors that create a 49:1 ratio can also be
used. Figure 8-2 shows the measured transfer function of the circuit shown in Figure 8-1.
8.2.1.3 Application Curves
5
4
3
2
1
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
ILOAD (A)
1
Figure 8-2. Low-Side, Current-Sense, Transfer Function
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9 Power Supply Recommendations
The TLV915x-Q1 is specified for operation from 2.7 V to 16 V (±1.35 V to ±8 V); many specifications apply from
–40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in the Section 6.8.
CAUTION
Supply voltages larger than 16 V can permanently damage the device; see the Absolute Maximum
Ratings.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Section
10 section.
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. As illustrated in Figure 10-2, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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10.2 Layout Example
VIN
+
VOUT
RG
RF
Figure 10-1. Schematic Representation
Place components close
to device and to each
other to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
NC
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
œIN
+IN
Vœ
V+
OUTPUT
NC
VIN
GND
GND
VSœ
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 10-2. Operational Amplifier Board Layout for Noninverting Configuration
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
Note
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 TI Precision Designs
The TLV915x-Q1 is featured in several TI Precision Designs, available online at http://www.ti.com/ww/en/analog/
precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications
experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout,
bill of materials, and measured performance of many useful circuits.
11.2 Documentation Support
11.2.1 Related Documentation
Texas Instruments, Analog Engineer's Circuit Cookbook: Amplifiers.
Texas Instruments, AN31 amplifier circuit collection.
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Support Resources
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11.5 Trademarks
TINA-TI™ are trademarks of Texas Instruments, Inc and DesignSoft, Inc.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
All trademarks are the property of their respective owners.
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Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTLV9152QDGKRQ1
PTLV9154QPWRQ1
ACTIVE
VSSOP
TSSOP
DGK
8
2500 RoHS (In work)
& Non-Green
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
ACTIVE
PW
14
2000 RoHS (In work)
& Non-Green
Call TI
TLV9152QDGKRQ1
TLV9154QPWRQ1
PREVIEW
PREVIEW
VSSOP
TSSOP
DGK
PW
8
2500 RoHS & Green
NIPDAU
Call TI
Level-1-260C-UNLIM
Call TI
-40 to 125
-40 to 125
27XT
14
2000 RoHS (In work)
& Non-Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV9152-Q1, TLV9154-Q1 :
Catalog: TLV9152, TLV9154
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
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