TLV9161-Q1 [TI]
汽车类、单通道、16V、11MHz 轨到轨输入和输出运算放大器;
| 型号： | TLV9161-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类、单通道、16V、11MHz 轨到轨输入和输出运算放大器 放大器 运算放大器 |
| 文件： | 总49页 (文件大小：2847K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV9161-Q1, TLV9162-Q1, TLV9164-Q1
ZHCSRZ5 –APRIL 2023
TLV916x-Q1 汽车类16V、11MHz、轨到轨输入或输出、
低失调电压、低噪声运算放大器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准
TLV916x-Q1 系列（TLV9161-Q1、TLV9162-Q1 和
TLV9164-Q1）是16V 通用汽车类运算放大器系列。这
些器件具有出色的直流精度和交流性能，包括轨到轨输
入或输出、低失调电压（±210µV，典型值）、低温漂
（±0.25µV/°C，典型值）和低噪声（1kHz 时为 6.8nV/
√Hz，10kHz 时为4.2nV/√Hz）。
– 温度等级1：–40°C 至+125°C，TA
– 器件HBM ESD 分类等级3A
(≥2500V)
– 器件CDM ESD 分类等级C3
(≥1500V)
• 低失调电压：±210µV
TLV916x-Q1 具有诸多特性，例如宽差分输入电压范
围、高短路电流 (±73mA) 和高压摆率 (33V/µs)，是一
款灵活可靠的高性能运算放大器，适用于汽车应用。
• 低失调电压漂移：±0.25µV/°C
• 低噪声：1kHz 时为6.8nV/√Hz，4.2nV/√Hz 宽带
• 高共模抑制：110dB
TLV916x-Q1 系列运算放大器采用标准封装，额定工作
温度范围为-40°C 至125°C。
• 低偏置电流：±10pA
• 轨至轨输入和输出
• 宽带宽：11MHz GBW，单位增益稳定
• 高压摆率：33V/µs
• 低静态电流：每个放大器2.4mA
• 宽电源电压：±1.35V 至±8V，2.7V 至16V
• 强大的EMIRR 性能
封装信息
器件型号(1)
封装尺寸（标称值）
2.90mm × 1.60mm
2.00mm × 1.25mm
4.90mm × 3.90mm
3.00mm × 3.00mm
8.65mm × 3.90mm
5.00mm × 4.40mm
封装
DBV（SOT-23，5)
DCK（SC70，5）
D（SOIC，8）
TLV9161-Q1
TLV9162-Q1
TLV9164-Q1
2 应用
DGK（VSSOP，8）
D（SOIC，14）
PW（TSSOP，14）
• 针对AEC-Q100 1 级应用进行了优化
• 信息娱乐系统与仪表组
• 被动安全
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 车身电子装置和照明
• 混合动力汽车/电动汽车逆变器和电机控制
• 车载充电器(OBC) 和无线充电器
• 动力总成电流传感器
• 高级驾驶辅助系统(ADAS)
• 高侧和低侧电流检测
TLV916x
+
+
Vshunt Rshunt
+
System
MCU
-
Vo
Load
-
-
Iload
GND
+
+
Vbus
Vbus
–
–
Iload
GND
System
Load
TLV916x
+
MCU
+
Vshunt
+
Rshunt
-
-
Vo
-
GND
GND
GND
GND
Low-Side Current Sense
High-Side Current Sense
电流检测应用中的TLV916x-Q1
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOSAD7
TLV9161-Q1, TLV9162-Q1, TLV9164-Q1
ZHCSRZ5 –APRIL 2023
www.ti.com.cn
Table of Contents
7.3 Feature Description...................................................18
7.4 Device Functional Modes..........................................25
8 Application and Implementation..................................26
8.1 Application Information............................................. 26
8.2 Typical Applications.................................................. 26
8.3 Power Supply Recommendations.............................27
8.4 Layout....................................................................... 28
9 Device and Documentation Support............................31
9.1 Device Support......................................................... 31
9.2 Documentation Support............................................ 31
9.3 接收文档更新通知..................................................... 31
9.4 支持资源....................................................................31
9.5 Trademarks...............................................................32
9.6 静电放电警告............................................................ 32
9.7 术语表....................................................................... 32
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information for Single Channel..................... 7
6.5 Thermal Information for Dual Channel........................7
6.6 Thermal Information for Quad Channel...................... 7
6.7 Electrical Characteristics.............................................8
6.8 Typical Characteristics..............................................10
7 Detailed Description......................................................17
7.1 Overview...................................................................17
7.2 Functional Block Diagram.........................................17
Information.................................................................... 32
4 Revision History
DATE
REVISION
NOTES
April 2023
*
Initial Release
Copyright © 2023 Texas Instruments Incorporated
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English Data Sheet: SBOSAD7
TLV9161-Q1, TLV9162-Q1, TLV9164-Q1
www.ti.com.cn
ZHCSRZ5 –APRIL 2023
5 Pin Configuration and Functions
OUT
Vœ
1
2
3
5
V+
IN+
Vœ
1
2
3
5
V+
IN+
4
INœ
INœ
4
OUT
Not to scale
Not to scale
图5-1. TLV9161-Q1 DBV Package,
5-Pin SOT-23
图5-2. TLV9161-Q1 DCK Package,
5-Pin SC70
(Top View)
(Top View)
表5-1. Pin Functions: TLV9161-Q1
PIN
TYPE(1)
DESCRIPTION
NAME
SOT-23 (DBV)
SC70 (DCK)
IN+
3
4
1
5
2
1
3
4
5
2
I
Noninverting input
I
Inverting input
IN–
OUT
V+
O
—
—
Output
Positive (highest) power supply
Negative (lowest) power supply
V–
(1) I = input, O = output
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Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1
English Data Sheet: SBOSAD7
TLV9161-Q1, TLV9162-Q1, TLV9164-Q1
ZHCSRZ5 –APRIL 2023
www.ti.com.cn
OUT1
IN1œ
IN1+
Vœ
1
2
3
4
8
7
6
5
V+
OUT2
IN2œ
IN2+
Not to scale
图5-3. TLV9162-Q1 D and DGK Package,
8-Pin SOIC and VSSOP
(Top View)
表5-2. Pin Functions: TLV9162-Q1
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
3
IN1+
IN1–
IN2+
IN2–
OUT1
OUT2
V+
I
I
Noninverting input, channel 1
Inverting input, channel 1
Noninverting input, channel 2
Inverting input, channel 2
Output, channel 1
2
5
I
6
I
1
O
O
—
—
7
Output, channel 2
8
Positive (highest) power supply
Negative (lowest) power supply
4
V–
(1) I = input, O = output
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English Data Sheet: SBOSAD7
TLV9161-Q1, TLV9162-Q1, TLV9164-Q1
www.ti.com.cn
ZHCSRZ5 –APRIL 2023
OUT1
IN1œ
IN1+
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT4
IN4œ
IN4+
Vœ
IN2+
IN2œ
OUT2
IN3+
IN3œ
OUT3
8
Not to scale
图5-4. TLV9164-Q1 D and PW Package,
14-Pin SOIC and TSSOP
(Top View)
表5-3. Pin Functions: TLV9164-Q1
PIN
TYPE(1)
DESCRIPTION
NAME
IN1+
NO.
3
I
Noninverting input, channel 1
Inverting input, channel 1
Noninverting input, channel 2
Inverting input, channel 2
Noninverting input, channel 3
Inverting input, channel 3
Noninverting input, channel 4
Inverting input, channel 4
Output, channel 1
2
I
I
IN1–
IN2+
5
6
I
IN2–
IN3+
10
9
I
I
IN3–
IN4+
12
13
1
I
I
IN4–
OUT1
OUT2
OUT3
OUT4
V+
O
O
O
O
—
—
7
Output, channel 2
8
Output, channel 3
14
4
Output, channel 4
Positive (highest) power supply
Negative (lowest) power supply
11
V–
(1) I = input, O = output
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Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1
English Data Sheet: SBOSAD7
TLV9161-Q1, TLV9162-Q1, TLV9164-Q1
ZHCSRZ5 –APRIL 2023
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
0
MAX
UNIT
V
20
(V+) + 0.5
VS + 0.2
10
Supply voltage, VS = (V+) –(V–)
Common-mode voltage(3)
V
(V–) –0.5
Signal input pins
Differential voltage(3)
Current(3)
V
mA
–10
V–
Shutdown pin voltage
V+
Output short-circuit(2)
Continuous
Operating ambient temperature, TA
Junction temperature, TJ
Storage temperature, Tstg
150
150
150
°C
°C
°C
–55
–65
(1) Operating the device beyond the ratings listed under Absolute Maximum Ratings will cause permanent damage to the device. These
are stress ratings only, based on process and design limitations, and this device has not been designed to function outside the
conditions indicated under Recommended Operating Conditions. Exposure to any condition outside Recommended Operating
Conditions for extended periods, including absolute-maximum-rated conditions, may affect device reliability and performance.
(2) Short-circuit to ground, one amplifier per package. Extended short-circuit current, especially with higher supply voltage, can cause
excessive heating and eventual destruction.
(3) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
6.2 ESD Ratings
VALUE
UNIT
TLV9161-Q1
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
±2000
±1500
V(ESD)
Electrostatic discharge
V
TLV9162-Q1 and TLV9164-Q1
V(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
±2500
±1500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
2.7
MAX
UNIT
VS
VI
16
V+
V
V
Supply voltage, (V+) –(V–)
Common mode voltage range
Specified temperature
V–
–40
TA
125
°C
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Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1
English Data Sheet: SBOSAD7
TLV9161-Q1, TLV9162-Q1, TLV9164-Q1
www.ti.com.cn
ZHCSRZ5 –APRIL 2023
6.4 Thermal Information for Single Channel
TLV9161-Q1
DBV
DCK
(SC70)
THERMAL METRIC(1)
UNIT
(SOT-23)
5 PINS
189.3
86.8
5 PINS
202.4
111.6
51.6
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
55.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
23.6
25.8
ψJT
55.5
51.4
ψJB
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Thermal Information for Dual Channel
TLV9162-Q1
D
DGK
(VSSOP)
THERMAL METRIC(1)
Unit
(SOIC)
8 PINS
130.8
74.0
8 PINS
173.9
65.7
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
RθJC(top)
RθJB
°C/W
°C/W
°C/W
°C/W
°C/W
74.3
95.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
25.8
10.9
ψJT
73.5
94.1
ψJB
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 Thermal Information for Quad Channel
TLV9164-Q1
D
PW
(TSSOP)
THERMAL METRIC(1)
UNIT
(SOIC)
14 PINS
94.9
14 PINS
120.0
50.4
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
51.1
51.4
63.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
15.3
8.1
ψJT
51.0
62.5
ψJB
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1
English Data Sheet: SBOSAD7
TLV9161-Q1, TLV9162-Q1, TLV9164-Q1
ZHCSRZ5 –APRIL 2023
www.ti.com.cn
6.7 Electrical Characteristics
For VS = (V+) –(V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
±0.21
±1.03
±1.2
VOS
Input offset voltage
mV
VCM = V–
TA = –40°C to 125°C
dVOS/dT
Input offset voltage drift
±0.25
±0.45
±0.45
±0.45
±0.45
VCM = V–
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
µV/℃
±2
±3
TLV9161-Q1, TLV9162-Q1,
V
CM = V–, VS = 5 V to 16 V
±2.2
±3.8
TLV9164-Q1, VCM = V–, VS
= 5 V to 16 V
Input offset voltage versus
power supply
PSRR
μV/V
TLV9161-Q1, TLV9162-Q1,
±2
±12
TLV9164-Q1, VCM = V–, VS TA = –40°C to 125°C
= 2.7 V to 16 V(1)
DC channel separation
0.4
µV/V
INPUT BIAS CURRENT
IB
Input bias current
±10
±10
pA
pA
IOS
Input offset current
NOISE
2.7
0.49
6.8
μVPP
EN
Input voltage noise
f = 0.1 Hz to 10 Hz
µVRMS
f = 1 kHz
eN
iN
Input voltage noise density
nV/√Hz
fA/√Hz
f = 10 kHz
4.2
Input current noise density f = 1 kHz
55
INPUT VOLTAGE RANGE
Common-mode voltage
range
VCM
(V+)
V
(V–)
85
VS = 16 V, V–< VCM < (V+)
–2 V (PMOS pair)
110
VS = 5 V, V–< VCM < (V+) –
75
98
90
2 V (PMOS pair)(1)
Common-mode rejection
ratio
VS = 2.7 V, V–< VCM < (V+)
–2 V (PMOS pair)
CMRR
dB
TA = –40°C to 125°C
VS = 2.7 –16 V, (V+) –1 V
< VCM < V+ (NMOS pair)
78
(V+) –2 V < VCM < (V+) –1
V
See 图6-6
INPUT IMPEDANCE
ZID
Differential
Common-mode
100 || 9
6 || 1
MΩ|| pF
TΩ|| pF
ZICM
OPEN-LOOP GAIN
VS = 16 V, VCM = VS / 2,
(V–) + 0.1 V < VO < (V+) –
0.1 V
120
104
90
136
136
125
125
105
105
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
VS = 5 V, VCM = VS / 2,
(V–) + 0.1 V < VO < (V+) –
0.1 V(1)
AOL
Open-loop voltage gain
dB
VS = 2.7 V, VCM = VS / 2,
(V–) + 0.1 V < VO < (V+) –
0.1 V(1)
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ZHCSRZ5 –APRIL 2023
6.7 Electrical Characteristics (continued)
For VS = (V+) –(V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
11
33
MHz
Slew rate
VS = 16 V, G = +1, VSTEP = 10 V, CL = 20 pF(2)
To 0.1%, VS = 16 V, VSTEP = 10 V, G = +1, CL = 20 pF
To 0.1%, VS = 16 V, VSTEP = 2 V, G = +1, CL = 20 pF
To 0.01%, VS = 16 V, VSTEP = 10 V, G = +1, CL = 20 pF
To 0.01%, VS = 16 V, VSTEP = 2 V, G = +1, CL = 20 pF
G = +1, RL = 10 kΩ, CL = 20 pF
V/μs
0.70
0.22
tS
Settling time
μs
0.89
0.42
Phase margin
64
°
Overload recovery time
VIN × gain > VS
120
ns
0.00005%
126
VS = 16 V, VO = 3 VRMS, G = 1, f = 1 kHz
dB
dB
dB
0.0032%
90
Total harmonic distortion +
noise
THD+N
VS = 10 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 128 Ω
VS = 10 V, VO = 0.4 VRMS, G = 1, f = 1 kHz, RL = 32 Ω
0.00032%
110
OUTPUT
VS = 16 V, RL = no load
6
25
60
VS = 16 V, RL = 10 kΩ
85
300
VS = 16 V, RL = 2 kΩ
VS = 2.7 V, RL = no load
VS = 2.7 V, RL = 10 kΩ
VS = 2.7 V, RL = 2 kΩ
Voltage output swing from Positive and negative
mV
rail
rail headroom
0.5
5
20
20
50
ISC
Short-circuit current
Capacitive load drive
±73
mA
pF
CLOAD
See 图6-33
Open-loop output
impedance
ZO
IO = 0 A
See 图6-30
Ω
POWER SUPPLY
2.4
2.8
2.84
2.92
2.98
TLV9162-Q1, TLV9164-Q1,
IO = 0 A
TA = –40°C to 125°C
TA = –40°C to 125°C
Quiescent current per
amplifier
IQ
mA
2.48
TLV9161-Q1, IO = 0 A
(1) Specified by characterization only.
(2) See Slew Rate vs. Input Step Voltage for more information.
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Product Folder Links: TLV9161-Q1 TLV9162-Q1 TLV9164-Q1
English Data Sheet: SBOSAD7
TLV9161-Q1, TLV9162-Q1, TLV9164-Q1
ZHCSRZ5 –APRIL 2023
www.ti.com.cn
6.8 Typical Characteristics
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ(unless otherwise noted)
45
40
35
30
25
20
15
10
5
30
25
20
15
10
5
0
-675 -525 -375 -225 -75
0
75
Offset Voltage (µV)
225 375 525 675
0.1
0.2
0.3
0.4
0.5
0.6
Offset Voltage Drift (µV/°C)
0.7
0.8
0.9
D001
D002
Distribution from 74 amplifiers, TA = 25°C
图6-1. Offset Voltage Production Distribution
Distribution from 74 amplifiers
图6-2. Offset Voltage Drift Distribution
500
400
300
200
100
0
2000
1600
1200
800
400
0
-400
-800
-1200
-1600
-2000
-100
-200
-300
-400
-500
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D014
D013
VCM = V+
VCM = V–
Data from 74 amplifiers
Data from 74 amplifiers
图6-4. Offset Voltage vs Temperature
图6-3. Offset Voltage vs Temperature
2000
1600
1200
800
2000
1600
1200
800
400
400
0
0
-400
-800
-1200
-1600
-2000
-400
-800
-1200
-1600
-2000
-8 -7 -6 -5 -4 -3 -2 -1
0
1
Common-Mode Voltage (V)
2
3
4
5
6
7
8
4
4.5
5
5.5
Common-Mode Voltage (V)
6
6.5
7
7.5
8
D015
D060
TA = 25°C
TA = 25°C
Data from 74 amplifiers
Data from 74 amplifiers
图6-5. Offset Voltage vs Common-Mode Voltage
图6-6. Offset Voltage vs Common-Mode Voltage (Transition
Region)
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ(unless otherwise noted)
2000
1600
1200
800
2000
1600
1200
800
400
400
0
0
-400
-800
-1200
-1600
-2000
-400
-800
-1200
-1600
-2000
-8 -7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
8
4
4.5
5
5.5
6
6.5
7
7.5
8
Common-Mode Voltage (V)
Common-Mode Voltage (V)
TA = 125°C
TA = 125°C
Data from 74 amplifiers
Data from 74 amplifiers
图6-7. Offset Voltage vs Common-Mode Voltage
图6-8. Offset Voltage vs Common-Mode Voltage (Transition
Region)
2000
1600
1200
800
2000
1600
1200
800
400
400
0
0
-400
-800
-1200
-1600
-2000
-400
-800
-1200
-1600
-2000
-8 -7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
8
4
4.5
5
5.5
6
6.5
7
7.5
8
Common-Mode Voltage (V)
Common-Mode Voltage (V)
TA = –40°C
TA = –40°C
Data from 74 amplifiers
Data from 74 amplifiers
图6-9. Offset Voltage vs Common-Mode Voltage
图6-10. Offset Voltage vs Common-Mode Voltage (Transition
Region)
500
400
300
200
100
0
75
G=-1
G=1
G=11
G=101
G=1001
60
45
30
15
0
-100
-200
-300
-400
-500
-15
-30
-45
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
100
1k
10k 100k
Frequency (Hz)
1M
10M
Supply Voltage (V)
D005
VCM = V–
Data from 74 amplifiers
图6-12. Closed-Loop Gain vs Frequency
图6-11. Offset Voltage vs Power Supply
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ(unless otherwise noted)
20
15
10
5
600
550
500
450
400
350
300
250
200
150
100
50
IB-
IB+
IOS
IB-
IB+
IOS
0
-5
-10
-15
-20
0
-50
-100
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-8
-6
-4
-2
0
2
Common-Mode Voltage (V)
4
6
8
D020
D019
No Load
No Load
图6-14. Input Bias Current and Offset Current vs Temperature
图6-13. Input Bias Current and Offset Current vs Common-
Mode Voltage
V+
V+ - 1V
V+ - 2V
V+ - 3V
V+ - 4V
V+ - 5V
V+ - 6V
V+ - 7V
50
SR+
SR-
45
40
35
30
25
20
15
10
5
V+ - 8V
-40°C
25°C
V+ - 9V
125°C
V+ - 10V
0
10
20
30
40
50
60
Output Current (mA)
70
80
90 100
0
0
0.5
1
1.5
2
2.5
3
Input Step (V)
3.5
4
4.5
5
D021
D035
VS = 16 V
图6-15. Slew Rate vs Input Step Voltage
图6-16. Output Voltage Swing vs Output Current (Sourcing)
V- + 10V
V- + 9V
V- + 8V
V- + 7V
V- + 6V
V- + 5V
V- + 4V
V- + 3V
V- + 2V
V- + 1V
V-
V+
-40°C
25°C
125°C
V+ - 1V
V+ - 2V
V+ - 3V
V+ - 4V
-40°C
25°C
125°C
V+ - 5V
0
10
20
30
40
Output Current (mA)
50
60
70
80
90 100
0
10
20
30
40
Output Current (mA)
50
60
70
80
90 100
D022
D049
VS = 16 V
VS = 5 V
图6-17. Output Voltage Swing vs Output Current (Sinking)
图6-18. Output Voltage Swing vs Output Current (Sourcing)
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ(unless otherwise noted)
V- + 5V
V- + 4V
V- + 3V
V- + 2V
V- + 1V
V-
120
105
90
75
60
45
30
15
0
-40°C
25°C
125°C
CMRR
PSRR+
PSRR-
0
10
20
30
40
50
60
Output Current (mA)
70
80
90 100
1k
10k
100k
Frequency (Hz)
1M
10M
D050
D006
VS = 5 V
图6-20. CMRR and PSRR vs Frequency
图6-19. Output Voltage Swing vs Output Current (Sinking)
1000
1000
100
10
60
80
100
80
100
10
100
120
140
120
1
1
140
100 120 140
0.1
-40
0.1
-40
-20
0
20
40 60
Temperature (°C)
80
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D023
D051
VS = 16 V, VCM = V–
图6-21. CMRR vs Temperature
VS = 5 V, VCM = V–
图6-22. CMRR vs Temperature
1000
60
80
100
10
80
100
10
1
100
120
140
160
100
1
0.1
120
0.01
0.1
140
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Temperature (°C)
D052
图6-24. PSRR vs Temperature
VS = 2.7 V, VCM = V–
图6-23. CMRR vs Temperature
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ(unless otherwise noted)
2
1.5
1
100
10
1
0.5
0
-0.5
-1
-1.5
-2
Time (1s/div)
10
100
1k
Frequency (Hz)
10k
D025
D007
图6-25. 0.1-Hz to 10-Hz Noise
图6-26. Input Voltage Noise Spectral Density vs Frequency
2.6
2.55
2.5
2.45
2.4
2.8
2.4
2
2.35
2.3
2.25
2.2
2.15
2.1
2.05
2
1.95
1.9
1.6
1.2
0.8
0.4
0
Vs=2.7V
Vs=5V
Vs=16V
1.85
1.8
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Supply Voltage (V)
D027
VCM = V–
VCM = V–
图6-28. Quiescent Current vs Temperature
图6-27. Quiescent Current vs Supply Voltage
145
1000
100
10
VS = 2.7V
VS = 5V
VS = 16V
140
135
130
125
120
115
110
105
100
1
0.1
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
100
1k
10k 100k
Frequency (Hz)
1M
10M
D028
D099
图6-29. Open-Loop Voltage Gain vs Temperature (dB)
图6-30. Open-Loop Output Impedance vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ(unless otherwise noted)
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
RISO = 0W, Overshoot (+)
RISO = 0W, Overshoot (-)
RISO = 50W, Overshoot (+)
RISO = 50W, Overshoot (-)
RISO = 0W, Overshoot (+)
RISO = 0W, Overshoot (-)
RISO = 50W, Overshoot (+)
RISO = 50W, Overshoot (-)
0
80
160
240 320
Capacitive Load (pF)
400
480
560
0
80
160
240 320
Capacitive Load (pF)
400
480
560
D029
D030
20-mVpp output step, G = +1
20-mVpp output step, G = –1
图6-32. Small-Signal Overshoot vs Capacitive Load
图6-31. Small-Signal Overshoot vs Capacitive Load
70
65
60
55
50
45
40
35
30
25
20
20
Input
Output
10
0
-10
-20
Time (2 µs/div)
0
20 40 60 80 100 120 140 160 180 200 220
Capacitive Load (pF)
D033
D004
CL = 20 pF, G = 1, 20-mVpp step response
G = +1
图6-34. Small-Signal Step Response
图6-33. Phase Margin vs Capacitive Load
20
4
Input
Output
Input
Output
3
2
10
0
1
0
-1
-2
-3
-4
-10
-20
Time (2 µs/div)
Time (2 µs/div)
D054
D034
CL = 20 pF, G = –1, 20-mVpp step response
图6-35. Small-Signal Step Response
CL = 20 pF, G = 1, 5-Vpp step response
图6-36. Large-Signal Step Response
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ(unless otherwise noted)
4
3
20
16
12
8
Vs=16V
Vs=2.7V
Input
Output
2
1
0
-1
-2
-3
-4
4
0
Time (2 µs/div)
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
D055
图6-38. Maximum Output Voltage vs Frequency
CL = 20 pF, G = –1, 5-Vpp step response
图6-37. Large-Signal Step Response
-60
120
110
100
90
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
80
70
60
50
40
30
20
100
1k
10k 100k
Frequency (Hz)
1M
10M
10M
100M
Frequency (Hz)
1G
D011
D012
图6-39. Channel Separation vs Frequency
图6-40. EMIRR (Electromagnetic Interference Rejection Ratio)
vs Frequency
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7 Detailed Description
7.1 Overview
The TLV916x-Q1 family (TLV9161-Q1, TLV9162-Q1, and TLV9164-Q1) is a family of 16-V, general-purpose,
automotive operational amplifiers.
These devices offer excellent DC precision and AC performance, including rail-to-rail input or output, low offset
(±210 µV, typical), low offset drift (±0.25 µV/°C, typical), and 11-MHz bandwidth.
Features such as wide differential input range, high short-circuit current (±73 mA), and high slew rate (33 V/μs)
make the TLV916x-Q1 a flexible, robust, and high-performance operational amplifier for 16-V automotive
applications.
7.2 Functional Block Diagram
+
NCH Input
Stage
–
IN+
IN-
+
–
16-V
OUT
Gain
Stage
Output
Stage
Differential
MUX-Friendly
Front End
Slew
Boost
Shutdown
Circuitry
+
PCH Input
Stage
–
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7.3 Feature Description
7.3.1 Input Protection Circuitry
The TLV916x-Q1 uses a special input architecture to eliminate the requirement for input protection diodes but
still provides robust input protection under transient conditions. 图 7-1 shows conventional input diode protection
schemes that are activated by fast transient step responses and introduce signal distortion and settling time
delays because of alternate current paths, as shown in 图 7-2. For low-gain circuits, these fast-ramping input
signals forward-bias back-to-back diodes, causing an increase in input current and resulting in extended settling
time.
V+
V+
VIN+
VIN+
VOUT
VOUT
TLV916x
~0.7 V
16 V
VINꢀ
VINꢀ
Vꢀ
Vꢀ
TLV916x Provides Full 16-V
Differential Input Range
Conventional Input Protection
Limits Differential Input Range
图7-1. TLV916x-Q1 Input Protection Does Not Limit Differential Input Capability
1
Ron_mux
Vn = 8 V
RFILT
8 V
Sn
D
1
2
~–7.3 V
8 V
CFILT
CS
CD
VIN–
2
Ron_mux
Sn+1
V
n+1 = –8 V RFILT
–8 V
~0.7 V
VOUT
CFILT
CS
Idiode_transient
VIN+
–8 V
Input Low-Pass Filter
Simplified Mux Model
Buffer Amplifier
图7-2. Back-to-Back Diodes Create Settling Issues
The TLV916x-Q1 family of operational amplifiers provides a true high-impedance differential input capability
using a patented input protection architecture that does not introduce additional signal distortion or delayed
settling time, making the device an optimal op amp for multichannel, high-switched, input applications. The
TLV916x-Q1 tolerates a maximum differential swing (voltage between inverting and non-inverting pins of the op
amp) of up to 16 V, making the device suitable for use as a comparator or in applications with fast-ramping input
signals such as data-acquisition systems; see the TI TechNote MUX-Friendly Precision Operational Amplifiers
for more information.
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7.3.2 EMI Rejection
The TLV916x-Q1 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the TLV916x-Q1 benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. 图 7-3
shows the results of this testing on the TLV916x-Q1. 表 7-1 provides the EMIRR IN+ values for the TLV916x-Q1
at particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of
Operational Amplifiers application report contains detailed information on the topic of EMIRR performance as it
relates to op amps and is available for download from www.ti.com.
120
110
100
90
80
70
60
50
40
30
20
10M
100M
Frequency (Hz)
1G
D012
图7-3. EMIRR Testing
表7-1. TLV9161-Q1 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
400 MHz
50.0 dB
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
5 GHz
56.3 dB
65.6 dB
70.0 dB
78.9 dB
91.0 dB
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
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7.3.3 Thermal Protection
The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This
phenomenon is called self heating. The absolute maximum junction temperature of the TLV916x-Q1 is 150°C.
Exceeding this temperature causes damage to the device. The TLV916x-Q1 has a thermal protection feature
that reduces damage from self heating. The protection works by monitoring the temperature of the device and
turning off the op amp output drive for temperatures above 170°C. 图 7-4 shows an application example for the
TLV9162-Q1 that has significant self heating because of its power dissipation (0.627 W). In this example, both
channels have a quiescent power dissipation while one of the channels has a significant load. Thermal
calculations indicate that for an ambient temperature of 60°C, the device junction temperature reaches 175°C.
The actual device, however, turns off the output drive to recover towards a safe junction temperature. 图 7-4
shows how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so
the output is 5 V. When self heating causes the device junction temperature to increase above the internal limit,
the thermal protection forces the output to a high-impedance state and the output is pulled to ground through
resistor RL. If the condition that caused excessive power dissipation is not removed, the amplifier will oscillate
between a shutdown and enabled state until the output fault is corrected. Please note that thermal performance
can vary greatly depending on the package selected and the PCB layout design. This example uses the thermal
performance of the TSSOP (8) package.
One channel has load
Consider IQ of two channels
TA = 60°C
5 V
16 V
PD = 0.627W
JA = 183.4°C/W
0 V
TJ = 183.4°C/W × 0.627W + 60°C
TJ = 175°C (expected)
ꢀ
TLV9162
170ºC
ꢁ
IOUT = 50 mA
+
5 V
–
RL
100
+
–
VIN
5 V
图7-4. Thermal Protection
7.3.4 Capacitive Load and Stability
The TLV916x-Q1 features an output stage capable of driving moderate capacitive loads, and by leveraging an
isolation resistor, the device can easily be configured to drive larger capacitive loads. Increasing the gain
enhances the ability of the amplifier to drive greater capacitive loads; see 图 7-5 and 图 7-6. The particular op
amp circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing
whether an amplifier will be stable in operation.
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70
60
50
40
30
20
10
70
60
50
40
30
20
10
0
RISO = 0W, Overshoot (+)
RISO = 0W, Overshoot (-)
RISO = 50W, Overshoot (+)
RISO = 50W, Overshoot (-)
RISO = 0W, Overshoot (+)
RISO = 0W, Overshoot (-)
RISO = 50W, Overshoot (+)
RISO = 50W, Overshoot (-)
0
0
80
160
240 320
Capacitive Load (pF)
400
480
560
0
80
160
240 320
Capacitive Load (pF)
400
480
560
D030
D029
图7-5. Small-Signal Overshoot vs Capacitive Load 图7-6. Small-Signal Overshoot vs Capacitive Load
(20-mVpp Output Step, G = +1) (20-mVpp Output Step, G = -1)
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small
resistor, RISO, in series with the output, as shown in 图 7-7. This resistor significantly reduces ringing and
maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with the
capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing
the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low
output levels. A high capacitive load drive makes the TLV916x-Q1 well suited for applications such as reference
buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in 图 7-7 uses an isolation resistor,
RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase
margin.
+Vs
Vout
Riso
+
Cload
+
Vin
-Vs
œ
图7-7. Extending Capacitive Load Drive With the TLV9161-Q1
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7.3.5 Common-Mode Voltage Range
The TLV916x-Q1 is a 16-V, rail-to-rail input operational amplifier with an input common-mode range that extends
to both supply rails. This wide range is achieved with paralleled complementary N-channel and P-channel
differential input pairs, as shown in 图 7-8. The N-channel pair is active for input voltages close to the positive
rail, typically from (V+) – 1 V to the positive supply. The P-channel pair is active for inputs from the negative
supply to approximately (V+) – 2 V. There is a small transition region, typically (V+) – 2 V to (V+) – 1 V in
which both input pairs are on. This transition region can vary modestly with process variation. Within this region
PSRR, CMRR, offset voltage, offset drift, noise, and THD performance may be degraded compared to operation
outside this region.
图6-5 shows this transition region for a typical device in terms of input voltage offset in more detail.
For more information on common-mode voltage range and PMOS/NMOS pair interaction, see Op Amps With
Complementary-Pair Input Stages application note.
V+
IN-
PMOS
PMOS
NMOS
IN+
NMOS
V-
图7-8. Rail-to-Rail Input Stage
7.3.6 Phase Reversal Protection
The TLV916x-Q1 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This condition is most often encountered in non-inverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The TLV916x-Q1 is a rail-to-rail input op amp; therefore, the common-mode range
can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits
into the appropriate rail. For more information on phase reversal, see Op Amps With Complementary-Pair Input
Stages application note.
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7.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage
breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to
the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them
from accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. 图 7-9 shows an illustration of the ESD circuits contained in the TLV916x-Q1 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or
the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain
inactive during normal circuit operation.
TVS
RF
+VS
VDD
50
50
R1
RS
IN–
IN+
–
+
Power-Supply
ESD Cell
RL
ID
+
–
VIN
VSS
–VS
TVS
图7-9. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event is very short in duration and very high voltage (for example; 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example; 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit
(labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
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7.3.8 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a
linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the TLV916x-Q1 is approximately 120 ns.
7.3.9 Typical Specifications and Distributions
Designers often have questions about a typical specification of an amplifier in order to design a more robust
circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an
amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These
deviations often follow Gaussian (bell curve), or normal distributions, and circuit designers can leverage this
information to guardband their system, even when there is not a minimum or maximum specification in the
Electrical Characteristics table.
0.00312% 0.13185%
0.13185% 0.00312%
0.00002%
0.00002%
2.145% 13.59% 34.13% 34.13% 13.59% 2.145%
1
1 1 1 1 1 1 1 1
1
1
1
ꢀ-61 ꢀ-51 ꢀ-41 ꢀ-31 ꢀ-21 ꢀ-1
ꢀ+1 ꢀ+21 ꢀ+31 ꢀ+41 ꢀ+51 ꢀ+61
ꢀ
图7-10. Ideal Gaussian Distribution
图 7-10 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ, or sigma,
is the standard deviation of a system. For a specification that exhibits this kind of distribution, approximately two-
thirds (68.26%) of all units can be expected to have a value within one standard deviation, or one sigma, of the
mean (from µ –σto µ + σ).
Depending on the specification, values listed in the typical column of the Electrical Characteristics table are
represented in different ways. As a general rule of thumb, if a specification naturally has a nonzero mean (for
example, like gain bandwidth), then the typical value is equal to the mean (µ). However, if a specification
naturally has a mean near zero (like input offset voltage), then the typical value is equal to the mean plus one
standard deviation (µ + σ) in order to most accurately represent the typical value.
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This chart can be used to calculate approximate probability of a specification in a unit; for example, for TLV916x-
Q1, the typical input voltage offset is 210 µV, so 68.2% of all TLV916x-Q1 devices are expected to have an offset
from –210 µV to 210 µV. At 4 σ (±840 µV), 99.9937% of the distribution has an offset voltage less than ±840
µV, which means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873
units.
Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits
will be removed from production material. For example, the TLV916x-Q1 family has a maximum offset voltage of
1 mV at 25°C, and even though this corresponds to about 5-σ (≈1 in 1.7 million units), which is extremely
unlikely, TI assures that any unit with larger offset than 1 mV will be removed from production material.
For specifications with no value in the minimum or maximum column, consider selecting a sigma value of
sufficient guardband for the application, and design worst-case conditions using this value. For example, the 6-
σ value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be an
option as a wide guardband to design a system around. In this case, the TLV916x-Q1 family does not have a
maximum or minimum for offset voltage drift, but based on the typical value of 0.25 µV/°C in the Electrical
Characteristics table, it can be calculated that the 6-σ value for offset voltage drift is about 1.5 µV/°C. When
designing for worst-case system conditions, this value can be used to estimate the worst possible offset across
temperature without having an actual minimum or maximum value.
However, process variation and adjustments over time can shift typical means and standard deviations, and
unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a
device. This information should be used only to estimate the performance of a device.
7.4 Device Functional Modes
The TLV916x-Q1 has a single functional mode and is operational when the power-supply voltage is greater than
2.7 V (±1.35 V). The maximum power supply voltage for the TLV916x-Q1 is 16 V (±8 V).
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TLV916x-Q1 family offers excellent DC precision and AC performance. These devices operate up to 16-V
supply rails and offer true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as 11-MHz
bandwidth and high output drive. These features make the TLV916x-Q1 a robust, high-performance operational
amplifier for 16-V industrial applications.
8.2 Typical Applications
8.2.1 Low-Side Current Measurement
图 8-1 shows the TLV9161-Q1 configured in a low-side current sensing application. For a full analysis of the
circuit shown in 图 8-1 including theory, calculations, simulations, and measured data, see TI Precision Design
TIPD129, 0-A to 1-A Single-Supply Low-Side Current-Sensing Solution.
VCC
5 V
LOAD
TLV9161
+
VOUT
–
RSHUNT
ILOAD
100 m
LM7705
RF
5.76 k
RG
120
图8-1. TLV9161-Q1 in a Low-Side, Current-Sensing Application
8.2.1.1 Design Requirements
The design requirements for this design are:
• Load current: 0 A to 1 A
• Output voltage: 4.9 V
• Maximum shunt voltage: 100 mV
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8.2.1.2 Detailed Design Procedure
The transfer function of the circuit in 图8-1 is given in 方程式1:
V
= I
× R × Gain
SHUNT
(1)
OUT
LOAD
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using 方程式2:
V
SHUNT_MAX
100 mV
1 A
R
=
=
= 100 mΩ
(2)
SHUNT
I
LOAD_MAX
Using 方程式 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the TLV916x-Q1 to produce an output voltage of 0 V to 4.9 V. The gain needed by the TLV916x-Q1
to produce the necessary output voltage is calculated using 方程式3:
V
− V
− V
OUT_MAX
OUT_MIN
Gain =
(3)
V
IN_MAX
IN_MIN
Using 方程式 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. 方程式 4 is
used to size the resistors, RF and RG, to set the gain of the TLV916x-Q1 to 49 V/V.
R
F
Gain = 1 +
(4)
R
G
Choosing RF as 5.76 kΩ, RG is calculated to be 120 Ω. RF and RG were chosen as 5.76 kΩ and 120 Ω because
the values are standard value resistors that create a 49:1 ratio. Other resistors that create a 49:1 ratio can also
be used. However, excessively large resistors generate thermal noise that exceeds the intrinsic noise of the op
amp. 图8-2 shows the measured transfer function of the circuit shown in 图8-1.
8.2.1.3 Application Curves
5
4
3
2
1
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
ILOAD (A)
1
图8-2. Low-Side, Current-Sense, Transfer Function
8.3 Power Supply Recommendations
The TLV916x-Q1 is specified for operation from 2.7 V to 16 V (±1.35 V to ±8 V); many specifications apply from
–40°C to 125°C or with specific supply voltage and test conditions.
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CAUTION
Supply voltages larger than 20 V can permanently damage the device; see the Absolute Maximum
Ratings section.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
section.
8.4 Layout
8.4.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed
to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in 图8-4, keeping RF and RG
close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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8.4.2 Layout Example
V-
C3
INPUT
OUTPUT
2
1
3
R3
+
–
4
C4
C2
V+
R1
C1
R2
图8-3. Schematic for Non-inverting Configuration Layout Example
GND
GND
OUTPUT
V-
GND
图8-4. Operational Amplifier Board Layout for Non-inverting Configuration - SC70 (DCK) Package
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GND
GND
GND
V+
INPUT A
OUTPUT B
V-
GND
GND
GND
图8-5. Example Layout for VSSOP-8 (DGK) Package
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9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
9.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
备注
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation, see the following:
1. Texas Instruments, Analog Engineer's Circuit Cookbook: Amplifiers
2. Texas Instruments, AN31 amplifier circuit collection application note
3. Texas Instruments, MUX-Friendly, Precision Operational Amplifiers application brief
4. Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application note
5. Texas Instruments, Op Amps With Complementary-Pair Input Stages application note
9.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
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9.5 Trademarks
TINA-TI™ is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
所有商标均为其各自所有者的财产。
9.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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23-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV9161QDBVRQ1
TLV9161QDCKRQ1
TLV9162QDGKRQ1
TLV9162QDRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SC70
DBV
DCK
DGK
D
5
5
3000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2W2H
1NJ
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
VSSOP
SOIC
8
2S5T
8
T9162Q
TLV9164QDRQ1
SOIC
D
14
14
TLV9164QD
T9164PW
TLV9164QPWRQ1
TSSOP
PW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jul-2023
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV9161-Q1, TLV9162-Q1, TLV9164-Q1 :
Catalog : TLV9161, TLV9162, TLV9164
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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