TLV9301IDBVR_技术文档

TLV9301, TLV9302, TLV9304

SBOS941D – FEBRUARY 2019 – REVISED AUGUST 2021

TLV930x 40-V, 1-MHz, RRO Operational Amplifiers for Cost-Sensitive Systems

1 Features

3 Description

•

Low offset voltage: ±0.5 mV

The TLV930x family (TLV9301, TLV9302, and

Low offset voltage drift: ±2 µV/°C

Low noise: 33 nV/√Hz at 1 kHz

High common-mode rejection: 110 dB

Low bias current: ±10 pA

Rail-to-rail output

Wide bandwidth: 1-MHz GBW

TLV9304) is

a

family of 40-V, cost-optimized

operational amplifiers. These devices offer strong

general-purpose DC and AC specifications, including

rail-to-rail output, low offset (±0.5 mV, typ), low offset

drift (±2 µV/°C, typ), and 1-MHz bandwidth.

Convenient features such as wide differential input-

voltage range, high output current (±60 mA), and

high slew rate (3 V/µs) make the TLV930x a robust

operational amplifier for high-voltage, cost-sensitive

applications.

High slew rate: 3 V/µs

Low quiescent current: 150 µA per amplifier

Wide supply: ±2.25 V to ±20 V, 4.5 V to 40 V

Robust EMI performance: 72 dB at 1 GHz

MUX-friendly/comparator inputs:

– Differential and common-mode input voltage

range to supply rail

The TLV930x family of op amps is available in

standard packages and is specified from –40°C to

125°C.

•

Industry-standard packages:

– Single in SOT-23-5 and SC70

– Dual in SOIC-8, TSSOP-8, and VSSOP-8

– Quad in SOIC-14 and TSSOP-14

Device Information

PART NUMBER⁽¹⁾

PACKAGE

BODY SIZE (NOM)

2.90 mm × 1.60 mm

2.00 mm × 1.25 mm

4.90 mm × 3.91 mm

2.90 mm × 1.60 mm

4.40 mm × 3.00 mm

2.30 mm × 2.00 mm

8.65 mm × 3.91 mm

5.00 mm × 4.40 mm

SOT-23 (5)

TLV9301

2 Applications

SC70 (5)

SOIC (8)

•

Merchant network and server PSU

Industrial AC-DC

Merchant DC/DC

Motor drives: AC and servo drive power supplies

Building automation

SOT-23-8

TSSOP (8)

VSSOP (8)

SOIC (14)

TSSOP (14)

TLV9302

TLV9304

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

R_G

R_F

R₁

V_OUT

V_IN

C₁

1

2pR₁C₁

f

=

-3 dB

V_OUT

V_IN

R_F

1

1 + sR₁C₁

=

1 +

(

R_G

TLV930x in a Single-Pole, Low-Pass Filter

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TLV9301, TLV9302, TLV9304

SBOS941D – FEBRUARY 2019 – REVISED AUGUST 2021

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings ....................................... 5

6.2 ESD Ratings .............................................................. 5

6.3 Recommended Operating Conditions ........................5

6.4 Thermal Information for Single Channel .................... 5

6.5 Thermal Information for Dual Channel .......................6

6.6 Thermal Information for Quad Channel ..................... 6

6.7 Electrical Characteristics ............................................7

6.8 Typical Characteristics................................................9

7 Detailed Description......................................................16

7.1 Overview...................................................................16

7.2 Functional Block Diagram.........................................16

7.3 Feature Description...................................................17

7.4 Device Functional Modes..........................................24

8 Application and Implementation..................................25

8.1 Application Information............................................. 25

8.2 Typical Applications.................................................. 25

9 Power Supply Recommendations................................27

10 Layout...........................................................................27

10.1 Layout Guidelines................................................... 27

10.2 Layout Example...................................................... 27

11 Device and Documentation Support..........................30

11.1 Device Support........................................................30

11.2 Documentation Support.......................................... 30

11.3 Receiving Notification of Documentation Updates..30

11.4 Support Resources................................................. 30

11.5 Trademarks............................................................. 30

11.6 Electrostatic Discharge Caution..............................31

11.7 Glossary..................................................................31

12 Mechanical, Packaging, and Orderable

Information.................................................................... 32

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (February 2021) to Revision D (August 2021)

Page

•

Removed preview note and added thermal data for VSSOP-8 (DGK) package in Thermal Information for Dual

Channel.............................................................................................................................................................. 6

Changes from Revision B (March 2020) to Revision C (February 2021)

Page

•

Updated the numbering format for tables, figures, and cross-references throughout the document..................1

Removed preview notation from TLV9302 SOT-23 (8) package from Device Information table........................ 1

Removed preview notation from TLV9302 VSSOP (8) package from Device Information table........................ 1

Removed Table of Graphs table from the Specifications section....................................................................... 9

Removed Related Links section from the Device and Documentation Support section...................................30

Changes from Revision A (April 2019) to Revision B (March 2020)

Page

•

Changed the TLV9301 and TLV9304 device statuses from Advance Information to Production Data ..............1

Removed preview notation from TLV9301 SOT-23 (5) package from Device Information table........................ 1

Removed preview notation from TLV9301 SC70 (5) package from Device Information table............................1

Removed preview notation from TLV9304 SOIC (14) package from Device Information table..........................1

Removed preview notation from TLV9304 TSSOP (14) package from Device Information table...................... 1

Removed preview notation from TLV9301 DBV package (SOT-23) in the Pin Configuration and Functions

section................................................................................................................................................................ 3

Removed preview notation from TLV9301 DCK package (SC70) in the Pin Configuration and Functions

section................................................................................................................................................................ 3

Removed preview notation from TLV9304 D (SOIC) and TSSOP (PW) packages in the Pin Configuration and

Functions section................................................................................................................................................3

•

Changes from Revision * (February 2019) to Revision A (April 2019)

Page

•

Changed the TLV9302 device status from Advance Information to Production Data ........................................1

2

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5 Pin Configuration and Functions

OUT

Vœ

1

2

3

5

V+

IN+

Vœ

1

2

3

5

V+

IN+

4

INœ

4

OUT

Not to scale

Figure 5-1. TLV9301 DBV Package

5-Pin SOT-23

Figure 5-2. TLV9301 DCK Package

5-Pin SC70

Top View

Table 5-1. Pin Functions: TLV9301

DBV

I/O

DESCRIPTION

NAME

DCK

+IN

–IN

3

4

1

5

2

1

3

4

5

2

I

Noninverting input

I

Inverting input

OUT

V+

O

—

Output

Positive (highest) power supply

Negative (lowest) power supply

V–

OUT1

1

2

3

4

8

7

6

5

V+

IN1œ

IN1+

Vœ

OUT2

IN2œ

IN2+

Not to scale

Figure 5-3. TLV9302 D, DDF, DGK, and PW Package

8-Pin SOIC, TSOT, TSSOP, and VSSOP

Top View

Table 5-2. Pin Functions: TLV9302

I/O

DESCRIPTION

NAME

NO.

3

+IN A

+IN B

–IN A

–IN B

OUT A

OUT B

V+

I

Noninverting input, channel A

Noninverting input, channel B

Inverting input, channel A

Inverting input, channel B

Output, channel A

5

2

I

6

I

1

O

—

7

Output, channel B

8

Positive (highest) power supply

Negative (lowest) power supply

V–

4

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OUT1

IN1œ

IN1+

V+

1

2

3

4

5

6

7

14

13

12

11

10

9

OUT4

IN4œ

IN4+

Vœ

IN2+

IN2œ

OUT2

IN3+

IN3œ

OUT3

8

Not to scale

Figure 5-4. TLV9304 D and PW Package

14-Pin SOIC and TSSOP

Top View

Table 5-3. Pin Functions: TLV9304

I/O

DESCRIPTION

NAME

NO.

3

+IN A

+IN B

+IN C

+IN D

–IN A

–IN B

–IN C

–IN D

I

Noninverting input, channel A

Noninverting input, channel B

Noninverting input, channel C

Noninverting input, channel D

Inverting input, channel A

Inverting input, channel B

Inverting input, channel C

Inverting input, channel D

Output, channel A

5

10

12

2

I

6

I

9

I

13

1

I

OUT A

OUT B

OUT C

OUT D

V+

O

—

7

Output, channel B

8

Output, channel C

14

4

Output, channel D

Positive (highest) power supply

Negative (lowest) power supply

V–

11

4

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6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)⁽¹⁾

MIN

0

MAX

42

UNIT

V

Supply voltage, V_S= (V+) – (V–)

Common-mode voltage⁽³⁾

(V–) – 0.5

(V+) + 0.5

V_S+ 0.2

10

V

Signal input pins

Differential voltage^{(3) (4)}

Current⁽³⁾

V

–10

mA

Output short-circuit⁽²⁾

Continuous

Operating ambient temperature, T_A

Junction temperature, T_J

Storage temperature, T_stg

–55

–65

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) Short-circuit to ground, one amplifier per package.

(3) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be

current limited to 10 mA or less.

(4) Large differential voltages applied between IN+ and IN– for extended periods of time may cause a long-term shift to the input offset

voltage. This effect increases as temperature rises above 25°C.

6.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

4.5

MAX

UNIT

V_S

V_I

Supply voltage, (V+) – (V–)

Input voltage range

40

(V+) – 2

125

V

(V–) – 0.1

–40

T_A

Specified temperature

°C

6.4 Thermal Information for Single Channel

TLV9301

THERMAL METRIC⁽¹⁾

DBV (SOT-23)

5 PINS

192.5

DCK (SC70)

UNIT

5 PINS

203.9

116.2

51.7

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

113.3

60.2

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

37.6

24.6

ψ_JB

60.1

51.9

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

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6.5 Thermal Information for Dual Channel

TLV9302

THERMAL METRIC⁽¹⁾

D (SOIC)

8 PINS

DDF (SOT-23-8)

8 PINS

DGK (VSSOP)

8 PINS

PW (TSSOP)

8 PINS

UNIT

Junction-to-ambient thermal

resistance

R_θJA

138.7

150.4

189.3

188.4

°C/W

Junction-to-case (top) thermal

resistance

R_θJC(top)

R_θJB

78.7

82.2

27.8

85.6

70.0

8.1

75.8

111.0

15.4

77.1

119.1

14.2

°C/W

Junction-to-board thermal resistance

Junction-to-top characterization

parameter

ψ_JT

Junction-to-board characterization

parameter

ψ_JB

81.4

N/A

69.6

N/A

109.3

N/A

117.4

N/A

°C/W

Junction-to-case (bottom) thermal

resistance

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.6 Thermal Information for Quad Channel

TLV9304

THERMAL METRIC⁽¹⁾

D (SOIC)

14 PINS

105.5

61.4

PW (TSSOP)

14 PINS

134.5

55.4

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

61.0

79.2

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

21.6

9.3

ψ_JB

60.3

78.4

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6

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6.7 Electrical Characteristics

For V_S= (V+) – (V–) = 4.5 V to 40 V (±2.25 V to ±20 V) at T_A= 25°C, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and

V_OUT= V_S/ 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OFFSET VOLTAGE

±0.5

±2.5

V_OS

Input offset voltage

V_CM= V–

mV

T_A= –40°C to 125°C

±2.75

dV_OS/dT

PSRR

Input offset voltage drift

T_A= –40°C to 125°C

±2

5

µV/℃

µV/V

Input offset voltage versus

power supply

V_CM= V–

f = 0 Hz

±5

Channel separation

INPUT BIAS CURRENT

I_B

Input bias current

±10

pA

I_OS

Input offset current

NOISE

6

1

µV_PP

E_N

Input voltage noise

f = 0.1 Hz to 10 Hz

µV_RMS

f = 1 kHz

f = 10 kHz

f = 1 kHz

33

30

5

e_N

i_N

Input voltage noise density

Input current noise

nV/√Hz

fA/√Hz

INPUT VOLTAGE RANGE

Common-mode voltage

range

V_CM

(V–) – 0.2

95

(V+) – 2

V

V_S= 40 V, (V–) – 0.1 V < V_CM

< (V+) – 2 V

110

90

dB

Common-mode rejection

ratio

V_S= 4.5 V, (V–) – 0.1 V <

V_CM< (V+) – 2 V

CMRR

T_A= –40°C to 125°C

(V+) – 2 V < V_CM< (V+) + 0.1

V

See Common-Mode Voltage Range

INPUT CAPACITANCE

Z_ID

Differential

110 || 4

6 || 1.5

MΩ || pF

Z_ICM

Common-mode

TΩ || pF

OPEN-LOOP GAIN

V_S= 40 V, V_CM= V–

(V–) + 0.1 V < V_O< (V+) –

0.1 V

120

116

130

127

A_OL

Open-loop voltage gain

dB

T_A= –40°C to 125°C

FREQUENCY RESPONSE

GBW

SR

Gain-bandwidth product

1

3

MHz

V/µs

Slew rate

V_S= 40 V, G = +1, C_L= 20 pF

To 0.1%, V_S= 40 V, V_STEP= 10 V , G = +1, CL = 20 pF

To 0.1%, V_S= 40 V, V_STEP= 2 V , G = +1, CL = 20 pF

To 0.01%, V_S= 40 V, V_STEP= 10 V , G = +1, CL = 20 pF

To 0.01%, V_S= 40 V, V_STEP= 2 V , G = +1, CL = 20 pF

G = +1, R_L= 10 kΩ, C_L= 20 pF

5

2.5

6

t_S

Settling time

µs

3.5

60

1

Phase margin

°

Overload recovery time

V_IN× gain > V_S

µs

Total harmonic distortion +

noise

THD+N

V_S= 40 V, V_O= 1 V_RMS, G = -1, f = 1 kHz

0.003%

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6.7 Electrical Characteristics (continued)

For V_S= (V+) – (V–) = 4.5 V to 40 V (±2.25 V to ±20 V) at T_A= 25°C, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and

V_OUT= V_S/ 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT

V_S= 40 V, R_L= no load

3

50

V_S= 40 V, R_L= 10 kΩ

V_S= 40 V, R_L= 2 kΩ

V_S= 4.5 V, R_L= no load

V_S= 4.5 V, R_L= 10 kΩ

V_S= 4.5 V, R_L= 2 kΩ

75

250

1

350

Voltage output swing from Positive and negative rail

mV

rail

headroom

20

30

75

40

I_SC

Short-circuit current

Capacitive load drive

±60

mA

Ω

C_LOAD

See Typical Characteristics

600

Open-loop output

impedance

Z_O

f = 1 MHz, I_O= 0 A

POWER SUPPLY

150

175

Quiescent current per

amplifier

I_Q

I_O= 0 A

µA

T_A= –40°C to 125°C

8

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6.8 Typical Characteristics

at T_A= 25°C, V_S= ±20 V, V_CM= V_S/ 2, R_LOAD= 10 kΩ connected to V_S/ 2, and C_L= 100 pF (unless otherwise noted)

25%

20%

15%

10%

5%

25%

20%

15%

10%

5%

0

D001

Offset Voltage (mV)

Offset Voltage Drift (mV/èC)

D002

T_A= 25°C

Figure 6-1. Offset Voltage Production Distribution

Figure 6-2. Offset Voltage Drift Distribution

1000

1200

800

600

900

600

400

300

200

0

-200

-400

-600

-800

-1000

-300

-600

-900

-1200

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

D004

D003

V_CM= V–

V_CM= V+

Figure 6-4. Offset Voltage vs Temperature

Figure 6-3. Offset Voltage vs Temperature

800

600

400

200

0

750

600

450

300

150

0

-150

-300

-450

-600

-750

-200

-400

-600

-800

-20 -16 -12

-8

-4

0

4

8

Common Mode Voltage (V)

12

16

20

0

4

8

12 16 20 24 28 32 36 40 44

Supply Voltage (V)

D005

D008

T_A= 25°C

Figure 6-5. Offset Voltage vs Common-Mode Voltage

Figure 6-6. Offset Voltage vs Power Supply

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6.8 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±20 V, V_CM= V_S/ 2, R_LOAD= 10 kΩ connected to V_S/ 2, and C_L= 100 pF (unless otherwise noted)

100

80

60

40

20

0

150

125

100

75

70

60

50

40

30

20

10

0

Gain

Phase

G = 1

G = -1

G = 10

G = 100

G = 1000

50

-10

-20

-30

25

-20

0

100

1k

10k

Frequency (Hz)

100k

1M

100

1k

10k

Frequency (Hz)

100k

1M

C001

C002

C_LOAD= 15 pF

Figure 6-8. Closed-Loop Gain and Phase vs Frequency

Figure 6-7. Open-Loop Gain and Phase vs Frequency

3

320

I_B-

I_B+

I_OS

2.5

I_B+

2

280

240

200

160

120

80

I_OS

1.5

1

0.5

0

-0.5

-1

40

-1.5

-2

0

-2.5

-40

-20 -16 -12

-8

-4

0

4

8

Common Mode Voltage (V)

12

16

20

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

D010

D011

Figure 6-9. Input Bias Current vs Common-Mode Voltage

Figure 6-10. Input Bias Current vs Temperature

V+

V+ ꢀ 1 V

V+ ꢀ 2 V

V+ ꢀ 3 V

V+ ꢀ 4 V

V+ ꢀ 5 V

V+ ꢀ 6 V

Vꢀ + 10 V

Vꢀ + 9 V

Vꢀ + 8 V

Vꢀ + 7 V

Vꢀ + 6 V

Vꢀ + 5 V

Vꢀ + 4 V

Vꢀ + 3 V

Vꢀ + 2 V

Vꢀ + 1 V

Vꢀ

-40°C

25°C

85°C

125°C

V+ ꢀ 7 V

-40°C

25°C

85°C

125°C

V+ ꢀ 8 V

V+ ꢀ 9 V

V+ ꢀ 10 V

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

Output Current (mA)

D012

Figure 6-11. Output Voltage Swing vs Output Current (Sourcing) Figure 6-12. Output Voltage Swing vs Output Current (Sinking)

10

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6.8 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±20 V, V_CM= V_S/ 2, R_LOAD= 10 kΩ connected to V_S/ 2, and C_L= 100 pF (unless otherwise noted)

5

4.5

4

5

4.5

4

-40èC

3.5

3

3.5

3

25èC

125èC

85èC

125èC

2.5

2

2.5

2

1.5

1

1.5

1

-40èC

25èC

0.5

0

0.5

0

10

20

30

40

Output Current (mA)

50

60

70

80

90 100

0

10

20

30

40

Output Current (mA)

50

60

70

80

90 100

D013

V_S= 5 V

Figure 6-13. Output Voltage Swing vs Output Current (Sourcing) Figure 6-14. Output Voltage Swing vs Output Current (Sinking)

110

100

90

80

70

60

50

40

30

20

10

0

120

115

110

105

100

95

PSRR+

PSRR-

CMRR

90

100

1k

10k 100k

Frequency (Hz)

1M

10M

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

C003

D015

f = 0 Hz

Figure 6-15. CMRR and PSRR vs Frequency

Figure 6-16. CMRR vs Temperature (dB)

2

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

Time (1s/Div)

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

C015

D016

f = 0 Hz

Figure 6-18. 0.1-Hz to 10-Hz Noise

Figure 6-17. PSRR vs Temperature (dB)

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6.8 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±20 V, V_CM= V_S/ 2, R_LOAD= 10 kΩ connected to V_S/ 2, and C_L= 100 pF (unless otherwise noted)

-40

-50

120

110

100

90

80

70

60

50

40

30

20

10

0

R_L= 10 kW

R_L= 2 kW

R_L= 600 W

R_L= 128 W

-60

-70

-80

-90

-100

-110

100

1k

Frequency (Hz)

10k

10

100

1k

Frequency (Hz)

10k

100k

C012

C017

BW = 80 kHz, V_OUT= 3.5 V_RMS

Figure 6-20. THD+N Ratio vs Frequency

Figure 6-19. Input Voltage Noise Spectral Density vs Frequency

-30

150

145

140

135

130

125

120

115

110

-40

-50

-60

-70

-80

R_L= 10 kW

R_L= 2 kW

-90

R_L= 549 W

R_L= 128 W

-100

0.001

0.01

0.1

Amplitude (V_RMS

1

10 20

0

4

8

12

16

20

24

Supply Voltage (V)

28

32

36

40

)

C023

D021

BW = 80 kHz, f = 1 kHz

Figure 6-21. THD+N vs Output Amplitude

Figure 6-22. Quiescent Current vs Supply Voltage

150

145

140

135

130

152

148

144

140

136

132

128

124

120

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

D022

D023

Figure 6-23. Quiescent Current vs Temperature

Figure 6-24. Open-Loop Voltage Gain vs Temperature (dB)

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6.8 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±20 V, V_CM= V_S/ 2, R_LOAD= 10 kΩ connected to V_S/ 2, and C_L= 100 pF (unless otherwise noted)

780

720

660

600

540

480

420

360

300

240

180

120

33

30

27

24

21

18

15

12

9

R_ISO= 0 W, Positive Overshoot

R_ISO= 0 W, Negative Overshoot

R_ISO= 50 W, Positive Overshoot

R_ISO= 50 W, Negative Overshoot

6

3

0

40

80

120 160 200 240 280 320 360

Cap Load (pF)

100

1k

10k 100k

Frequency (Hz)

1M

10M

C007

C013

G = –1, 100-mV output step

Figure 6-26. Small-Signal Overshoot vs Capacitive Load

Figure 6-25. Open-Loop Output Impedance vs Frequency

55

50

45

40

35

30

25

64

60

56

52

48

44

40

36

32

28

24

20

R_ISO= 0 W, Positive Overshoot

15

R_ISO= 0 W, Negative Overshoot

R_ISO= 50 W, Positive Overshoot

R_ISO= 50 W, Negative Overshoot

10

5

0

40

80

120 160 200 240 280 320 360

Cap Load (pF)

0

100 200 300 400 500 600 700 800 900 1000

Cap Load (pF)

C008

C009

G = 1, 100-mV output step

G = –1, 100-mV output step

Figure 6-27. Small-Signal Overshoot vs Capacitive Load

Figure 6-28. Small-Signal Overshoot vs Capacitive Load

Input

Output

Input

Output

Time (20µs/Div)

Time (500ns/div)

C016

C018

G = –10

Figure 6-29. No Phase Reversal

Figure 6-30. Positive Overload Recovery

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6.8 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±20 V, V_CM= V_S/ 2, R_LOAD= 10 kΩ connected to V_S/ 2, and C_L= 100 pF (unless otherwise noted)

Input

Output

Input

Output

Time (500ns/div)

Time (2ms/div)

C018

C010

C005

C021

G = –10

C_L= 20 pF, G = 1, 20-mV step response

Figure 6-31. Negative Overload Recovery

Figure 6-32. Small-Signal Step Response

Input

Output

Input

Output

Time (1µs/div)

C011

C_L= 20 pF, G = 1

R_L= 1 kΩ, C_L= 20 pF, G = –1, 10-mV step response

Figure 6-34. Large-Signal Step Response (Falling)

Figure 6-33. Small-Signal Step Response

Input

Output

Input

Output

Time (1µs/div)

Time (2µs/div)

C005

C_L= 20 pF, G = 1

C_L= 10 pF, G = –1

Figure 6-35. Large-Signal Step Response (Rising)

Figure 6-36. Large-Signal Step Response

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6.8 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±20 V, V_CM= V_S/ 2, R_LOAD= 10 kΩ connected to V_S/ 2, and C_L= 100 pF (unless otherwise noted)

100

80

45

40

35

30

25

20

15

10

5

V_S= 40 V

V_S= 30 V

V_S= 15 V

60

40

20

Sourcing

Sinking

0

-20

-40

-60

-80

-100

0

1k

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

10k

100k

Frequency (Hz)

1M

10M

D038

C020

Figure 6-37. Short-Circuit Current vs Temperature

Figure 6-38. Maximum Output Voltage vs Frequency

-60

100

-70

-80

90

80

70

60

50

40

30

-90

-100

-110

-120

-130

100

1k

10k 100k

Frequency (Hz)

1M

10M

1M

10M

100M

Frequency (Hz)

1G

C014

C004

Figure 6-39. Channel Separation vs Frequency

Figure 6-40. EMIRR (Electromagnetic Interference Rejection

Ratio) vs Frequency

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7 Detailed Description

7.1 Overview

The TLV930x family (TLV9301, TLV9302, and TLV9304) is a family of 40-V, cost-optimized operational

amplifiers. These devices offer strong general-purpose DC and AC specifications, including rail-to-rail output,

low offset (±0.5 mV, typ), low offset drift (±2 µV/°C, typ), and 1-MHz bandwidth.

Convenient features such as wide differential input-voltage range, high output current (±60 mA), and high slew

rate (3 V/µs) make the TLV930x a robust operational amplifier for high-voltage, cost-sensitive applications.

The TLV930x family of op amps is available in standard packages and is specified from –40°C to 125°C.

7.2 Functional Block Diagram

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7.3 Feature Description

7.3.1 Input Protection Circuitry

The TLV930x uses a patented input architecture to eliminate the requirement for input protection diodes but still

provides robust input protection under transient conditions. Figure 7-1 shows conventional input diode protection

schemes that are activated by fast transient step responses and introduce signal distortion and settling time

delays because of alternate current paths, as shown in Figure 7-2. For low-gain circuits, these fast-ramping input

signals forward-bias back-to-back diodes, causing an increase in input current and resulting in extended settling

time.

V+

V_IN+

V_OUT

TLV930x

~0.7 V

40 V

V_IN-

V-

TLV930x Provides Full 40-V

Differential Input Range

Conventional Input Protection

Limits Differential Input Range

Figure 7-1. TLV930x Input Protection Does Not Limit Differential Input Capability

1

R_{on_mux}

V_n= 10 V

R_FILT

10 V

S_n

D

1

2

~œ9.3 V

10 V

C_FILT

C_S

C_D

VINœ

2

R_{on_mux}

S_n+1

V_n+1= œ10 V R_FILT

œ10 V

~0.7 V

VOUT

C_FILT

C_S

I_{diode_transient}

VIN+

œ10 V

Input Low-Pass Filter

Simplified Mux Model

Buffer Amplifier

Figure 7-2. Back-to-Back Diodes Create Settling Issues

The TLV930x family of operational amplifiers provides a true high-impedance differential input capability for high-

voltage applications. This patented input protection architecture does not introduce additional signal distortion or

delayed settling time, making the device an optimal op amp for multichannel, high-switched, input applications.

The TLV930x tolerates a maximum differential swing (voltage between inverting and noninverting pins of the op

amp) of up to 40 V, making the device suitable for use as a comparator or in applications with fast-ramping input

signals.

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7.3.2 EMI Rejection

The TLV930x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from

sources such as wireless communications and densely-populated boards with a mix of analog signal chain and

digital components. EMI immunity can be improved with circuit design techniques; the TLV930x benefits from

these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the

immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure

7-3 shows the results of this testing on the TLV930x. Table 7-1 shows the EMIRR IN+ values for the TLV930x at

particular frequencies commonly encountered in real-world applications. Table 7-1 lists applications that may be

centered on or operated near the particular frequency shown. The EMI Rejection Ratio of Operational Amplifiers

application report contains detailed information on the topic of EMIRR performance as it relates to op amps and

is available for download from www.ti.com.

100

90

80

70

60

50

40

30

1M

10M

100M

Frequency (Hz)

1G

C004

Figure 7-3. EMIRR Testing

Table 7-1. TLV930x EMIRR IN+ for Frequencies of Interest

FREQUENCY

APPLICATION OR ALLOCATION

EMIRR IN+

Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)

applications

400 MHz

59.5 dB

Global system for mobile communications (GSM) applications, radio communication, navigation,

GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications

900 MHz

1.8 GHz

2.4 GHz

3.6 GHz

5 GHz

68.9 dB

77.8 dB

78.0 dB

88.8 dB

87.6 dB

GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)

802.11b, 802.11g, 802.11n, Bluetooth^®, mobile personal communications, industrial, scientific and

medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)

Radiolocation, aero communication and navigation, satellite, mobile, S-band

802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite

operation, C-band (4 GHz to 8 GHz)

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7.3.3 Phase Reversal Protection

The TLV930x family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the

input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting

circuits when the input is driven beyond the specified common-mode voltage range, causing the output to

reverse into the opposite rail. The TLV930x is a rail-to-rail input op amp; therefore, the common-mode range can

extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into

the appropriate rail. This performance is shown in Figure 7-4.

Input

Output

Time (20µs/Div)

C016

Figure 7-4. No Phase Reversal

7.3.4 Thermal Protection

The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This

phenomenon is called self heating. The absolute maximum junction temperature of the TLV930x is 150°C.

Exceeding this temperature causes damage to the device. The TLV930x has a thermal protection feature that

prevents damage from self heating. The protection works by monitoring the temperature of the device and

turning off the op amp output drive for temperatures above 140°C. Figure 7-5 shows an application example

for the TLV9301 that has significant self heating (159°C) because of its power dissipation (0.81 W). Thermal

calculations indicate that for an ambient temperature of 65°C the device junction temperature must reach 187°C.

The actual device, however, turns off the output drive to maintain a safe junction temperature. Figure 7-5 shows

how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the

output is 3 V. When self heating causes the device junction temperature to increase above 140°C, the thermal

protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL.

3 V

T_A= 65°C

30 V

P_D= 0.81W

ꢀ_JA= 138.7°C/W

T_J= 138.7°C/W × 0.81W + 65°C

0 V

T_J= 177.3°C (expected)

-

150°C

140ºC

TLV9301

+

I_OUT= 30 mA

+

3 V

œ

RL

100 Ω

+

V_IN

3 V

œ

Figure 7-5. Thermal Protection

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7.3.5 Capacitive Load and Stability

The TLV930x features a resistive output stage capable of driving smaller capacitive loads, and by leveraging

an isolation resistor, the device can easily be configured to drive large capacitive loads. Increasing the gain

enhances the ability of the amplifier to drive greater capacitive loads; see Figure 7-6 and Figure 7-7. The

particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when

establishing whether an amplifier is stable in operation.

55

50

45

40

35

30

25

20

15

10

5

33

30

27

24

21

18

15

12

9

R_ISO= 0 W, Positive Overshoot

R_ISO= 0 W, Negative Overshoot

R_ISO= 50 W, Positive Overshoot

R_ISO= 50 W, Negative Overshoot

R_ISO= 0 W, Positive Overshoot

R_ISO= 0 W, Negative Overshoot

R_ISO= 50 W, Positive Overshoot

R_ISO= 50 W, Negative Overshoot

6

3

0

40

80

120 160 200 240 280 320 360

Cap Load (pF)

0

40

80

120 160 200 240 280 320 360

Cap Load (pF)

C008

C007

Figure 7-6. Small-Signal Overshoot vs Capacitive

Load (100-mV Output Step, G = 1)

Figure 7-7. Small-Signal Overshoot vs Capacitive

Load (100-mV Output Step, G = –1)

For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small (10

Ω to 20 Ω) resistor, R_ISO, in series with the output, as shown in Figure 7-8. This resistor significantly reduces

ringing and maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel

with the capacitive load, then a voltage divider is created, thus introducing a gain error at the output and

slightly reducing the output swing. The error introduced is proportional to the ratio R_ISO/ R_L, and is generally

negligible at low output levels. A high capacitive load drive makes the TLV930x well suited for applications such

as reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 7-8 uses an

isolation resistor, R_ISO, to stabilize the output of an op amp. R_ISOmodifies the open-loop gain of the system for

increased phase margin. For additional information on techniques to optimize and design using this circuit, TI

Precision Design TIDU032 details complete design goals, simulation, and test results.

+V_s

V_out

R_iso

+

C_load

+

V_in

-V_s

œ

Figure 7-8. Extending Capacitive Load Drive With the TLV9301

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7.3.6 Common-Mode Voltage Range

The TLV930x is a 40-V, rail-to-rail output operational amplifier with an input common-mode range that extends

100 mV beyond V– and within 2 V of V+ for normal operation. The device accomplishes this performance

through a complementary input stage, using a P-channel differential pair. Additionally, a complementary N-

channel differential pair has been included in parallel with the P-channel pair to eliminate common undesirable

op amp behaviors, such as phase reversal.

The TLV930x can operate with common mode ranges beyond 100 mV of the top rail, but with reduced

performance above (V+) – 2 V. The N-channel pair is active for input voltages close to the positive rail, typically

(V+) – 1 V to 100 mV above the positive supply. The P-channel pair is active for inputs from 100 mV below the

negative supply to approximately (V+) – 2 V. There is a small transition region, typically (V+) –2 V to (V+) – 1

V in which both input pairs are on. This transition region can vary modestly with process variation, and within

the transition region and N-channel region, many specifications of the op amp, including PSRR, CMRR, offset

voltage, offset drift, noise and THD performance may be degraded compared to operation within the P-channel

region.

Table 7-2. Typical Performance for Common-Mode Voltages Within 2 V of the Positive Supply

PARAMETER

MIN

TYP

MAX

UNIT

Input common-mode voltage

(V+) – 2

(V+) + 0.1

V

Offset voltage

1.5

2

mV

Offset voltage drift

Common-mode rejection

Open-loop gain

µV/°C

dB

75

0.7

dB

Gain-bandwidth product

MHz

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7.3.7 Electrical Overstress

Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress

(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even

the output pin. Each of these different pin functions have electrical stress limits determined by the voltage

breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to

the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them

from accidental ESD events both before and during product assembly.

Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is

helpful. Figure 7-9 shows an illustration of the ESD circuits contained in the TLV930x (indicated by the dashed

line area). The ESD protection circuitry involves several current-steering diodes connected from the input and

output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device

or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain

inactive during normal circuit operation.

TVS

R_F

+V_S

V_DD

TLV930x

100 Ω

R₁

R_S

INœ

œ

IN+

+

Power Supply

ESD Cell

R_L

I_D

+

V_IN

œ

V_SS

œV_S

TVS

Figure 7-9. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application

An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns), whereas an EOS event

is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-circuit

ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).

During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit

(labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.

Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if

activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by

turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting

resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.

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7.3.8 Overload Recovery

Overload recovery is defined as the time required for the op amp output to recover from a saturated state to

a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds

the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the

saturation region, the charge carriers in the output devices require time to return back to the linear state. After

the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the

propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.

The overload recovery time for the TLV930x is approximately 1 µs.

7.3.9 Typical Specifications and Distributions

Designers often have questions about a typical specification of an amplifier in order to design a more robust

circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an

amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These

deviations often follow Gaussian ("bell curve"), or normal distributions, and circuit designers can leverage this

information to guardband their system, even when there is not a minimum or maximum specification in Section

6.7.

0.00312% 0.13185%

0.13185% 0.00312%

0.00002%

2.145% 13.59% 34.13% 34.13% 13.59% 2.145%

1

1 1 1 1 1 1 1 1

1

ꢀ-61 ꢀ-51 ꢀ-41 ꢀ-31 ꢀ-21 ꢀ-1

ꢀ+1 ꢀ+21 ꢀ+31 ꢀ+41 ꢀ+51 ꢀ+61

ꢀ

Figure 7-10. Ideal Gaussian Distribution

Figure 7-10 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ,

or sigma, is the standard deviation of a system. For a specification that exhibits this kind of distribution,

approximately two-thirds (68.26%) of all units can be expected to have a value within one standard deviation, or

one sigma, of the mean (from µ–σ to µ+σ).

Depending on the specification, values listed in the typical column in Section 6.7 are represented in different

ways. As a general rule of thumb, if a specification naturally has a nonzero mean (for example, like gain

bandwidth), then the typical value is equal to the mean (µ). However, if a specification naturally has a mean near

zero (like input offset voltage), then the typical value is equal to the mean plus one standard deviation (µ + σ) in

order to most accurately represent the typical value.

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You can use this chart to calculate approximate probability of a specification in a unit; for example, for TLV930x,

the typical input voltage offset is 500 µV, so 68.2% of all TLV930x devices are expected to have an offset from

–500 µV to +500 µV. At 4 σ (±2000 µV), 99.9937% of the distribution has an offset voltage less than ±2000 µV,

which means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873 units.

Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits

will be removed from production material. For example, the TLV930x family has a maximum offset voltage of 2.5

mV at 125°C, and even though this corresponds to 5 σ (≈1 in 1.7 million units), which is extremely unlikely, TI

assures that any unit with larger offset than 2.5 mV will be removed from production material.

For specifications with no value in the minimum or maximum column, consider selecting a sigma value of

sufficient guardband for your application, and design worst-case conditions using this value. For example, the 6σ

value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be an option

as a wide guardband to design a system around. In this case, the TLV930x family does not have a maximum or

minimum for offset voltage drift, but based on Figure 6-2 and the typical value of 2 µV/°C in Section 6.7, it can

be calculated that the 6-σ value for offset voltage drift is about 12 µV/°C. When designing for worst-case system

conditions, this value can be used to estimate the worst possible offset across temperature without having an

actual minimum or maximum value.

However, process variation and adjustments over time can shift typical means and standard deviations, and

unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a

device. This information should be used only to estimate the performance of a device.

7.4 Device Functional Modes

The TLV930x has a single functional mode and is operational when the power-supply voltage is greater than 4.5

V (±2.25 V). The maximum power supply voltage for the TLV930x is 40 V (±20 V).

24

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8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The TLV930x family offers excellent DC precision and DC performance. These devices operate up to 40-V

supply rails and offer true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as 1-MHz

bandwidth and high output drive. These features make the TLV930x a robust, high-performance operational

amplifier for high-voltage industrial applications.

8.2 Typical Applications

8.2.1 High Voltage Precision Comparator

Many different systems require controlled voltages across numerous system nodes to ensure robust operation.

A comparator can be used to monitor and control voltages by comparing a reference threshold voltage with an

input voltage and providing an output when the input crosses this threshold.

The TLV930x family of op amps make excellent high voltage comparators due to their MUX-friendly input stage

(see Section 7.3.1). Previous generation high-voltage op amps often use back-to-back diodes across the inputs

to prevent damage to the op amp which greatly limits these op amps to be used as comparators, but the

TLV930x's patented input stage allows the device to have a wide differential voltage between the inputs.

V+

+

V_IN

V_OUT

V_TH

V+

R₁

R₂

Figure 8-1. Typical Comparator Application

8.2.1.1 Design Requirements

The primary objective is to design a 40-V precision comparator.

•

System supply voltage (V+): 40 V

Resistor 1 value: 100 kΩ

Resistor 2 value: 100 kΩ

Reference threshold voltage (V_TH): 20 V

Input voltage range (V_IN): 0 V – 40 V

Output voltage range (V_OUT): 0 V – 40 V

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8.2.1.2 Detailed Design Procedure

This noninverting comparator circuit applies the input voltage (V_IN) to the noninverting terminal of the op amp.

Two resistors (R₁and R₂) divide the supply voltage (V+) to create a mid-supply threshold voltage (V_TH) as

calculated in Equation 1. The circuit is shown in Figure 8-1. When V_INis less then V_TH, the output voltage

transitions to the negative supply and equals the low-level output voltage. When V_INis greater than V_TH, the

output voltage transitions to the positive supply and equals the high-level output voltage.

In this example, resistor 1 and 2 have been selected to be 100 kΩ, which sets the reference threshold at 20 V.

However, resistor 1 and 2 can be adjusted to modify the threshold using Equation 1. Resistor 1 and 2's values

have also been selected to reduce power consumption, but these values can be further increased to reduce

power consumption, or reduced to improve noise performance.

R

2

V

=

ìV₊

2

TH

R + R

1

(1)

8.2.1.3 Application Curve

45

40

35

30

25

20

15

10

5

Input

Output

0

-5

0

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Time (ms)

2

comp

Figure 8-2. Comparator Output Response to Input Voltage

26

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9 Power Supply Recommendations

The TLV930x is specified for operation from 4.5 V to 40 V (±2.25 V to ±20 V); many specifications apply from

–40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature

are presented in Section 6.7.

CAUTION

Supply voltages larger than 40 V can permanently damage the device; see the Absolute Maximum

Ratings table.

Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or

high-impedance power supplies. For more detailed information on bypass capacitor placement, refer to Section

10.

10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

•

Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.

Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to

the analog circuitry.

– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

•

Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital

and analog grounds paying attention to the flow of the ground current.

In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as

possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as

opposed to in parallel with the noisy trace.

•

Place the external components as close to the device as possible. As illustrated in Figure 10-2, keeping RF

and RG close to the inverting input minimizes parasitic capacitance.

Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

•

Cleaning the PCB following board assembly is recommended for best performance.

Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic

package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to

remove moisture introduced into the device packaging during the cleaning process. A low temperature, post

cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

10.2 Layout Example

VIN

+

VOUT

RG

RF

Figure 10-1. Schematic Representation

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Place components close

to device and to each

other to reduce parasitic

errors

Run the input traces

as far away from

the supply lines

as possible

VS+

RF

NC

Use a low-ESR,

ceramic bypass

capacitor

RG

GND

œIN

+IN

Vœ

V+

OUTPUT

NC

VIN

GND

VSœ

VOUT

Ground (GND) plane on another layer

Use low-ESR,

ceramic bypass

capacitor

Figure 10-2. Operational Amplifier Board Layout for Noninverting Configuration

GND

OUT

V-

GND

Figure 10-3. Example Layout for SC70 (DCK) Package

28

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GND

V+

INPUT A

OUTPUT B

V-

GND

Figure 10-4. Example Layout for VSSOP-8 (DGK) Package

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 TINA-TI^™(Free Software Download)

TINA^™is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a

free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range

of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain

analysis of SPICE, as well as additional design capabilities.

Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing

capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select

input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.

Note

These files require that either the TINA software (from DesignSoft^™) or TINA-TI software be installed.

Download the free TINA-TI software from the TINA-TI folder.

11.1.1.2 TI Precision Designs

The TLV930x is featured in several TI Precision Designs, available online at http://www.ti.com/ww/en/analog/

precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications

experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout,

bill of materials, and measured performance of many useful circuits.

11.2 Documentation Support

11.2.1 Related Documentation

Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application report

Texas Instruments, Capacitive Load Drive Solution using an Isolation Resistor reference design

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

11.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.5 Trademarks

TINA-TI^™are trademarks of Texas Instruments, Inc and DesignSoft, Inc.

TINA^™and DesignSoft^™are trademarks of DesignSoft, Inc.

TI E2E^™is a trademark of Texas Instruments.

Bluetooth^®is a registered trademark of Bluetooth SIG, Inc.

All trademarks are the property of their respective owners.

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11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

32

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PACKAGE MATERIALS INFORMATION

www.ti.com

26-Aug-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV9301IDBVR

TLV9301IDCKR

TLV9302IDDFR

SOT-23

SC70

DBV

DCK

DDF

5

8

3000

180.0

178.0

180.0

8.4

9.0

8.4

3.2

2.4

3.2

2.5

3.2

1.4

1.2

1.4

4.0

8.0

Q3

SOT-

23-THIN

TLV9302IDGKR

TLV9302IDR

VSSOP

SOIC

DGK

D

8

2500

2000

2500

2000

330.0

12.4

16.4

12.4

5.3

6.4

7.0

6.5

6.9

3.4

5.2

3.6

9.0

5.6

1.4

2.1

1.6

2.1

1.6

8.0

12.0

16.0

12.0

Q1

TLV9302IPWR

TLV9304IDR

TSSOP

SOIC

PW

D

8

14

TLV9304IPWR

TSSOP

PW

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Aug-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLV9301IDBVR

TLV9301IDCKR

TLV9302IDDFR

TLV9302IDGKR

TLV9302IDR

SOT-23

SC70

DBV

DCK

DDF

DGK

D

5

3000

2500

2000

2500

2000

210.0

190.0

210.0

366.0

853.0

366.0

185.0

190.0

185.0

364.0

449.0

364.0

35.0

30.0

35.0

50.0

35.0

50.0

SOT-23-THIN

VSSOP

SOIC

8

TLV9302IPWR

TLV9304IDR

TSSOP

SOIC

PW

D

8

14

TLV9304IPWR

TSSOP

PW

Pack Materials-Page 2

PACKAGE OUTLINE

DBV0005A

SOT-23 - 1.45 mm max height

S

C

A

L

E

4

.

0

SMALL OUTLINE TRANSISTOR

C

3.0

2.6

0.1 C

1.75

1.45

0.90

B

A

PIN 1

INDEX AREA

1

2

5

2X 0.95

1.9

3.05

2.75

1.9

4

3

0.5

5X

0.3

0.15

0.00

(1.1)

TYP

0.2

C A B

0.25

GAGE PLANE

0.22

0.08

TYP

8

0

TYP

0.6

0.3

TYP

SEATING PLANE

4214839/F 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.25 mm per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

1

5

5X (0.6)

SYMM

(1.9)

2

3

2X (0.95)

4

(R0.05) TYP

(2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214839/F 06/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

1

5

5X (0.6)

SYMM

(1.9)

2

3

2X(0.95)

4

(R0.05) TYP

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4214839/F 06/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

PW0008A

TSSOP - 1.2 mm max height

S

C

A

L

E

2

.

8

0

SMALL OUTLINE PACKAGE

C

6.6

6.2

SEATING PLANE

TYP

PIN 1 ID

AREA

A

0.1 C

6X 0.65

8

5

1

3.1

2.9

NOTE 3

2X

1.95

4

0.30

0.19

8X

4.5

4.3

1.2 MAX

B

0.1

C A

B

NOTE 4

(0.15) TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.75

0.50

0 - 8

DETAIL A

TYPICAL

4221848/A 02/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

PW0008A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

8X (1.5)

SYMM

8X (0.45)

(R0.05)

1

4

TYP

8

SYMM

6X (0.65)

5

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221848/A 02/2015

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0008A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

8X (1.5)

SYMM

(R0.05) TYP

8X (0.45)

1

4

8

SYMM

6X (0.65)

5

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

4221848/A 02/2015

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DDF0008A

SOT-23 - 1.1 mm max height

S

C

A

L

E

4

.

0

PLASTIC SMALL OUTLINE

C

2.95

2.65

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

A

6X 0.65

8

1

2.95

2.85

NOTE 3

2X

1.95

4

5

0.4

0.2

8X

0.1

C A

B

1.65

1.55

B

1.1 MAX

0.20

0.08

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.1

0.0

0 - 8

0.6

0.3

DETAIL A

TYPICAL

4222047/B 11/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DDF0008A

SOT-23 - 1.1 mm max height

PLASTIC SMALL OUTLINE

8X (1.05)

SYMM

1

8

8X (0.45)

SYMM

6X (0.65)

5

4

(R0.05)

TYP

(2.6)

LAND PATTERN EXAMPLE

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4222047/B 11/2015

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DDF0008A

SOT-23 - 1.1 mm max height

PLASTIC SMALL OUTLINE

8X (1.05)

SYMM

(R0.05) TYP

8

1

8X (0.45)

SYMM

6X (0.65)

5

4

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4222047/B 11/2015

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

C

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

A

PIN 1 ID AREA

6X .050

[1.27]

8

1

2X

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

4

5

8X .012-.020

[0.31-0.51]

B

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

1

8

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

5

4

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

1

8

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

5

4

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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型号：	TLV9301IDBVR
厂家：	TEXAS INSTRUMENTS
描述：	TLV930x 40-V, 1-MHz, RRO Operational Amplifiers for Cost-Sensitive Systems
文件：	总57页 (文件大小：3822K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLV9301IDBVR [TI]

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