TLV935X-Q1 [TI]
TLV935x-Q1 3.5-MHz, 40-V, RRO, MUX-Friendly Automotive Operational Amplifier for Cost-Sensitive Systems;
| 型号： | TLV935X-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TLV935x-Q1 3.5-MHz, 40-V, RRO, MUX-Friendly Automotive Operational Amplifier for Cost-Sensitive Systems |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV9351-Q1, TLV9352-Q1, TLV9354-Q1
SBOSA34C – JANUARY 2021 – REVISED SEPTEMBER 2021
TLV935x-Q1 3.5-MHz, 40-V, RRO, MUX-Friendly Automotive Operational Amplifier
for Cost-Sensitive Systems
1 Features
3 Description
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•
•
•
•
•
•
Low offset voltage: ±350 µV
Low offset voltage drift: ±1.5 µV/°C
Low noise: 15 nV/√Hz at 1 kHz
High common-mode rejection: 110 dB
Low bias current: ±10 pA
The TLV935x-Q1 family (TLV9351-Q1, TLV9352-Q1,
and TLV9354-Q1) is a family of 40-V cost-optimized
automotive operational amplifiers.
These devices offer strong DC and AC specifications,
including rail-to-rail output, low offset (±350 µV,
typ), low offset drift (±1.5 µV/°C, typ), and 3.5-MHz
bandwidth.
Rail-to-rail output
MUX-friendly/comparator inputs
– Amplifier operates with differential inputs up to
supply rail
– Amplifier can be used in open-loop or as
comparator
Wide bandwidth: 3.5-MHz GBW
High slew rate: 20 V/µs
Low quiescent current: 600 µA per amplifier
Wide supply: ±2.25 V to ±20 V, 4.5 V to 40 V
Robust EMIRR performance: EMI/RFI filters on
input pins
Unique features such as differential input-voltage
range to the supply rail, high output current (±60 mA),
and high slew rate (20 V/µs) make the TLV935x-Q1
a robust operational amplifier for high-voltage, cost-
sensitive applications.
•
•
•
•
•
The TLV935x-Q1 family of op amps is available in
standard packages and is specified from –40°C to
125°C.
Device Information
2 Applications
PART NUMBER(1)
PACKAGE
BODY SIZE (NOM)
2.90 mm × 1.60 mm
4.90 mm × 3.90 mm
3.00 mm × 3.00 mm
8.65 mm × 3.90 mm
4.20 mm × 1.90 mm
5.00 mm × 4.40 mm
•
•
•
•
•
•
•
•
•
Optimized for AEC-Q100 grade 1 applications
Infotainment and cluster
Passive safety
TLV9351-Q1
SOT-23 (5)
SOIC (8)
TLV9352-Q1
TLV9354-Q1
VSSOP (8)
SOIC (14)
SOT-23 (14)
TSSOP (14)
Body electronics and lighting
HEV/EV inverter and motor control
On-board (OBC) and wireless changer
Powertrain current sensor
Advanced driver assistance systems (ADAS)
Single-supply, low-side current sensing
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
RG
RF
R1
VOUT
VIN
C1
1
2pR1C1
f
=
-3 dB
VOUT
VIN
RF
1
1 + sR1C1
=
1 +
(
(
RG
TLV935x-Q1 in a Single-Pole, Low-Pass Filter
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV9351-Q1, TLV9352-Q1, TLV9354-Q1
SBOSA34C – JANUARY 2021 – REVISED SEPTEMBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings ....................................... 6
6.2 ESD Ratings .............................................................. 6
6.3 Recommended Operating Conditions ........................6
6.4 Thermal Information for Single Channel .................... 6
6.5 Thermal Information for Dual Channel .......................7
6.6 Thermal Information for Quad Channel ..................... 7
6.7 Electrical Characteristics ............................................8
6.8 Typical Characteristics..............................................10
7 Detailed Description......................................................17
7.1 Overview...................................................................17
7.2 Functional Block Diagram.........................................17
7.3 Feature Description...................................................18
7.4 Device Functional Modes..........................................25
8 Application and Implementation..................................26
8.1 Application Information............................................. 26
8.2 Typical Applications.................................................. 26
9 Power Supply Recommendations................................28
10 Layout...........................................................................28
10.1 Layout Guidelines................................................... 28
10.2 Layout Example...................................................... 29
11 Device and Documentation Support..........................31
11.1 Device Support........................................................31
11.2 Documentation Support.......................................... 31
11.3 Receiving Notification of Documentation Updates..31
11.4 Support Resources................................................. 31
11.5 Trademarks............................................................. 31
11.6 Electrostatic Discharge Caution..............................32
11.7 Glossary..................................................................32
12 Mechanical, Packaging, and Orderable
Information.................................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 2021) to Revision C (September 2021)
Page
•
•
•
•
Deleted preview note from SOIC (14) package throughout data sheet. ............................................................1
Deleted preview note from SOT-23 (14) package throughout data sheet. ........................................................ 1
Deleted preview note from SOIC (8) package throughout data sheet. ..............................................................1
Deleted preview note from SOT-23 (5) package throughout data sheet. .......................................................... 1
Changes from Revision A (March 2021) to Revision B (May 2021)
Page
Deleted preview note from TSSOP (14) package throughout data sheet. .........................................................1
Deleted preview note from PW package in Thermal Information for Quad Channel table................................. 7
•
•
Changes from Revision * (January 2021) to Revision A (March 2021)
Page
•
Changed device status from Advance Information to Production Data ............................................................. 1
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5 Pin Configuration and Functions
OUT
Vœ
1
2
3
5
V+
IN+
4
INœ
Not to scale
Figure 5-1. TLV9351-Q1 DBV Package
5-Pin SOT-23
Top View
Table 5-1. Pin Functions: TLV9351-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
3
IN+
IN–
OUT
V+
I
Noninverting input
4
I
Inverting input
1
O
—
—
Output
5
Positive (highest) power supply
Negative (lowest) power supply
V–
2
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OUT1
IN1œ
IN1+
Vœ
1
2
3
4
8
7
6
5
V+
OUT2
IN2œ
IN2+
Not to scale
Figure 5-2. TLV9352-Q1 D and DGK Package
8-Pin SOIC and VSSOP
Top View
Table 5-2. Pin Functions: TLV9352-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
3
IN1+
IN2+
IN1–
IN2–
I
I
Noninverting input, channel 1
Noninverting input, channel 1
Inverting input, channel 1
Inverting input, channel 2
Output, channel 1
5
2
I
6
I
OUT1
OUT2
V+
1
O
O
—
—
7
Output, channel 2
8
Positive (highest) power supply
Negative (lowest) power supply
V–
4
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OUT1
IN1œ
IN1+
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT4
IN4œ
IN4+
Vœ
IN2+
IN2œ
OUT2
IN3+
IN3œ
OUT3
8
Not to scale
Figure 5-3. TLV9354-Q1 D, DYY, and PW Package
14-Pin SOIC, SOT-23, and TSSOP
Top View
Table 5-3. Pin Functions: TLV9354-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
3
IN1+
IN2+
IN3+
IN4+
IN1–
IN2–
IN3–
IN4–
OUT1
OUT2
OUT3
OUT4
V+
I
I
Noninverting input, channel 1
Noninverting input, channel 2
Noninverting input, channel 3
Noninverting input, channel 4
Inverting input, channel 1
Inverting input, channel 2
Inverting input, channel 3
Inverting input, channel 4
Output, channel 1
5
10
12
2
I
I
I
6
I
9
I
13
1
I
O
O
O
O
—
—
7
Output, channel 2
8
Output, channel 3
14
4
Output, channel 4
Positive (highest) power supply
Negative (lowest) power supply
V–
11
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
MIN
0
MAX
42
UNIT
V
Supply voltage, VS = (V+) – (V–)
Common-mode voltage (3)
(V–) – 0.5
(V+) + 0.5
VS + 0.2
10
V
Signal input pins
Differential voltage(3)
Current (3)
V
–10
–55
–65
mA
Output short-circuit (2)
Continuous
Operating ambient temperature, TA
Junction temperature, TJ
Storage temperature, Tstg
150
150
150
°C
°C
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Short-circuit to ground, one amplifier per package.
(3) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
4.5
MAX
40
UNIT
VS
VI
Supply voltage, (V+) – (V–)
Input voltage range
V
V
(V–) – 0.1
–40
(V+) – 2
125
TA
Specified ambient temperature
°C
6.4 Thermal Information for Single Channel
TLV9351-Q1
DBV
(SOT-23)
THERMAL METRIC (1)
UNIT
5 PINS
187.4
86.2
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
54.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
27.8
ψJB
54.3
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Thermal Information for Dual Channel
TLV9352-Q1
D
DGK
UNIT
THERMAL METRIC (1)
(SOIC)
(VSSOP)
8 PINS
132.6
73.4
8 PINS
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
176.5
68.1
98.2
12.0
96.7
N/A
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
76.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
24.0
ψJB
75.4
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 Thermal Information for Quad Channel
TLV9354-Q1
D
DYY
(SOT-23)
PW
(TSSOP)
THERMAL METRIC (1)
UNIT
(SOIC)
14 PINS
101.4
57.6
14 PINS
110.7
55.9
14 PINS
118
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
47.6
60.9
6
57.3
35.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
18.5
2.3
ψJB
56.9
35.1
60.4
N/A
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.7 Electrical Characteristics
For VS = (V+) – (V–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
±0.35
±1.8
±2
VOS
Input offset voltage
VCM = V–
mV
TA = –40°C to 125°C
dVOS/dT
PSRR
Input offset voltage drift
TA = –40°C to 125°C
TA = –40°C to 125°C
±1.5
±2
5
µV/℃
μV/V
µV/V
Input offset voltage
versus power supply
VCM = V–
f = 0 Hz
±5
Channel separation
INPUT BIAS CURRENT
IB
Input bias current
±10
±10
pA
pA
IOS
Input offset current
NOISE
2
0.33
15
μVPP
EN
Input voltage noise
f = 0.1 Hz to 10 Hz
µVRMS
f = 1 kHz
f = 10 kHz
f = 1 kHz
Input voltage noise
density
eN
iN
nV/√Hz
fA/√Hz
14
Input current noise
2
INPUT VOLTAGE RANGE
Common-mode voltage
range
VCM
(V–) – 0.2
(V+) – 2
V
VS = 40 V, (V–) – 0.1 V < VCM < (V+)
– 2 V (Main input pair)
95
82
110
90
Common-mode rejection
ratio
CMRR
TA = –40°C to 125°C
dB
VS = 4.5 V, (V–) – 0.1 V < VCM < (V+)
– 2 V (Main input pair)
INPUT CAPACITANCE
ZID
Differential
100 || 3
6 || 1
MΩ || pF
TΩ || pF
ZICM
Common-mode
OPEN-LOOP GAIN
120
130
127
VS = 40 V, VCM = V–
(V–) + 0.1 V < VO < (V+) – 0.1 V
AOL Open-loop voltage gain
dB
TA = –40°C to 125°C
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6.7 Electrical Characteristics (continued)
For VS = (V+) – (V–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
3.5
20
5
MHz
V/μs
Slew rate
VS = 40 V, G = +1, CL = 20 pF
To 0.01%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF
To 0.01%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF
To 0.1%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF
To 0.1%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF
G = +1, RL = 10 kΩ
4
tS
Settling time
μs
4
3
Phase margin
60
600
°
Overload recovery time
VIN × gain > VS
ns
Total harmonic distortion
+ noise (1)
THD+N
VS = 40 V, VO = 1 VRMS, G = 1, f = 1 kHz
0.001%
OUTPUT
VS = 40 V, RL = no load(2)
5
50
10
55
VS = 40 V, RL = 10 kΩ
VS = 40 V, RL = 2 kΩ
VS = 4.5 V, RL = no load(2)
VS = 4.5 V, RL = 10 kΩ
VS = 4.5 V, RL = 2 kΩ
200
1
250
Voltage output swing
from rail
Positive and negative rail headroom
mV
20
30
75
40
ISC
Short-circuit current
Capacitive load drive
±60
300
mA
pF
CLOAD
Open-loop output
impedance
ZO
f = 1 MHz, IO = 0 A
VCM = V–, IO = 0 A
600
Ω
POWER SUPPLY
650
800
850
Quiescent current per
amplifier
IQ
µA
TA = –40°C to 125°C
(1) Third-order filter; bandwidth = 80 kHz at –3 dB.
(2) Specified by characterization only.
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6.8 Typical Characteristics
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
33
30
27
24
21
18
15
12
9
50
40
30
20
10
0
6
3
0
D001
D002
Offset Voltage Drift (µV/C)
Offset Voltage (µV)
Distribution from 60 amplifiers
Distribution from 15462 amplifiers, TA = 25°C
Figure 6-2. Offset Voltage Drift Distribution
Figure 6-1. Offset Voltage Production Distribution
900
400
300
200
100
0
700
500
300
100
-100
-300
-500
-700
-900
-100
-200
-300
-400
-40 -20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
D003
D004
VCM = V–
VCM = V+
Figure 6-4. Offset Voltage vs Temperature
Figure 6-3. Offset Voltage vs Temperature
800
600
400
200
0
800
600
400
200
0
-200
-400
-600
-800
-200
-400
-600
-800
-20
-15
-10
-5
0
5
10
15
20
16
16.5
17
17.5
18
18.5
19
19.5
20
VCM
VCM
D005
D005
TA = 25°C
TA = 25°C
Figure 6-5. Offset Voltage vs Common-Mode Voltage
Figure 6-6. Offset Voltage vs Common-Mode Voltage (Transition
Region)
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
800
600
400
200
0
800
600
400
200
0
-200
-400
-600
-800
-200
-400
-600
-800
-20
-15
-10
-5
0
5
10
15
20
-20
-15
-10
-5
0
5
10
15
20
VCM
VCM
D006
D007
TA = 125°C
TA = –40°C
Figure 6-8. Offset Voltage vs Common-Mode Voltage
100 200
Figure 6-7. Offset Voltage vs Common-Mode Voltage
600
500
400
300
200
100
0
Gain (dB)
Phase (ꢀ)
90
80
70
60
50
40
30
20
10
0
175
150
125
100
75
50
-100
-200
-300
-400
-500
-600
25
0
-25
-50
-75
-100
-10
-20
100
1k
10k
100k
1M
10M
0
5
10
15
20
25
30
35
40
45
Frequency (Hz)
Supply Voltage (V)
C002
D008
CL = 20 pF
Figure 6-10. Open-Loop Gain and Phase vs Frequency
Figure 6-9. Offset Voltage vs Power Supply
80
70
60
50
40
30
20
10
0
6
4.5
3
G = ꢀ1
G = 1
G = 10
G = 100
G = 1000
1.5
0
-1.5
-3
-4.5
IBꢀ
IB+
IOS
-6
-10
-20
-7.5
-20 -16 -12
-8
-4
0
4
8
12
16
20
100
1k
10k
100k
1M
10M
Common Mode Voltage (V)
Frequency (Hz)
D010
C001
Figure 6-12. Input Bias Current vs Common-Mode Voltage
Figure 6-11. Closed-Loop Gain vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
150
125
100
75
V+
V+ ꢀ 1 V
V+ ꢀ 2 V
V+ ꢀ 3 V
V+ ꢀ 4 V
V+ ꢀ 5 V
V+ ꢀ 6 V
V+ ꢀ 7 V
V+ ꢀ 8 V
V+ ꢀ 9 V
V+ ꢀ 10 V
IBꢀ
IB+
IOS
50
25
0
-25
-50
-75
-100
-40°C
25°C
125°C
-40
-20
0
20
40
60
80
100 120 140
0
10
20
30
40
50
60
70
80
90 100
Temperature (°C)
Output Current (mA)
D011
D012
Figure 6-13. Input Bias Current vs Temperature
Vꢀ + 8 V
Figure 6-14. Output Voltage Swing vs Output Current (Sourcing)
135
-40°C
25°C
125°C
CMRR
PSRR+
PSRRꢀ
120
105
90
75
60
45
30
15
0
Vꢀ + 7 V
Vꢀ + 6 V
Vꢀ + 5 V
Vꢀ + 4 V
Vꢀ + 3 V
Vꢀ + 2 V
Vꢀ + 1 V
Vꢀ
0
10
20
30
40
50
60
70
80
90 100
100
1k
10k
100k
1M
10M
Output Current (mA)
Frequency (Hz)
D012
C003
Figure 6-15. Output Voltage Swing vs Output Current (Sinking)
Figure 6-16. CMRR and PSRR vs Frequency
135
130
125
120
170
165
160
155
150
145
140
115
PMOS (VCM ꢀ V+ ꢁ 1.5 V)
110
NMOS (VCM V+ ꢁ 1.5 V)
105
100
95
90
85
-40
-20
0
20
40
60
80
100 120 140
-40 -20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
D015
D016
f = 0 Hz
f = 0 Hz
Figure 6-17. CMRR vs Temperature (dB)
Figure 6-18. PSRR vs Temperature (dB)
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
1
0.8
0.6
0.4
0.2
0
200
100
10
-0.2
-0.4
-0.6
-0.8
-1
1
1
10
100
1k
10k
100k
Time (1s/div)
Frequency (Hz)
C017
C019
Figure 6-20. Input Voltage Noise Spectral Density vs Frequency
Figure 6-19. 0.1-Hz to 10-Hz Noise
-32
-40
-32
RL = 10 kꢀ
RL = 2 kꢀ
RL = 604 ꢀ
RL = 128 ꢀ
RL = 128 ꢀ
-40
RL = 604 ꢀ
RL = 2 kꢀ
RL = 10 kꢀ
-48
-48
-56
-56
-64
-64
-72
-72
-80
-80
-88
-88
-96
-96
-104
-112
-104
-112
100
1k
10k
0.001
0.01
0.1
1
10 20
Frequency (Hz)
Amplitude (Vrms)
C012
C023
BW = 80 kHz, VOUT = 1 VRMS
BW = 80 kHz, f = 1 kHz
Figure 6-22. THD+N vs Output Amplitude
Figure 6-21. THD+N Ratio vs Frequency
580
570
560
550
540
530
520
510
500
490
480
700
675
650
625
600
575
550
525
500
475
450
0
4
8
12
16
20
24
28
32
36
40
-40
-20
0
20
40
60
80
100 120 140
Supply Voltage (V)
Temperature (°C)
D021
D022
VCM = V–
Figure 6-23. Quiescent Current vs Supply Voltage
Figure 6-24. Quiescent Current vs Temperature
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
140
135
130
125
120
115
700
650
600
550
500
450
400
350
300
250
200
150
VS = 4 V
VS = 40 V
-40 -20
0
20
40
60
80
100 120 140
100
1k
10k
100k
1M
10M
Temperature (°C)
Frequency (Hz)
D023
C013
Figure 6-25. Open-Loop Voltage Gain vs Temperature (dB)
Figure 6-26. Open-Loop Output Impedance vs Frequency
60
80
70
60
50
40
30
50
40
30
20
20
RISO = 0 ꢀ, Positive Overshoot
RISO = 0 ꢀ, Positive Overshoot
RISO = 0 ꢀ, Negative Overshoot
RISO = 50 ꢀ, Positive Overshoot
RISO = 50 ꢀ, Negative Overshoot
RISO = 0 ꢀ, Negative Overshoot
10
0
10
0
RISO = 50 ꢀ, Positive Overshoot
RISO = 50 ꢀ, Negative Overshoot
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Cap Load (pF)
Cap Load (pF)
C007
C008
G = –1, 10-mV output step
G = 1, 10-mV output step
Figure 6-27. Small-Signal Overshoot vs Capacitive Load
Figure 6-28. Small-Signal Overshoot vs Capacitive Load
60
Input
Output
50
40
30
20
10
Time (20us/div)
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Cap Load (pF)
C016
C009
VIN = ±20 V; VS = VOUT = ±17 V
Figure 6-30. No Phase Reversal
Figure 6-29. Phase Margin vs Capacitive Load
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
Input
Input
Output
Output
Time (100ns/div)
Time (100ns/div)
C018
C010
C005
C018
C011
C005
G = –10
G = –10
Figure 6-31. Positive Overload Recovery
Figure 6-32. Negative Overload Recovery
Input
Output
Input
Output
Time (300ns/div)
Time (1µs/div)
CL = 20 pF, G = –1, 20-mV step response
CL = 20 pF, G = 1, 20-mV step response
Figure 6-34. Small-Signal Step Response
Figure 6-33. Small-Signal Step Response, Rising
Input
Output
Input
Output
Time (300ns/div)
Time (300ns/div)
CL = 20 pF, G = 1
CL = 20 pF, G = 1
Figure 6-35. Large-Signal Step Response (Rising)
Figure 6-36. Large-Signal Step Response (Falling)
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
100
80
60
Input
Output
40
20
Sourcing
Sinking
0
-20
-40
-60
-80
-100
Time (2µs/div)
-40 -20
0
20
40
60
80
100 120 140
Temperature (°C)
C021
D014
CL = 20 pF, G = –1
Figure 6-37. Large-Signal Step Response
Figure 6-38. Short-Circuit Current vs Temperature
-50
45
40
35
30
25
20
15
10
5
VS = 40 V
VS = 30 V
VS = 15 V
VS = 2.7 V
-60
-70
-80
-90
-100
-110
-120
-130
0
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
C020
C014
Figure 6-39. Maximum Output Voltage vs Frequency
Figure 6-40. Channel Separation vs Frequency
110
100
90
80
70
60
50
40
1M
10M
100M
Frequency (Hz)
1G
C004
Figure 6-41. EMIRR (Electromagnetic Interference Rejection Ratio) at Inputs vs Frequency
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7 Detailed Description
7.1 Overview
The TLV935x-Q1 family (TLV9351-Q1, TLV9352-Q1, and TLV9354-Q1) is a family of 40-V, cost-optimized
automotive operational amplifiers. These devices offer strong general-purpose DC and AC specifications,
including rail-to-rail output, low offset (±350 µV, typ), low offset drift (±1.5 µV/°C, typ), and 3.5-MHz bandwidth.
Convenient features such as wide differential input-voltage range, high output current (±60 mA), and high slew
rate (20 V/μs) make the TLV935x-Q1 a robust operational amplifier for high-voltage, cost-sensitive applications.
The TLV935x-Q1 family of op amps is available in standard packages and is specified from –40°C to 125°C.
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINÛ
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
VÛ
(Ground)
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7.3 Feature Description
7.3.1 Input Protection Circuitry
The TLV935x-Q1 uses a patented input architecture to eliminate the requirement for input protection diodes
but still provides robust input protection under transient conditions. Figure 7-1 shows conventional input diode
protection schemes that are activated by fast transient step responses and introduce signal distortion and
settling time delays because of alternate current paths, as shown in Figure 7-2. For low-gain circuits, these
fast-ramping input signals forward-bias back-to-back diodes, causing an increase in input current and resulting in
extended settling time.
V+
V+
VIN+
VIN+
VOUT
VOUT
TLV935x
~0.7 V
40 V
VINꢀ
VINꢀ
Vꢀ
Vꢀ
OPAx990 Provides Full 40-V
Differential Input Range
Conventional Input Protection
Limits Differential Input Range
Figure 7-1. TLV935x-Q1 Input Protection Does Not Limit Differential Input Capability
1
Ron_mux
Vn = 10 V
RFILT
10 V
Sn
D
1
2
~œ9.3 V
10 V
CFILT
CS
CD
VINœ
2
Ron_mux
Sn+1
Vn+1 = œ10 V RFILT
œ10 V
~0.7 V
VOUT
CFILT
CS
Idiode_transient
VIN+
œ10 V
Input Low-Pass Filter
Simplified Mux Model
Buffer Amplifier
Figure 7-2. Back-to-Back Diodes Create Settling Issues
The TLV935x-Q1 family of operational amplifiers provides a true high-impedance differential input capability
for high-voltage applications. This patented input protection architecture does not introduce additional signal
distortion or delayed settling time, making the device an optimal op amp for multichannel, high-switched,
input applications. The TLV935x-Q1 tolerates a maximum differential swing (voltage between inverting and
noninverting pins of the op amp) of up to 40 V, making the device suitable for use as a comparator or in
applications with fast-ramping input signals.
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7.3.2 EMI Rejection
The TLV935x-Q1 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the TLV935x-Q1 benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify
the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.
Figure 7-3 shows the results of this testing on the TLV935x-Q1. Table 7-1 shows the EMIRR IN+ values
for the TLV935x-Q1 at particular frequencies commonly encountered in real-world applications. Table 7-1 lists
applications that may be centered on or operated near the particular frequency shown. The EMI Rejection Ratio
of Operational Amplifiers (SBOA128) application report contains detailed information on the topic of EMIRR
performance as it relates to op amps and is available for download from www.ti.com.
110
100
90
80
70
60
50
40
1M
10M
100M
1G
Frequency (Hz)
C004
Figure 7-3. EMIRR Testing
Table 7-1. TLV935x-Q1 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
400 MHz
71 dB
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
5 GHz
80 dB
87 dB
90 dB
92 dB
94 dB
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
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7.3.3 Phase Reversal Protection
The TLV935x-Q1 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The TLV935x-Q1 is a rail-to-rail input op amp; therefore, the common-mode range
can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits
into the appropriate rail.
7.3.4 Thermal Protection
The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This
phenomenon is called self heating. The absolute maximum junction temperature of the TLV935x-Q1 is 150°C.
Exceeding this temperature causes damage to the device. The TLV935x-Q1 has a thermal protection feature
that prevents damage from self heating. The protection works by monitoring the temperature of the device and
turning off the op amp output drive for temperatures above 140°C. Figure 7-4 shows an application example for
the TLV9351-Q1 that has significant self heating (159°C) because of its power dissipation (0.81 W). Thermal
calculations indicate that for an ambient temperature of 65°C the device junction temperature will reach 187°C.
The actual device, however, turns off the output drive to maintain a safe junction temperature. Figure 7-4 shows
how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the
output is 3 V. When self heating causes the device junction temperature to increase above 140°C, the thermal
protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL.
3 V
TA = 65°C
30 V
PD = 0.81W
JA = 138.7°C/W
0 V
TJ = 138.7°C/W × 0.81W + 65°C
TJ = 177.3°C (expected)
ꢀ
150°C
140ºC
TLV9351
ꢁ
IOUT = 30 mA
+
3 V
–
RL
100
+
–
VIN
3 V
Figure 7-4. Thermal Protection
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7.3.5 Capacitive Load and Stability
The TLV935x-Q1 features a resistive output stage capable of driving smaller capacitive loads, and by leveraging
an isolation resistor, the device can easily be configured to drive large capacitive loads. Increasing the gain
enhances the ability of the amplifier to drive greater capacitive loads; see Figure 7-5 and Figure 7-6. The
particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when
establishing whether an amplifier is stable in operation.
80
70
60
50
40
30
20
10
0
60
50
40
30
20
10
0
RISO = 0 ꢀ, Positive Overshoot
RISO = 0 ꢀ, Negative Overshoot
RISO = 50 ꢀ, Positive Overshoot
RISO = 50 ꢀ, Negative Overshoot
RISO = 0 ꢀ, Positive Overshoot
RISO = 0 ꢀ, Negative Overshoot
RISO = 50 ꢀ, Positive Overshoot
RISO = 50 ꢀ, Negative Overshoot
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Cap Load (pF)
Cap Load (pF)
C008
C007
Figure 7-5. Small-Signal Overshoot vs Capacitive
Load (100-mV Output Step, G = 1)
Figure 7-6. Small-Signal Overshoot vs Capacitive
Load (100-mV Output Step, G = –1)
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small (10
Ω to 20 Ω) resistor, RISO, in series with the output, as shown in Figure 7-7. This resistor significantly reduces
ringing and maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with
the capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly
reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible
at low output levels. A high capacitive load drive makes the TLV935x-Q1 well suited for applications such
as reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 7-7 uses an
isolation resistor, RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for
increased phase margin. For additional information on techniques to optimize and design using this circuit, TI
Precision Design TIDU032 details complete design goals, simulation, and test results.
+Vs
Vout
Riso
+
Cload
+
Vin
-Vs
œ
Figure 7-7. Extending Capacitive Load Drive With the TLV9351-Q1
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7.3.6 Common-Mode Voltage Range
The TLV935x-Q1 is a 40-V, rail-to-rail output operational amplifier with an input common-mode range
that extends 100 mV beyond V– and within 2 V of V+ for normal operation. The device accomplishes
this performance through a complementary input stage, using a P-channel differential pair. Additionally, a
complementary N-channel differential pair has been included in parallel with the P-channel pair to eliminate
common undesirable op amp behaviors, such as phase reversal.
The TLV935x-Q1 can operate with common mode ranges beyond 100 mV of the top rail, but with reduced
performance above (V+) – 2 V. The N-channel pair is active for input voltages close to the positive rail, typically
(V+) – 1 V to 100 mV above the positive supply. The P-channel pair is active for inputs from 100 mV below the
negative supply to approximately (V+) – 2 V. There is a small transition region, typically (V+) –2 V to (V+) – 1
V in which both input pairs are on. This transition region can vary modestly with process variation, and within
the transition region and N-channel region, many specifications of the op amp, including PSRR, CMRR, offset
voltage, offset drift, noise and THD performance may be degraded compared to operation within the P-channel
region.
Table 7-2. Typical Performance for Common-Mode Voltages Within 2 V of the Positive Supply
PARAMETER
MIN
TYP
MAX
UNIT
Input common-mode voltage
(V+) – 2
(V+) + 0.1
V
Offset voltage
1.5
2
mV
Offset voltage drift
Common-mode rejection
Open-loop gain
µV/°C
dB
75
75
1.5
dB
Gain-bandwidth product
MHz
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7.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even
the output pin. Each of these different pin functions have electrical stress limits determined by the voltage
breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to
the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them
from accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event
is helpful. Figure 7-8 shows an illustration of the ESD circuits contained in the TLV935x-Q1 (indicated by the
dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the
input and output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption
device or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to
remain inactive during normal circuit operation.
TVS
RF
+VS
VDD
TLV935x
100
100
R1
RS
IN–
IN+
–
+
Power Supply
ESD Cell
RL
ID
+
–
VIN
VSS
–VS
TVS
Figure 7-8. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit
(labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
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7.3.8 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to
a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds
the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the TLV935x-Q1 is approximately 600 ns.
7.3.9 Typical Specifications and Distributions
Designers often have questions about a typical specification of an amplifier in order to design a more robust
circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an
amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These
deviations often follow Gaussian ("bell curve"), or normal distributions, and circuit designers can leverage this
information to guardband their system, even when there is not a minimum or maximum specification in Section
6.7.
0.00312% 0.13185%
0.13185% 0.00312%
0.00002%
0.00002%
2.145% 13.59% 34.13% 34.13% 13.59% 2.145%
1
1 1 1 1 1 1 1 1
1
1
1
ꢀ-61 ꢀ-51 ꢀ-41 ꢀ-31 ꢀ-21 ꢀ-1
ꢀ+1 ꢀ+21 ꢀ+31 ꢀ+41 ꢀ+51 ꢀ+61
ꢀ
Figure 7-9. Ideal Gaussian Distribution
Figure 7-9 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ,
or sigma, is the standard deviation of a system. For a specification that exhibits this kind of distribution,
approximately two-thirds (68.26%) of all units can be expected to have a value within one standard deviation, or
one sigma, of the mean (from µ – σ to µ + σ).
Depending on the specification, values listed in the typical column of Section 6.7 are represented in different
ways. As a general rule of thumb, if a specification naturally has a nonzero mean (for example, like gain
bandwidth), then the typical value is equal to the mean (µ). However, if a specification naturally has a mean near
zero (like input offset voltage), then the typical value is equal to the mean plus one standard deviation (µ + σ) in
order to most accurately represent the typical value.
You can use this chart to calculate approximate probability of a specification in a unit; for example, for TLV935x-
Q1, the typical input voltage offset is 350 µV, so 68.2% of all TLV935x-Q1 devices are expected to have an offset
from –350 µV to 350 µV. At 4 σ (±1400 µV), 99.9937% of the distribution has an offset voltage less than ±1400
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µV, which means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873
units.
Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits
will be removed from production material. For example, the TLV935x-Q1 family has a maximum offset voltage
of 1.8 mV at 125°C, and even though this corresponds to about 5 σ (≈1 in 1.7 million units), which is extremely
unlikely, TI assures that any unit with larger offset than 1.8 mV will be removed from production material.
For specifications with no value in the minimum or maximum column, consider selecting a sigma value of
sufficient guardband for your application, and design worst-case conditions using this value. For example, the
6-σ value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be an
option as a wide guardband to design a system around. In this case, the TLV935x-Q1 family does not have a
maximum or minimum for offset voltage drift, but based on the typical value of 1.5 µV/°C in Section 6.7, it can
be calculated that the 6-σ value for offset voltage drift is about 9 µV/°C. When designing for worst-case system
conditions, this value can be used to estimate the worst possible offset across temperature without having an
actual minimum or maximum value.
However, process variation and adjustments over time can shift typical means and standard deviations, and
unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a
device. This information should be used only to estimate the performance of a device.
7.4 Device Functional Modes
The TLV935x-Q1 has a single functional mode and is operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the TLV935x-Q1 is 40 V (±20 V).
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TLV935x-Q1 family offers excellent DC precision and DC performance. These devices operate up to 40-V
supply rails and offer true rail-to-rail output, low offset voltage and offset voltage drift, as well as 3.5-MHz
bandwidth and high output drive. These features make the TLV935x-Q1 a robust, high-performance operational
amplifier for high-voltage cost-sensitive applications.
8.2 Typical Applications
8.2.1 High Voltage Precision Comparator
Many different systems require controlled voltages across numerous system nodes to ensure robust operation.
A comparator can be used to monitor and control voltages by comparing a reference threshold voltage with an
input voltage and providing an output when the input crosses this threshold.
The TLV935x-Q1 family of op amps make excellent high voltage comparators due to their MUX-friendly input
stage (see Section 7.3.1). Previous generation high-voltage op amps often use back-to-back diodes across the
inputs to prevent damage to the op amp which greatly limits these op amps to be used as comparators, but the
TLV935x-Q1's patented input stage allows the device to have a wide differential voltage between the inputs.
V+
+
VIN
VOUT
VTH
V+
R1
R2
Figure 8-1. Typical Comparator Application
8.2.1.1 Design Requirements
The primary objective is to design a 40-V precision comparator.
•
•
•
•
•
•
System supply voltage (V+): 40 V
Resistor 1 value: 100 kΩ
Resistor 2 value: 100 kΩ
Reference threshold voltage (VTH): 20 V
Input voltage range (VIN): 0 V – 40 V
Output voltage range (VOUT): 0 V – 40 V
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8.2.1.2 Detailed Design Procedure
This noninverting comparator circuit applies the input voltage (VIN) to the noninverting terminal of the op amp.
Two resistors (R1 and R2) divide the supply voltage (V+) to create a mid-supply threshold voltage (VTH) as
calculated in Equation 1. The circuit is shown in Figure 8-1. When VIN is less then VTH, the output voltage
transitions to the negative supply and equals the low-level output voltage. When VIN is greater than VTH, the
output voltage transitions to the positive supply and equals the high-level output voltage.
In this example, resistor 1 and 2 have been selected to be 100 kΩ, which sets the reference threshold at 20 V.
However, resistor 1 and 2 can be adjusted to modify the threshold using Equation 1. Resistor 1 and 2's values
have also been selected to reduce power consumption, but these values can be further increased to reduce
power consumption, or reduced to improve noise performance.
R
2
V
=
ìV+
2
TH
R + R
1
(1)
8.2.1.3 Application Curve
45
40
35
30
25
20
15
10
5
Input
Output
0
-5
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Time (ms)
2
comp
Figure 8-2. Comparator Output Response to Input Voltage
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9 Power Supply Recommendations
The TLV935x-Q1 is specified for operation from 4.5 V to 40 V (±2.25 V to ±20 V); many specifications apply from
–40°C to 125°C.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see Section 6.1.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high-impedance power supplies. For more detailed information on bypass capacitor placement, refer to Section
10.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. As illustrated in Figure 10-2, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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10.2 Layout Example
VIN
+
VOUT
RG
RF
Figure 10-1. Schematic Representation
Place components close
to device and to each
other to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
NC
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
œIN
+IN
Vœ
V+
OUTPUT
NC
VIN
GND
GND
VSœ
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 10-2. Operational Amplifier Board Layout for Noninverting Configuration
GND
GND
OUT
V-
GND
Figure 10-3. Example Layout for SC70 (DCK) Package
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GND
GND
GND
V+
INPUT A
OUTPUT B
V-
GND
GND
GND
Figure 10-4. Example Layout for VSSOP-8 (DGK) Package
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
Note
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 TI Precision Designs
The TLV935x-Q1 is featured in several TI Precision Designs, available online at http://www.ti.com/ww/en/analog/
precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications
experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout,
bill of materials, and measured performance of many useful circuits.
11.2 Documentation Support
11.2.1 Related Documentation
•
•
•
•
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers
Texas Instruments, Capacitive Load Drive Solution using an Isolation Resistor
Texas Instruments, Analog Engineer's Circuit Cookbook: Amplifiers
Texas Instruments, AN31 amplifier circuit collection
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TINA-TI™ are trademarks of Texas Instruments, Inc and DesignSoft, Inc.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
All trademarks are the property of their respective owners.
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11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTLV9354QDRQ1
TLV9351QDBVRQ1
TLV9352QDGKRQ1
TLV9352QDRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOT-23
VSSOP
SOIC
D
14
5
3000
TBD
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
DBV
DGK
D
3000 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
2JMF
27ST
8
8
T9352Q
TLV9354QDYYRQ1
TLV9354QPWRQ1
ACTIVE SOT-23-THIN
ACTIVE TSSOP
DYY
PW
14
14
TLV9354Q
T9354Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Oct-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV9351-Q1, TLV9352-Q1, TLV9354-Q1 :
Catalog : TLV9351, TLV9352, TLV9354
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV9351QDBVRQ1
TLV9352QDGKRQ1
TLV9352QDRQ1
SOT-23
VSSOP
SOIC
DBV
DGK
D
5
8
3000
2500
3000
3000
180.0
330.0
330.0
330.0
8.4
3.2
5.3
6.4
6.9
3.2
3.4
5.2
5.6
1.4
1.4
2.1
1.6
4.0
8.0
8.0
8.0
8.0
Q3
Q1
Q1
Q1
12.4
12.4
12.4
12.0
12.0
12.0
8
TLV9354QPWRQ1
TSSOP
PW
14
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV9351QDBVRQ1
TLV9352QDGKRQ1
TLV9352QDRQ1
SOT-23
VSSOP
SOIC
DBV
DGK
D
5
8
3000
2500
3000
3000
210.0
366.0
853.0
853.0
185.0
364.0
449.0
449.0
35.0
50.0
35.0
35.0
8
TLV9354QPWRQ1
TSSOP
PW
14
Pack Materials-Page 2
PACKAGE OUTLINE
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
C
3.36
3.16
SEATING PLANE
PIN 1 INDEX
AREA
A
0.1 C
12X 0.5
14
1
4.3
4.1
NOTE 3
2X
3
7
8
0.31
0.11
14X
0.1
C A
B
1.1 MAX
2.1
1.9
B
0.2
0.08
TYP
SEE DETAIL A
0.25
GAUGE PLANE
0°- 8°
0.1
0.0
0.63
0.33
DETAIL A
TYP
4224643/B 07/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
5. Reference JEDEC Registration MO-345, Variation AB
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EXAMPLE BOARD LAYOUT
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
SYMM
14X (1.05)
1
14
14X (0.3)
SYMM
12X (0.5)
8
7
(R0.05) TYP
(3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224643/B 07/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
SYMM
14X (1.05)
1
14
14X (0.3)
SYMM
12X (0.5)
8
7
(R0.05) TYP
(3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 20X
4224643/B 07/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/F 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/F 06/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/F 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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